BD8P250MUF-C [ROHM]
BD8P250MUF-C是具备升压控制功能的同步整流降压DC/DC转换器。可根据各种要求实现通用设计的DC/DC转换器，在冷启动等输入电压下降时允许输出电压下降的情况下，可用作降压DC/DC转换器，在需要保持输出电压的情况下，可连接专用的升压FET用作升降压DC/DC转换器。凭借Quick Buck Booster技术升降压工作时也可实现高速响应，能够降低输出电容器的容量值。;
| 型号： | BD8P250MUF-C |
| 厂家： | 
ROHM |
| 描述： | BD8P250MUF-C是具备升压控制功能的同步整流降压DC/DC转换器。可根据各种要求实现通用设计的DC/DC转换器，在冷启动等输入电压下降时允许输出电压下降的情况下，可用作降压DC/DC转换器，在需要保持输出电压的情况下，可连接专用的升压FET用作升降压DC/DC转换器。凭借Quick Buck Booster技术升降压工作时也可实现高速响应，能够降低输出电容器的容量值。 电容器 转换器 |
| 文件： | 总45页 (文件大小：3349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
2.7 V to 36 V Input, 2 A
SingleBuckDC/DCConverterwithBoostFunction
For Automotive
BD8P250MUF-C
General Description
Key Specifications
BD8P250MUF-C is a synchronous rectification buck DC/DC
converter with a boost control function. This DC/DC
converter enables a common design that can meet a variety
of demands, including the use as a buck DC/DC converter if
a drop of the output voltage is acceptable during the input
voltage drop such as a cold cranking, and the use as a
buck-boost DC/DC with an exclusive boost-FET connected
if the output voltage must be maintained. The Quick Buck
Booster® technology realizes a high-speed response even
during buck-boost operations, allowing reduction in the
capacitance value of the output capacitor.
Input Voltage A:
3.5 V to 36 V
(Buck DC/DC Converter, Initial startup is over 4.8 V)
Input Voltage B:
(Buck-Boost DC/DC Converter, Initial startup is over 7.5 V)
Output Voltage:
Output Current in Buck Operation:
Output Current in Buck-Boost Operation: 0.8 A(Max)
Switching Frequency:
Shutdown Circuit Current:
Quiescent Current:
2.7 V to 36 V
5.0 V(Typ)
2 A(Max)
2.2 MHz(Typ)
3.5 µA(Typ)
8 µA(Typ)
-40 °C to +125 °C
Operating Temperature:
Features
Package
W(Typ) x D(Typ) x H(Max)
4.00 mm x 4.00 mm x 1.00 mm
Quick Buck Booster®
VQFN24FV4040
Nano Pulse Control™
AEC-Q100 Qualitied (Note 1)
Boost Control Function
LLM(Light Load Mode)
Spread Spectrum Function
Power Good Function
Soft Start Function
Current Mode Control
Enlarged View
Phase Compensation Included
Over Current Protection
Input Under Voltage Lockout Protection
Thermal Shutdown Protection
Output Over Voltage Protection
Short Circuit Protection
VQFN24FV4040
Wettable Flank Package
Wettable Flank QFN Package
(Note 1) Grade 1
Applications
Automotive Equipment
(Cluster Panel, Infotainment Systems)
Other Electronic Equipment
Typical Application Circuit
BD8P250MUF-C
CBOOT
BD8P250MUF-C
CBOOT
Exclusive Boost-FET
BD90302NUF-C
VIN
VIN
VIN
BOOT
VIN
BOOT
L1
L1
VOUT
VOUT
SW
SW
SW2 PVOUT
CTLIN
PVIN
EN
PVIN
EN
VOUT
VOUT
CIN
CIN
COUT
VCC_EX
VCC_EX
PGND
COUT
VMODE
RCTL
MODE
SSCG
VMODE
MODE
SSCG
CTLOUT
PGOOD
VREG
CTLOUT
PGOOD
VREG
RPGOOD
RPGOOD
GND PGND
GND PGND
CREG
CREG
A. Buck DC/DC Converter
B. Buck-Boost DC/DC Converter (Use Exclusive Boost-FET)
Figure 1. Application Circuit
Quick Buck Booster® is a registered trademark of ROHM Co., Ltd.
Nano Pulse Control™ is a trademark of ROHM Co., Ltd.
〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays
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BD8P250MUF-C
Pin Configuration
EN
VIN
1
2
3
4
5
6
18 CTLOUT
17 SSCG
16 N.C
PVIN
PVIN
PVIN
N.C
EXP-PAD
15 BOOT
14 SW
13 SW
(TOP VIEW)
Figure 2. Pin Configuration
Pin Descriptions
Pin No.
Pin Name
EN
Function
Enable pin. Apply Low-level (0.8 V or lower) to turn this device off. Apply High-level (2.0
V or higher) to turn this device on. This pin must be terminated.
1
2
VIN
Power supply input pin of the internal circuitry. Connect this pin to PVIN pin.
Power supply input pins that are used for the output stage of the switching regulator.
Connecting input ceramic capacitors with values of 4.7 µF(Typ) and 0.1 µF to this pin is
recommended.
3to5
PVIN
6
7,8
N.C
PGND
N.C.
No connection pin. Leave these pins open, or connect to PVIN pin.
Ground pins for the output stage of the switching regulator.
No connection pin. Leave these pins open, or connect to PGND pin.
No connection pin. Leave this pin open.
9to10
11
N.C.
Switching node pins. These pins are connected to the source of the High Side FET and
drain of the Low Side FET.
12to14
SW
Connect a bootstrap capacitor of 0.1 µF between this pin and the SW pins.
The voltage of this capacitor is the gate drive voltage of the High Side FET.
15
16
BOOT
N.C.
No connection pin. Leave this pin open.
Pin to select Spread Spectrum function. Connect this pin to VREG pin or GND pin.
Connect to VREG pin to enable Spread Spectrum function and connect to GND pin to
disable Spread Spectrum function.
17
SSCG
Pin used to control the exclusive Boost-FET. When using the exclusive Boost-FET,
connect this pin to CTLIN pin of the exclusive Boost-FET. Connect this pin to GND pin
through a pull-down 1 kΩ resistor when not using the exclusive Boost-FET.
18
19
CTLOUT
PGOOD
Power Good pin, an open drain output. Connect to VREG pin or suitable voltage supply
through a pull-up resistor. Using a 10 kΩ to 100 kΩ resistance is recommended.
20
21
22
VOUT
VCC_EX
GND
Sense pin of output voltage. This pin is controlled to become 5.0 V(Typ).
Internal power supply pin. Connect this pin to VOUT pin.
Ground pin.
Internal power supply output pin. This node supplies power 5.0 V(Typ) to other blocks
which are mainly responsible for the control function of the switching regulator. Connect
a ceramic capacitor with value of 1.0 µF(Typ) to ground.
23
VREG
Pin for setting switching control mode. Turning this pin’s signal to Low-level (0.8 V or
lower) enables the LLM control and the mode is automatically switched between the
LLM control and PWM (Pulse Wide Modulation) control. Turning this pin’s signal to
High-level (2.0 V or higher) enables the forced PWM control.This pin must be
terminated.
24
-
MODE
A backside heat dissipation pad. Connecting to the internal PCB ground plane by using
via provides excellent heat dissipation characteristics.
EXP-PAD
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BD8P250MUF-C
Block Diagram
VCC_EX
VREG
VIN
VREF
tsdout
VREG
tsdout
VREF
VIN
uvloout
porout
TSD
UVLO
POR
VREF
GND
pgout
OSC
clk
SSCG
MODE
BOOST Comp
clk
mode
VOUT
Boost Duty
CTLOUT
MODE
VIN
pgout
EN
VREF
VREG
scpout
porout
VOUT
SCP
uvloout
scpout
ovpout
mode
HOCP Comp
FB
BOOT
PVIN
VREG
GmAmp1
Clamper
GmAmp2
PWM Comp
VREF
Vc
Control
Logic
Driver
Soft
Start
SW
clk
Vr
Ramp
SLEEP Comp
ZX Comp
sleep
VREF
Current
Sense
VREF
VREF
pgout
PGOOD
PGND
PGOOD
OVP
ovpout
Figure 3. Block Diagram
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BD8P250MUF-C
Description of Blocks
•GmAmp1
This block is an error amplifier and its inputs are the reference voltage VREF and the division voltage FB of VOUT pin. It
controls the GmAmp1 output such that the VREF voltage and the FB voltage equal.
•GmAmp2
This block sends the signal Vc which is composed of the GmAmp1 output and the current sense signal to PWM Comp.
•Soft Start
It is a function to prevent overshoot of inrush current and the output voltage by gradually raising the input reference
voltage of GmAmp1 upon power supply ON. Soft start time is 1.0 ms(Typ).
•OSC
This block generates the clock frequency. Connect SSCG pin to GND pin to disable Spread Spectrum function and
connect SSCG pin to VREG pin to enable it. This function becomes invalid when PGOOD output is Low or during
Buck-Boost operation.
•Ramp
This block generates the saw tooth waveform Vr from the clock signal generated by OSC.
•Current Sense
This block detects the amount of change in inductor current through the Low Side FET and sends a current sense signal to
GmAmp2.
•Clamper
This block clamps GmAmp1 output voltage and inductor current. It works as over current protection and LLM control
current.
•PWM Comp
This block compares the saw tooth waveform Vr with the GmAmp2 output Vc and controls the duty cycle of the output
switching pulse.
•Control Logic
This block receives the signal generated by the PWM Comp and outputs the control signal to the output MOSFET. In
addition, it controls ON/OFF of the switching during light load and upon abnormal detection.
•TSD
This block is a thermal shutdown circuit. It will shut down the device to prevent thermal damage or a thermal-runaway of
the device when the chip temperature reaches to approximately 175 °C(Typ) or more. When the chip temperature falls
below the TSD threshold, the circuits are automatically restored to normal operation with hysteresis of 25 °C(Typ). Note
that the thermal shutdown circuit is intended to prevent destruction of the device. Therefore, it is highly recommended to
always keep the device temperature within Tjmax = 150 °C. Operation above operating temperature range will reduce the
lifetime of the device. The restart need the input voltage like the startup. The regulator restarts the operation with soft start.
•SCP
This is the short circuit protection circuit. Turns OFF the output stage MOSFET for 15.4 ms (Typ) if it detects the VOUT pin
voltage to be 55 % (Typ) or lower for 0.1 ms (Typ) or longer. Then, a restart is performed with the soft start. The SCP
functions is masked for 1.4 ms (Typ) after the soft start. The input voltage required for the restoration is the same as that
for the startup.
•OVP
This is the output over voltage protection circuit. When it detects the VOUT pin voltage is 120 % (Typ) or more for 1 µs
(Typ) or longer, the output MOSFET are turned OFF. When it detects the VOUT pin voltage is less than 120 % (Typ) for 7
µs (Typ) or longer, it returns to normal operation.
•UVLO
The UVLO block is for under voltage lockout protection. It will shut down the device when the VIN falls to 2.4 V(Typ) or
lower. The release voltage is 4.45 V(Typ) when the exclusive Boost-FET is not used, and is 7.15 V(Typ) when used with
the exclusive Boost-FET. The regulator restarts the operation with soft start when the release voltage is satisfied.
•VREG
This block is the internal power supply circuit. It outputs 5.0 V(Typ) and is the power supply to the control circuit and driver.
The input of this block during startup is the VIN pin voltage. When the PGOOD output becomes High, the VCC_EX pin
voltage becomes its input supply, and consequently, high efficiency is achieved.
•VREF
The VREF block generates the internal reference voltage.
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Description of Blocks – continued
•MODE
When MODE pin is 2.0 V or more, the device works by forced PWM control. When MODE pin is 0.8 V or less, the device
enables the LLM control and the mode is automatically switched between the LLM control and PWM control. However,
during Buck-Boost operation, the device works on forced PWM control.
•Driver
This circuit drives the gates of the output MOSFET.
•PGOOD
When the VOUT pin voltage reaches within ±5 %, the built-in Nch MOSFET turns OFF and the PGOOD output turns High.
In addition, the PGOOD output turns Low when the VOUT pin voltage reaches outside ±10 %.
•POR
The POR block is the input under voltage lockout protection for the internal power supply. It will shut down the device when
the VREG voltage falls to 2.85 V (Typ) or less. When the release voltage of 3.0 V (Typ) is satisfied, the regulator restarts
the operation with soft start.
•SLEEP Comp
This block controls the VOUT pin voltage in PFM control from 101 % of PWM control to 102 % of PWM control.
•ZX Comp
This block stops the switching by detecting the reverse SW output current at LLM control.
•BOOST Comp, Boost Duty
This is the control circuit of the Boost signal. When used with the exclusive Boost-FET, PGOOD output is High and the VIN
pin voltage becomes 140 % (Typ) or less of the VOUT pin voltage, an ON pulse with 70 % (Typ) duty is output by CTLOUT
pin and putting the device in Buck-Boost operation. It returns to Buck operation with 10 % (Typ) of hysteresis.
•HOCP Comp
This block limits current of the High Side FET. When it detects current of 4 A (Min) or more, High Side FET is turned OFF.
This function works only in abnormal situations such as when the SW pin is shorted to GND.
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BD8P250MUF-C
Absolute Maximum Ratings (Ta=25°C)
Parameter
Symbol
Rating
Unit
Input Voltage
VVIN, VPVIN
VEN
-0.3 to +42
-0.3 to +42
-0.3 to +49
-0.3 to +7
V
V
V
V
EN Voltage
BOOT Voltage
VBOOT
Voltage from SW to BOOT
ΔVBOOT
MODE, SSCG, VOUT, VCC_EX,
VREG, PGOOD, CTLOUT Voltage
VMODE, VSSCG, VVOUT, VVCC_EX
VVREG, VPGOOD, VCTLOUT
,
-0.3 to +7
V
Maximum Junction Temperature
Storage Temperature Range
Tjmax
Tstg
150
˚C
˚C
-55 to +150
Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by
increasing board size and copper area so as not to exceed the maximum junction temperature rating.
Thermal Resistance (Note 1)
Thermal Resistance (Typ)
Parameter
Symbol
Unit
1s(Note 3)
2s2p(Note 4)
VQFN24FV4040
Junction to Ambient
Junction to Top Characterization Parameter(Note 2)
θJA
107.4
9
32.6
4
°C/W
°C/W
ΨJT
(Note 1) Based on JESD51-2A(Still-Air).
(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside
surface of the component package.
(Note 3) Using a PCB board based on JESD51-3.
(Note 4) Using a PCB board based on JESD51-5, 7.
Layer Number of
Measurement Board
Material
FR-4
Board Size
Single
114.3 mm x 76.2 mm x 1.57 mmt
Top
Copper Pattern
Thickness
Footprints and Traces
70 μm
Layer Number of
Measurement Board
Thermal Via(Note 5)
Material
FR-4
Board Size
114.3 mm x 76.2 mm x 1.6 mmt
2 Internal Layers
Pitch
Diameter
4 Layers
1.20 mm
Φ0.30 mm
Top
Copper Pattern
Bottom
Thickness
Copper Pattern
Thickness
Copper Pattern
Thickness
Footprints and Traces
70 μm
74.2 mm x 74.2 mm
35 μm
74.2 mm x 74.2 mm
70 μm
(Note 5) This thermal via connects with the copper pattern of all layers.
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BD8P250MUF-C
Recommended Operating Conditions
Parameter
Symbol
VINA
Min
3.5
2.7
Typ
Max
36
Unit
V
Input Voltage A
(Not use Exclusive Boost-FET)
Input Voltage B
(Use Exclusive Boost-FET)
-
-
VINB
36
V
Operating Temperature
Topr
-40
-
-
-
+125
2.0
˚C
Output Current in Buck Operation
IOUTBUCK
A
Output Current in Buck-Boost
Operation
IOUTBOOST
-
-
0.8
A
SW Minimum ON Time(Note1)
Input Capacitor(Note2)
VREG Capacitor(Note2)
tONMIN
CIN
-
45
4.7
1.0
-
-
ns
µF
µF
2.3
0.48
CREG
2.1
(Note 1) This parameter is for 1A output. Not 100 % tested.
(Note 2) Ceramic capacitor is recommended. The capacitor value including temperature change, DC bias change, and aging change must be considered.
Electrical Characteristics (Unless otherwise specified Ta = -40 ˚C to +125 ˚C, VIN = 12 V, VEN = 5 V)
Limit
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
VIN
Shutdown Circuit Current
Quiescent Current (VIN)
ISDN
-
-
3.5
1.4
7.0
2.8
µA
µA
VEN=0 V, Ta<105 °C
VMODE=0 V,
VOUT=VVCC_EX=5.5 V,
Ta<105 °C
IQVIN
VMODE=0 V,
Quiescent Current (VOUT
)
IQVOUT
VUVLOL
VUVLOHA
-
16
2.4
32
2.6
µA
V
VOUT=VVCC_EX=5.5 V,
Ta<105 °C
UVLO Detection Voltage
UVLO Release Voltage A
2.2
4.25
VIN Falling
VIN Rising,
4.45
4.65
V
CTLOUT Pin=0 V
or 1 kΩ pull-down
VIN Rising,
UVLO Release Voltage B
VUVLOHB
6.9
7.15
7.4
V
CTLOUT Pin=Open
or CTLIN Pin(Note 3)
EN/MODE/SSCG
EN Threshold Voltage High
EN Threshold Voltage Low
EN Input Current
VENH
VENL
2.0
0
-
-
VIN
0.8
1.0
5.5
0.8
1.0
5.5
0.8
1.0
V
V
IEN
-
0
-
µA
V
VEN=5 V
MODE Threshold Voltage High
MODE Threshold Voltage Low
MODE Input Current
VMODEH
VMODEL
IMODE
VSSCGH
VSSCGL
ISSCG
2.0
0
-
V
-
0
-
µA
V
VMODE=5 V
VSSCG=5 V
VVREG Falling
SSCG Threshold Voltage High
SSCG Threshold Voltage Low
SSCG Input Current
2.0
0
-
V
-
0
µA
VREG
VREG Voltage
VREG
4.80
2.70
5.00
2.85
5.20
3.00
V
V
POR Detection Voltage
VPORL
(Note 3) CTLIN is the pin of exclusive boost-FET.
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Electrical Characteristics – continued
(Unless otherwise specified Ta = -40 ˚C to +125 ˚C, VIN = 12 V, VEN = 5 V)
Limit
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
VOUT
Output Voltage
VOUT1
VOUT2
tSS
4.90
4.90
0.5
5.000
5.075
1.0
5.10
5.25
1.5
V
V
PWM Control
LLM Control, VMODE=0 V,
Including output ripple
Output Voltage (LLM) (Note 4)
Soft Start Time
ms
SW
High Side FET ON Resistance
Low Side FET ON Resistance
High Side FET Leakage Current
RONH
RONL
-
-
-
110
110
0
220
220
10
mΩ ISW=-50 mA
mΩ ISW=50 mA
VIN=36 V, VEN=0 V, VSW=0 V,
ILEAKSWH
µA
µA
Ta<105 ˚C
VIN=36 V, VEN=0 V, VSW=36
Low Side FET Leakage Current
ILEAKSWL
-
0
10
V,
Ta<105 ˚C
Switching Frequency
Over Current Protection(Note 4)
Spread Spectrum
fSW
IOCP
fSSCG
2.0
3.1
-
2.2
3.6
2.4
4.1
-
MHz
A
fSW
x 110 %
MHz VSSCG=5 V
Spread Spectrum Modulation Cycle tSSCGCYCLE
-
220
-
µs
VSSCG=5 V
PGOOD
VOUT1
x 92 %
VOUT1
x 95 %
VOUT1
x 98 %
PGOOD Threshold Voltage 1
PGOOD Hysteresis Voltage 1
PGOOD Threshold Voltage 2
PGOOD Hysteresis Voltage 2
PGOOD Leakage Current
PGOOD ON Resistance
SCP/OVP
VPG1
VPGhys1
VPG2
V
V
VOUT Rising
VOUT1
x -5 %
-
-
VOUT Falling
VOUT1
VOUT1
VOUT1
V
VOUT Falling
x 102 % x 105 % x 108 %
VOUT1
VPGhys2
IPGLEAK
RPG
-
-
-
-
1
V
VOUT Rising
x +5 %
0
µA
Ω
VPGOOD=5 V, VOUT=5.0 V
IPGOOD=1 mA, VEN=0 V
250
500
VOUT1
VOUT1
VOUT1
OVP Detection Voltage
SCP Detection Voltage
BOOST
VOVP
VSCP
V
V
x 115 % x 120 % x 125 %
VOUT1
x 50 %
VOUT1
x 55 %
VOUT1
x 60 %
VIN Falling,
VOUT
VOUT
VOUT
Buck-Boost Threshold Voltage
Buck-Boost Hysteresis Voltage
CTLOUT ON Duty
VBOOST
VBOOSThys
DCTLOUT
V
V
CTLOUT Pin=Open
or CTLIN Pin(Note 3)
VIN Rising,
CTLOUT Pin=Open
or CTLIN Pin(Note 3)
VIN=6.5 V,
x 131 % x 140 % x 149 %
VOUT
-
-
x +10 %
70
66
74
%
CTLOUT Pin=Open
or CTLIN Pin(Note 3)
(Note 3) CTLIN is the pin of exclusive boost-FET.
(Note 4) This is design value. Not production tested.
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BD8P250MUF-C
Typical Performance Curves
(Unless otherwise specified VIN = VEN
)
20
20
18
16
14
12
10
8
VEN = 0V
18
16
14
12
10
8
+ 125 °C
+ 125 °C
+ 25 °C
+ 25 °C
6
6
4
4
2
2
- 40 °C
24
- 40 °C
18
0
0
0
6
12
18
30
36
0
6
12
24
30
36
Input Voltage : VIN[V]
Input Voltage : VIN[V]
Figure 4. Shutdown Circuit Current vs Input Voltage
Figure 5. Quiescent Current at No Load vs Input Voltage
5.10
2.00
VIN = 12V
VIN = 12V
5.08
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
1.75
1.50
1.25
1.00
0.75
0.50
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
Temperature[°C]
Temperature[°C]
Figure 6. Output Voltage vs Temperature
Figure 7. Soft Start Time vs Temperature
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Typical Performance Curves – continued
2.60
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
4.65
4.60
4.55
4.50
4.45
4.40
4.35
4.30
4.25
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
Temperature[°C]
Temperature[°C]
Figure 8. UVLO Detection Voltage vs Temperature
Figure 9. UVLO Release Voltage A vs Temperature
7.40
3.00
7.35
7.30
7.25
7.20
7.15
7.10
7.05
7.00
6.95
6.90
2.95
2.90
2.85
2.80
2.75
2.70
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
Temperature[°C]
Temperature[°C]
Figure 10. UVLO Release Voltage B vs Temperature
Figure 11. POR Detection Voltage vs Temperature
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Typical Performance Curves – continued
2.00
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VIN = 12V
1.80
High
1.60
1.40
1.20
+ 125 °C
Low
1.00
- 40 °C, + 25 °C
0.80
-50 -25
0
25
50
75 100 125
0
6
12
18
24
30
36
EN Voltage : VEN[V]
Temperature[°C]
Figure 12. EN/MODE/SSCG Threshold Voltage vs Temperature
Figure 13.EN Input Current vs EN Voltage
1.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VIN = 12V
0.9
VIN = 12V
0.8
0.7
0.6
0.5
0.4
0.3
+ 125 °C
+ 125 °C
- 40 °C, + 25 °C
- 40 °C, + 25 °C
0.2
0.1
0.0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SSCG Voltage : VSSCG[V]
MODE Voltage : VMODE[V]
Figure 14. MODE Input Current vs MODE Voltage
Figure 15. SSCG Input Current vs SSCG Voltage
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Typical Performance Curves – continued
220
220
200
180
160
140
120
100
80
VIN = 12V
200
VIN = 12V
180
160
140
120
100
80
60
60
40
40
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
Temperature[°C]
Temperature[°C]
Figure 16. High Side FET ON Resistance vs Temperature
Figure 17. Low Side FET ON Resistance vs Temperature
4.1
2.40
VIN = 12V
2.35
VIN = 12V
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
2.30
2.25
2.20
2.15
2.10
2.05
2.00
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
Temperature[°C]
Temperature[°C]
Figure 18.Switching Frequency vs Temperature
Figure 19. Over Current Protection vs Temperature
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Typical Performance Curves – continued
4.90
5.65
5.60
5.55
5.50
5.45
5.40
5.35
5.30
5.25
5.20
5.15
5.10
VIN = 12V
VIN = 12V
4.85
4.80
4.75
4.70
VOUT Rising
VOUT Rising
4.65
VOUT Falling
4.60
4.55
4.50
4.45
4.40
4.35
VOUT Falling
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
Temperature[°C]
Figure 20. PGOOD Threshold Voltage 1 vs Temperature
Temperature[°C]
Figure 21. PGOOD Threshold Voltage 2 vs Temperature
1.0
500
VIN = 12V
0.9
VIN = 12V, VEN = 0V
450
0.8
0.7
0.6
0.5
0.4
400
350
300
250
200
150
100
- 40 °C, + 25 °C
0.3
+ 125 °C
0.2
0.1
0.0
0
1
2
3
4
5
6
-50 -25
0
25
50
75 100 125
PGOOD Voltage : VPGOOD[V]
Temperature[°C]
Figure 22. PGOOD Leakage Current vs PGOOD Voltage
Figure 23. PGOOD ON Resistance vs Temperature
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Typical Performance Curves – continued
6.25
3.00
2.95
2.90
2.85
2.80
2.75
2.70
2.65
2.60
2.55
2.50
VIN = 12V
6.20
VIN = 12V
6.15
6.10
6.05
6.00
5.95
5.90
5.85
5.80
5.75
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
Temperature[°C]
Figure 24. OVP Detection Voltage vs Temperature
Temperature[°C]
Figure 25. SCP Detection Voltage vs Temperature
74
7.95
VIN = 6.5V
73
72
71
70
69
68
67
66
7.75
7.55
7.35
7.15
6.95
6.75
6.55
VIN Rising
VIN Falling
-50 -25
0
25
50
75 100 125
-50 -25
0
25
Temperature[°C]
Figure 26. Buck-Boost Threshold Voltage vs Temperature
50
75 100 125
Temperature[°C]
Figure 27. CTLOUT ON Duty vs Temperature
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Function Explanations
1. Quick Buck Booster®
Quick Buck Booster® is a buck-boost control technology to maintain a stable output voltage even when a significant
drop of the supply voltage occurs in a short period of time such as the startup profile of ISO16750-2. Quick Buck
Booster® controls the boost side switch in a fixed duty cycle to remove the Right-Half-Plane-Zero that may cause
problems in buck-boost operations, and can achieve the transfer characteristics equivalent to those in the buck
operation even in the buck-boost operation. This enables a facilitation of the phase compensation setting and a
reduction in the output capacitance. In addition, it realizes a smooth switching of operations by performing a pulse
width modulation with the buck side switch during both of the buck and buck-boost operations, enabling a high-speed
transient response to a steep variation in the power supply or the load.
(1) Frequency Characteristics
Since Quick Buck Booster® enables to remove the Right-Half-Plane-Zero, the phase compensation for the
buck-boost control will not involve the Right-Half-Plane-Zero.
Phase
Gain
Phase
Gain
Figure 28. Frequency Characteristics at Buck Control
(VIN = 12 V, IOUT = 0.4 A, L1 = 3.3 µH, COUT = 44 µF)
Figure 29. Frequency Characteristics at Buck-Boost Control
(VIN = 4 V, IOUT = 0.4 A, L1 = 3.3 µH, COUT = 44 µF)
(2) Quick Buck Booster® Operation Wave Form
A decrease in VIN voltage drives the boost side switch in a fixed duty cycle, starting the boost operation.
Correspondingly, the buck side duty cycle is automatically corrected to the optimum value to supply a stable output
voltage.
VIN (4 V/div)
VIN (4 V/div)
VSW (4 V/div)
VSW (4 V/div)
VSW2 (4 V/div)
VSW2 (4 V/div)
VOUT (2 V/div)
VOUT (2 V/div)
Time (1 µs/div)
Time (1 µs/div)
Figure 30. Change Wave Form
Figure 31.Change Wave Form
to Buck-Boost Control from Buck Control
to Buck Control from Buck-Boost Control
(VIN = Sweep Down, IOUT = 0.4 A, L1 = 3.3 µH, COUT = 44 µF)
(VIN = Sweep Up, IOUT = 0.4 A, L1 = 3.3 µH, COUT = 44 µF)
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Function Explanations – continued
2. Nano Pulse ControlTM
Nano Pulse ControlTM is an original technology developed by ROHM Co., Ltd. It enables to control voltage stably,
which is difficult in the conventional technology, even in a narrow SW ON time such as less than 50 ns at typical
condition.
3. Enable Control
The shutdown of the device can be controlled by the voltage applied to the EN pin. When EN pin voltage reaches 2.0
V or higher, VREG starts up and the device operates. However, there is a delay time of 0.5 ms (Typ) before the
beginning of the soft start. When EN pin voltage drops to 0.8 V or lower, the device is shut down.
VENH
VENH
2.0 V
2.0 V
VENL
0.8 V
VEN
VOUT
tDLY
tDLY
tSS
tSS
0.5 ms(Typ)
0.5 ms(Typ)
1.0 ms(Typ)
1.0 ms(Typ)
Figure 32. Enable ON/OFF Timing Chart
4. Power Good Function
When the VOUT pin voltage reaches a voltage within ±5 % (Typ), the open drain MOSFET of the PGOOD pin is turned
OFF and the output is switched to “High”. In addition, when the VOUT pin voltage varies beyond the ±10 % (Typ)
range, the open drain MOSFET of the PGOOD pin is turned ON and the PGOOD pin is pulled down with an
impedance of 250 Ω (Typ). Using a resistance of 10kΩ to 100kΩ, pull it up to the VREG pin or the power supply.
VPGhys2
VPG2
+5 %(Typ)
105 %(Typ)
VOUT
VPGhys1
-5 %(Typ)
VPG1
95 %(Typ)
VPGOOD
Figure 33. PGOOD Timing Chart
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Function Explanations – continued
5. Under Voltage Lockout Protection (UVLO/POR)
The input under voltage lockout protection circuit monitors the voltage of the VIN and VREG pins. UVLO and POR
monitor the VIN and VREG voltages, respectively. The device is shut down when either of them is detected, and
started up with the soft start when both are released. When an exclusive boost-FET is not used, VREG at 2.85 V(Typ)
or lower brings the device to the standby state, and VIN at 4.45 V(Typ) or higher prompts the startup operation. When
an exclusive boost-FET is used, VIN at 2.4 V(Typ) or lower brings the device to the standby state, and VIN at 7.15 V
(Typ) or higher prompts the startup operation.
VUVLOHA
4.45 V(Typ)
VIN
VUVLOL
2.4 V(Typ)
VPORH
3.0 V(Typ)
VPORL
2.85 V(Typ)
VREG
UVLO
POR
VOUT
tDLY
tSS
0.5 ms(Typ) 1.0 ms(Typ)
Figure 34. UVLO/POR Timing Chart (Not Use Exclusive Boost-FET)
VUVLOHB
7.15 V(Typ)
VIN
VUVLOL
2.4 V(Typ)
VPORH
3.0 V(Typ)
VPORL
2.85 V(Typ)
VREG
UVLO
POR
VOUT
tDLY
tSS
0.5 ms(Typ) 1.0 ms(Typ)
Figure 35. UVLO/POR Timing Chart (Use Exclusive Boost-FET)
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Function Explanations – continued
6. LLM control and Forced PWM control
Under a heavy load, the switching operation is performed with the Pulse Width Modulation (PWM) control at a fixed
frequency. When the load is lighter, the operation is changed over to the Light Load Mode (LLM) control to improve the
efficiency. However, the operation is forced into the PWM control when the MODE pin is “High” (2.0 V or higher),
during the startup, or during the buck-boost operation. Although the efficiency under a light load is reduced under the
forced PWM control compared with the LLM control, the operation is performed in the continuous current mode at a
fixed frequency over the entire load range, enabling reduction in the output ripple voltage.
LLM Control
Forced PWM Control
Output Current IOUT[A]
Figure 36. Efficiency (LLM Control and Forced PWM Control)
VOUT (50 mV/div)
offset 5 V
VOUT (50 mV/div)
offset 5 V
Time (2 µs/div)
VSW (5 V/div)
VSW (5 V/div)
Figure 37. SW Waveform(LLM)
(VIN = 12 V, IOUT = 50 mA)
Figure 38. SW Waveform(PWM)
(VIN = 12 V, IOUT = 1 A)
For BD8P250MUF-C, the operation is changed over to the LLM control when the load current decreases to 0.4 A (Typ)
or lower. Under the LLM control, the switching is stopped when the output voltage rises to 102 % (Typ) or higher. While
the switching is stopped, the circuit current is reduced by stopping the circuits other than the output voltage monitor.
When the load current decreases the output voltage to 101 % (Typ) of the specified voltage or lower, the switching
resumes. Depending on the conditions, since the output ripple voltage may fall within the audible range in operations
under the LLM control, use the device under the forced PWM control if it is necessary to avoid the audible range.
VEN
VOUT1×102 % (Typ)
VOUT1×101 % (Typ)
VOUT1 5.0 V(Typ)
VOUT
0.4 A
(Typ)
Inductor
Current
0.4 A
IOUT
Figure 39. LLM Control Timing Chart
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Function Explanations – continued
7. Frequency Division Function
BD8P250MUF-C drives the high side FET with a bootstrap and requires the ON time of the low side FET to charge
the BOOT pin. Therefore, the minimum OFF time of the SW pin is specified, and the output voltage is limited by the
minimum OFF time under the condition in which the input and output voltages are close. The prevent this situation,
OFF pulses are skipped when the input and output voltages are small to keep the high side FET turned ON and
increase the ON duty of the SW pin. Three consecutive OFF pulses are skipped at a maximum. In this case, the
output voltage can be calculated with the following equation.
(
)
푉푂푈푇 = 푀푎푥퐷푢푡푦 × 푉 − 푅푂푁퐻 × ꢀ푂푈푇 − 푅ꢁ퐶 × ꢀ푂푈푇
퐼푁
푓
푆푊
( )
ꢃ × 푉 − 푅푂푁퐻 × ꢀ푂푈푇 − 푅ꢁ퐶 × ꢀ푂푈푇 [V]
퐼푁
= ꢂ1 − 푡푂퐹퐹
×
4
푀푎푥퐷푢푡푦
푉
퐼푁
is the SW pin Maximum ON Duty [%]
is the Input Voltage [V]
푅푂푁퐻
ꢀ푂푈푇
푅ꢁ퐶
푡푂퐹퐹
ꢄ
ꢅꢆ
is the High Side FET ON Resistance (Refer to Page.8) [Ω]
is the Output Current [A]
is the DCR of Inductor [Ω]
is the SW pin Minimum OFF Time [s] (Typ : 100 ns)
is the Switching Frequency (Refer to Page.8) [Hz]
VIN
VOUT
VSW
Figure 40. Frequency Division Function
8. Buck-Boost Control
When BD8P250MUF-C is used with BD90302NUF-C, an exclusive boost-FET, a drop of the output voltage can be
prevented by the buck-boost operation even when the input voltage is decreased due to a cold cranking, etc. The
buck operation is performed if the input voltage is 140 %(Typ) of the output voltage or higher. If not, the buck-boost
operation is performed. During the buck-boost operation, an ON pulse at 70 %(Typ) duty is outputted from the
CTLOUT pin to control the exclusive boost-FET. The buck operation is restored with a hysteresis of 10 %(Typ) or
when the PGOOD output is changed over to “Low”. In addition, the maximum output current is 2.0 A and 0.8 A during
the buck and buck-boost operations, respectively.
VIN
VBOOSThys
VBOOST
+10 %(Typ)
VOUT×140 ％（Typ)
VOUT
100 %
VSW
ON Duty
0 %
100 %
VCTLOUT
DCTLOUT
70 %(Typ)
ON Duty
0 %
Figure 41. Buck-Boost Control
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Function Explanations – continued
9. Spread Spectrum Function
Connecting the SSCG pin with VREG pin activates the Spread Spectrum function, reducing the EMI noise level.
When the Spread Spectrum function is activated, the switching frequency alternates between 2.2 MHz(Typ) and its
+10 %(Typ) with a ramp. The period of the ramp is 220 µs(Typ). However, this function is masked when the PGOOD
output is “Low” or during the buck-boost operation. This function is disabled when the SSCG pin is connected with the
ground.
VSSCG
VEN
VPG1
95 %(Typ)
VOUT
tSSCGCYCLE
220 µs(Typ)
fSSCG
+10 %(Typ)
fSW
2.2 MHz(Typ)
fSW
tDLY
0.5 ms(Typ)
VPGOOD
SSCG State
SSCG OFF
Figure 42. Spread Spectrum Function Timing Chart
SSCG ON
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Protection
1. Over Current Protection (OCP)
The over current protection (OCP) function is realized through the detection of the inductor current. The over current limit
is designed to be 3.6 A(Typ). The output voltage is decreased when the OCP detection occurs. It should be noted that the
OCP detection current for the output current is decreased during the buck-boost operation.
IOCP
3.6 A(Typ)
Inductor
Current
IOUT
VOUT
Figure 43. Over Current Protection
2. Short Circuit Protection (SCP)
The short circuit protection (SCP) function compares the VOUT pin voltage with the internal reference voltage and turns
OFF the output stage MOSFET for 15.4 ms(Typ) if it detects the VOUT pin voltage to be 55 %(Typ) or lower for 0.1 ms
(Typ) or longer. Then, a restart is performed with the soft start. The SCP function is masked for 1.4 ms(Typ) after the soft
start. The input voltage required for the restoration is the same as that for the startup.
VOUT
VSCP
55 %(Typ)
15.4 ms (Typ)
1.4 ms (Typ)
Under 0.1 ms
(Typ)
0.1 ms
(Typ)
SCP Mask
VSW
HiZ
Switching
Switching
Figure 44. SCP Timing Chart (Short Circuit Devision)
Output Load
Condition
Normal
Normal
Over Load
IOCP
3.6 A(Typ)
IOUT
VOUT
VSCP
55 %(Typ)
1.4 ms
(Typ)
1.4 ms
(Typ)
0.1 ms
(Typ)
15.4 ms
(Typ)
15.4 ms
(Typ)
0.1 ms
(Typ)
0.1 ms
(Typ)
VSW
Switching
Switching
HiZ
HiZ
HiZ
Switching
Switching
Figure 45. SCP Tinimg Chart (Self Return)
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Protection – continued
3. Thermal shutdown (TSD)
The device is shutdown when the chip temperature exceeds Tj = 175 °C (Typ). The thermal cutoff circuit is exclusively for
the purpose of cutting off the device from a thermal runaway under an abnormal condition exceeding Tjmax = 150 °C. It is
not intended for the protection or guarantee of the set. Therefore, do not design a set protection utilizing the function of this
circuit. The input voltage required for the restoration is the same as that for the startup. A restart is performed with the soft
start.
VIN
VEN
VPORH
3.0 V(Typ)
VREG
TSD Detect
175 ℃ (Typ)
TSD Releace
150 ℃ (Typ)
Tj
VOUT
tDLY tSS
0.5 ms(Typ) 1.0 ms(Typ)
Figure 46. TSD Timing Chart
4. Over Voltage Protection (OVP)
The over voltage protection (OVP) function compares the VOUT pin voltage with the internal reference voltage and turns
OFF the output stage MOSFET if the VOUT pin voltage exceeds 120 % (Typ) of the internal reference voltage for 1 μs
(Typ) or longer. It is restored when VOUT pin voltage falls below the threshold for 7 μs (Typ) or longer.
VOVP
120 %(Typ)
VOUT
VSW
HiZ
Switching
Switching
1 µs (Typ)
Figure 47. OVP Timing Chart
7 µs (Typ)
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BD8P250MUF-C
Selection of Components Externally Connected
Contact us if not use the recommended constant in this section.
The figure below is the application sample circuit.
BD8P250MUF-C
CBOOT
LF1
VBAT
VIN
BOOT
L1
VOUT
SW
PVIN
EN
ROUT
VOUT
VCC_EX
CF1
CBLK
CIN2
CIN1
VMODE
RCTL
MODE
SSCG
COUT2
COUT1
CTLOUT
PGOOD
VREG
RPGOOD
GND PGND
CREG
Figure 48. Application Sample Circuit 1
BD8P250MUF-C
CBOOT
LF1
VBAT
VIN
BOOT
BD90302NUF-C
L1
VOUT
SW2 PVOUT
SW
PVIN
EN
VOUT
CTLIN
PGND
VCC_EX
CF1
CBLK
CIN2
CIN1
VMODE
MODE
SSCG
COUT2
COUT1
CTLOUT
PGOOD
VREG
ROUT
RPGOOD
GND PGND
CREG
Figure 49. Application Sample Circuit 2
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Selection of Components Externally Connected - continued
1. Selection of the inductor L1 value
Role of the inductor in the switching regulator is that it also serves as a filter for smoothing the output voltage to supply a
continuous current to the load. The Inductor ripple current ΔIL that flows to the inductor becomes small when an inductor
with a large inductance value is selected. Consequently, the voltage of the output ripple ΔVP-P also becomes small. It is
the trade-off between the size and the cost of the inductor.
The inductance of the inductor is shown in the following equation:
(ꢇ
ꢍꢇ
)×ꢇ
ꢎꢏꢐ ꢎꢏꢐ
ꢈꢉ(ꢊꢋꢌ)
퐿 =
[H]
ꢇ
×푓 ×∆퐼
푆푊 ꢑ
ꢈꢉ(ꢊꢋꢌ)
Where:
푉
is the maximum input voltage
퐼푁 (ꢒꢓꢔ)
푉푂푈푇
is the output voltage
ꢄ
훥ꢀꢕ
is the switching frequency
is the peak to peak inductor current
ꢅꢆ
In current mode control, sub-harmonic oscillation may happen. The slope compensation circuit is integrated into the IC
in order to prevent sub-harmonic oscillation. The sub-harmonic oscillation depends on the rate of increase of output
switch current. If the inductor value is too small, the sub-harmonic oscillation may happen because the inductor ripple
current ΔIL is increased. And if the inductor value is too large, the feedback loop may not achieve stability because the
inductor ripple current ΔIL is decreased. Therefore, use an inductor value of the inductor within the range of 2.2 µH to 10
µH.
The smaller the ΔIL, the smaller the Inductor core loss (iron loss), and the smaller is the loss due to ESR of the output
capacitor. In effect, ΔVP-P (Output peak-to-peak ripple voltage) will be reduced. ΔVP-P is shown in the following equation.
∆퐼
ꢑ
∆푉
= ∆ꢀꢕ × 퐸ꢖ푅 + 8×퐶
[V]
(a)
푃ꢍ푃
×푓
ꢎꢏꢐ
푆푊
Where:
퐸ꢖ푅
ꢗ푂푈푇
훥ꢀꢕ
is the equivalent series resistance of the output capacitor
is the output capacitance
is the peak to peak inductor current
is the switching frequency
ꢄ
ꢅꢆ
Generally, even if ΔIL is somewhat large, the ΔVP-P target is satisfied because the ceramic capacitor has a very-low ESR.
It also contributes to the miniaturization of the application board. Also, because of the lower rated current, smaller
inductor is possible since the inductance is small. The disadvantages are increase in core losses in the inductor and the
decrease in maximum output current. When other capacitors (electrolytic capacitor, tantalum capacitor, and electro
conductive polymer etc.) are used for output capacitor COUT, check the ESR from the manufacturer's data sheet and
determine the ΔIL to fit within the acceptable range of ΔVP-P. Especially in the case of electrolytic capacitor, because the
decrease in capacitance at low temperatures is significantly large, this will make ΔVP-P increase. When using capacitor
at low temperature, this is an important consideration.
The shielded type (closed magnetic circuit type) is the recommended type of inductor to be used. Please note that
magnetic saturation may occur. It is important not to saturate the core in all cases. Precautions must be taken into
account on the given provisions of the current rating because it differs on every manufacturer. Please confirm the rated
current at maximum ambient temperature of application to the manufacturer.
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Selection of Components Externally Connected - continued
2. Selection of Output Capacitor COUT
The output capacitor is selected based on the ESR that is required from the equation (a). ΔVP-P can be reduced by using
a capacitor with a small ESR. The ceramic capacitor is the best option that meets this requirement. It is because not
only does it has a small ESR but the ceramic capacitor also contributes to the size reduction of the application circuit.
Please confirm the frequency characteristics of ESR from the datasheet of the manufacturer, and consider a low ESR
value for the switching frequency being used. It is necessary to consider the ceramic capacitor because the DC biasing
characteristic is important. For the voltage rating of the ceramic capacitor, twice or more than the maximum output
voltage is usually required. By selecting a high voltage rating, it is possible to reduce the influence of DC bias
characteristics. Moreover, in order to maintain good temperature characteristics, the one with the characteristics of X7R
or better is recommended. Because the voltage rating of a large ceramic capacitor is low, the selection becomes difficult
for an application with high output voltage. In that case, please connect multiple ceramic capacitors in series or select
electrolytic capacitor. Consider having a voltage rating of 1.2 times or more of the output voltage when using electrolytic
capacitor. Electrolytic capacitors have a high voltage rating, large capacitance, small amount of DC biasing
characteristics, and are generally reasonable. Since the electrolytic capacitor is usually OPEN when it fails, it is effective
to use for applications when reliability is required such as automotive. But there are disadvantages such as, ESR is
relatively high, and decreases capacitance value at low temperatures. In this case, please take note that ΔVP-P may
increase at low temperature conditions. Moreover, consider the lifetime characteristic of this capacitor because it has a
possibility to dry up. A tantalum capacitor and a conductive polymer hybrid capacitor have excellent temperature
characteristics unlike the electrolytic capacitor. Moreover, since their ESR is smaller than an electrolytic capacitor, the
ripple voltage is relatively-small over a wide temperature range. Since these capacitors have almost no DC bias
characteristics, design will be easier. Regarding voltage rating, the tantalum capacitor is selected such that its
capacitance is twice the value of the output voltage, and for the conductive polymer hybrid capacitor, it is selected such
that the voltage rating is 1.2 times the value of the output voltage. The disadvantage of a tantalum capacitor is that it is
SHORTED when it is destroyed, and its breakdown voltage is low. It is not generally selected in an application that
reliability is a demand such as in automotive. An electro conductive polymer hybrid capacitor is OPEN when destroyed.
Though it is effective for reliability, its disadvantage is that it is generally expensive.
To improve the performance of ripple voltage in this condition, following is recommended:
1. Use low ESR capacitor like ceramic or conductive polymer hybrid capacitor.
2. Use a capacitor COUT with a higher capacitance value.
These capacitors are rated in ripple current. The RMS values of the ripple current that can be obtained in the following
equation must not exceed the ripple current rating.
∆퐼
ꢑ
ꢀ퐶푂(ꢘꢒꢅ)
=
[A]
ꢙ2
√
Where:
ꢀ퐶푂(ꢘꢒꢅ) is the value of the ripple electric current
is the peak to peak inductor current
∆ꢀꢕ
In addition, for the total value of capacitance in the output line COUT(Max), choose a capacitance value less than the
value obtained by the following equation:
ꢚ
×(퐼
ꢍ퐼
푆푊(ꢊ푖푛)
)
)
푆푊푆ꢐ퐴ꢛꢐ ꢊꢋꢌ
(
푆푆(ꢊ푖푛)
ꢗ푂푈푇(ꢒꢓꢔ)
<
[F]
ꢇ
ꢎꢏꢐ
Where:
ꢀꢅꢆ(ꢒꢜꢝ)
푡ꢅꢅ(ꢒꢜꢝ)
ꢀꢅꢆꢅ푇ꢞꢘ푇(ꢒꢓꢔ)
푉푂푈푇
is the OCP operation switch current (Min)
is the Soft Start Time (Min)
is the maximum output current during startup
is the output voltage
Startup failure may happen if the limits from the above-mentioned are exceeded. Especially if the capacitance value is
extremely large, over-current protection may be activated by the inrush current at startup preventing the output to turn
on. Please confirm this on the actual application. For stable transient response, the loop is dependent to COUT. Please
select after confirming the setting of the phase compensation circuit.
Also, in case of large changing input voltage and load current, select the capacitance accordingly by verifying that the
actual application setup meets the required specification.
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Selection of Components Externally Connected - continued
3. Selection of Input Capacitor CIN, CBLK
The input capacitor is usually required for two types of decoupling: capacitors CIN and bulk capacitors CBLK
For the decoupling capacitors, two ceramic capacitors are required: CIN1 with a small capacitance and CIN2 with a large
capacitance. CIN1 and CIN2 can reduce the switching noise and ripple noise, respectively. The effects of these ceramic
capacitors are obtained by placing them as close as possible to the PVIN and VIN pins. For CIN2, it is recommended to
use a capacitor with the capacitance value of 2.3 µF or more, also, with the voltage rating that is 1.2 times or more of the
maximum input voltage and 2 times or more of the normal input voltage.
.
The capacitor value including device variation, temperature change, DC bias change, and aging change must be larger
than minimum value. Also, the IC might not operate properly when the PCB layout or the position of the capacitor is not
good. Please check “Notes on the PCB Layout Design” on page 34, 35.
The bulk capacitor is optional. The bulk capacitor prevents the decrease in the line voltage and serves as a backup
power supply to keep the input voltage constant. A low ESR electrolytic capacitor with large capacitance is suitable for
the bulk capacitor. It is necessary to select the best capacitance value for each set of application. In that case, please
take note not to exceed the rated ripple current of the capacitor.
The RMS value of the input ripple current ICIN(RMS) is obtained in the following equation:
ꢇ
×(ꢇ ꢍꢇ
)
ꢎꢏꢐ
ꢟ
ꢎꢏꢐ
ꢈꢉ
ꢀ퐶퐼푁(ꢘꢒꢅ) = ꢀ푂푈푇(ꢒꢞ푋)
×
[A]
ꢇ
ꢈꢉ
Where:
ꢀ푂푈푇(ꢒꢞ푋) is the maximum output current.
In addition, in automotive and other applications requiring high reliability, it is recommended to connect the capacitors in
parallel to accommodate multiple electrolytic capacitors and minimize the chances of drying up. For ceramic capacitors,
it is recommended to make two series + two parallel structures to decrease the risk of capacitor destruction due to short
circuit conditions.
When the impedance on the input side is high for some reason (because the wiring from the power supply to VIN is long,
etc.), then high capacitance is needed. In actual conditions, it is necessary to verify that there are no problems like IC
turns off, or the output overshoots due to the change in VIN at transient response.
4. Selection of the Bootstrap Capacitor
Bootstrap capacitor CBOOT value shall be 0.1 μF. Connect the bootstrap capacitor between SW pin and BOOT pin.
Recommended products are described in Application Examples1 on page 27.
5. Selection of the VREG Capacitor.
VREG capacitor CREG shall be 1.0 μF(Typ) ceramic capacitor. Connect the VREG capacitor between VREG pin and
GND. Recommended products are described in Application Examples1 on page 27.
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Application Examples 1
Table1. Specification Example 1
Parameter
Product Name
Symbol
IC
Specification Case
BD8P250MUF-C
8 V to 18 V
Input Voltage
VIN
Output Voltage
VOUT
IOUT
fSW
5.0 V
Output Current
Typ 1.0 A / Max 1.5 A
2.2 MHz
Switching Frequency
Operation Temperature
Ta
-40°C to +105 °C
BD8P250MUF-C
CBOOT
LF1
VBAT
VIN
BOOT
L1
VOUT
SW
PVIN
EN
ROUT
VOUT
VCC_EX
CF1
CBLK
CIN2
CIN1
VMODE
RCTL
MODE
SSCG
COUT2
COUT1
CTLOUT
PGOOD
VREG
RPGOOD
GND PGND
CREG
Figure 50. Reference Circuit 1
Table 2. Parts List 1
No Package
Parameters
Part Name (Series)
Type
Manufacturer
NICHICON
Electrolytic
capacitor
CBLK
φ10 mm×L10 mm
220 μF, 50 V
UCD1H221MNL1GS
CIN1
CIN2
1005
0.1 μF, X7R, 50 V
4.7 μF, X7R, 50 V
0.1 μF, X7R, 50 V
1.0 μF, X7R, 16 V
Short
GCM155R71H104K
GCM32ER71H475K
GCM155R71H104K
GCM188R71C105K
-
Ceramic
Ceramic
Ceramic
Ceramic
-
MURATA
MURATA
MURATA
MURATA
-
3225
CBOOT
CREG
ROUT
RCTL
RPGOOD
L1
1005
1608
-
1005
1 kΩ, 1 %, 1/16 W
100 kΩ, 1 %, 1/16 W
3.3 μH
MCR01MZPF1001
MCR01MZPF1003
CLF6045NIT-3R3N-D
GCM32ER11A226K
GCM32ER11A226K
GCM32ER71H475K
CLF6045NIT-2R2N-D
Chip resistor
Chip resistor
Inductor
Ceramic
Ceramic
Ceramic
Inductor
ROHM
ROHM
TDK
1005
W6.0×H4.5×L6.3 mm3
3225
COUT1
COUT2
CF1
22 μF, R, 10 V
22 μF, R, 10 V
4.7 μF, X7R, 50 V
2.2 μH
MURATA
MURATA
MURATA
TDK
3225
3225
LF1
W6.0×H4.5×L6.3 mm3
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Application Examples 1 – continued
（VIN = VEN, Ta = 25°C）
100
90
80
VMODE = 0 V
Phase
Gain
70
60
50
40
30
VMODE = 5 V
20
10
0
0.01
0.1
1
10
100
1000
Output Current [mA]
Figure 51. Efficiency vs Output Current
(VIN = 12 V)
Figure 52. Frequency Characteristic
(VIN = 12 V, IOUT = 1 A)
VMODE (5 V/div)
VSW (10 V/div)
VOUT (20 mV/div, AC)
VOUT (200 mV/div)
offset 5 V
Time (500 ns/div)
Time (100 µs/div)
Figure 53. Output Ripple Voltage
(VIN = 12 V, IOUT = 1 A)
Figure 54. MODE ON/OFF Response
(VIN = 12 V, IOUT = 50 mA)
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Application Examples 1 – continued
（VIN = VEN, Ta = 25°C）
VOUT (200 mV/div)
offset 5 V
VOUT (200 mV/div)
offset 5 V
IOUT (1 A/div)
IOUT (1 A/div)
Inductor Current (1 A/div)
Inductor Current(1A/div)
Time (500 µs/div)
Time (500 µs/div)
Figure 55. Load Response 1
Figure 56. Load Response 2
(VIN = 12 V, VMODE = 5 V, IOUT = 0 A to 1.5 A)
(VIN = 12 V, VMODE = 0 V, IOUT = 0 A to 1.5 A)
VIN (5 V/div)
VIN (10 V/div)
VOUT (200 mV/div)
VOUT (200 mV/div)
offset 5 V
offset 5 V
Time (200 µs/div)
Time (200 µs/div)
Figure 57. Line Response 1
(VIN = 12 V to 6 V, IOUT = 1 A)
Figure 58. Line Response 2
(VIN = 12 V to 36 V, IOUT = 1 A)
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BD8P250MUF-C
Application Examples 2
Table 3. Specification Example 2
Parameter
Product Name 1
Symbol
IC1
Specification Case
BD8P250MUF-C
BD90302NUF-C
4 V to 18 V
Product Name 2
Input Voltage
IC2
VIN
Output Voltage
VOUT
IOUT
fSW
5.0 V
Output Current
Typ 0.4 A / Max 0.6 A
2.2 MHz
Switching Frequency
Operation Temperature
Ta
-40 °C to +105 °C
BD8P250MUF-C
CBOOT
LF1
VBAT
VIN
BOOT
BD90302NUF-C
L1
VOUT
SW2 PVOUT
SW
PVIN
EN
VOUT
CTLIN
PGND
VCC_EX
CF1
CBLK
CIN2
CIN1
VMODE
MODE
SSCG
COUT2
COUT1
CTLOUT
PGOOD
VREG
ROUT
RPGOOD
GND PGND
CREG
Figure 59. Reference Circuit 2
Table 4. Parts List 2
No
Package
Parameters
Part Name (Series)
Type
Manufacturer
NICHICON
Electrolytic
capacitor
CBLK
φ10 mm×L10 mm
220 μF, 50 V
UCD1H221MNL1GS
CIN1
CIN2
1005
0.1 μF, X7R, 50 V
4.7 μF, X7R, 50 V
0.1 μF, X7R, 50 V
1.0 μF, X7R, 16 V
Short
GCM155R71H104K
GCM32ER71H475K
GCM155R71H104K
GCM188R71C105K
-
Ceramic
Ceramic
Ceramic
Ceramic
-
MURATA
MURATA
MURATA
MURATA
-
3225
CBOOT
CREG
ROUT
RPGOOD
L1
1005
1608
-
1005
W6.0×H4.5×L6.3 mm3
3225
100 kΩ, 1 %, 1/16 W
3.3 μH
MCR01MZPF1003
CLF6045NIT-3R3N-D
GCM32ER11A226K
GCM32ER11A226K
GCM32ER71H475K
CLF6045NIT-2R2N-D
Chip resistor
Inductor
Ceramic
Ceramic
Ceramic
Inductor
ROHM
TDK
COUT1
COUT2
CF1
22 μF, R, 10 V
22 μF, R, 10 V
4.7 μF, X7R, 50 V
2.2 μH
MURATA
MURATA
MURATA
TDK
3225
3225
LF1
W6.0×H4.5×L6.3 mm3
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Application Examples 2 – continued
（VIN = VEN, Ta = 25°C）
100
90
80
70
Phase
Gain
VMODE = 0 V
60
50
40
30
VMODE = 5 V
20
10
0
0.01
0.1
1
10
100
1000
Output Current [mA]
Figure 60. Efficiency vs Output Current
(VIN = 12 V)
Figure 61. Frequency characteristic
(VIN = 4 V, IOUT = 0.4 A)
VMODE (5 V/div)
VSW (10 V/div)
VOUT (20 mV/div, AC)
VOUT (200 mV/div)
offset 5 V
Time (500 ns/div)
Time (100 µs/div)
Figure 62. Output Ripple Voltage
(VIN = 4 V, IOUT = 0.4 A)
Figure 63. MODE ON/OFF Response
(VIN = 12 V, IOUT = 50 mA)
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Application Examples 2 – continued
（VIN = VEN, Ta = 25°C）
VOUT (200 mV/div)
offset 5 V
VOUT (200 mV/div)
offset 5 V
IOUT (1 A/div)
IOUT (1 A/div)
Inductor Current (1 A/div)
Time (500 µs/div)
Time (500 µs/div)
Inductor Current (1 A/div)
Figure 64. Load Response 1
(VIN = 12 V, VMODE = 5 V, IOUT = 0 A to 1.5 A)
Figure 65. Load Response 2
(VIN = 4 V, IOUT = 0 A to 0.6 A)
VIN (5 V/div)
VIN(10 V/div)
VOUT(200mV/div)
offset 5 V
V (200 mV/div)
OUT
offset 5 V
Time (200 µs/div)
Inductor Current (1 A/div)
Time (200 µs/div)
Figure 66. Line Response 1
(VIN = 12 V to 4 V, IOUT = 0.4 A)
Figure 67. Line Response 2
(VIN = 12 V to 36 V, IOUT = 1 A)
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BD8P250MUF-C
Automotive Power Supply Line Circuit
Reverse-Touching
Protection Diode
BATTERY
LINE
D
VIN
BD8P250MUF-C
L
C
C
TVS
π-type filter
Figure 68. Automotive Power Supply Line Circuit
As a reference, the automotive power supply line circuit example is given in Figure 68.
π-type filter is a third-order LC filter. In general, it is used in combination with decoupling capacitors for high frequency. Large
attenuation characteristics can be obtained and thus excellent characteristic as a EMI filter. Devices used for π-type filters
should be placed close to each other.
TVS (Transient Voltage Suppressors) is used for primary protection of the automotive power supply line. Since it is
necessary to withstand high energy of load dump surge, a general zener diode is insufficient. Recommended device is
shown in the following table.
In addition, a reverse polarity protection diode is needed considering if a power supply such as BATTERY is accidentally
connected in the opposite direction.
Table 5. Reference Parts of Automotive Power Supply Line Circuit
Device
Part name (series)
CLF series
Manufacturer
TDK
Device
TVS
D
Part name (series)
SMB series
Manufacturer
Vishay
L
L
XAL series
Coilcraft
S3A to S3M series
Vishay
C
CJ series / CZ series
NICHICON
Recommended Parts Manufacturer List
Shown below is the list of the recommended parts manufacturers for reference.
Type
Electrolytic Capacitor
Ceramic Capacitor
Hybrid Capacitor
Inductor
Manufacturer
NICHICON
Murata
URL
www.nichicon.co.jp
www.murata.com
www.sunelec.co.jp
product.tdk.com
www.coilcraft.com
www.sumida.com
www.vishay.com
www.rohm.com
Suncon
TDK
Inductor
Coilcraft
SUMIDA
Vishay
Inductor
Diode
Diode/Resistor
ROHM
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PCB Layout Design
PCB layout design for DC/DC converter power supply IC is as important as the circuit design. Appropriate layout can avoid
various problems caused by power supply circuit. Figure 69-a to 69-c figure show the current path in a buck converter circuit.
The Loop 1 in Figure 69-a is a current path when H-side switch is ON and L-side switch is OFF, the Loop 2 in Figure 69-b is
when H-side switch is OFF and L-side switch is ON. The thick line in Figure 69-c shows the difference between Loop1 and
Loop2. The current in thick line change sharply each time the switching element H-side and L-side switch change from OFF
to ON, and vice versa. These sharp changes induce several harmonics in the waveform. Therefore, the loop area of thick
line that is consisted by input capacitor and IC should be as small as possible to minimize noise. For more detail refer to
application note of switching regulator series “PCB Layout Techniques of Buck Converter”.
Loop1
VIN
VOUT
L
H-side switch
CIN
COUT
L-side switch
GND
GND
Figure 69-a. Current path when H-side switch = ON, L-side switch = OFF
VIN
VOUT
L
H-side switch
CIN
COUT
Loop2
L-side switch
GND
GND
Figure 69-b. Current path when H-side switch = OFF, L-side switch = ON
VIN
VOUT
L
H-side FET
CIN
COUT
L-side FET
GND
GND
Figure 69-c. Difference of current and critical area in layout
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PCB Layout Design – continued
When designing the PCB layout, please pay extra attention to the following points.
1. Place the input decoupling capacitors of 4.7 µF (CIN2) for the VIN pin (2-pin) and 0.1 µF (CIN1) for the PVIN pin (3-, 4-,
and 5-pin) so that the distance of the route between the PVIN and PGND (7-, 8-pin) pins is as short as possible. The
reduction in high-frequency noise is more effective when the capacitor with the smaller capacitance of 0.1 µF (CIN1) is
placed closer to the PVIN pin than the capacitor of 4.7 µF (CIN2).
2. Place the IC, input capacitor, output inductor, and output capacitor on the same surface layer of the board, and
connect the parts on the same layer.
3. Place the ground plane on the layer nearest to the surface layer on which the IC is placed.
4. The GND pin (22-pin) is the reference ground and the PGND pin is the power ground. These pins may be connected
via the back surface of the IC. However, since the power ground on the input capacitor side contains the noise
component of the switching frequency, it is recommended to separate the power ground from the adjacent reference
ground pattern. Connect the separated power ground to the ground plane using as many vias as possible.
5. Place the bypass capacitor between the VREG (23-pin) and GND pins at a position as close as possible to the pin.
6. Place the capacitors connected between the SW pin (12-, 13-, and 14-pin) and the BOOT (15-pin) at positions as
close as possible to each pin.
7. To minimize the radiated noise from the switching node, keep the distance from the SW pin to the inductor short, and
do not extend the area of copper foil pattern more than necessary.
8. Place the output capacitor near the inductor and the power ground.
9. Place the wire for the feedback line from the output away from the inductor and the switching node. If the wire is
affected by the external noise, an error can occur in the output voltage or the operation can be destabilized. Therefore,
move the feedback line to the back surface through a via, and connect the line to the VOUT pin (20-pin).
10. ROUT (optional) is for measuring the frequency characteristics of the feedback. By inserting a resistor in ROUT, the
frequency characteristics (phase margin) of the feedback can be measured. ROUT should be short-circuited for the
normal use.
Reference Ground
Reference Ground
Power Ground
Power Ground
Figure 70. Evaluation Board Layout Example
(Buck DC/DC Converter)
Figure 71. Evaluation Board Layout Example
(Buck-Boost DC/DC Converter)
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BD8P250MUF-C
Power Dissipation
For thermal design, be sure to operate the IC within the following conditions.
(Since the temperatures described hereunder are all guaranteed temperatures, take margin into account.)
1. The ambient temperature Ta is to be 125 °C or less.
2. The chip junction temperature Tj is to be 150 °C or less.
The chip junction temperature Tj can be considered in the following two patterns:
1. To obtain Tj from the package surface center temperature Tt in actual use
ꢠ푗 = ꢠ푡 + 휓퐽푇 × ꢡ [°C]
2. To obtain Tj from the ambient temperature Ta
ꢠ푗 = ꢠ푎 + 휃퐽ꢞ × ꢡ [°C]
Where:
휓퐽푇
휃퐽ꢞ
is junction to top characterization parameter (Refer to page 6)
is junction to ambient (Refer to page 6)
The heat loss W of the IC can be obtained by the formula shown below:
푉푂푈푇
푉푂푈푇
2
ꢡ = 푅푂푁퐻 × ꢀ푂푈푇
×
+ 푅푂푁ꢕ × ꢀ푂푈푇2 ꢢ1 −
ꢣ
푉
푉
퐼푁
퐼푁
ꢙ
(
)
+푉 × ꢀ퐶퐶 + × 푡푟 + 푡ꢄ × 푉 × ꢀ푂푈푇 × ꢄ
[W]
퐼푁
퐼푁
ꢅꢆ
2
Where:
푅푂푁퐻
푅푂푁ꢕ
ꢀ푂푈푇
is the High Side FET ON Resistance (Refer to page 8) [Ω]
is the Low Side FET ON Resistance (Refer to page 8) [Ω]
is the Load Current [A]
푉푂푈푇
is the Output Voltage [V]
푉
퐼푁
is the Input Voltage [V]
ꢀ퐶퐶
푡푟
푡ꢄ
is the Circuit Current [A] (Typ : 50 µA)
is the Switching Rise Time [s] (Typ : 5 ns)
is the Switching Fall Time [s] (Typ : 5 ns)
is the Switching Frequency (Refer to page 8) [Hz]
ꢄ
ꢅꢆ
tr
tf
2
1. 푅푂푁퐻 × ꢀ푂푈푇
2
2. 푅푂푁ꢕ × ꢀ푂푈푇
3. ꢙ × (푡푟 + 푡ꢄ) × 푉 × ꢀ푂 × ꢄ
퐼푁
ꢅꢆ
2
Figure 72. SW Waveform
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I/O Equivalence Circuits
1.EN, 17.SSCG, 24.MODE
19. PGOOD
EN/
PGOOD
SSCG/
MODE
100Ω
10kΩ
GND
GND
GND
12,13,14.SW, 15.BOOT
20.VOUT, 21.VCC_EX, 23.VREG
VIN
BOOT
VREG
PVIN
VREG
SW
VREG
GND
GND
VCC_EX
PGND
GND
100kΩ
18. CTLOUT
GND
VREG
VOUT
9MΩ
CTLOUT
3MΩ
GND
GND
GND
GND
*Resistance value is Typ.
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BD8P250MUF-C
Operational Notes
1. Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2. Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at
all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic
capacitors.
3. Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. However,
pins that drive inductive loads (e.g. motor driver outputs, DC-DC converter outputs) may inevitably go below ground
due to back EMF or electromotive force. In such cases, the user should make sure that such voltages going below
ground will not cause the IC and the system to malfunction by examining carefully all relevant factors and conditions
such as motor characteristics, supply voltage, operating frequency and PCB wiring to name a few.
4. Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5. Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating
conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical
characteristics.
6. Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and
routing of connections.
7. Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
8. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
9. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
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Operational Notes – continued
10. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
Pin B
B
E
C
Pin A
B
C
E
P
P+
P+
N
P+
P
P+
N
N
N
N
N
N
N
Parasitic
Elements
Parasitic
Elements
P Substrate
GND GND
P Substrate
GND
GND
Parasitic
Elements
Parasitic
Elements
N Region
close-by
Figure 73. Example of Monolithic IC Structure
11. Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
12. Thermal Shutdown Circuit (TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the
junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj
falls below the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
13. Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
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BD8P250MUF-C
Ordering Information
B D 8 P 2
5
0 M U F
-
CE 2
Part Number
Package
Product class
MUF: VQFN024FV4040
C for Automotive applications
Packaging and forming specification
E2: Embossed tape and reel
Marking Diagram
VQFN24FV4040 (TOP VIEW)
Part Number Marking
8 P 2 5 0
LOT Number
Pin 1 Mark
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Physical Dimension and Packing Information
Package Name
VQFN24FV4040
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BD8P250MUF-C
Revision History
Date
Revision
001
Changes
11.Sep.2018
New Release
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Notice
Precaution on using ROHM Products
(Note 1)
1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment
,
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
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a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
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H2S, NH3, SO2, and NO2
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[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
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[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
Rev.003
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
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A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
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When disposing Products please dispose them properly using an authorized industry waste company.
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Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
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4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
Rev.003
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Daattaasshheeeett
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3. The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
Rev.001
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