BD9215F [ROHM]
Analog Circuit, 1 Func, PDSO28, SOP-28;型号: | BD9215F |
厂家: | ROHM |
描述: | Analog Circuit, 1 Func, PDSO28, SOP-28 光电二极管 |
文件: | 总5页 (文件大小:206K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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STRUCTURE
Silicon Monolithic Integrated Circuit
DC-AC Inverter Control IC
NAME OF PRODUCT
TYPE
BD9215F、BD9215FV
FUNCTION
・ 36V High voltage process
・ 1ch control with Full-Bridge
・ Lamp current and voltage sense feed back control
・ Sequencing easily achieved with Soft Start Control
・ Short circuit protection with Timer Latch
・ Under Voltage Lock Out
・ Mode-selectable the operating or stand-by mode by stand-by pin
・ For master IC, Synchronous operating with BD9898F/FV
・ BURST mode controlled by PWM and DC input
・ Output liner Control by external DC voltage
○Absolute Maximum Ratings(Ta = 25℃)
Parameter
Supply Voltage
Symbol
VCC
Limits
Unit
V
36
BST pin
BST
40
36
V
SW pin
SW
V
BST-SW voltage difference
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
BST-SW
Topr
Tstg
Tjmax
15
V
-40~+85
-55~+150
+150
℃
℃
℃
749*1(BD9215F)
1062*2(BD9215FV)
Power Dissipation
Pd
mW
*1Pd derate at 6.0mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm)
*2Pd derate at 8.5mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm)
〇Operating condition
Parameter
Symbol
Limits
16.0~30.0 ※
5.0~37.5
5.0~14.0
30~110
Unit
V
Supply voltage
VCC
BST
BST voltage
V
BST-SW voltage difference
DRIVER frequency
BST-SW
FOUT
fBCT
V
kHz
kHz
BCT oscillation frequency
0.05~1.00
※For Operation condition of Supply voltage, Please see NOTE FOR USE(4page), more information.
Status of this document
The Japanese version of this document is the official specification.
Please use the translation version of this document as a reference to expedite understanding of the official version.
If these are any uncertainty in translation version of this document, official version takes priority.
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○Electric Characteristics(Ta=25℃、VCC=24V、STB=UVLO=3.0V)
Limits
Parameter
((WHOLE DEVICE))
Operating current
Symbol
MIN.
TYP.
MAX.
Unit
Conditions
Icc1
Icc2
-
-
5.0
60
9.0
mA
FOUT=60kHz, FB=GND, BST=OPEN
Stand-by current
140
μA
((STAND BY CONTROL))
Stand-by voltage H
VstH
VstL
2
-
-
VCC
0.8
V
V
System ON
System OFF
Stand-by voltage L
-0.3
((UVLO BLOCK)))
Operating voltage (UVLO)
Hesteresis width (UVLO)
((REG BLOCK))
Vuvlo
2.16
2.25
2.34
V
V
⊿Vuvlo
0.085
0.110
0.135
REG output voltage
VREG
IREG
7.35
20
7.50
-
7.65
-
V
REG source current
((OSC BLOCK))
mA
RT pin Voltage
VRT
ISS
1.05
1.7
1.50
2.2
1.95
2.7
V
μA
V
Soft start current
SS operation start Voltage
SS term END Voltage
SRT ON resistance
VSS_ST
VSS_ED
RSRT
0.18
1.35
-
0.20
1.50
85
0.22
1.65
170
V
Ω
((BOSC BLOCK))
BOSC Max voltage
VBCTH
VBCTL
IBCT
1.94
0.4
2
2.06
0.6
V
V
A
fBCT=0.3kHz
fBCT=0.3kHz
VBCT=0.2V
BOSC Min voltage
0.5
BOSC constant current
BOSC frequency
1.35/BRT 1.5/BRT 1.65/BRT
fBCT
291
300
309
Hz (BRT=37.8kΩ BCT=0.047μF)
((FEED BACK BLOCK))
IS threshold voltage 1
IS threshold voltage 2
VS threshold voltage
IS source current 1
VIS1
VIS2
1.225
-
1.25
VREFIN
1.25
-
1.275
VIS1
1.28
0.9
V
V
V
VREF applying voltage
VVS
1.22
-
IIS1
μA DUTY=2.2V
μA DUTY=0V IS=1.0V
μA
IS source current 2
IIS2
40
50
60
VS source current
IVS
-
-
0.9
IS COMP detect voltage 1
IS COMP detect voltage 2
VREF input voltage range
((DUTY BLOCK))
VISCOMP1
VISCOMP2
VREFIN
0.606
-
0.625
0.50
-
0.644
-
V
V
V
VREFIN≧1.25V
VREFIN= 1V
0.6
1.6
No effect at VREF>1.25V
High voltage
3.8
-
-
-
4.0
-
4.2
0.5
V
V
VDUTY-OUTH
VDUTY-OUTL
RDUTY-OUT_sink
RDUTY-OUT_source
Low voltage
DUTY-OUT sink resistance
DUTY-OUT source resistance
((OUTPUT BLOCK))
LN output sink resistance
LN output source resistance
HN output sink resistance
HN output source resistance
MAX DUTY
150
300
300
600
Ω
Ω
RsinkLN
RsourceLN
RsinkHN
RsourceLN
MAX DUTY
TOFF
1.8
4.5
3.5
9.0
3.5
9.0
48.5
200
60
7.0
18.0
7.0
Ω
Ω
Ω
Ω
%
1.8
VBST-VSW=7.0V
VBST-VSW=7.0V
FOUT=60kHz
4.5
18.0
49.5
400
62.1
46.0
100
57.9
OFF period
ns
Drive output frequency
((TIMER LATCH BLOCK))
Timer Latch setting voltage
Timer Latch setting current
((COMP BLOCK))
FOUT
kHz RT=21k Ω
VCP
ICP
3.88
1.6
4.0
2.1
4.12
2.6
V
μA
VCOMPH
3.88
0.15
4.0
4.12
0.25
V
V
VSS>1.65V
COMP over voltage detect voltage
Hysterisis width (COMP)
((Synchronous Block))
High voltage
⊿VCOMPH
0.20
VCT_SYNCH
VCT_SYNCL
RSYNC_OUT_sink
RSYNC_OUT_source
3.8
-
-
-
4.0
-
4.2
0.5
V
V
Low voltage
CT_SYNC_OUT sink resistance
CT_SYNC_OUT source resistance
150
300
300
400
Ω
Ω
(This product is not designed to be radiation-resistant.)
REV. C
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〇Package Dimensions
Device Mark
BD9215FV
BD9215F
1
1
Lot No.
SSOP-B28 (Unit:mm)
SOP28 (Unit:mm)
〇Pin Description
PIN No.
1
PIN NAME
PGND
LN2
FUNCTION
Ground for FET drivers
〇Block Diagram
NMOS FET driver
2
NMOS FET driver
3
HN2
Lower rail voltage for HN2 output
Boot-Strap input for HN2 output
BURST signal output pin
4
SW2
5
BST2
DUTY_OUT
6
CT_SYNC_OUT CT synchronous signal output pin
7
External resistor from SRT to RT for
adjusting the start-up triangle oscillator
External resistor from RT to GND for
8
SRT
RT
9
adjusting the triangle oscillator
GROUND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
BCT
BRT
DUTY
STB
CP
External capacitor from BCT to GND for
adjusting the BURST triangle oscillator
External resistor from BRT to GND for
adjusting the BURST triangle oscillator
Control PWM mode and BURST mode
Stand-by switch
External capacitor from CP to GND for
Timer Latch
Reference voltage input pin for Error
amplifier
VREF
VS
Error amplifier input
Error amplifier input
Error amplifier output
IS
FB
External capacitor from SS to GND for Soft
Start Control
SS
Over voltage detect pin
COMP
VCC
UVLO
REG
BST1
SW1
HN1
LN1
Supply voltage input
External Under Voltage Lock Out
Internal regulator output
Boot-Strap input for HN1 output
Lower rail voltage for HN1 output
NMOS FET driver
NMOS FET driver
REV. C
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〇NOTE FOR USE
1. This product is produced with strict quality control, but might be destroyed if used beyond its absolute
maximum ratings. Once IC is destroyed, failure mode will be difficult to determine, like short mode or
open mode. Therefore, physical protection countermeasure, like fuse is recommended in case operating
conditions go beyond the expected absolute maximum ratings.
2. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is
within recommended operating range. The standard electrical characteristic values cannot be guaranteed
at other voltages in the operating ranges, however the variation will be small. When it is used in between
STB-UVLO Diode short etc., the IC can operate VCC≧9V. Please refer to a Technical Note in detail.
3. Mounting failures, such as misdirection or miscounts, may harm the device.
4. A strong electromagnetic field may cause the IC to malfunction.
5. The GND pin should be the location within ±0.3V compared with the PGND pin. ALL Pin (except BST1, BST2,
HN1, HN2,) Voltage should be under VCC voltage +0.3V
6. BD9215F, BD9215FV incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown
circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not
designed to protect the IC or guarantee its operation of the thermal shutdown circuit is assumed.
7. When modifying the external circuit components, make sure to leave an adequate margin for external
components actual value and tolerance as well as dispersion of the IC.
8. About the external FET, theparasitic Capacitor may cause the gate voltage to change, when the drain voltage
is switching. Make sure to leave adequate margin for this IC variation.
9. Under operating CP charge (under error mode) analog dimming and burst dimming are not operate.
10. Under operating Slow Start Control (SS is less than 1.5V), It does not operate Timer Latch.
11. By STB voltage, BD9215F, BD9215FV are changed to 2 states. Therefore, do not input STB pin voltage between
one state and the other state (0.8~2.0V).
12. The pin connected a connector need to connect to the resistor for electrical surge destruction.
13. This IC is a monolithic IC which (as shown is Fig-1) has P+ substrate and between the various pins.
A P-N junction is formed from this P layer of each pin. For example, the relation between each potential
is as follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can
result in mutual interference among circuits as well as operation faults and physical damage. Accordingly
you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than
the GND (P substrate) voltage to an input pin.
Transistor (NPN)
Resistance
B
(PinA)
(PinB)
E
C
GND
N
N
P+
P+
P
N
N
N
P substrate
GND
Parasitic diode
P substrate
GND
Parasitic diode
(PinB)
(PinA)
B C
Parasitic diode
E
GND
GND
Other adjacent components
Parasitic diode
Fig-1 Simplified structure of a Bipolar IC
REV. C
Notice
N o t e s
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which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
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However, should you incur any damage arising from any inaccuracy or misprint of such
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The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
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R0039
A
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