BD9573MUF-M_技术文档

Datasheet

Power Management IC

For Automotive R-Car Series

BD9573MUF-M

General Description

Key Specifications

BD9573MUF-M is a Power Management Integrated

Circuit (PMIC) designed specifically for use on R-Car

series processor for In-Vehicle Infotainment (IVI)

systems and Instrument Cluster Panel.



Input Voltage Range:

3.0 V to 3.6 V

5 V (Typ)

0.2 A (Max)

1.8 V (Typ)

1.0 A (Max)

VOUT1 (VD50) Output Voltage:

VOUT1 (VD50) Output Current:

VOUT2 (VD18) Output Voltage:

VOUT2 (VD18) Output Current:

VOUT3 (DDR) Output Voltage:

Features

1.35 V (Typ, DDR3L)^{(Note 2)}

1.50 V (Typ, DDR3)^{(Note 2)}



AEC-Q100 Qualified^{(Note 1)}

Customizable Power Up / Down Sequence and

State Control



VOUT3 (DDR) Output Current:

VOUT4 (VD10A, VD10B) Output Voltage:

1.03 V (Typ)

VOUT4 (VD10A, VD10B) Output Current:

2.0 A (Max)



Fewer External Components Count / Compact Size

Power Control Logic with Processor Interface and

Event Detection



5.2 A (Max)

2.5 V (Typ)

0.15 A (Max)



Built-in UVLO, SCP, OVP, UVP, OCP and TSD

Protection



VOUTL1 (VL25) Output Voltage:

VOUTL1 (VL25) Output Current:

(Note 1) Grade 2

VOUTS1 (VS33) Output Voltage: VIN7 = 3.3 V (Typ)

Applications

VOUTS1 (VS33) Output Current:

0.3 A (Max)



In-Vehicle Infotainment (IVI) Systems

Instrument Cluster Panel

Operating Ambient Temperature Range:

-40 °C to +105 °C

(Note 2) Select Voltage by the DDR_SEL pin.

Special Characteristics

Output Voltage:

(VOUT1 (VD50), VOUT2 (VD18), VOUT3 (DDR),

VOUT4 (VD10A, VD10B), VOUTL1 (VL25),

VOUTS1 (VS33))

Package

W (Typ) x D (Typ) x H (Max)

VQFN56FV8080

(Wettable Flank)

8.0 mm x 8.0 mm x 1.0 mm

Enlarged View

VQFN56FV8080

Wettable Flank Package

〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays.

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Block Diagram

VREF

OSC

Boost Converter VD50

L_VOUT2

TSD

I2C

Buck Converter VD18

Buck Converter DDR

C_VOUT2

L_VOUT3

C_VOUT3

Control

L_VOUT4A

Buck Converter VD10A

Buck Converter VD10B

C_VOUT4

L_VOUT4B

ERROR

WDT

LDO25 VL25

RESET

TEST

SW VS33

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Pin Configuration

(TOP VIEW)

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Pin Description

Pin No.

Pin Name

I/O

Function

1

2

3

4

5

6

7

PGND2

SW2

-

Power GND for VOUT2

-

High side MOSFET source / Low side MOSFET sink pin for

VOUT2

High side MOSFET source / Low side MOSFET sink pin for

VOUT2

O

SW2

O

VIN2

I (POWER)

I

Power supply for VOUT2

Feedback pin for VOUT2

VIN2

FB2

VOUT3 Voltage is changed by DDR_SEL.

DDR_SEL = H: 1.5 V, DDR_SEL = L: 1.35 V

(internal 100 kΩ pull down)

8

DDR_SEL

I

9

VIN3

I (POWER)

Power supply for VOUT3

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

I (POWER)

Power supply for VOUT3

High side MOSFET source / Low side MOSFET sink pin for

SW3

O

VOUT3

High side MOSFET source / Low side MOSFET sink pin for

VOUT3

SW3

O

PGND3

FB3

-

Power GND for VOUT3

Feedback pin for VOUT3

GND

-

I

AGND

WDO

-

O (O.D.)^{(Note 1)}

Watchdog Timer error signal.

Power On (internal 100 kΩ pull down)

Reset signal for SoC

RSTB

PRESETB

SYNC

INTB

I

O (O.D.)^{(Note 1)}

I

External sync for DCDC (internal 100 kΩ pull down)

Interrupt signal

O (O.D.)^{(Note 1)}

Clock signal input as Watch Dog Timer function.

(internal 100 kΩ pull down)

Watch Dog Timer function setting ON/OFF.

(internal 100 kΩ pull down)

WDI

I

WDEN

SDA

I

I/O (O.D.)^{(Note 1)}

I2C Data

SCL

I/O (O.D.)^{(Note 1)}

I2C CLK

PGD

O (O.D.)^{(Note 1)}

POWER Good Function

Feedback pin for VOUT4

Power GND for VOUT4

FB4

I

PGND4

SW4

-

High side MOSFET source / Low side MOSFET sink pin for

VOUT4

High side MOSFET source / Low side MOSFET sink pin for

VOUT4

O

SW4

O

VIN4

I (POWER)

I

Power supply for VOUT4

VIN4

Power supply for VOUT4

Adjust shutdown timing of VD18. Multi-threshold PIN.

(internal 2 MΩ pull down)

SEQCNT[1]

35

36

VOUT1_EN

TEST

I

Enable control pin for VOUT1 (internal 100 kΩ pull down)

Connected to AGND. TEST MODE PIN

Adjust start and OFF timing. Multi-threshold PIN.

(internal 2 MΩ pull down)

37

38

39

SEQCNT[0]

VIN5

I

I (POWER)

Power supply for VOUT4

VIN5

Power supply for VOUT4

(Note 1) O.D. = Open Drain

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Pin Description - continued

Pin No.

40

Pin Name

SW5

I/O

O

Function

High side MOSFET source / Low side MOSFET sink pin for

VOUT4

High side MOSFET source / Low side MOSFET sink pin for

VOUT4

41

SW5

O

42

43

44

45

46

47

PGND5

VOUTL1

VIN6

-

Power GND for VOUT4

Output of VOUTL1

-

O

I (POWER)

O

Power supply for VOUTL1

Power supply for VOUTS1

SW Output

VIN7

VOUTS1

Control Gate of External PMOS SW. When use External PMOS.

If External PMOS SW is not used, please connect to GND.

48

GATECNT

O

49

50

51

52

53

54

55

56

VFIL

VIN

O

Output of filtering VIN.

Power supply for PMIC

Feedback pin for VOUT1

Power supply for VOUT1

Output of LDSW

I (POWER)

FB1

I

VIN1

I (POWER)

VLSO

VOUT1

SW1

O

-

Output of VOUT1

High side MOSFET source / Low side MOSFET sink pin for

VOUT1

PGND1

Power GND for VOUT1

GND

-

EXP-PAD (CORNER)

EXP-PAD (CENTER)

-

(EXP-PAD (CORNER) short-circuit with EXP-PAD (CENTER)

into the Package)

GND (Connect to common GND of PCB)

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Footprint Dimension

Package Name

VQFN56FV8080

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Ordering Information

B D 9 5 7 3 M U F -

ME 2

Part Number

Package

Product Rank

MUF: VQFN56FV8080

M: for Automotive

Packaging and forming specification

E2: Embossed tape and reel

Marking Diagram

VQFN56FV8080 (TOP VIEW)

Part Number Marking

B D 9 5 7 3 M U F

LOT Number

Pin 1 Mark

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Contents

General Description........................................................................................................................................................................1

Features..........................................................................................................................................................................................1

Applications ....................................................................................................................................................................................1

Key Specifications ..........................................................................................................................................................................1

Special Characteristics ...................................................................................................................................................................1

Package..........................................................................................................................................................................................1

Block Diagram ................................................................................................................................................................................2

Pin Configuration ............................................................................................................................................................................3

Pin Description................................................................................................................................................................................4

Physical Dimension and Packing Information.................................................................................................................................6

Footprint Dimension........................................................................................................................................................................7

Ordering Information.......................................................................................................................................................................8

Marking Diagram ............................................................................................................................................................................8

Contents .........................................................................................................................................................................................9

Device Feature...................................................................................................................................................................13

Output Voltage Table ......................................................................................................................................................13

Signal Line Diagram for PMIC........................................................................................................................................14

Application .........................................................................................................................................................................15

Electrical Characteristics....................................................................................................................................................17

Absolute Maximum Ratings............................................................................................................................................17

Thermal Resistance .......................................................................................................................................................18

Recommended Operating Conditions ............................................................................................................................19

DC Characteristics .........................................................................................................................................................20

Protection Mode (Under Voltage Lock Out)....................................................................................................................24

Protection Mode (Thermal Shutdown)............................................................................................................................24

Protection Mode .............................................................................................................................................................24

Function Description ..........................................................................................................................................................25

Pin Control Function.......................................................................................................................................................25

4.1.1

4.1.2

4.1.3

4.1.4

4.1.5

4.1.6

4.1.7

4.1.8

4.1.9

4.1.10

VOUT1_EN Input.................................................................................................................................................25

RSTB Input ..........................................................................................................................................................25

PIN Setting Judge Timing ....................................................................................................................................25

Output Power-ON / Output Power-OFF Sequence..............................................................................................26

VOUT2 (VD18) Discharge Start Timing ...............................................................................................................27

Countermeasures for Hang-Up............................................................................................................................27

Interval Setting.....................................................................................................................................................28

Initializing Control Circuit .....................................................................................................................................29

VOUT1 Mode Setting...........................................................................................................................................29

State Machine ..................................................................................................................................................31

Whole Sequence Control................................................................................................................................................33

4.2.1

Whole Sequence (State Chart)............................................................................................................................33

General Sequence Description............................................................................................................................33

I2C Accessible State Condition............................................................................................................................33

EEPROM Load Function and Internal OSC Stable Time.....................................................................................34

Prevention of Repetition for Protection Error, EEPROM CRC Error ....................................................................34

4.2.2

4.2.3

4.2.4

4.2.5

VOUT1/VOUTL1 Disable Setting without EEPROM.......................................................................................................35

VOUTS1 Disable Setting without EEPROM, Internal/External SW Mode Setting ..........................................................36

I2C I/F.............................................................................................................................................................................37

Interrupt Function ...........................................................................................................................................................41

4.6.1

4.6.2

Interrupt Function Description..............................................................................................................................41

Interruption Factor ...............................................................................................................................................42

Power Abnormality Monitoring Function (Protection Error Detection).............................................................................45

SYNC Function...............................................................................................................................................................47

WDT Function ................................................................................................................................................................48

Register Specification ........................................................................................................................................................51

Register Map..................................................................................................................................................................51

Register Description.......................................................................................................................................................52

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

5.2.6

5.2.7

5.2.8

5.2.9

5.2.10

5.2.11

5.2.12

Recognition Code Indicator..................................................................................................................................52

FuSa Mode (Error Detection/Rectification Mode) ................................................................................................52

Spread Spectrum Clock Generation Control for Internal OSC.............................................................................53

SMRB control Using I2C Control (Software Manual Reset for PRESETB) ..........................................................54

Watch Dog Timer Setting.....................................................................................................................................54

Oscillator Enable in STANDBY State...................................................................................................................54

The PGD pin output assert condition Setting.......................................................................................................55

PMIC Internal Status............................................................................................................................................55

I2C FuSa mode Error bit location.........................................................................................................................56

INTB Interruption Factor and Mask Condition ..................................................................................................57

POW Setting ....................................................................................................................................................60

VOUT Voltage SET ..........................................................................................................................................63

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5.2.13

VOUTS1 OCP SET ..........................................................................................................................................65

Typical Performance Curves..............................................................................................................................................66

Line Regulation ..............................................................................................................................................................66

Load Regulation .............................................................................................................................................................68

Power Efficiency.............................................................................................................................................................70

Power ON Waveform......................................................................................................................................................72

Power OFF Waveform....................................................................................................................................................74

Load Transient................................................................................................................................................................76

Operational Notes..............................................................................................................................................................78

Revision History.................................................................................................................................................................81

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Table 1: Output Voltage Table of Each State .........................................................................................................................13

Table 2: Application Circuit Components List.........................................................................................................................16

Table 3: Absolute Maximum Ratings......................................................................................................................................17

Table 4: Recommended Operating Conditions ......................................................................................................................19

Table 5: DC Characteristics (Unless otherwise specified, Tj = -40 °C to +150 °C, VIN = 3.3 V)............................................20

Table 6: Logic Characteristics (Unless otherwise specified, Tj = -40 °C to +150 °C, VIN = 3.3 V).........................................23

Table 7: Protection Mode (General).......................................................................................................................................24

Table 8: Protection Mode (VD50, DDR, VD18, VD10) ...........................................................................................................24

Table 9: Protection Mode (VL25) ...........................................................................................................................................24

Table 10: Protection Mode (VS33).........................................................................................................................................24

Table 11: SEQCNT[0] Operation Mode..................................................................................................................................28

Table 12: SEQCNT[1] Operation Mode..................................................................................................................................28

Table 13: Initializing Control Circuit........................................................................................................................................29

Table 14: I2C Accessible Condition .......................................................................................................................................33

Table 15: Interruption at Primary Level ..................................................................................................................................43

Table 16: Interruption at Secondary Level 2 ..........................................................................................................................44

Table 17: WDT setting (NG_RATIO[1:0] = “00”).....................................................................................................................49

Table 18: WDT setting (NG_RATIO[1:0] = “01”).....................................................................................................................49

Table 19: WDT setting (NG_RATIO[1:0] = “10”).....................................................................................................................49

Table 20: WDT setting (NG_RATIO[1:0] = “11”).....................................................................................................................49

Table 21: I2C I/F Register Map..............................................................................................................................................51

Table 22: PMIC Internal State................................................................................................................................................55

Table 23: PON/POFF Trigger Signal......................................................................................................................................61

Table 24: PON/POFF Interval................................................................................................................................................62

Table 25: VOUT1 Tuning Voltage ..........................................................................................................................................63

Table 26: VOUT2 Tuning Voltage ..........................................................................................................................................63

Table 27: VOUT3 Tuning Voltage ..........................................................................................................................................64

Table 28: VOUT4 Tuning Voltage ..........................................................................................................................................64

Table 29: VOUTL1 Tuning Voltage ........................................................................................................................................65

Table 30: VOUTS1 OCP Current (Internal) and Voltage (External)........................................................................................65

Figure 1. An Example of Signal Line Diagram for PMIC ........................................................................................................14

Figure 2. Application Circuit...................................................................................................................................................15

Figure 3. Application Circuit (External MOS) .........................................................................................................................15

Figure 4. RSTB Operation Timing Chart................................................................................................................................25

Figure 5. Output Power-ON Operation Timing Chart (Default Register Setting)....................................................................26

Figure 6. Output Power-OFF Operation Timing Chart (Default Register Setting) ..................................................................26

Figure 7. VOUT2 Discharge Start Timing ..............................................................................................................................27

Figure 8. SEQCNT Circuit .....................................................................................................................................................28

Figure 9. Whole Sequence1 (Mode B)...................................................................................................................................29

Figure 10. Whole Sequence2 (Mode B).................................................................................................................................29

Figure 11. Error Case (Mode B).............................................................................................................................................30

Figure 12. Main State Machine..............................................................................................................................................31

Figure 13. Sub State Machine ...............................................................................................................................................32

Figure 14. Whole Sequence (State Chart).............................................................................................................................33

Figure 15. Sequence at Protection Error Occurrence (Timing Chart) ....................................................................................34

Figure 16. VOUT1 Disable Setting without EEPROM............................................................................................................35

Figure 17. VOUTL1 Disable Setting without EEPROM..........................................................................................................35

Figure 18. VOUT1 and VOUTL1 OFF Circuit ........................................................................................................................35

Figure 19. VOUTS1 Disable Setting without EEPROM .........................................................................................................36

Figure 20. VOUTS1 Internal/External Setting........................................................................................................................36

Figure 21. VOUTS1 OFF Circuit and SW Mode Selection.....................................................................................................36

Figure 22. I2C Basic Protocol................................................................................................................................................37

Figure 23. I2C Protocol (Each Access Mode)........................................................................................................................37

Figure 24. I2C Protocol (FuSa Mode)....................................................................................................................................38

Figure 25. I2C Data Format (FuSa Mode type2 = ECC at Calculation) .................................................................................40

Figure 26. Error Detection Judgement by ECC Calculation...................................................................................................40

Figure 27. Error Correction Calculation .................................................................................................................................40

Figure 28. Interruption Factor/Mask/Request ........................................................................................................................41

Figure 29. Interrupt Function Description...............................................................................................................................41

Figure 30. System Diagram of Interruption Function .............................................................................................................42

Figure 31. Power Abnormality Monitoring Circuit...................................................................................................................45

Figure 32. Timing Chart when Protection Error Factor Occur 1.............................................................................................45

Figure 33. Timing Chart when Protection Error Factor Occur 2.............................................................................................46

Figure 34. WDT Function.......................................................................................................................................................48

Figure 35. WDT NG RATIO ...................................................................................................................................................48

Figure 36. WDT Detection Time when NG_RATIO[1:0] = “00”...............................................................................................50

Figure 37. WDT Detection Time when NG_RATIO[1:0] = “01”...............................................................................................50

Figure 38. Modulation Waveform of SSCG............................................................................................................................53

Figure 39. VOUT1 Output Voltage vs VIN .............................................................................................................................66

Figure 40. VOUT2 Output Voltage vs VIN .............................................................................................................................66

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Figure 41. VOUT3 Output Voltage vs VIN (VOUT3 = 1.35 V Setting)....................................................................................66

Figure 42. VOUT3 Output Voltage vs VIN (VOUT3 = 1.5 V Setting)......................................................................................66

Figure 43. VOUT4 Output Voltage vs VIN .............................................................................................................................67

Figure 44. VOUTL1 Output Voltage vs VIN ...........................................................................................................................67

Figure 45. VOUT1 Output Voltage vs IOUT...........................................................................................................................68

Figure 46. VOUT2 Output Voltage vs IOUT...........................................................................................................................68

Figure 47. VOUT3 Output Voltage vs IOUT (VOUT3 = 1.35 V Setting).................................................................................68

Figure 48. VOUT3 Output Voltage vs IOUT (VOUT3 = 1.5 V Setting)...................................................................................68

Figure 49. VOUT4 Output Voltage vs IOUT...........................................................................................................................69

Figure 50. VOUTL1 Output Voltage vs IOUT.........................................................................................................................69

Figure 51. VOUT1 Power Efficiency vs IOUT........................................................................................................................70

Figure 52. VOUT2 Power Efficiency vs IOUT........................................................................................................................70

Figure 53. VOUT3 Power Efficiency vs IOUT (VOUT3 = 1.35 V Setting) ..............................................................................70

Figure 54. VOUT3 Power Efficiency vs IOUT (VOUT3 = 1.5 V Setting) ................................................................................70

Figure 55. VOUT4 Power Efficiency vs IOUT........................................................................................................................71

Figure 56. VOUT1 Power ON Waveform...............................................................................................................................72

Figure 57. VOUT2 Power ON Waveform...............................................................................................................................72

Figure 58. VOUT3 Power ON Waveform (VOUT3 = 1.35 V Setting) .....................................................................................72

Figure 59. VOUT3 Power ON Waveform (VOUT3 = 1.5 V Setting).......................................................................................72

Figure 60. VOUT4 Power ON Waveform...............................................................................................................................73

Figure 61. VOUTL1 Power ON Waveform.............................................................................................................................73

Figure 62. VOUTS1 Power ON Waveform.............................................................................................................................73

Figure 63. VOUT1 Power OFF Waveform.............................................................................................................................74

Figure 64. VOUT2 Power OFF Waveform.............................................................................................................................74

Figure 65. VOUT3 Power OFF Waveform (VOUT3 = 1.35 V Setting) ...................................................................................74

Figure 66. VOUT3 Power OFF Waveform (VOUT3 = 1.5 V Setting) .....................................................................................74

Figure 67. VOUT4 Power OFF Waveform.............................................................................................................................75

Figure 68. VOUTL1 Power OFF Waveform...........................................................................................................................75

Figure 69. VOUTS1 Power OFF Waveform...........................................................................................................................75

Figure 70. VOUT1 Load Transient (IOUT = 0 A to 100 mA (SR = 100 mA/µs)) .....................................................................76

Figure 71. VOUT2 Load Transient (IOUT = 0 A to 0.5 A (SR = 1 A/µs)).................................................................................76

Figure 72. VOUT3 Load Transient (VOUT3 = 1.35 V Setting, IOUT = 0 A to 1 A (SR = 1 A/µs)) ...........................................76

Figure 73. VOUT3 Load Transient (VOUT3 = 1.5 V Setting, IOUT = 0 A to 1 A (SR = 1 A/µs)) .............................................76

Figure 74. VOUT4 Load Transient (IOUT = 0 A to 2.05 A (SR = 1 A/µs))...............................................................................77

Figure 75. VOUTL1 Load Transient (IOUT = 0 A to 75 mA (SR = 100 mA/µs).......................................................................77

Figure 76. Example of Monolithic IC Structure ......................................................................................................................79

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Device Feature

Output Voltage Table

Table 1: Output Voltage Table of Each State

Channel

VD50

VD18

DDR

Rail name

VOUT1

Output [V]

5.0

Iomax [A]

0.2

STANDBY

OFF

ACTIVE

ON

VOUT2

1.8

1.0

OFF

ON

1.35 (DDR3L)

1.50 (DDR3)

VOUT3

2.0

OFF

ON

VD10A

VD10B

VOUT4

1.03

2.50

5.2

OFF

ON

VL25

VS33

VOUTL1

VOUTS1

0.15

0.3

OFF

ON

VIN7

(Analog Switch)

OFF

ON

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1. Device Feature - continued

Signal Line Diagram for PMIC

Bidirectional Voltage Level

Translator

R-car D3

BD9573MUF-M

I2C_SCL

I2C_SDA

INTB (Open Drain)

PRESETB (Open Drain)

PGD (Open Drain)

DDR_SEL

VIN or GND

100 kΩ

SYNC

WDI

GND (When not in use)

100 kΩ

GND (When not in use)

WDEN

100 kΩ

WDO (Open Drain)

SEQCNT[1:0]

GND or VMID_L

or VMID_H or VIN

2 MΩ

RSTB

System Controller

100 kΩ

VOUT1_EN

Figure 1. An Example of Signal Line Diagram for PMIC

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Application

LOAD

VREF

OSC

Boost Converter VD50

L_VOUT2

TSD

I2C

LOAD

Buck Converter VD18

Buck Converter DDR

C_VOUT2

L_VOUT3

LOAD

C_VOUT3

Control

L_VOUT4A

LOAD

Buck Converter VD10A

Buck Converter VD10B

C_VOUT4

L_VOUT4B

ERROR

WDT

LDO25 VL25

LOAD

RESET

TEST

SW VS33

Figure 2. Application Circuit

Figure 3 shows the case of external FET for VOUTS1.

When output current is over 0.3 A or more, external FET is used.

VIN

VIN7

C_VIN

R_M

F_PMOS

VOUTS1

SW VS33

C_VOUTS1

GATECNT

Figure 3. Application Circuit (External MOS)

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2. Application - continued

Table 2: Application Circuit Components List

Value

Parts Name

Unit

Vendor

Parts Number

Size (mm)

Min^{(Note 1)}

Typ

Max

C_VINx

C_VFIL

-

10

-

μF

μH

μF

μH

μF

μH

μF

-

MURATA

TDK

GCM21BR70J106KE22

GCM188R71C105KA64

GCM21BR70J106KE22

GCM31CR71A226KE02

TFM252012ALMA2R2MTAA

TFM252012ALMAR22MTAA

GCM31CR70J226KE26

CGA4J1X7T0J226M

GCM31CR70J226KE26

CGA4J1X7T0J226M

TFM252012ALMAR33MTAA

GCM31CR70J226KE26

CGA4J1X7T0J226M

GCM31CR70J226KE26

CGA4J1X7T0J226M

TFM252012ALMAR22MTAA

GCM32ER70J476KE19

CGA4J1X7T0J226M

GCM32ER70J476KE19

CGA4J1X7T0J226M

GCM21BR70J106KE22

-

2012

1608

2012

3216

2520

3216

2012

3216

2012

2520

3216

2012

3216

2012

2520

3225

2012

3225

2012

-

1

-

C_LSO

-

10 x 2

-

C_VOUT1

C_LOAD1

L_VOUT1

L_VOUT2

-

22

-

22

-

2.2

-

0.22

-

TDK

-

22

-

MURATA

TDK

C_VOUT2

-

or 22

-

22 x 2

-

MURATA

TDK

C_LOAD2

L_VOUT3

C_VOUT3

or 22 x 2

-

0.33

-

TDK

-

22

-

MURATA

TDK

-

or 22

-

22 x 3

-

MURATA

TDK

C_LOAD3

or 22 x 3

-

L_VOUT4A

L_VOUT4B

-

0.22

-

TDK

-

0.22

-

TDK

-

47 x 2

-

MURATA

TDK

C_VOUT4

C_LOAD4

-

or 22 x 4

-

47 x 4

-

MURATA

TDK

or 22 x 8

-

C_VOUTL1

C_LOADL1

C_VOUTS1

C_LOADS1

F_PMOS

R_M

-

1

-

10

-

MURATA

-

300

10

-

MURATA

-

GCM21BR70J106KE22

-

2012

-

1

-

300

-

ROHM

RQ1A070ZPHZG

TSMT8

1005

-

100

10

1

kΩ

MCR01MZPF1003

R_PGD

-

MCR01MZPF1002

R_EEROR

R_RESET

R_SDA

-

MCR01MZPF1002

-

MCR01MZPF1002

-

MCR01MZPF1001

R_SCL

-

1

MCR01MZPF1001

R_WDO

-

10

MCR01MZPF1002

(Note 1) Please set in consideration of temperature properties and DC bias properties not to become less than the minimum.

Please consider it based on enough evaluations with the actual model.

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Electrical Characteristics

Absolute Maximum Ratings

Table 3: Absolute Maximum Ratings

Parameter

Symbol

Rating

-0.3 to +7.0

-0.3 to VIN+0.3

-0.3 to VIN1+0.3

-0.3 to +7.0

-0.3 to VINx+0.3

-0.3 to +7.0

-0.3 to VINx+0.3

-0.3 to +10.0

-0.3 to +7.0

-0.3 to VIN+0.3

-0.3 to +7.0

-0.3 to VIN+0.3

-3.0

Unit

V

Input Voltage 1

VIN, VIN1, VIN2, VIN3, VIN4, VIN5, VIN6, VIN7

Input Voltage 2

FB1, FB2, FB3, FB4

V

Output Voltage 1

VFIL

V

Output Voltage 2

VLSO

VOUT1

V

Output Voltage 3

V

Output Voltage 4

VOUTL1, VOUTS1

GATECNT

V

Output Voltage 5

V

SW to GND Voltage 1

SW to GND Voltage 2

Logic Input Voltage 1

Logic Input Voltage 2

Logic Input Voltage 3

Logic Output Voltage 1

Logic Output Voltage 2

Logic Output Pin Current Low 1

Logic Output Pin Current Low 2

Storage Temperature Range

SW2, SW3, SW4, SW5

SW1

V

RSTB, SDA, SCL

SYNC, WDI, WDEN, VOUT1_EN, DDR_SEL

SEQCNT[0], SEQCNT[1]

INTB, PGD, WDO

PRESETB

V

PRESETB, INTB, PGD, WDO

SDA, SCL

mA

°C

-20.0

Tstg

-55 to +150^{(Note 1)}

Maximum Junction

Temperature

Tjmax

150

Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open

circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case

the IC is operated over the absolute maximum ratings.

Caution2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of

the properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration

by increasing board size and copper area so as not to exceed the maximum junction temperature rating.

(Note 1) Operation is not guaranteed.

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3. Electrical Characteristics - continued

Thermal Resistance^{(Note 1)}

Thermal Resistance (Typ)

Parameter

Symbol

Unit

1s^{(Note 3)}

2s2p^{(Note 4)}

VQFN56FV8080

Junction to Ambient

Junction to Top Characterization Parameter^{(Note 2)}

θ_JA

59.8

4.0

22.2

2.0

°C/W

Ψ_JT

(Note 1) Based on JESD51-2A(Still-Air).

(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside

surface of the component package.

(Note 3) Using a PCB board based on JESD51-3.

(Note 4) Using a PCB board based on JESD51-5, 7.

Layer Number of

Measurement Board

Material

FR-4

Board Size

Single

114.3 mm x 76.2 mm x 1.57 mmt

Top

Copper Pattern

Thickness

70 μm

Footprints and Traces

Thermal Via^{(Note 5)}

Layer Number of

Measurement Board

Material

FR-4

Board Size

114.3 mm x 76.2 mm x 1.6 mmt

2 Internal Layers

Pitch

Diameter

4 Layers

1.20 mm

Φ0.30 mm

Top

Copper Pattern

Bottom

Thickness

70 μm

Copper Pattern

Thickness

35 μm

Copper Pattern

Thickness

70 μm

Footprints and Traces

74.2 mm x 74.2 mm

(Note 5) This thermal via connects with the copper pattern of all layers.

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3. Electrical Characteristics - continued

Recommended Operating Conditions

Table 4: Recommended Operating Conditions

Parameter

Symbol

VIN

Min

3.0

Typ

3.3

-

Max

3.6

Unit

V

Power Supply Voltage

Power Supply Voltage 1

Power Supply Voltage 2

Power Supply Voltage 3

Power Supply Voltage 4

Power Supply Voltage 5

Power Supply Voltage 6

Power Supply Voltage 7

VIN1

VIN2

VIN3

VIN4

VIN5

VIN6

VIN7

3.0

3.6

V

3.0

3.6

V

3.0

3.6

V

3.0

3.6

V

3.0

3.6

V

3.0

3.6

V

3.0

3.6

V

RSTB, SYNC, WDI,

Logic Input Voltage Low 1

Logic Input Voltage High 1

Logic Input Voltage Low 2

Logic Input Voltage High 2

Input Voltage Low 3

-0.3

1.2

+0.5

V

WDEN, VOUT1_EN, DDR_SEL

RSTB, SYNC, WDI,

WDEN, VOUT1_EN, DDR_SEL

-

VIN + 0.3

+0.5

V

SCL, SDA

-0.3

1.2

-

V

SCL, SDA

-

VIN + 0.3

VIN x 0.1

VIN x 0.5

VIN x 0.8

VIN x 0.3

2.2

V

SEQCNT[0], SEQCNT[1]

-0.3

VIN x 0.2

VIN x 0.6

VIN x 0.9

1.8

-

V

SEQCNT[0], SEQCNT[1]

Input Voltage Middle Low 3

Input Voltage Middle High 3

Input Voltage High 3

-

V

SEQCNT[0], SEQCNT[1]

-

V

SEQCNT[0], SEQCNT[1]

-

V

SYNC Input Frequency Range

SYNC Input Pulse Duty Range

SYNC

Ta

2.0

50

25

MHz

%

°C

45

55

Operating Ambient

Temperature

Operating Junction

Temperature

-40

+105

+150

Tj

-40

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3. Electrical Characteristics - continued

DC Characteristics

Table 5: DC Characteristics (Unless otherwise specified, Tj = -40 °C to +150 °C, VIN = 3.3 V)

Standard Value

Parameter

Symbol

Unit

Conditions

Min

Typ

Max

[General]

STANDBY

(VIN, VIN1 to VIN7 total)

ACTIVE

Bias Current 1

ICC_1

ICC_2

-

0.5

6

-

mA

Bias Current 2

12

mA (VIN, VIN1 to VIN7 total,

Switching stop)

VFIL UVLO

Threshold Voltage

VFIL UVLO

Hysteresis Voltage

VIN1 to VIN7 UVP

Threshold Voltage

VIN1 to VIN7 UVP Hysteresis

Voltage

VFIL_UVLO

dVFIL_UVLO

VIN1-7_UVP

2.7

-

2.8

0.1

2.7

2.9

-

V

VFIL: Sweep down

VFIL: Sweep up

VIN1 to VIN7: Sweep

down

2.6

2.8

dVIN1-7_UVP

R_VFIL

-

0.1

10

-

V

VIN1 to VIN7: Sweep up

-

VFIL Resistance

Ω

[VOUT1 (VD50)]

Output Voltage

VOUT1

4.91

1.912

1.8

5.00

2.250

2.0

5.09

2.588

2.2

V

Io = 0 mA

Switching Frequency

Synchronization Frequency

Fosc_VOUT1

Fsync_VOUT1

MHz SSCG = OFF

MHz SYNC = 2 MHz

VIN to VOUT1

V/ms (DCDC converter

Soft-start time rate)

Soft-Start Time Rate

Tssr_VOUT1

-

4.2

-

0 V to 5 V

(Include LDSW on time)

VOUT1 Soft Start time

Tss_VOUT1

-

1.57

-

ms

Upper-Side ON Resistance

Lower-Side ON Resistance

Ronh_VOUT1

Rohl_VOUT1

-

250

200

500

400

mΩ

-

Detect a peak current

flowing in Low-side FET

Over Current Protection

SCP Detecting Voltage

OCP_VOUT1

SCP_VOUT1

1.2

-

A

V

VOUT1

x 0.7

VOUT1

x 0.8

VOUT1

x 0.9

-

VOUT1

x 1.13

VOUT1

x 1.2

VOUT1

x 1.27

OVP Detecting Voltage

OVP_VOUT1

Ron_LS

V

mΩ

A

-

Load Switch ON Resistance

-

2.2

-

200

400

-

Load Switch

Over Current Protection

OCP_LDSW

Rdis_VOUT1

-

Output Discharge Resistance

25

50

Ω

VOUT1 Discharge

[VOUT2 (VD18)]

Output Voltage

VOUT2

1.7676

1.8000

2.250

2.0

1.8324

2.588

2.2

V

Io = 0 mA

Switching Frequency

Synchronization Frequency

Soft-Start Time Rate

Upper-Side ON Resistance

Lower-Side ON Resistance

Fosc_VOUT2

Fsync_VOUT2

Tss_VOUT2

Ronh_ VOUT2

Rohl_VOUT2

1.912

MHz SSCG = OFF

MHz SYNC = 2 MHz

1.8

-

1.0

-

V/ms

mΩ

-

160

320

200

100

mΩ

Detect a peak current

flowing in High-side FET

Over Current Protection

SCP Detecting Voltage

OCP_VOUT2

SCP_VOUT2

2.5

-

A

V

VOUT2

x 0.73

VOUT2

x 1.13

VOUT2

x 0.80

VOUT2

x 1.2

VOUT2

x 0.87

VOUT2

x 1.27

-

OVP Detecting Voltage

OVP_VOUT2

Rdis_VOUT2

V

-

Output Discharge Resistance

20

55

150

Ω

FB2 Discharge

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3.4 DC Characteristics - continued

(Unless otherwise specified, Tj = -40 °C to +150 °C, VIN = 3.3 V)

Standard Value

Typ

Parameter

[VOUT3 (DDR)]

Symbol

Unit

Conditions

Min

Max

Io = 0 mA

DDR_SEL = L

Io = 0 mA

Output Voltage 1

Output Voltage 2

VOUT3_1

VOUT3_2

1.3257

1.473

1.3500

1.500

1.3743

1.527

V

DDR_SEL = H

Switching Frequency

Fosc_VOUT3

Fsync_VOUT3

Tss_VOUT3

1.912

2.250

2.0

2.588

2.2

-

MHz SSCG = OFF

MHz SYNC = 2 MHz

Synchronization Frequency

Soft-Start Time Rate

1.8

-

1.0

V/ms

mΩ

-

Upper-Side ON Resistance

Lower-Side ON Resistance

Ronh_VOUT3

Rohl_VOUT3

100

70

200

140

mΩ

Detect a peak current

flowing in High-side FET

Over Current Protection

SCP Detecting Voltage

OCP_VOUT3

SCP_VOUT3

3.6

-

A

V

VOUT3

x 0.73

VOUT3

x 1.13

VOUT3

x 0.80

VOUT3

x 1.2

VOUT3

x 0.87

VOUT3

x 1.27

-

OVP Detecting Voltage

OVP1_VOUT3

Rdis_VOUT3

V

-

Output Discharge Resistance

20

40

80

Ω

FB3 Discharge

[VOUT4 (VD10A, VD10B) ]

Output Voltage

VOUT4

1.0115

1.912

1.8

1.0300

2.250

2.0

1.0485

2.588

2.2

V

Io = 0 mA

Switching Frequency

Synchronization Frequency

Soft-Start Time Rate

Fosc_VOUT4

Fsync_VOUT4

Tss_VOUT4

MHz SSCG = OFF

MHz SYNC = 2 MHz

-

1.0

-

V/ms

mΩ

-

Ronh_VOUT4A

Ronh_VOUT4B

Rohl_VOUT4A

Rohl_VOUT4B

OCP_VOUT4A

OCP_VOUT4B

Upper-Side ON Resistance

Lower-Side ON Resistance

Over Current Protection

SCP Detecting Voltage

-

100

70

-

200

140

-

mΩ

A

-

Detect a peak current

flowing in High-side FET

3.6

VOUT4

x 0.73

VOUT4

x 0.80

VOUT4

x 0.87

SCP_VOUT4

V

-

VOUT4

x 1.07

VOUT4

x 1.14

VOUT4

x 1.21

OVP Detecting Voltage

OVP_VOUT4

Rdis_VOUT4

V

-

Output Discharge Resistance

15

30

60

Ω

FB4 Discharge

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3.4 DC Characteristics - continued

(Unless otherwise specified, Tj = -40 °C to +150 °C, VIN = 3.3 V)

Standard Value

Typ

Parameter

Symbol

Unit

V

Conditions

Min

Max

[VOUTL1 (VL25)]

Output Voltage

VOUTL1

2.455

2.500

2.545

Io = 0 mA

Soft-Start Time Rate

On Resistance

Tss_VOUTL1

Ron_VOUTL1

OCP_VOUTL1

-

1.0

-

2

-

V/ms -

-

Ω

Ids = 50 mA

Over Current Protection

350

mA

-

VOUTL1 VOUTL1 VOUTL1

x 0.73 x 0.8 x 0.87

VOUTL1 VOUTL1 VOUTL1

SCP Detecting Voltage

SCP_ VOUTL1

V

OVP Detecting Voltage

OVP_ VOUTL1

Rdis_ VOUTL1

V

-

x 1.13

x 1.2

x 1.27

Output Discharge Resistance

75

150

300

Ω

VOUTL1 Discharge

[VOUTS1 (VS33)]

Soft-Start Time Rate

Tss_VOUTS1

Rdis_VOUTS1

Ron_VOUTS1

Ron_GATECNT

-

1

30

-

50

V/ms -

Output Discharge Resistance

SW ON Resistance

15

100

10

Ω

mΩ

Ω

VOUTS1 Discharge

250

25

450

50

-

GATECNT ON Resistance

GATECNT = 0.5 V

GATECNT

Rup_GATECNT

OCP_VOUTS1_IN

OCP_VOUTS1_EX

-

2

-

MΩ

mA

-

Pull Up Resistance

SW OCP Detecting Current

(Internal)

SW OCP Detecting Voltage

(External)

510

60

90

120

mV ΔV = VIN7-VOUTS1

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3.4 DC Characteristics - continued

Table 6: Logic Characteristics (Unless otherwise specified, Tj = -40 °C to +150 °C, VIN = 3.3 V)

Standard Value

Parameter

[Logic Block]

[Logic Input 1] (RSTB, SYNC, WDI, WDEN, VOUT1_EN, DDR_SEL)

Symbol

Unit

Conditions

Min

Typ

Max

Input Voltage Low 1

Input Voltage High 1

Pull down Resistance 1

VIL1

VIH1

RIN1

-0.3

1.2

-

+0.5

VIN+0.3

-

V

-

100

kΩ

[Logic Input 2] (SDA, SCL)

Input Voltage Low 2

Input Voltage High 2

Input Current 2

VIL2

VIH2

IIN2

-0.3

1.2

-1

-

+0.5

VIN+0.3

+1

V

-

0

-

μA

V

Acknowledge ON Voltage

VACK

-0.3

+0.4

Iload = -20 mA

[Logic Input 3] (SEQCNT[0], SEQCNT[1])

Input Voltage Low 3

VIL3

-0.3

VIN x 0.2

VIN x 0.6

VIN x 0.9

-

VIN x 0.1

VIN x 0.5

VIN x 0.8

VIN x 0.3

-

V

-

Input Voltage Middle Low 3

Input Voltage Middle High 3

Input Voltage High 3

VIML3

VIMH3

VIH3

-

V

-

V

Pull down Resistance 3

RIN3

2

MΩ

[Logic Output Voltage Low1] (Open Drain Output)

INTB, PGD, WDO Logic_out_low1

-0.3

-

+0.7

+0.5

V

Iload = -3 mA

[Logic Output Voltage Low2] (Open Drain Output)

PRESETB Logic_out_low2

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3. Electrical Characteristics - continued

Protection Mode (Under Voltage Lock Out)

All power supply shuts down at the same time when the VFIL UVLO signal is detected. There is no sequence in this

shutdown mode and the BD9573MUF-M cannot receive any external signals during this time.

Protection Mode (Thermal Shutdown)

Built-in internal Thermal Shutdown (TSD) circuit is provided to protect IC from heat destruction. Operation usage should

stay within the allowable loss range. Continuous use beyond this range can cause chip temperature Tj to increase and

consequently activate the TSD circuit. Threshold is 175 °C (Typ). TSD over 10 µs shuts down all power supplies at the

same time. Please consider the set design not to exceed TSD for safety use.

Protection Mode

Table 7: Protection Mode (General)

Protection Mode

UVLO Protection (VFIL)

Thermal Shutdown

SW

Hi-Z

Output

Function

PMIC is shut down immediately.

All Registers are reset.

PMIC is shut down immediately.

Some registers (SEQ reset Register) are reset.

Low (Discharge)

Table 8: Protection Mode (VD50, DDR, VD18, VD10)

Protection Mode

SW

Output

Function

Under Voltage Protection[UVP]

(VIN1 to VIN5)^{(Note 1)}

PMIC is shut down immediately.

Some registers (SEQ reset Register) are reset.

Timer latch (1 ms).

Hi-Z

Low (Discharge)

Short Circuit Protection

Over Voltage Protection

Hi-Z

Low (Discharge)

PMIC is shut down.

Some registers (SEQ reset Register) are reset.

PMIC is shut down immediately.

Some registers (SEQ reset Register) are reset.

Duty is restricted.

Timer latch (1 ms).

PMIC is shut down.

Over Current Protection

Hi-Z

Low (Discharge)

Some registers (SEQ reset Register) are reset.

(Note 1) VOUT1 or VOUTL1 output can be set to disable by connecting the VIN1 pin or the VIN6 pin to GND.

Please refer to section 4.3 VOUT1/VOUTL1 Disable Setting without EEPROM.

Table 9: Protection Mode (VL25)

Protection Mode

Output

Function

Under Voltage Protection[UVP]

(VIN6)^{(Note 1)}

PMIC is shut down immediately.

Some registers (SEQ reset Register) are reset.

Timer latch (1 ms).

Low (Discharge)

Short Circuit Protection

Over Voltage Protection

Low (Discharge)

PMIC is shut down.

Some registers (SEQ reset Register) are reset.

PMIC is shut down immediately.

Some registers (SEQ reset Register) are reset.

(Note 1) VOUT1 or VOUTL1 output can be set to disable by connecting the VIN1 pin or the VIN6 pin to GND.

Please refer to section 4.3 VOUT1/VOUTL1 Disable Setting without EEPROM.

Table 10: Protection Mode (VS33)

Protection Mode

Output

Function

Under Voltage Protection[UVP]

(VIN7)

PMIC is shut down immediately.

Some registers (SEQ reset Register) are reset.

Timer latch (1 ms).

Low (Discharge)

Over Current Protection

Low (Discharge)

PMIC is shut down.

Some registers (SEQ reset Register) are reset.

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Function Description

Pin Control Function

4.1.1 VOUT1_EN Input

VOUT1 Mode is selected by VOUT1_EN (pin) condition at UVLO release timing.

At the judgement timing, VOUT1 output voltage is

Mode A: controlled sequentially by the register setting. (VOUT1_EN (pin) = H at UVLO release timing).

Mode B: controlled by VOUT1_EN (pin) individually, and register setting is ignored.

(VOUT1_EN (pin) = L at UVLO release timing).

(Note) Most of timing charts in this data sheet are based on Mode A. Regarding Mode B, please refer to section 4.1.9 VOUT1 Mode Setting.

4.1.2 RSTB Input

The RSTB pin input is control signal to start Output Power-ON / Output Power-OFF.

Output Power-ON starts by inputting RSTB = H level and Output Power-OFF starts by inputting RSTB = L level.

Between the completion of Output Power-OFF and beginning of Output Power-ON (STANDBY state),

internal functions (except particular functions) are initialized and stops the circuit oscillator for low power

consumption with OSC_EN register = “0” setting.

Even though in STANDBY state, circuit oscillation starts with OSC_EN register = “1” setting.

(Note) In case RSTB = L level is detected during Power-ON Sequence, Power-OFF sequence starts immediately.

Figure 4. RSTB Operation Timing Chart

4.1.3 PIN Setting Judge Timing

The SEQCNT[1:0] pin (Select Power-ON / Power-OFF interval) and the DDR_SEL pin (select DDR output voltage)

settings are judged just before EEPROM Load.

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4.1 Pin Control Function – continued

4.1.4 Output Power-ON / Output Power-OFF Sequence

Output Power-ON starts by input of RSTB = H level.

In Output Power-ON operation,

(1) Internal Oscillation Operation (OSC Stable), (2) EEPROM Load, (3) Delay and (4) Power-ON sequence

are consecutively activated as shown in the following figure.

Regarding the interval T1 and T4, please refer to section 4.1.7 Interval Setting.

(1)

(2)

(3)

(4)

Internal Oscillation Operation: BD9573MUF-M waits 110 µs (Max) for stable oscillation internally.

EEPROM Load: Some of the functions can be selected by EEPROM setting value (Max 2 ms).

Delay: BD9573MUF-M execute delay for internal setting (Max 2 ms) before Power-ON.

Power-ON sequence: Activates Output Power-ON and PRESETB = H negate in order and with interval as in

following figure. PGD is asserted when all output voltage levels are over 75 % (Typ) x V_OUT

.

Figure 5. Output Power-ON Operation Timing Chart (Default Register Setting)

Output Power-OFF starts by input of RSTB = L level.

For Output Power-OFF operation, Power-OFF sequence activates as in following figure.

Regarding the interval T2 and T3, please refer to section 4.1.7 Interval Setting.

PGD is negated when one of the output power starts discharging.

Power-OFF operation is completed when all SHDN (= output voltage levels are under 200 mV (Typ)) is asserted.

Figure 6. Output Power-OFF Operation Timing Chart (Default Register Setting)

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4.1 Pin Control Function – continued

4.1.5 VOUT2 (VD18) Discharge Start Timing

In case all previous output’s SHDN is not asserted after the interval T3, VOUT2 output does not start discharging

until all previous output’s SHDN assertion.

4.1.6 Countermeasures for Hang-Up

In case any SHDN signal keeps low (shutdown is not detected) during Power-Off sequence, the sequence is never

completed and sequence cannot shift to next. As countermeasure for this Hang-Up situation, Hang-Up Timer is

implemented.

Hang-Up Timer counts the time of Power-OFF Sequence, and if it continues over 400 ms, internal state transitions

to STANDBY automatically. In Mode B, VOUT1 also has Hang-Up Timer individually. If VOUT1 Power-OFF

Sequence continues over 100 ms, internal state transitions to STANDBY automatically.

Figure 7. VOUT2 Discharge Start Timing

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4.1

Pin Control Function – continued

4.1.8 Initializing Control Circuit

There are 2 initialize conditions. Details of the initializing conditions are shown in following table.

Table 13: Initializing Control Circuit

Reset Name

VDD reset

Initializing Condition

UVLO of VFIL

Initializing Target Circuit

Every Control Circuit

Every Control Circuit except some I2C registers.

In more detail, please refer Table 21 I2C I/F Register Map.

SEQ reset state transition to STANDBY state

4.1.9 VOUT1 Mode Setting

In Mode B, VOUT1 is managed in Sub State. Regarding Main State and Sub State, please refer State Machine.

VOUT1 Sub State is activated only in limited Main State. Regarding the “limited Main State”, and Sub State, please

refer Figure 12 Main State Machine and Figure 13 Sub State Machine.

Figure 9. Whole Sequence1 (Mode B)

Figure 10. Whole Sequence2 (Mode B)

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4.1.9

VOUT1 Mode Setting – continued

When protection error or Hang Up Timer Overflow occurs, all outputs start to Power-OFF at the same time

regardless the error is due to VOUT1 or other channels. In this case, VOUT1_EN (pin) = L and RSTB (pin) = L is

needed to Re Power-ON.

Figure 11. Error Case (Mode B)

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4.1 Pin Control Function – continued

4.1.10 State Machine

BD9573MUF-M has two State Machine, Main and Sub. Sub State Machine is for VOUT1 individual control in

Mode B.

Figure 12. Main State Machine

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4.1.10 State Machine - continued

Figure 13. Sub State Machine

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4. Function Description – continued

Whole Sequence Control

4.2.1 Whole Sequence (State Chart)

Figure 14. Whole Sequence (State Chart)

4.2.2 General Sequence Description

(SHUTDOWN to STANDBY)

BD9573MUF-M is in SHUTDOWN state during VIN Power off.

After the input of VIN power, internal state starts transition from SHUTDOWN to STANDBY.

In STANDBY state,

Case1: OSC disable (OSC_EN register = “0” setting)

Case2: OSC enable (OSC_EN register = “1” setting)

In Case2, I2C write in STANDBY state is possible since OSC clock is supplied.

[Output Power-ON] (STANDBY to ACTIVE)

By the input of RSTB (pin) = H level, internal state starts transition from STANDBY to ACTIVE, and it initiate

Output Power-ON. PGD (pin) output is asserted when all output voltage levels are over 75 % (Typ) x V_OUT

PRESETB (pin) is asserted with the interval setting. Then, the transition to ACTIVE state is completed.

.

[Output Power-OFF] (ACTIVE to STANDBY)

By the input of RSTB (pin) = L level, internal state starts transition from ACTIVE to STANDBY and it initiate

Output Power-OFF.

After Power-OFF sequence is completed, BD9573MUF-M is initialized and stops OSC, then completes

transition to STANDBY state.

(STANDBY to SHUTDOWN)

UVLO of VFIL becomes effective during VIN power OFF.

4.2.3 I2C Accessible State Condition

I2C accessibility is restricted to only in STANDBY state and ACTIVE state.

Table 14: I2C Accessible Condition

Internal State

I2C read

I2C write

Disable (with OSC_EN register = “0”) /

Enable (with OSC_EN register = “1”)

STANDBY

Enable

Disable

Enable

EEPROM Load

Disable

Enable

Disable

Power-ON STANDBY, ACTIVE,

Power-OFF STANDBY

Other

(Note) Only OSC_EN register can be written without OSC_EN register = “1” setting in STANDBY State.

Some register I2C read value in STANDBY State are 0x00 (initial value), and they may differ from the value after Power-ON.

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4.2 Whole Sequence Control – continued

4.2.4 EEPROM Load Function and Internal OSC Stable Time

By connecting external EEPROM to I2C I/F pin (I2C_SCL, I2C_SDA), functions can be customized by the

parameters written in EEPROM.

EEPROM load operates before Power-ON sequence started by RSTB = H level.

If EEPROM is connected, 2 ms (Max) EEPROM load time is needed.

Case1: with EEPROM and correct response from EEPROM, EEPROM parameters are loaded.

Case2: with EEPROM and no response (not Acknowledgement) from EEPROM, initial value is used.

Case3: with EEPROM and can not read check code (CON_CHK_CODE is not 0x8E), initial value is used.

Case4: with EEPROM and CRC error has occurred, internal state returns to STANDBY.

In Case2 and Case3, NO_EEP register is set to “1”.

In Case4, EEP_CRC_ERR register is set to “1”.

Regarding “CON_CHK_CODE” and detailed EEPROM setting, please refer to BD9573MUF-M EEPROM setting

sheet.

4.2.5 Prevention of Repetition for Protection Error, EEPROM CRC Error

When Protection Function is activated by VR (Voltage Regulator)’s malfunction, every output power is turned off at

once and transitions to STANDBY state. In this case, there is a possibility that RSTB = H level is maintained and

internal state starts transition from STANDBY to ACTIVE. At that time, every output power is turned off at once

again and it may be repeated if the factor of malfunction is not removed.

This kind of repetition is also concerned for EEPROM CRC Error case.

To prevent this repetition, state transition from STANDBY does not start until the input of RSTB = L level.

Figure 15. Sequence at Protection Error Occurrence (Timing Chart)

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4. Function Description - continued

VOUT1/VOUTL1 Disable Setting without EEPROM

Without EEPROM setting, VOUT1 or VOUTL1 output can be set to disable by connecting VIN1 or VIN6 to GND.

In this case, disable setting outputs are excluded from the Power-ON / Power-OFF sequence automatically.

VOUT1 and VOUTL1 disable setting is judged just before EEPROM Load.

Figure 16. VOUT1 Disable Setting without EEPROM

Figure 17. VOUTL1 Disable Setting without EEPROM

LDO25

Boost Converter

Figure 18. VOUT1 and VOUTL1 OFF Circuit

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4. Function Description - continued

VOUTS1 Disable Setting without EEPROM, Internal/External SW Mode Setting

VOUTS1 output mode is selected by GATECNT (pin).

Mode1: Using VOUTS1 internally (GATECNT = L)

Mode2: Using VOUTS1 externally (GATECNT = H)

Without EEPROM setting, VOUTS1 output can be set to disable by connecting VIN7 and GATECNT to GND.

In this case, disable setting outputs are excluded from the Power-ON / Power-OFF sequence automatically.

Internal/External setting is judged at the end of Self Diagnosis, and Disable setting is judged just before EEPROM Load.

When Power-On, VOUTS1 is used as internal SW for 4.1 ms (±15 %). VOUTS1 changes to external SW after

POWER-ON completion. Therefore, voltage drop may occur in VOUTS1 when big current is loaded from VOUTS1 before

POWER-ON completion.

Figure 19. VOUTS1 Disable Setting without EEPROM

Figure 20. VOUTS1 Internal/External Setting

VS33 (SW)

OFF

EXTERNAL SW ON (GATECNT = H)

INTERNAL SW ON (GATECNT = L)

Figure 21. VOUTS1 OFF Circuit and SW Mode Selection

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4. Function Description - continued

I2C I/F

I2C Slave Interface of 1ch is installed in BD9573MUF-M.

I2C Protocol

1 to 7

Figure 22. I2C Basic Protocol

Single Mode

S

0

1

0

A

D7 D6 D5 D4 D3 D2 D1 D0

Write Data

A

P

W

Slave Address

Register Address

S

0

1

0

S

0

1

0

1

A

D7 D6 D5 D4 D3 D2 D1 D0 NA

Read Data

P

W

R

Slave Address

Mutiple Mode

S

0

1

0

A

D7 D6 D5 D4 D3 D2 D1 D0

Write Data (Addr: N)

A

FromMaster to Slave

FromSlave to Master

START condition

STOPcondition

W

Slave Address

Register Address ( = N)

S

P

A

D7 D6 D5 D4 D3 D2 D1 D0

Write Data (Addr: N+1)

D7 D6 D5 D4 D3 D2 D1 D0

Write Data

P

Acknow ledge

NA Not Acknow ledge

S

0

1

0

A

S

0

1

0

1

A

P

D7 D6 D5 D4 D3 D2 D1 D0

Read Data (Addr: N)

A

W

R

Slave Address

Register Address ( = N)

Slave Address

D7 D6 D5 D4 D3 D2 D1 D0

Read Data (Addr: N+1)

D7 D6 D5 D4 D3 D2 D1 D0 NA

Read Data

Figure 23. I2C Protocol (Each Access Mode)

Slave Address

Support 7 bit Address mode

Slave Address: 0x30 (When 8 bit description, it is 0x60 in Write mode and 0x61 in Read mode)

Speed Mode

(1) Fast mode

(2) Fast mode plus

Frequency

(1) Fast mode: 400 kHz (Max)

(2) Fast mode plus: 1 MHz (Max)

I2C accessible State condition

(1) I2C read condition: except EEPROM Load state

(2) I2C write condition: In STANDBY state (with OSC_EN register = “1” setting) or ACTIVE state

(Note) For I2C write condition in STANDBY state, 110 µs (Max) wait time after OSC_EN register = “1” is needed.

ACK/NACK Criterion

NACK is output when the Slave Address is not set to 0x30.

NACK is output without the I2C accessible State condition.

ACK is output even with read/write access to register address that is not being used.

ACK is output even with write access to RO attribute register.

Bus Clear

If the data line (SDA) is stuck LOW, please send 18 clock pulses. SDA bus is released by this procedure.

If not, then use the Hardware reset or cycle power to clear the bus.

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4.5 I2C I/F – continued

FuSa Mode (Error Detection / Rectification Mode)

FuSa (Functional Safety) mode is a function to detect/rectify transfer error. The 2nd byte of writing data at I2C transfer

is given as a FuSa byte to confirm.

Normal I2C mode or FuSa mode (type1 and type2) is selectable by I2C FuSa mode register.

The transfer protocol for this uses the same conventional I2C protocol.

Continuous data write with register address increment is supported.

(Odd-bytes of writing data are the actual data and even-bytes are FuSa byte for confirmation. Address increments

every 2 bytes.)

(If FuSa byte returns with error, then the corresponding byte is not written. If the FuSa byte returns without error, then

the corresponding byte is written).

FuSa Mode is applied not only write data but also read data by I2C FuSa mode register setting.

Mode switching is valid from the next transferred byte after settings are changed.

Single Mode

FromMaster to Slave

FromSlave to Master

START condition

STOPcondition

S

0

1

0

A

D7 D6 D5 D4 D3 D2 D1 D0

Write Data

A

P

W

S

P

A

Slave Address

Register Address

FuSa Byte

Acknow ledge

NA Not Acknow ledge

S

0

1

0

A

S

0

1

0

1

A

D7 D6 D5 D4 D3 D2 D1 D0

Read Data

A

NA P

W

R

Slave Address

FuSa Byte

Multiple Mode

S

0

1

0

A

D7 D6 D5 D4 D3 D2 D1 D0

Write Data (Addr: N)

A

W

Slave Address

Register Address ( = N)

FuSa Byte (Addr: N+1)

FuSa Byte (Addr: N)

D7 D6 D5 D4 D3 D2 D1 D0

Write Data (Addr: N+1)

P

S

0

1

0

A

S

0

1

0

1

A

D7 D6 D5 D4 D3 D2 D1 D0

A

P

A

W

R

Slave Address

Register Address ( = N)

FuSa Byte (Addr: N+1)

Slave Address

Read Data (Addr: N)

NA

FuSa Byte (Addr: N)

A

Read Data (Addr: N+1)

FuSa Byte

Figure 24. I2C Protocol (FuSa Mode)

[FuSa Mode Type1 : Compare Write Data and FuSa Byte]

Write Data 8 bit

FuSa Byte 8 bit

Writes properly to register.

==

(1) Does not write in register.

(2) Asserts interrupt while changing bit of I2C / Thermal

Error Status register. (MD1 interrupt)

I2C_IMASK = “1” (Mask setting)

=> Do no assert

I2C_IMASK = “0” (Mask released)

=> Assert the INTB pin output

MD1 bit is cleared by writing in “1”.

[FuSa Mode Type2 : Error Correction by FuSa Byte (1 bit error)]

Writes properly to register.

Write Data 8 bit

FuSa Byte 8 bit

(1) Rectify with FuSa Byte and writes to register.

(2) Asserts interrupt while changing bit of I2C / Thermal

Error Status register. (MD2_E1 interrupt)

I2C_IMASK = “1” (Mask setting)

=> Do not assert the INTB pin output

I2C_IMASK = “0” (Mask released)

ECC Calculation (1 bit error)

=> Assert the INTB pin output

MD2_E1 bit is cleared by writing in “1”.

(3) The cause of error is indicated in the I2C MD2_E1

Bit1 register by asserting the corresponding bit.

This is indicated in I2C MD2_E1 Bit2 register if

P[4:0] has an error. (Error rectification is

unnecessary.)

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4.5 I2C I/F – continued

[FuSa Mode Type2: Error Correction by FuSa Byte (Error more than 2 bit)]

ECC Calculation (No error)

Writes properly to register.

Write Data 8 bit

FuSa Byte 8 bit

(1) Does not write in register.

Write Data 8 bit

(2) Asserts interrupt while changing bit of I2C /

Thermal Error Status register. (MD2_E2 interrupt)

I2C_IMASK = “1” (Mask setting)

=> Do not assert the INTB pin output

I2C_IMASK = “0” (Mask released)

ECC Calculation (2 bit error)

=> Assert the INTB pin output

MD2_E2 bit is cleared by writing in “1”.

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4.5 I2C I/F – continued

ECC Calculation Specification

Arrange and add P[4:0] on LSB as FuSa byte[7:0] for FuSa mode type2.

I2C Data Stream

D7 D6 D5 D4 D3 D2 D1 D0

Write Data (Addr: N)

A

0

P4 P3 P2 P1 P0

FuSa byte (Addr: N)

Figure 25. I2C Data Format (FuSa Mode type2 = ECC at Calculation)

Transmitter [Encode]

Calculation method of P[4:0] added to DI[7:0] data (“^” means XOR calculation)

^

Receiver [Decode]

Error detecting and rectifying method by ECC Factor, receiving DI[7:0] and P[4:0].

ECC Factor Calculation Method

=> Error Detection Judgment/Error

(1) Error Detection Judgment

Error Detection Judgment based on ECC Factor

Figure 26. Error Detection Judgement by ECC Calculation

(2) Error Rectification

Error Correction is operated by following calculation for Single bit Error.

Figure 27. Error Correction Calculation

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4. Function Description - continued

Interrupt Function

4.6.1 Interrupt Function Description

Interruptions are notified from the INTB pin when interruption requests are enabled by any interruption factors.

The meaning of the words relevant to interruption are defined as followed.

“Interruption Factor”:

“Interruption Mask”:

Factor of any condition where an interruption is made.

Controls which interruption factors cause an interruption to occur.

(Masked: No interruption / No Mask: interruption occurs).

Interruption request only becomes active when the interruption factor is active and the

interruption is not masked.

“Interruption Request”:

Interruption Factor

(1: With Factor / 0: Without Factor)

Interruption Request

(1: With request / 0: Without request)

Interruption Mask

(1: Mask / 0: Mask released)

Figure 28. Interruption Factor/Mask/Request

Each factor can be masked, read or cleared by I2C. Also, INTB utilizes active-low pin operation.

Figure 29. Interrupt Function Description

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4.6 Interrupt Function – continued

4.6.2 Interruption Factor

Interruption request notice function is implemented in 2 levels for the factor.

(1)

(2)

Primary level interruption register of final stage

Interruption register in secondary level of each function block stage

Following figure shows the logical flowchart of Interruption Factor/Mask/Request implemented in BD9573MUF-M.

Figure 30. System Diagram of Interruption Function

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4.6.2 Interruption Factor – continued

Following Shows All Interruption Factors.

(A) Interruption in Primary level

Interruption Factor register: INT IntReq register

Interruption Mask register: INT IntMask register

Table 15: Interruption at Primary Level

Interruption Factor

(INT IntReq Register) (INT IntMask Register)

Interruption Mask

Active Condition of Interruption

Factor

Detail of Interruption Factor

I2C Transfer Error,

Thermal Error (TSD)

Error judged at writing register,

Thermal Error detection

I2CTHM_INT

I2CTHM_IMASK

OVP_INT

SCP_INT

OCP_INT

UVP_INT

SYS_INT

OVP_IMASK

SCP_IMASK

OCP_IMASK

UVP_IMASK

SYS_IMASK

OVP Error Status

SCP Error Status

OCP Error Status

UVP Error Status

System Error Status

OVP detection

SCP detection

OCP detection

UVP detection

System Error detection

(B) Interruption in Secondary Level

Regarding factors in Secondary Level, please refer the next page.

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4.6.2 Interruption Factor – continued

Table 16: Interruption at Secondary Level 2

Interruption Request

MD1

Interruption Mask

Detail of Interruption Factor

FuSa Mode Type1 error

MD2_E1

I2C_IMASK

-

FuSa Mode Type2 error 1 bit

MD2_E2

FuSa Mode Type2 error more than 2 bit

Thermal Shutdown

TSD

VOUT1_OVP

VOUT2_OVP

VOUT3_OVP

VOUT4_OVP

VOUTL1_OVP

VOUT1_OCP

VOUT2_OCP

VOUT3_OCP

VOUT4A_OCP

VOUT4B_OCP

VOUTS1_OCP

LDSW_OCP

VOUT1_SCP

VOUT2_SCP

VOUT3_SCP

VOUT4_SCP

VOUTL1_SCP

VIN1_UVP

VD50 power Output over voltage protection

VD18 power Output over voltage protection

DDR power Output over voltage protection

VD10 power Output over voltage protection

VL25 power Output over voltage protection

VD50 power Output over current protection

VD18 power Output over current protection

DDR power Output over current protection

VD10A power Output over current protection

VD10B power Output over current protection

VS33 power Output over current protection

LDSW power Output over current protection

VD50 power Output short circuit protection

VD18 power Output short circuit protection

DDR power Output short circuit protection

VD10 power Output short circuit protection

VL25 power Output short circuit protection

VD50 power Input under voltage protection

VD18 power Input under voltage protection

DDR power Input under voltage protection

VD10A power Input under voltage protection

VD10B power Input under voltage protection

VL25 power Input under voltage protection

VS33 power Input under voltage protection

WDI Input Clock Frequency Error

-

VIN2_UVP

VIN3_UVP

VIN4_UVP

VIN5_UVP

VIN6_UVP

VIN7_UVP

WDT_ERR

WDT_E_IMASK

EEPCRC_E_IMASK

EEP_END_IMASK

POFFHUT_E_IMASK

V1_HUT_E_IMASK

EEP_CRC_ERR

EEP_END

CRC Error during EEPROM Load

EEPROM Load End

POFF_HUT_ERR

V1_HUT_ERR

Hang-Up Timer counts over 400 ms

Hang-Up Timer for VOUT1 (only for Mode B), 100 ms

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4. Function Description – continued

Power Abnormality Monitoring Function (Protection Error Detection)

VIN

C_VIN

L_VOUT

SW

DCDC Converter

C_VOUT

PGND

FB

EN

SCP

OVP

Logic

Figure 31. Power Abnormality Monitoring Circuit

Power Abnormality Monitoring Function for SCP and OCP work as follows:

LDSW_OCP function is excluded.

Figure 32. Timing Chart when Protection Error Factor Occur 1

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4.7 Power Abnormality Monitoring Function (Protection Error Detection) – continued

Power Abnormality Monitoring Function for OVP and TSD work as follows:

Figure 33. Timing Chart when Protection Error Factor Occur 2

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4. Function Description – continued

SYNC Function

The SYNC pin is used to synchronize the DC/DC switching frequency with external pulse clock signal.

SYNC input frequency range is from 1.8 MHz to 2.2 MHz, and SYNC input pulse duty range is from 45 % to 55 %.

Entering abnormal clock through the SYNC pin (e.g. out of range signal) may cause malfunction.

The external pulse clock signal is reflected in ACTIVE mode. This pin can be remained open if synchronization is not

needed. The SYNC pin needs 10 kΩ external pull down resistor when synchronization signal is supplied from R-car

SoC.

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4. Function Description – continued

WDT Function

Watch Dog Timer (WDT) monitors the WDI pin input by detecting the rising edge of WDI input pulse.

This function is enabled by WDEN (pin) = H in ACTIVE state. If WDT Error is detected, the WDO pin output is negated.

WDT starts from rising edge of WDIN

The detection guaranteed

WDT

WDT Fast N.G.

WDT Slow N.G.

WDIN

Trigger Open Window

t_WF(Min)

t (ms)

t_WF(Max)

t_OK(Typ)

t_WS(Min)

t_WS(Max)

Figure 34. WDT Function

WDT FAST N.G. Detection

1. WDI input signal is ignored when WDEN = L or internal state is not ACTIVE. WDT is activated when WDEN = H.

2. For the initial duration just after WDEN goes to high, only SLOW N.G. time detection works and FAST N.G. does not

work. If rise edge of WDI comes within SLOW N.G. time, then

(1) both FAST N.G. and SLOW N.G. time detections start to work. (TYPE register (0x16[5]) = H)

(2) only SLOW N.G. time detection starts to work. (TYPE register (0x16[5]) = L)

3. These time detection monitors the time until next rising edge and when it detects WDI edge within FAST N.G. time

(t_WF), WDO becomes LOW. WDO goes back to High after 100 ms (Typ) delay.

4. When WDO becomes High, WDT is activated again and operation resumes.

Only SLOW N.G. time detection works until the next first rising edge, and both SLOW and FAST N.G. starts at the

first rising edge like state 1.

When WDEN is Low, WDO becomes H and WDT is disabled. During this period, WDI input signal is ignored and WDO

output is not affected.

Regarding WDI input signal, over 200 μs H level is required to be detected as “H” level.

FAST/SLOW N.G. Detection Area is determined by FAST_NG[2:0] and NG_RATIO[1:0] register setting.

WDIN input clock duration is set by FAST_NG[2:0] register value.

rise edge of WDI

OK Area

Fast NG : OK Area = 1 : 1

NG_RATIO[1:0] = "00"

Slow NG

Fast NG

Fast NG : OK Area = 1 : 3

NG_RATIO[1:0] = "01"

Slow NG

OK Area

Fast NG : OK Area = 1 : 7

NG_RATIO[1:0] = "10"

Slow NG

OK Area

Fast NG : OK Area = 1 : 15

NG_RATIO[1:0] = "11"

OK Area

Slow NG

Figure 35. WDT NG RATIO

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4.9 WDT Function – continued

Table 17: WDT setting (NG_RATIO[1:0] = “00”)

Fast NG Detection (ms)

FAST_NG[2:0]

Slow NG Detection (ms)

t_OK(ms)

(Typ)

t_WF(Min)

t_WF(Max)

t_WS(Min)

3.6

t_WS(Max)

4.6

“000”

“001”

“010”

“011”

“100”

“101”

“110”

“111”

1.7

2.3

3.0

6.0

3.4

4.6

7.4

9.2

6.8

9.2

12.0

24.0

48.0

96.0

192.0

384.0

14.5

18.5

13.5

27.5

55.0

110.0

220.0

18.5

36.5

73.0

146.0

292.0

29.5

36.5

59.5

73.0

119.0

238.0

476.0

146.0

292.0

583.0

Table 18: WDT setting (NG_RATIO[1:0] = “01”)

Fast NG Detection (ms)

FAST_NG[2:0]

Slow NG Detection (ms)

t_OK(ms)

(Typ)

t_WF(Min)

t_WF(Max)

t_WS(Min)

7.2

t_WS(Max)

9.2

“000”

“001”

“010”

“011”

“100”

“101”

“110”

“111”

1.7

2.3

4.8

9.7

3.4

4.6

14.8

18.4

6.8

9.2

19.0

39.0

78.0

156.0

311.0

622.0

29.0

37.0

13.5

27.5

55.0

110.0

220.0

18.5

36.5

73.0

146.0

292.0

59.0

73.0

119.0

238.0

476.0

952.0

146.0

292.0

584.0

1166.0

Table 19: WDT setting (NG_RATIO[1:0] = “10”)

Fast NG Detection (ms)

FAST_NG[2:0]

Slow NG Detection (ms)

t_OK(ms)

(Typ)

t_WF(Min)

t_WF(Max)

t_WS(Min)

14.4

t_WS(Max)

18.4

“000”

“001”

“010”

“011”

“100”

“101”

“110”

“111”

1.7

2.3

8.4

17.0

3.4

4.6

29.6

36.8

6.8

9.2

33.5

58.0

74.0

13.5

27.5

55.0

110.0

220.0

18.5

36.5

73.0

146.0

292.0

68.0

118.0

238.0

476.0

952.0

1904.0

146.0

292.0

584.0

1168.0

2332.0

137.0

275.0

550.0

1100.0

Table 20: WDT setting (NG_RATIO[1:0] = “11”)

Fast NG Detection (ms)

FAST_NG[2:0]

Slow NG Detection (ms)

t_OK(ms)

(Typ)

t_WF(Min)

t_WF(Max)

t_WS(Min)

28.8

t_WS(Max)

36.8

“000”

“001”

“010”

“011”

“100”

“101”

“110”

“111”

1.7

2.3

15.5

32.0

3.4

4.6

59.2

73.6

6.8

9.2

63.0

116.0

236.0

476.0

952.0

1904.0

3808.0

148.0

292.0

584.0

1168.0

2336.0

4664.0

13.5

27.5

55.0

110.0

220.0

18.5

36.5

73.0

146.0

292.0

127.0

256.0

512.0

1025.0

2050.0

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4.9 WDT Function – continued

Figure 36. WDT Detection Time when NG_RATIO[1:0] = “00”

Figure 37. WDT Detection Time when NG_RATIO[1:0] = “01”

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Register Specification

Register Map

…Initializes at either VIN reset (VFIL UVLO) or

SEQ reset (STANDBY transition)

…Initializes only at VIN reset (VFIL UVLO)

Table 21: I2C I/F Register Map

Address

0x00

Register Name

Vendor Code

Bit[7]

Bit[6]

1

0

Bit[5]

Bit[4]

1

0

Bit[3]

Bit[2]

Bit[1]

Bit[0]

R/W

RO

-

Default

0xDB

0x73

0x01

-

1

0

-

0

1

0

-

1

0

-

0

-

1

0

-

1

-

0x01

0x02

-

Product Code

Product Revision

-

I2C_SMOD[1:0]

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

-

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

-

I2C FuSa Mode

-

SMOD_read

-

R/W

-

0x00

0x03

0x00

0x01

0x20

0x00

0x3F

-

0x00

0x20

-

SSCG_FORM[1:0]

SSCG Cnt

SMRB Write Protect

SMRB Cnt

Watch Dog Timer setting

SSCG_PERI

SSCG_EN

SMRB_WP[7:0]

-

TYPE

-

SMRB_hist

NG_RATIO[1:0]

-

SMRB_asrt

OSC_EN

-

FAST_NG[2:0]

OSC Enable

PGD Setting

-

PGD_SETTING[5:0]

-

PMIC_STATE[3:0]

I2C_MD2_E1_BIT[7:0]

I2C_MD2_E1_BIT_P[4:0]

PMIC Internal Status

I2C MD2_E1 Bit 1

I2C MD2_E1 Bit 2

I2C / Thermal Error Status

NO_EEP

RO

-

TSD

-

MD2_E2

-

MD2_E1

MD1

R/W

-

I2C / Thermal Error Mask

-

I2C_IMASK

VOUTL1_OVP

VOUT4_OVP VOUT3_OVP VOUT2_OVP VOUT1_OVP

OVP Error Status

SCP Error Status

OCP Error Status

VOUTL1_SCP

VOUT4_SCP VOUT3_SCP VOUT2_SCP VOUT1_SCP

-

VOUTS1_OCP

VOUT4B_OCP VOUT4A_OCP VOUT3_OCP VOUT2_OCP VOUT1_OCP

LDSW_OCP

-

UVP Error Status

System Status

System Status Mask

VIN7_UVP VIN6_UVP VIN5_UVP VIN4_UVP VIN3_UVP VIN2_UVP VIN1_UVP

EEP_CRC_ERR

V1_HUT_ERR

HUT_ERR

EEP_END

EEP_END_IMASK EEPCRC_E_IMASK

-

WDT_ERR

WDT_E_IMASK

-

V1_HUT_E_IMASK HUT_E_IMASK

-

SYS_INT

UVP_INT

I2CTHM_INT

0x30

0x31

-

INT IntReq

INT IntMask

OCP_INT

SCP_INT

OVP_INT

R/W

-

0x00

-

I2CTHM_IMASK

SYS_IMASK UVP_IMASK

OCP_IMASK SCP_IMASK OVP_IMASK

-

POW_WP[7:0]

0x40

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

-

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

0x60

0x61

POW Write Protect

POW Trigger VOUT1

POW Trigger VOUT2

POW Trigger VOUT3

POW Trigger VOUT4

POW Trigger VOUTL1

POW Trigger VOUTS1

POW Trigger PRESETB

POW Wait VOUT1

POW Wait VOUT2

POW Wait VOUT3

POW Wait VOUT4

POW Wait VOUTL1

POW Wait VOUTS1

POW Wait PRESETB

R/W

-

0x00

0x20

0x61

0x45

0x73

0x36

0x52

0x04

0x00

-

0x00

0x43

0x00

0x37

0x00

0x3E/0x27

0x23/0x27

0x00

0x19

0x00

0x40

0x10/0x06

0x16/0x08

0x33

POFF_TRG_VOUT1[3:0]

POFF_TRG_VOUT2[3:0]

POFF_TRG_VOUT3[3:0]

POFF_TRG_VOUT4[3:0]

POFF_TRG_VOUTL1[3:0]

POFF_TRG_VOUTS1[3:0]

POFF_TRG_PRESETB[3:0]

POFF_WAIT_VOUT1[3:0]

POFF_WAIT_VOUT2[3:0]

POFF_WAIT_VOUT3[3:0]

POFF_WAIT_VOUT4[3:0]

POFF_WAIT_VOUTL1[3:0]

POFF_WAIT_VOUTS1[3:0]

POFF_WAIT_PRESETB[3:0]

PON_TRG_VOUT1[3:0]

PON_TRG_VOUT2[3:0]

PON_TRG_VOUT3[3:0]

PON_TRG_VOUT4[3:0]

PON_TRG_VOUTL1[3:0]

PON_TRG_VOUTS1[3:0]

PON_TRG_PRESETB[3:0]

PON_WAIT_VOUT1[3:0]

PON_WAIT_VOUT2[3:0]

PON_WAIT_VOUT3[3:0]

PON_WAIT_VOUT4[3:0]

PON_WAIT_VOUTL1[3:0]

PON_WAIT_VOUTS1[3:0]

PON_WAIT_PRESETB[3:0]

-

V1_SIGN

VOUT1_TUNE[2:0]

VOUT1 TUNE

RO

-

R/W

RO

R/W

RO

R/W

RO

R/W

RO

R/W

V2_SIGN

VOUT2_TUNE[2:0]

VOUT2 TUNE

-

V3_SIGN

VOUT3_TUNE[4:0]

VOUT3 TUNE

(Note 1)

(Note 2)

-

V4_SIGN

VOUT4_TUNE[4:0]

VOUT4 TUNE

-

VL1_SIGN

VOUTL1_TUNE[2:0]

VOUTL1 TUNE

-

(Note 3)

(Note 4)

VOUTS1_OCP[5:0]

VOUTS1 OCP

-

(Note) Please do not access to the address except above.

(Note 1) DDR_SEL (pin) = L: Default value is 0x3E.

DDR_SEL (pin) = H: Default value is 0x27.

(Note 2) DDR_SEL (pin) = L: Default value is 0x23.

DDR_SEL (pin) = H: Default value is 0x27.

(Note 3) GATECNT (pin) = L: Default value is 0x10.

GATECNT (pin) = H: Default value is 0x06.

(Note 4) GATECNT (pin) = L: Default value is 0x16.

GATECNT (pin) = H: Default value is 0x08.

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5. Register Specification – continued

Register Description

5.2.1 Recognition Code Indicator

Register Name

Vendor Code

Address

0x00

D7

1

D6

1

D5

0

D4

1

D3

1

D2

0

D1

1

D0

1

R/W Default

RO 0xDB

Vendor Recognition Code

0xDB: Rohm

Register Name

Product Code

Address

0x01

D7

0

D6

1

D5

1

D4

1

D3

0

D2

0

D1

1

D0

1

R/W Default

RO 0x73

Product Recognition Code

0x73: BD9573MUF-M

Register Name

Address

0x02

D7

0

D6

D5

0

D4

0

D3

0

D2

0

D1

0

D0

1

R/W Default

RO 0x01

Product Revision

0

Product Revision Recognition Code

0x01: Rev.1 Sample

5.2.2 FuSa Mode (Error Detection / Rectification Mode)

Register Name

I2C FuSa Mode

Address

0x10

D7

-

D6

-

D5

-

D4

D3

-

D2

-

D1

D0

R/W Default

0x00

SMOD_

read

I2C_SMOD[1:0] R/W

I2C_SMOD[1:0]

FuSa Mode Setting

“00”: General mode (NO FuSa mode) => Normal I2C format without FuSa byte.

“01”: FuSa mode type1

FuSa byte = Write data. (No error if 2 transferring data bytes are the same value.)

When error is detected

=> Do not execute writing and assert MD1 Interruption Factor bit of I2C / Thermal Error Status

register.

(Assert the INTB pin output if I2C_IMASK mask is released by I2C / Thermal Error Mask register.)

“10”: FuSa mode type2

FuSa byte = ECC data. (Refer to section 4.5 I2C I/F for details regarding ECC mathematical operation

specification)

As a result of ECC mathematical operation,

At 1 bit Error (Rectify error of relevant bit)

=> Execute rectification writing and assert MD2_E1 Interruption Factor bit of I2C / Thermal Error

Status register.

(Assert the INTB pin output if I2C_IMASK mask is released by I2C / Thermal Error Mask

register, and also indicate location of relevant bit on I2C MD2_E1 Bit1 register and I2C MD2_E1

Bit2 register (for P[4:0])).

At 2 bit Error (Error Detection)

=> Do not execute writing and assert MD2_E2 Interruption Factor bit of I2C / Thermal Error Status

register.

(Assert the INTB pin output if I2C_IMASK mask is released by I2C / Thermal Error Mask

register.)

“11”: Reserved

SMOD_read

FuSa Mode Read Setting

0: FuSa Mode is applied only for I2C write data.

1: FuSa Mode is applied not only I2C write data, but also I2C read data.

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5.2 Register Description – continued

5.2.3 Spread Spectrum Clock Generation Control for Internal OSC

BD9573MUF-M has built-in SSCG (Spread Spectrum Clock Generator) with center spread.

Register Name

SSCG Cnt

Address

0x13

D7

-

D6

D5

SSCG_

FORM[1:0]

D4

D3

-

D2

-

D1

-

D0

R/W Default

R/W 0x00

SSCG_

PERI

SSCG_

EN

SSCG_EN

Enable signal of SSCG

0: SSCG Disable

1: SSCG Enable

SSCG_FORM[1:0]

Selection of SSCG modulation waveform

“00”: Normal Triangle

“01”: Original waveform1 (A:B:C = 4:1:4)

“10”: Original waveform2 (A:B:C = 3:3:3)

“11”: Original waveform3 (A:B:C = 2:5:2)

f

+2.5 %

A

B

C

t

0 %

Modulation period

(1/SSCG_RERI)

-2.5 %

Figure 38. Modulation Waveform of SSCG

SSCG_PERI

0: 122 Hz

1: 7.813 kHz

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5.2 Register Description – continued

5.2.4 SMRB control Using I2C Control (Software Manual Reset for PRESETB)

The PRESETB pin output can be controlled by these registers.

Register Name

Address

0x14

D7

D6

D5

D4

D3

D2

D1

D0

R/W Default

R/W 0x00

SMRB Write Protect

SMRB_WP[7:0]

Protection register for SMRB_asrt (Software Manual Reset for PRESETB)

0x9D: SMRB assert is enabled.

Others: SMRB assert is disabled.

Register Name

SMRB Cnt

Address

0x15

D7

-

D6

-

D5

-

D4

D3

-

D2

-

D1

-

D0

R/W Default

R/W 0x01

SMRB_

hist

SMRB_

asrt

SMRB_asrt

SMRB assert register

When this register is set to “0”, PRESETB is asserted to L. After 5ms, this register value is reset to “1” and

PRESETB is negated to H automatically.

SMRB_hist

SMRB status register

If SMRB assert is occurred, this register is set to “1”. Register value does not be initialized during STANDBY state

transition. Clear condition is I2C writing “1” or UVLO.

5.2.5 Watch Dog Timer Setting

Register Name

Address

0x16

D7

-

D6

-

D5

D4

D3

D2

D1

D0

R/W Default

R/W 0x20

Watch Dog Timer

setting

TYPE

NG_RATIO[1:0]

FAST_NG[2:0]

FAST_NG[2:0], NG_RATIO[1:0]

WDT N.G. detection area setting

Regarding these registers’ function, please refer to section 4.9 WDT Function.

TYPE

0: timeout detection (SLOW N.G.)

WDT detecting type setting

1: window detection (FAST/SLOW N.G.)

(Note) I2C write to Watch Dog Timer setting register when the WDEN pin H level is prohibited.

5.2.6 Oscillator Enable in STANDBY State

Register Name

OSC Enable

Address

0x17

D7

-

D6

-

D5

-

D4

-

D3

-

D2

-

D1

-

D0

R/W Default

R/W 0x00

OSC_

EN

OSC_EN

Oscillator Enable/Disable Selection in STANDBY state

0: Oscillator Disable in STANDBY state

1: Oscillator Enable in STANDBY state

(Note) For I2C write condition in STANDBY state, 110 µs (Max) wait time after OSC_EN register = “1” is needed.

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5.2 Register Description – continued

5.2.7 The PGD pin output assert condition Setting

Register Name

PGD Setting

Address

0x18

D7

-

D6

-

D5

D4

D3

D2

D1

D0

R/W Default

R/W 0x3F

PGD_SETTING[5:0]

The PGD pin output assert condition

PGD_SETTING[0] = 0: VOUT1 PGD is not the factor of the PGD pin output,

1: VOUT1 PGD is the factor of the PGD pin output.

PGD_SETTING[1] = 0: VOUT2 PGD is not the factor of the PGD pin output,

1: VOUT2 PGD is the factor of the PGD pin output.

PGD_SETTING[2] = 0: VOUT3 PGD is not the factor of the PGD pin output,

1: VOUT3 PGD is the factor of the PGD pin output.

PGD_SETTING[3] = 0: VOUT4 PGD is not the factor of the PGD pin output,

1: VOUT4 PGD is the factor of the PGD pin output.

PGD_SETTING[4] = 0: VOUTL1 PGD is not the factor of the PGD pin output,

1: VOUTL1 PGD is the factor of the PGD pin output.

PGD_SETTING[5] = 0: VOUTS1 PGD is not the factor of the PGD pin output,

1: VOUTS1 PGD is the factor of the PGD pin output.

For example, the PGD pin output is asserted by VOUT1, VOUT2, VOUT3 and VOUT4 PGD when

PGD_SETTING[5:0] = 0x0F.

In this case, the PGD pin output is negated at any one of VOUT1, VOUT2, VOUT3 or VOUT4 discharge start

timing.

5.2.8 PMIC Internal Status

Register Name

Address

0x20

D7

-

D6

-

D5

-

D4

D3

D2

D1

D0

R/W Default

RO 0x00

NO_

EEP

PMIC Internal Status

PMIC_STATE[3:0]

PMIC Internal State

PMIC Internal State is shown in the following table.

Table 22: PMIC Internal State

PMIC_STATE[3:0] Setting Value

PMIC Internal State

0x0

0x1

0x2

SHUTDOWN

STANDBY

OSC Stable

Delay

0x3

0x4

0x5

Power-ON STANDBY

Power-ON

0x6

ACTIVE

0x7

Power-OFF

0x8

0x9 to 0xF

Power-OFF STANDBY

State transition

NO_EEP

Judgement for EEPROM installation

0: With ACK from EEPROM (EEPROM is installed)

1: Without ACK from EEPROM (EEPROM is not installed)

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5.2 Register Description – continued

5.2.9 I2C FuSa mode Error bit location

Register Name

Address

0x21

D7

D6

D5

D4

D3

D2

D1

D0

R/W

RO

Default

0x00

I2C MD2_E1 Bit 1

I2C_MD2_E1_BIT[7:0]

Error bit location at FuSa mode type2

Set “1” to the bit location where error is detected and rectified in FuSa mode type2.

Register Name

Address

0x22

D7

-

D6

-

D5

-

D4

D3

D2

D1

D0

R/W

RO

Default

0x00

I2C MD2_E1 Bit 2

I2C_MD2_E1_BIT_P[4:0]

Error bit location (P code) at FuSa mode type2

Set “1” to the bit (P code value) location where error is detected and rectified in FuSa mode type2.

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5.2 Register Description – continued

5.2.10 INTB Interruption Factor and Mask Condition

(Note) Clear condition of Status registers is I2C writing “1” or UVLO.

Register Name

Address

D7

D6

D5

D4

D3

D2

D1

D0

R/W Default

I2C / Thermal Error

Status

MD2_

E2

MD2_

E1

0x23

-

TSD

-

MD1

R/W

0x00

MD1

I2C Write Error Status in FuSa Mode Type1

0: No Interruption Factor

1: with Interruption Factor

MD2_E1

I2C Write Error Status in FuSa Mode Type2 with 1 bit error

0: No Interruption Factor

1: with Interruption Factor

MD2_E2

I2C Write Error Status in FuSa Mode Type2 with more than 2 bit error

Thermal Shutdown Detection

0: No Interruption Factor

1: with Interruption Factor

TSD

0: No Interruption Factor

1: with Interruption Factor

Register Name

Address

D7

D6

D5

D4

D3

D2

D1

D0

R/W Default

I2C_

IMASK

I2C / Thermal Error Mask

0x24

-

R/W

0x00

I2C_IMASK

FuSa Mode Error (MD1, MD2_E1, MD2_E2) Interruption Factor Mask

0: Mask Disable

1: Mask Enable

Register Name

Address

D7

D6

D5

D4

D3

D2

D1

D0

R/W Default

VOUTL1

_OVP

VOUT4

_OVP

VOUT3

_OVP

VOUT2

_OVP

VOUT1

_OVP

OVP Error Status

0x25

-

R/W

0x00

VOUTx_OVP (x = 1 to 4 and L1)

0: No Interruption Factor

1: with Interruption Factor

Over Voltage Protection Detection

Register Name

Address

D7

D6

D5

D4

D3

D2

D1

D0

R/W Default

VOUTL1

_SCP

VOUT4

_SCP

VOUT3

_SCP

VOUT2

_SCP

VOUT1

_SCP

SCP Error Status

0x26

-

R/W

0x00

VOUTx_SCP (x = 1 to 4 and L1)

0: No Interruption Factor

1: with Interruption Factor

Short Circuit Protection Detection

Register Name

Address

D7

D6

D5

D4

D3

D2

D1

D0

R/W Default

LDSW

OCP

VOUTS1

OCP

VOUT4B VOUT4A

_OCP _OCP

VOUT3

_OCP

VOUT2

_OCP

VOUT1

_OCP

OCP Error Status

0x27

-

R/W

0x00

VOUTx_OCP (x = 1 to 3, 4A, 4B and S1), LDSW_OCP

0: No Interruption Factor

Over Current Protection Detection

1: with Interruption Factor

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5.2.10 INTB Interruption Factor and Mask Condition - continued

Register Name

Address

D7

D6

D5

D4

D3

D2

D1

D0

R/W Default

VIN7_

UVP

VIN6_

UVP

VIN5_

UVP

VIN4_

UVP

VIN3_

UVP

VIN2_

UVP

VIN1_

UVP

UVP Error Status

0x2A

-

R/W

0x00

VINx_UVP (x = 1 to 7)

Under Voltage Protection

0: No Interruption Factor

1: with Interruption Factor

Register Name

Address

D7

D6

D5

D4

D3

D2

D1

D0

R/W Default

V1_HUT_

ERR

HUT_

ERR

EEP_

END

EEP_CRC

_ERR

WDT_

ERR

System Status

0x2B

-

R/W

0x00

WDT_ERR

Watch Dog Timer Error

0: No Interruption Factor

1: with Interruption Factor

EEP_CRC_ERR

CRC Error during EEPROM Load

0: No Interruption Factor

1: with Interruption Factor

EEP_END

Notification of EEPROM Load Internal State completion

0: Before EEPROM Load Completion

1: EEPROM Load is completed

HUT_ERR

Power-OFF Sequence Hang-Up Timer counts over 400 ms

0: No Interruption Factor

1: with Interruption Factor

V1_HUT_ERR

V1 Power-OFF Hang-Up Timer counts over 100 ms

0: No Interruption Factor

1: with Interruption Factor

Register Name

Address

D7

D6

D5

D4

D3

D2

D1

D0

R/W Default

V1_HUT_

E_IMASK

HUT_E_

IMASK

EEP_END

_IMASK

EEPCRC

_E_IMASK

WDT_E_

IMASK

System Status Mask

0x2C

-

R/W

0x20

WDT_E_IMASK

0: Mask Disable

1: Mask Enable

Watch Dog Timer Error Interruption Factor Mask

EEPCRC_E_IMASK

0: Mask Disable

1: Mask Enable

CRC Error during EEPROM Load Interruption Factor Mask

EEP_END_IMASK

0: Mask Disable

1: Mask Enable

Notification of EEPROM Load Internal State completion Interruption Factor Mask

Hang-Up Timer Interruption Factor Mask

HUT_E_IMASK

0: Mask Disable

1: Mask Enable

V1_HUT_E_IMASK

0: Mask Disable

1: Mask Enable

V1 Hang-Up Timer Interruption Factor Mask

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5.2.10 INTB Interruption Factor and Mask Condition - continued

Register Name

Address

D7

D6

D5

D4

D3

D2

D1

D0

R/W Default

UVP_

INT

OCP_

INT

SCP_

INT

OVP_

INT

I2CTHM

_INT

INT IntReq

0x30

SYS_INT

-

R/W

0x00

I2CTHM_INT

Primary Level Interruption Factor of I2C / Thermal Error Status Register

Primary Level Interruption Factor of OVP Error Status Register

Primary Level Interruption Factor of SCP Error Status Register

Primary Level Interruption Factor of OCP Error Status Register

Primary Level Interruption Factor of UVP Error Status Register

Primary Level Interruption Factor of System Status Register

0: No Interruption Factor

1: with Interruption Factor

OVP_INT

0: No Interruption Factor

1: with Interruption Factor

SCP_INT

0: No Interruption Factor

1: with Interruption Factor

OCP_INT

0: No Interruption Factor

1: with Interruption Factor

UVP_INT

0: No Interruption Factor

1: with Interruption Factor

SYS_INT

0: No Interruption Factor

1: with Interruption Factor

Register Name

Address

D7

D6

D5

D4

D3

D2

D1

D0

R/W Default

SYS_

IMASK

UVP_

IMASK

OCP_

IMASK

SCP_

IMASK

OVP_

IMASK

I2CTHM

_IMASK

INT IntMask

0x31

-

R/W

0x00

I2CTHM_IMASK

0: Mask Disable

1: Mask Enable

Primary Level Interruption Factor of I2C / Thermal Error Status Register Mask

Primary Level Interruption Factor of OVP Error Status Register Mask

Primary Level Interruption Factor of SCP Error Status Register Mask

Primary Level Interruption Factor of OCP Error Status Register Mask

Primary Level Interruption Factor of UVP Error Status Register Mask

Primary Level Interruption Factor of System Status Register Mask

OVP_IMASK

0: Mask Disable

1: Mask Enable

SCP_IMASK

0: Mask Disable

1: Mask Enable

OCP_IMASK

0: Mask Disable

1: Mask Enable

UVP_IMASK

0: Mask Disable

1: Mask Enable

SYS_IMASK

0: Mask Disable

1: Mask Enable

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5.2 Register Description – continued

5.2.11 POW Setting

Register Name

Address

0x40

D7

D6

D5

D4

D3

D2

D1

D0

R/W Default

R/W 0x00

POW WriteProtect

POW_WP[7:0]

Protection register for POW Trigger and POW Wait

0xAB: Access for POW registers is enabled.

Others: Access for POW registers is disabled.

Register Name

Address

0x41

D7

D6

D5

D4

D3

D2

D1

D0

R/W Default

R/W 0x20

POW Trigger VOUT1

POFF_TRG_VOUT1

PON_TRG_VOUT1

Register Name

Address

0x42

D6

D5

D2

D1

R/W Default

R/W 0x61

POW Trigger VOUT2

POFF_TRG_VOUT2

PON_TRG_VOUT2

Register Name

Address

0x43

D6

D5

D2

D1

R/W Default

R/W 0x45

POW Trigger VOUT3

POFF_TRG_VOUT3

PON_TRG_VOUT3

Register Name

Address

0x44

D6

D5

D2

D1

R/W Default

R/W 0x73

POW Trigger VOUT4

POFF_TRG_VOUT4

PON_TRG_VOUT4

Register Name

Address

0x45

D6

D5

D2

D1

R/W Default

R/W 0x36

POW Trigger VOUTL1

POFF_TRG_VOUTL1

PON_TRG_VOUTL1

Register Name

Address

0x46

D6

D5

D2

D1

R/W Default

R/W 0x52

POW Trigger

VOUTS1

POFF_TRG_VOUTS1

PON_TRG_VOUTS1

Register Name

Address

0x47

D7

D6

D5

D4

D3

D2

D1

D0

R/W Default

R/W 0x04

POW Trigger

PRESETB

POFF_TRG_PRESETB

PON_TRG_PRESETB

PON_TRG_VOUTx^{(Note 1)}

POFF_TRG_VOUTx^{(Note 1)}

Trigger Signal Setting in Power-ON Sequence

Trigger Signal Setting in Power-OFF Sequence

The Order of Power-ON Sequence and Power-OFF Sequence is selected by POW Trigger VOUTx^{(Note 1)}registers.

POW Trigger VOUTx^{(Note 1)}registers’ value can be changed by EEPROM. Regarding default value of each registers,

please refer register map.

(e.g.)

By setting PON_TRG_VOUT2 = 0x1 (VOUT1 Enable Signal), VOUT2 starts Power-ON after VOUT1.

By setting POFF_TRG_VOUTL1 = 0x03 (VOUT3 Enable Signal), VOUTL1 starts Power-OFF after VOUT3.

By setting PON_TRG_VOUTL1 = 0xFF (Always OFF Setting), VOUTL1 never Power-ON. In this case, VOUTL1 is

excluded from the Power-ON / Power-OFF sequence automatically.

Setting over 2 signals triggering one Enable Signal is prohibited.

(Note 1) VOUTx = VOUT1 to VOUT4, VOUTL1 and VOUTS1

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5.2.11 POW Setting – continued

Table 23: PON/POFF Trigger Signal

PON_TRG_VOUTx^{(Note 1)}

/ POFF_TRG_VOUTx^{(Note 1)}

PON_TRG_PRESETB

Trigger Signal

/ POFF_TRG_PRESETB

0x0

0x1

RSTB (pin) = H level (Power-ON) / L level (Power-OFF)

VOUT1 Enable Signal

0x2

VOUT2 Enable Signal

0x3

VOUT3 Enable Signal

0x4

VOUT4 Enable Signal

0x5

VOUTL1 Enable Signal

VOUTS1 Enable Signal

PRESETB (pin)

0x6

0x7

0x8 to 0xF

Always OFF Setting

Register Name

Address

0x48

D7

D6

D5

D4

D3

D2

D1

D0

R/W Default

R/W 0x00

POW Wait VOUT1

POFF_WAIT_VOUT1

PON_WAIT_VOUT1

Register Name

Address

0x49

D6

D5

D2

D1

R/W Default

R/W 0x00

POW Wait VOUT2

POFF_WAIT_VOUT2

PON_WAIT_VOUT2

Register Name

Address

0x4A

D7

D6

D5

D4

D3

D2

D1

D0

R/W Default

R/W 0x00

POW Wait VOUT3

POFF_WAIT_VOUT3

PON_WAIT_VOUT3

Register Name

Address

0x4B

D6

D5

D2

D1

R/W Default

R/W 0x00

POW Wait VOUT4

POFF_WAIT_VOUT4

PON_WAIT_VOUT4

Register Name

Address

0x4C

D6

D5

D2

D1

R/W Default

R/W 0x00

POW Wait VOUTL1

POFF_WAIT_VOUTL1

PON_WAIT_VOUTL1

Register Name

Address

0x4D

D6

D5

D2

D1

R/W Default

R/W 0x00

POW Wait VOUTS1

POFF_WAIT_VOUTS1

PON_WAIT_VOUTS1

Register Name

Address

0x4E

D6

D5

D2

D1

R/W Default

R/W 0x00

POW Wait PRESETB

POFF_WAIT_PRESETB

PON_WAIT_PRESETB

PON_WAIT_VOUTx^{(Note 1)}

POFF_WAIT_VOUTx^{(Note 1)}

Interval Setting in Power-ON Sequence

Interval Setting in Power-OFF Sequence

The Interval of Power-ON Sequence and Power-OFF Sequence is selected by POW Wait VOUTx^{(Note 1)}registers.

POW Wait VOUTx^{(Note 1)}registers’ value can be changed by EEPROM. Regarding default value of each registers,

please refer register map.

(Note 1) VOUTx = VOUT1 to VOUT4, VOUTL1 and VOUTS1

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5.2.11 POW Setting – continued

Table 24: PON/POFF Interval

PON_WAIT_VOUTx^{(Note 1)}

/ POFF_WAIT_VOUTx^{(Note 1)}

PON_WAIT_PRESETB

Interval

/ POFF_WAIT_PRESETB

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

2 µs

500 µs

1 ms

2 ms

4 ms

5 ms

8 ms

10 ms

15 ms

20 ms

25 ms

30 ms

40 ms

45 ms

50 ms

60 ms

Please set Power-OFF interval not to exceed totally 400 ms (Power-OFF Sequence Hang Up Timer).

(Note 1) VOUTx = VOUT1 to VOUT4, VOUTL1 and VOUTS1

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5.2 Register Description – continued

5.2.12 VOUT Voltage SET

These VOUT voltage tuning registers are set via external EEPROM.

Register Name

VOUT1 TUNE

Address

0x50

D7

D6

-

D5

-

D4

-

D3

-

D2

D1

D0

R/W Default

V1_

SIGN

VOUT1_TUNE[2:0]

RO

0x00

V1_SIGN

VOUT1 Sign Bit

0: Plus

1: Minus

VOUT1_TUNE[2:0]

VOUT1 Tuning Bit

VOUT1 output voltage is tuned from default value (5.0 V) by these registers. Step: 100 mV.

Table 25: VOUT1 Tuning Voltage

VOUT1_TUNE[2:0]

Tuning Voltage (mV)

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0

100

200

300

400

500

Clipped to 500

Register Name

VOUT2 TUNE

Address

0x53

D7

D6

-

D5

-

D4

-

D3

-

D2

D1

D0

R/W

RO

Default

0x00

V2_

SIGN

VOUT2_TUNE[2:0]

V2_SIGN

VOUT2 Sign Bit

0: Plus

1: Minus

VOUT2_TUNE[2:0]

VOUT2 Tuning Bit

VOUT2 output voltage is tuned from default value (1.8 V) by these registers. Step: 20 mV.

Table 26: VOUT2 Tuning Voltage

VOUT2_TUNE[2:0] Tuning Voltage (mV)

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0

20

40

60

80

100

120

140

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5.2.12 VOUT Voltage SET – continued

Register Name

VOUT3 TUNE

Address

0x56

D7

D6

-

D5

-

D4

D3

D2

D1

D0

R/W Default

V3_

SIGN

VOUT3_TUNE[4:0]

RO

0x00

V3_SIGN

VOUT3 Sign Bit

0: Plus

1: Minus

VOUT3_TUNE[4:0]

VOUT3 Tuning Bit

VOUT3 output voltage is tuned from default value (1.35 V, 1.5 V) by these registers. Step: 10 mV.

Table 27: VOUT3 Tuning Voltage

VOUT3_TUNE[4:0] Tuning Voltage (mV)

0x0

0x1

0

10

0x2

20

……

0x1D

0x1E

0x1F

……

290

300

310

Register Name

VOUT4 TUNE

Address

0x59

D7

D6

-

D5

-

D4

D3

D2

D1

D0

R/W Default

V4_

SIGN

VOUT4_TUNE[4:0]

RO

0x00

V4_SIGN

VOUT4 Sign Bit

0: Plus

1: Minus

VOUT4_TUNE[4:0]

VOUT4 Tuning Bit

VOUT4 output voltage is tuned from default value (1.03 V) by these registers. Step: 10 mV.

Table 28: VOUT4 Tuning Voltage

VOUT4_TUNE[4:0] Tuning Voltage (mV)

0x0

0x1

0

10

0x2

20

……

0x1D

0x1E

0x1F

……

290

300

310

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5.2.12 VOUT Voltage SET – continued

Register Name

VOUTL1 TUNE

Address

0x5C

D7

D6

-

D5

-

D4

-

D3

-

D2

D1

D0

R/W Default

RO 0x00

VL1_

SIGN

VOUTL1_TUNE[2:0]

VL1_SIGN

VOUTL1 Sign Bit

0: Plus

1: Minus

VOUTL1_TUNE[2:0]

VOUTL1 Tuning Bit

VOUTL1 output voltage is tuned from default value (2.5 V) by these registers. Step: 40 mV.

Table 29: VOUTL1 Tuning Voltage

VOUTL1_TUNE[2:0] Tuning Voltage (mV)

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0

40

80

120

160

200

240

280

5.2.13 VOUTS1 OCP SET

Register Name

VOUTS1 OCP

Address

0x60

D7

-

D6

-

D5

D4

D3

D2

D1

D0

R/W Default

0x16/

R/W

VOUTS1_OCP[5:0]

0x08

VOUTS1_OCP[5:0]

VOUTS1 OCP setting. Step: 50 mA (Internal Mode), 10 mV (External Mode)

Default value is determined by GATECNT (pin) condition.

GATECNT (pin) = L: Default value is 0x16 (Internal: 1100 mA).

GATECNT (pin) = H: Default value is 0x08 (External: 90 mV).

Table 30: VOUTS1 OCP Current (Internal) and Voltage (External)

VOUTS1_OCP_SET[5:0]

Internal OCP Current (mA) External OCP Voltage (mV)

0x00

0x00 to 0x05

0x06

Function Disable

Clipped to 300

300

Clipped to 70

70

350

400

0x07

80

90

0x08

……

1100

……

0x16

230

……

1350

0x1B

280

Clipped 1350

0x1C to 0x3F

Clipped to 280

Internal OCP Current has ±50 % of deviation.

This is because it depends on Ron of internal SW.

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Typical Performance Curves

Unless otherwise specified: VIN = 3.3 V, Ta = 25 °C, IOUT = 0 A

Line Regulation

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

4.80

1.86

1.84

1.82

1.80

1.78

1.76

1.74

3.00

3.30

3.60

3.00

3.30

3.60

VIN [V]

Figure 39. VOUT1 Output Voltage vs VIN

Figure 40. VOUT2 Output Voltage vs VIN

1.55

1.54

1.53

1.52

1.51

1.50

1.49

1.48

1.47

1.46

1.45

1.40

1.39

1.38

1.37

1.36

1.35

1.34

1.33

1.32

1.31

1.30

3.00

3.30

3.60

3.00

3.30

3.60

VIN [V]

Figure 41. VOUT3 Output Voltage vs VIN

(VOUT3 = 1.35 V Setting)

Figure 42. VOUT3 Output Voltage vs VIN

(VOUT3 = 1.5 V Setting)

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6.1 Line Regulation - continued

2.60

2.55

2.50

2.45

2.40

1.07

1.06

1.05

1.04

1.03

1.02

1.01

1.00

0.99

3.00

3.30

3.60

3.00

3.30

3.60

VIN [V]

Figure 44. VOUTL1 Output Voltage vs VIN

Figure 43. VOUT4 Output Voltage vs VIN

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6. Typical Performance Curves – continued

Load Regulation

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

4.80

1.86

1.84

1.82

1.80

1.78

1.76

1.74

0.00

0.50

1.00

0

100

200

IOUT [A]

IOUT [mA]

Figure 46. VOUT2 Output Voltage vs IOUT

Figure 45. VOUT1 Output Voltage vs IOUT

1.55

1.54

1.53

1.52

1.51

1.50

1.49

1.48

1.47

1.46

1.45

1.40

1.39

1.38

1.37

1.36

1.35

1.34

1.33

1.32

1.31

1.30

0.00

1.00

2.00

0.00

1.00

2.00

IOUT [A]

Figure 47. VOUT3 Output Voltage vs IOUT

(VOUT3 = 1.35 V Setting)

Figure 48. VOUT3 Output Voltage vs IOUT

(VOUT3 = 1.5 V Setting)

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6.2 Load Regulation - continued

1.07

1.06

1.05

1.04

1.03

1.02

1.01

1.00

0.99

2.60

2.55

2.50

2.45

2.40

0

50

100

150

0.00

1.00

2.00

3.00

4.00

5.00

IOUT [mA]

IOUT [A]

Figure 49. VOUT4 Output Voltage vs IOUT

Figure 50. VOUTL1 Output Voltage vs IOUT

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6. Typical Performance Curves – continued

Power Efficiency

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

50

100

150

200

0

0.25

0.5

0.75

1

IOUT [mA]

IOUT [A]

Figure 51. VOUT1 Power Efficiency vs IOUT

Figure 52. VOUT2 Power Efficiency vs IOUT

100

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

IOUT [A]

Figure 53. VOUT3 Power Efficiency vs IOUT

(VOUT3 = 1.35 V Setting)

Figure 54. VOUT3 Power Efficiency vs IOUT

(VOUT3 = 1.5 V Setting)

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6.3 Power Efficiency -continued

100

90

80

70

60

50

40

30

20

10

0

0.0

1.0

2.0

3.0

4.0

5.0

IOUT [A]

Figure 55. VOUT4 Power Efficiency vs IOUT

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6. Typical Performance Curves – continued

Power ON Waveform

VOUT1 (1 V/div)

VOUT2 (500 mV/div)

SW1 (2 V/div)

SW2 (2 V/div)

500 µs/div

Figure 56. VOUT1 Power ON Waveform

Figure 57. VOUT2 Power ON Waveform

VOUT3 (500 mV/div)

SW3 (2 V/div)

500 µs/div

Figure 58. VOUT3 Power ON Waveform

(VOUT3 = 1.35 V Setting)

Figure 59. VOUT3 Power ON Waveform

(VOUT3 = 1.5 V Setting)

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6.4 Power ON Waveform- continued

VOUTL1 (500 mV/div)

VOUT4 (500 mV/div)

SW4 (2 V/div)

SW5 (2 V/div)

500 µs/div

Figure 60. VOUT4 Power ON Waveform

Figure 61. VOUTL1 Power ON Waveform

VOUTS1 (500 mV/div)

500 µs/div

Figure 62. VOUTS1 Power ON Waveform

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6. Typical Performance Curves – continued

Power OFF Waveform

VOUT1 (1 V/div)

VOUT2 (500 mV/div)

SW1 (2 V/div)

SW2 (2 V/div)

2 ms/div

5 ms/div

Figure 63. VOUT1 Power OFF Waveform

Figure 64. VOUT2 Power OFF Waveform

VOUT3 (500 mV/div)

SW3 (2 V/div)

5 ms/div

Figure 65. VOUT3 Power OFF Waveform

(VOUT3 = 1.35 V Setting)

Figure 66. VOUT3 Power OFF Waveform

(VOUT3 = 1.5 V Setting)

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6.5 Power OFF Waveform- continued

VOUT4 (500 mV/div)

VOUTL1 (500 mV/div)

SW4 (2 V/div)

SW5 (2 V/div)

2 ms/div

5 ms/div

Figure 67. VOUT4 Power OFF Waveform

Figure 68. VOUTL1 Power OFF Waveform

VOUTS1 (500 mV/div)

500 µs/div

Figure 69. VOUTS1 Power OFF Waveform

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6. Typical Performance Curves – continued

Load Transient

IOUT (200 mA/div)

IOUT (50 mA/div)

VOUT (20 mV/div)

VOUT (10 mV/div)

20 µs/div

50 µs/div

Figure 70. VOUT1 Load Transient

(IOUT = 0 A to 100 mA (SR = 100 mA/µs))

Figure 71. VOUT2 Load Transient

(IOUT = 0 A to 0.5 A (SR = 1 A/µs))

IOUT (500 mA/div)

VOUT (10 mV/div)

20 µs/div

Figure 72. VOUT3 Load Transient

Figure 73. VOUT3 Load Transient

(VOUT3 = 1.35 V Setting, IOUT = 0 A to 1 A (SR = 1 A/µs))

(VOUT3 = 1.5 V Setting, IOUT = 0 A to 1 A (SR = 1 A/µs))

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6.6 Load Transient- continued

IOUT (30 mA/div)

IOUT (1 A/div)

VOUT (10 mV/div)

VOUT (20 mV/div)

20 µs/div

100 µs/div

Figure 74. VOUT4 Load Transient

(IOUT = 0 A to 2.05 A (SR = 1 A/µs))

Figure 75. VOUTL1 Load Transient

(IOUT = 0 A to 75 mA (SR = 100 mA/µs)

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Operational Notes

1.

Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply

pins.

2.

Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the

digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog

block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and aging

on the capacitance value when using electrolytic capacitors.

3.

4.

Ground Voltage

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. However,

pins that drive inductive loads (e.g. motor driver outputs, DC-DC converter outputs) may inevitably go below ground due

to back EMF or electromotive force. In such cases, the user should make sure that such voltages going below ground

will not cause the IC and the system to malfunction by examining carefully all relevant factors and conditions such as

motor characteristics, supply voltage, operating frequency and PCB wiring to name a few.

Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations on

the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5.

6.

Recommended Operating Conditions

The function and operation of the IC are guaranteed within the range specified by the recommended operating

conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical

characteristics.

Inrush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow

instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.

Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of

connections.

7.

Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject

the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should

always be turned off completely before connecting or removing it from the test setup during the inspection process. To

prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and

storage.

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7. Operational Notes – continued

8.

Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and

unintentional solder bridge deposited in between pins during assembly to name a few.

9.

Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and

extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge

acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause

unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power

supply or ground line.

10. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example (refer to figure below):

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to

operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be

avoided.

Resistor

Transistor (NPN)

Pin A

Pin B

B

E

C

Pin A

B

C

E

P

P⁺

N

P⁺

P

P⁺

N

Parasitic

Elements

Parasitic

Elements

P Substrate

GND GND

P Substrate

GND

Parasitic

Elements

Parasitic

Elements

N Region

close-by

Figure 76. Example of Monolithic IC Structure

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7.

Operational Notes – continued

11. Ceramic Capacitor

When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with

temperature and the decrease in nominal capacitance due to DC bias and others.

12. Thermal Shutdown Circuit (TSD)

This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always be

within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the

junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. The IC should

be powered down and turned ON again to resume normal operation because the TSD circuit keeps the outputs at the

OFF state even if the Tj falls below the TSD threshold.

Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no

circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat

damage.

13. Over Current Protection Circuit (OCP)

This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This

protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should not

be used in applications characterized by continuous operation or transitioning of the protection circuit.

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Revision History

Date

Revision

001

Changes

29.May.2020

New Release

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Notice

Precaution on using ROHM Products

(Note 1)

1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment

,

aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,

bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales

representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any

ROHM’s Products for Specific Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.

Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the

use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our

Products under any special or extraordinary environments or conditions (as exemplified below), your independent

verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.

However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble

cleaning agents for cleaning residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PAA-E

Rev.004

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl₂, H₂S, NH₃, SO₂, and NO₂

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PAA-E

Rev.004


型号：	BD9573MUF-M
厂家：	ROHM
描述：	BD9573MUF-M is a Power Management Integrated Circuit (PMIC) designed specifically for use on R-Car series processor for In-Vehicle Infotainment (IVI) systems and Instrument Cluster Panel. 集成电源管理电路
文件：	总84页 (文件大小：3390K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BD9573MUF-M [ROHM]

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