BD9596BMWV-M [ROHM]
BD9596BMWV-M (Jarrell Cove) is a Power Management Integrated Circuit (PMIC) designed specifically for use on Intel® Atom™ E3800 series processors (Bay Trail-I platform) for in-vehicle infotainment (IVI) systems, industrial control systems.;
| 型号： | BD9596BMWV-M |
| 厂家： | 
ROHM |
| 描述： | BD9596BMWV-M (Jarrell Cove) is a Power Management Integrated Circuit (PMIC) designed specifically for use on Intel® Atom™ E3800 series processors (Bay Trail-I platform) for in-vehicle infotainment (IVI) systems, industrial control systems. 集成电源管理电路 |
| 文件： | 总78页 (文件大小：2744K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
Power Management IC for
Intel® AtomTM E3800 series
BD9596BMWV-M (Code name: Jarrell Cove)
General Description
Key Specifications
BD9596BMWV-M (Jarrell Cove) is a Power Management
Integrated Circuit (PMIC) designed specifically for use on
Intel® AtomTM E3800 series processors (Bay Trail-I
platform) for in-vehicle infotainment (IVI) systems,
industrial control systems.
Input Voltage Range:
VCC Output Voltage Range:
VCC Output Current:
(Output current depends on external component)
VNN Output Voltage Range:
VNN Output Current:
3.5V to 5.5V
0.5V to 1.2V
13.541A (Max)
0.5V to 1.2V
13.207A (Max)
Features
(Output current depends on external component.)
Complicated Power up / down sequence and state
control are embedded.
V1P0A Output Voltage:
V1P0A Output Current:
V1P0S Output Voltage:
V1P0S Output Current:
1.0V (Typ)
0.7A (Max)
1.0V (Typ)
Fewer external components count / compact size.
Controlling power regulation for each state (S4/S5, S3
and S0) results in a low power consumption.
Built-in reference clock (RTCCLK): 32.768kHz±5% to
reduce boot up time.
2.667A (Max)
(Output current depends on external component)
V1P05S Output Voltage:
V1P05S Output Current:
V1P24A Output Voltage:
V1P24A Output Current:
V1P24S Output Voltage:
V1P24S Output Current:
VSFR Output Voltage:
VSFR Output Current:
V1P8A Output Voltage:
V1P8A Output Current:
V1P8S Output Voltage:
V1P8S Output Current:
VSDIO Output Voltage:
VSDIO Output Current:
V3P3A Output Voltage:
V3P3A Output Current:
V3P3S Output Voltage:
V3P3S Output Current:
VRTC Output Voltage:
VRTC Output Current:
VDDQ Output Voltage Range:
VDDQ Output Current:
1.05V (Typ)
1.322A (Max)
1.24V (Typ)
0.05A (Max)
1.24V (Typ)
0.05A (Max)
1.35V (Typ)
0.5A (Max)
Power control logic with processor interface and event
detection.
SVID interface for control and register access.
Error mode indicator for debugging.
Built-in UVLO, SCP, OVP and TSD protection.
AEC-Q100 qualified (Note1)
.
1.8V (Typ)
1.8A (Max)
1.8V (Typ)
0.8A (Max)
(Note1:Grade3)
Applications
In-vehicle infotainment (IVI) systems
Industrial control systems
Intelligent vending systems
ATM
Point-of-sale (POS) terminals
etc
1.8V or 3.3V (Typ)
0.02A (Max)
3.3V (Typ)
0.1A (Max)
3.3V (Typ)
0.5A (Max)
3.3V (Typ)
0.12A (Max)
1.2V to 1.6V
4.51A (Max)
(Output current depends on external component.)
VTT Output Voltage:
VDDQ/2 (Typ)
0.53A (Max)
1MHz (Typ)
120mΩ(Typ)
VTT Output Current:
Switching Frequency:
Pch FET ON Resistance:
(V1P0A, V1P8A, V1P05S)
120mΩ(Typ)
Nch FET ON Resistance:
(V1P0A, V1P8A, V1P05S)
Operating Temperature Range:
-40℃ to +95℃
Package(s)
UQFN88MV0100
W(Typ) x D(Typ) x H(Max)
10.0mm x 10.0mm x 1.00mm
○Product structure：Silicon monolithic integrated circuit ○This product has no designed protection against radioactive rays.
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BD9596BMWV-M
Block Diagram
3.5V-5.5V
C1
5VIN_D
5VIN_A
U1
5VIN_A
DCDC5
VDD3
R1
C3
C25
C2
BG (1.2V)
UVLO
TSD
L5
Reference
block
SW_V1P05S
V1P05S
LDO1
VRTC
3.3V/0.12A
1.05V/1.332A
C26
S0
VDD3
PGND
LDO2
LDO3
LDO4
LDO5
V3P3A
S4/S5
FB_V1P05S
BOOT_VCC
3.3V/0.1A
C4
C5
C6
V3P3S
3.3V/0.5A
S0
C28
M5
M6
C27
HG_VCC
SW_VCC
LG_VCC
S0
L6
DCDC6
VCC
V1P24A
1.24V/0.05A
S4/S5
VID for VCC
C29
0.5～1.2V/13.541A
output current
depends on
external
R6
C30
PGND
Is+_VCC
VSDIO
3.3V or 1.8V
/0.02A
SDMMC3_PWREN_B
VDD1
R10
Is-_VCC
C7
component
Remote+_VCC
Remote-_VCC
SDMMC3_1P8EN_B
5VIN_A
VCC+
VCC-
VDD2
BOOT_VNN
C8
L1
SW_V1P0A
C32
M7
M8
V1P0A
1.0V/0.7A
DCDC1
S4/S5
VDD3
C31
HG_VNN
SW_VNN
LG_VNN
L7
S0
VNN
C9
DCDC7
PGND
C33
VID for VNN
FB_V1P0A
0.5～1.2V/13.207A
output current
depends on
external
R7 C34
R11
PGND
Is+_VNN
BOOT_V1P0S
Is-_VNN
Remote+_VNN
Remote-_VNN
M1
M2
C10
component
C11
L2
HG_V1P0S
SW_V1P0S
LG_V1P0S
VNN+
VNN-
V1P0S
DCDC2
S0
1.0V/2.667A
output current
depends on
external
C13
C12
R2
PGND
VRTC
Reference
clock
IS+_V1P0S
IS-V1P0S
FB_V1P0S
RTCCLK
R8
R12
R15
component
R13
R14
TEMP_COMP
OCP setting
voltage
5VIN_A
DCDC3
VDD1
C14
V3P3DIN
S0
S3 S4/S5
VRTC
L3
SW_V1P8A
V1P8A
S4/S5
1.8V/1.8A
RSMRST_B (Bay Trail)
DRAMPWROK (Bay Trail)
C15
PGND
COREPWROK (Bay Trail)
RTEST_B (Bay Trail)
PWRBTN_B (Bay Trail)
SUS_STAT_B (ICM)
FB_V1P8A
V1P8A_IN1
C16
UVLO
TSD
SLP_S3_B (Bay Trail)
SLP_S4_B (Bay Trail)
SRTC_RST_B (Bay Trail)
SUSPWRDNACK (Bay Trail)
SW1
Controller
V1P8S
1.8V/0.8A
S0
C17
V1P8A_IN2
V1P24S
1.24V/0.05A
LDO6
LDO8
SDMMC3_PWREN_B (Bay Trail)
SDMMC3_1P8_EN (Bay Trail)
POWER_ON (ICM)
SYNC (ICM)
S0
S0
C18
C35
VDD2
VSFR
1.35V/0.5A
ERROR
BOOT_VDDQ
VRTC VRTC
M3
M4
C19
C20
L4
HG_VDDQ
SW_VDDQ
LG_VDDQ
VDDQ
4.7kohm
4.7kohm
1.2-1.6V/4.51A
output current
depends on
external
DCDC4
S3
DATA
CLK
C22
R3
C21
PGND
VID for VCC VID for VNN
component
IS+_VDDQ
R9
IS-_VDDQ
FB_VDDQ
R4
R5
SVID_DATA (Bay Trail)
SVID_CLK (Bay Trail)
SVID_ALERT_B (Bay Trail)
SVID
Interface
VDDQIN
PGND
C23
C24
spare pin
AGND
LDO7
VTT
S0
VDDQ/2 V/0.530A
Figure 1. Block Diagram
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Component Selection
Table 1: Component Selection
Part No
Value
Compan
y
Part name
Part No
C1
C2
C3
C4
C5
C6
C7
Value
10uF
10uF
10uF
10uF
10uF
10uF
1uF
22uF
47uF
22uF
0.1uF
47uF x 2
0.1uF
22uF
47uF x 2
10uF
10uF
Company
Part name
U1
R1
R2
R3
R4
R5
R6
R7
-
1
560
1k
11k
16k
620
620
1k
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
MURATA
ROHM
ROHM
Taiyo
BD9596BMWV-M
C8
C9
R8
R9
2k
C10
C11
C12
C13
C14
C15
C16
C17
R10
R11
R12
R13
R14
R15
L1
910
910
8.2k
10k
8.2k
2.7k
6.8uH
NCP18X103F0SRB
NR3012
Yuden
L2
L3
L4
L5
L6
L7
1.0uH
3.3uH
1.0uH
3.3uH
Taiyo
Yuden
Taiyo
Yuden
VISHAY
NRS4018
NRS4018
C18
C19
C20
C21
C22
C23
10uF
10uF x 2
0.1uF
IHLP-2020-CZ
ER1R0MA1e3
NRS4018
Taiyo
Yuden
47uF x 2
0.1uF
0.33uH VISHAY
0.33uH VISHAY
IHLP-2020-CZ
ER0R33MA1e3
IHLP-2020-CZ
ER0R33MA1e3
SQA410EJ
SQA410EJ
SQA410EJ
10uF
M1
M2
M3
M4
M5
M6
M7
M8
VISHAY
VISHAY
VISHAY
VISHAY
Infineon
C24
C25
C26
C27
10uF
10uF x 2
47uF x 2
10uF x 4
0.1uF
220uF x 2
47uF x 2
0.1uF
SQA410EJ
IPG20N04S4L-08
C28
C29_1
C29_2
C30
Panasonic
Panasonic
2R5TAE220M9
2R5TAE220M9
Infineon
IPG20N04S4L-08
C31
C32
C33_1
C33_2
C34
10uF x 4
0.1uF
220uF x 2
47uF x 2
0.1uF
C35
10uF
*These values and parts may be changed for improvement etc.
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BD9596BMWV-M
Pin Configuration
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
1
2
66
REMOTE_P_VNN
IS_M_VNN
IS_P_VNN
PGND1
IS_P_VDDQ
65
IS_M_VDDQ
3
64
FB_VDDQ
4
63
BOOT_VDDQ
5
62
LG_VNN
HG_VDDQ
6
61
SW_VNN
SW_VDDQ
7
60
HG_VNN
LG_VDDQ
8
59
BOOT_VNN
VDD1
PGND5
9
58
FB_V1P0A
10
11
12
13
14
15
16
17
18
19
20
21
22
57
SW_V1P8A
PGND2
VDD2
56
SW_V1P0A
55
FB_V1P8A
V1P8S
PGND4
54
VDDQ_IN
53
V1P8S
VTT
52
V1P8A_IN1
V1P8A_IN1
VSFR
PGND3
51
RTEST_B
50
RSMRST_B
49
V1P8A_IN2
V1P24S
DRAMPWROK
48
COREPWROK
47
SRTC_RST_B
SUS_STAT_B
ERROR
DATA
46
CLK
45
PWRBTN_B
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Figure 2. Pin Configuration
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Pin Description
Table 2: BD9596BMWV-M Pin Description
Pin No.
Pin Name
Connect to
PMIC
I/O
I
Function
VNN output remote sensing pin
1
REMOTE_P_VNN
2
IS_M_VNN
IS_P_VNN
PGND1
PMIC
PMIC
-
I
Negative input of current sensing pin for VNN
Positive input of current sensing pin for VNN
Power GND pin1
3
I
4
-
5
LG_VNN
External
External
External
PMIC
POWER
External
-
O
Low side MOSFET gate driver pin for VNN
High side MOSFET source pin for VNN
High side MOSFET gate driver pin for VNN
6
SW_VNN
O
7
HG_VNN
O
8
BOOT_VNN
VDD1
I
High side MOSFET driver power supply pin for VNN
Power supply pin for V1P8A
High side MOSFET source pin for V1P8A
Power GND pin2
9
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SW_V1P8A
PGND2
O
-
FB_V1P8A
V1P8S
PMIC
SOC
I
Feedback pin for V1P8A
Output voltage for V1P8S
Output voltage for V1P8S
1.8V power supply pin1
O
V1P8S
SOC
O
V1P8A_IN1
V1P8A_IN1
VSFR
POWER
POWER
SOC
I
I
1.8V power supply pin1
O
Output voltage for VSFR
1.8V power supply pin2
V1P8A_IN2
V1P24S
POWER
SOC
I
O
Output voltage for V1P24S
RTC detect signal pin
SRTC_RST_B
SUS_STAT_B
ERROR
SOC
O
Platform
-
O
SUS_STAT_B pin
O
ERROR signal pin
Input signal from Bay Trail; indicates S4 state entry upon
assertion and exit upon de-assertion
Input signal form Bay Trail; indicates S3 state entry upon
assertion and exit upon de-assertion
SLP_S4_B
SLP_S3_B
SDMMC3_1P8_EN
SDMMC3_PWR_EN_B
SYNC
SOC
I
SOC
I
SOC
I
Input signal from SOC (select 1.8V or 3.3V for SD)
Input signal to enable SD card power
External synchronous clock input
Spare pin1
SOC
I
Platform
-
I
SPARE1
O (OD)
I
SVID_CLK
SVID_DATA
SOC
SVID clock
SOC
I/O (OD) SVID data
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Pin Description – continued
Pin No.
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
Pin Name
SVID_ALERT_B
SUSPWRDNACK
RTCCLK
Connect to
SOC
SOC
SOC
POWER
POWER
-
I/O
Function
O (OD)
SVID alert
Input signal from Bay Trail that turns off the SUS rails in
junction with the assertion of SLP_S4_B.
I
O
32kHz clock output pin
V3P3DIN
V5IN_A
I
Logic power supply pin
I
5V power supply pin
AGND1
-
Analog GND pin1
V3P3S
SOC
POWER
SOC
-
O
Output voltage for V3P3S
5V power supply pin
V5IN_D
I
V3P3A
O
Output voltage for V3P3A
Output voltage for VRTC
Output voltage for V1P24A
Output voltage for VSDIO
Over current protect voltage setting pin
POWER_ON pin
VRTC
O
V1P24A
SOC
SOC
PMIC
Platform
SOC
-
O
VSDIO
O
TEMP_COMP
POWER_ON
PWRBTN_B
CLK
I
I
O (OD)
Boot up signal output pin
Connect 4.7kohm resisters to VRTC
Connect 4.7kohm resisters to VRTC
-
DATA
-
-
COREPWROK asserts when all voltage rails that are ON in
S0
DRAMPWROK asserts when voltage rail VDDQ is within
10% of its normal voltage
COREPWROK
DRAMPWROK
RSMRST_B
RTEST_B
PGND3
SOC
SOC
SOC
SOC
-
O (OD)
O (OD)
O (OD)
RSMRST_B asserts when voltage rail V3P3A is valid
TEST Pin
O (OD)
-
O
I
Power GND pin3
VTT
DDR
POWER
-
Output voltage for VTT
VDDQ_IN
PGND4
VDDQ power supply pin
-
Power GND pin4
SW_V1P0A
VDD2
External
POWER
PMIC
-
O
I
High side MOSFET source pin for V1P0A
Power supply pin for V1P0A
Feedback pin for V1P0A
FB_V1P0A
PGND5
I
-
Power GND pin5
LG_VDDQ
SW_VDDQ
HG_VDDQ
External
External
External
O
O
O
Low side MOSFET gate driver pin for VDDQ
High side MOSFET source pin for VDDQ
High side MOSFET gate driver pin for VDDQ
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Pin Description – continued
Pin No.
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
Pin Name
BOOT_VDDQ
FB_VDDQ
Connect to
PMIC
PMIC
PMIC
PMIC
PMIC
External
External
External
-
I/O
I
Function
High side MOSFET driver power supply pin for VDDQ
Feedback pin for VDDQ
I
IS_M_VDDQ
IS_P_VDDQ
BOOT_V1P0S
HG_V1P0S
SW_V1P0S
LG_V1P0S
PGND6
I
Negative input of current sensing pin for VDDQ
Positive input of current sensing pin for VDDQ
High side MOSFET driver power supply pin for V1P0S
High side MOSFET gate driver pin for V1P0S
High side MOSFET source pin for V1P0S
Low side MOSFET gate driver pin for V1P0S
Power GND pin6
I
I
O
O
O
-
IS_P_V1P0S
IS_M_V1P0S
FB_V1P0S
FB_V1P05S
PGND7
PMIC
PMIC
PMIC
PMIC
-
I
Positive input of current sensing pin for V1P0S
Negative input of current sensing pin for V1P0S
Feedback pin for V1P0S
I
I
I
Feedback pin for V1P05S
-
Power GND pin7
SW_V1P05S
VDD3
External
POWER
PMIC
External
External
External
-
O
I
High side MOSFET source pin for V1P05S
Power supply pin for V1P05S
BOOT_VCC
HG_VCC
I
High side MOSFET driver power supply pin for VCC
High side MOSFET gate driver pin for VCC
High side MOSFET source pin for VCC
Low side MOSFET gate driver pin for VCC
Power GND pin8
O
O
O
-
SW_VCC
LG_VCC
PGND8
IS_P_VCC
PMIC
PMIC
PMIC
PMIC
PMIC
I
Positive input of current sensing pin for VCC
Negative input of current sensing pin for VCC
VCC output remote sensing pin
IS_M_VCC
REMOTE_P_VCC
REMOTE_M_VCC
REMOTE_M_VNN
I
I
I
VCC GND remote sensing pin
I
VNN GND remote sensing pin
*OD=Open Drain
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BD9596BMWV-M
Package Outline
(UNIT: mm)
PKG: UQFN88MV0100
Figure 3. Package Outline
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BD9596BMWV-M
Footprint Dimension
(UNIT: mm)
PKG: UQFN88MV0100
Figure 4. Footprint Dimension
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BD9596BMWV-M
Ordering Information
B D 9 5 9 6 B M W V
ME 2
Part Number
Package
Packaging and forming specification
MWV: UQFN88MV0100 E2: Embossed tape and reel
Physical Dimension Tape and Reel Information
<Tape and Real Information>
Tape
Embossed carrier tape (with dry pack)
Quantity
1000pcs
E2
Direction of feed
Marking Diagram
Table 3: Marking Diagram and 3D image of package
UQFN88MV0100
10.00mm x 10.00mm x 1.00mm
UQFN88MV0100 (TOP VIEW)
Part Number Marking
LOT Number
1234567890
1PIN MARK
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Table of Contents
1.
2.
Device Feature...................................................................................................................................................................12
Output Features..............................................................................................................................................................12
Output Voltage Table ......................................................................................................................................................12
Power Management Diagram for Jarrell Cove PMIC......................................................................................................13
Power Rail Diagram for Jarrell Cove PMIC ....................................................................................................................14
Application .........................................................................................................................................................................15
Power-up Sequence.......................................................................................................................................................15
Power-down Sequence ..................................................................................................................................................17
Logic Block Diagram.......................................................................................................................................................19
Input Capacitor Selection ...............................................................................................................................................20
Bootstrap Capacitor........................................................................................................................................................20
Inductor Current Sensing................................................................................................................................................20
SYNC function................................................................................................................................................................21
Electrical Characteristics....................................................................................................................................................22
Absolute Maximum Ratings (Ta=25ºC)...........................................................................................................................22
Recommended Operating Conditions (Ta=25ºC)............................................................................................................23
DC Characteristics..........................................................................................................................................................24
Protection Mode (Under Voltage Lock Out)....................................................................................................................28
Protection Mode (Thermal Shut Down) ..........................................................................................................................28
Protection Mode .............................................................................................................................................................28
DAC Code for VCC and VNN .........................................................................................................................................29
Serial VID Command......................................................................................................................................................31
Register Code.................................................................................................................................................................32
Typical Performance Curves..............................................................................................................................................37
Load Regulation .............................................................................................................................................................37
Temperature Characteristics...........................................................................................................................................41
Efficiency ........................................................................................................................................................................45
Transient Response........................................................................................................................................................47
Sequence...........................................................................................................................................................................51
State Machine.................................................................................................................................................................51
Cold Boot Timing Chart ..................................................................................................................................................52
Cold Off Timing Chart .....................................................................................................................................................53
Enter SOC S4 Timing Chart ...........................................................................................................................................54
Exit SOC S4 Timing Chart..............................................................................................................................................55
Enter SOC S3 Timing Chart ...........................................................................................................................................56
Exit SOC S3 Timing Chart..............................................................................................................................................57
I/O Interface Signals.......................................................................................................................................................58
I/O Equivalent Circuit .........................................................................................................................................................61
Operational Notes ..............................................................................................................................................................71
Power Dissipation ..............................................................................................................................................................73
Soldering Condition............................................................................................................................................................74
History................................................................................................................................................................................75
1.1
1.2
1.3
1.4
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3.
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.
5.
4.1
4.2
4.3
4.4
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
6.
7.
8.
9.
10.
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1. Device Feature
1.1 Output Features
(Bay Trail)
IMVP7Lite compliant DC/DC regulator VCC (0.5V-1.2V / 13.541A (output current depends on external component))
IMVP7Lite compliant DC/DC regulator VNN (0.5V-1.2V / 13.207A (output current depends on external component))
DCDC regulator V1P0A (1.0V / 0.700A)
DCDC regulator V1P0S (1.0V / 2.667A (output current depends on external component))
DCDC regulator V1P05S (1.05V / 1.322A)
LDO V1P24A (1.24V / 0.050A)
LDO V1P24S (1.24V / 0.050A)
LDO VSFR (1.35V / 0.500A)
DCDC regulator V1P8A (1.8V / 1.800A)
Load switch V1P8S (1.8V / 0.800A)
LDO VSDIO (1.8V or 3.3V / 0.020A)
LDO V3P3A (3.3V / 0.100A)
LDO V3P3S (3.3V / 0.500A)
LDO VRTC (3.3V / 0.120A)
DCDC regulator VDDQ (1.2-1.6V / 4.510A (output current depends on external component))
LDO VTT (VDDQ/2 V / 0.530A)
*IMVP7Lite compliant DC/DC regulators do not have full features. (IMVP7Lite)
1.2 Output Voltage Table
Table 4: Output voltage table of each S-state
Channel
DCDC1
DCDC2
DCDC3
DCDC4
DCDC5
DCDC6
DCDC7
SW1
LDO1
LDO2
LDO3
LDO4
Rail name
V1P0A
V1P0S
V1P8A
VDDQ
V1P05S
VCC
VNN
V1P8S
VRTC
V3P3A
V3P3S
V1P24A
VSDIO
V1P24S
VTT
Source [V]
1.0V
Iomax [mA]
700 (Note 1)
2667 (Note 2)
1800 (Note 1)
4510 (Note 2)
1322 (Note 1)
13541 (Note 2)
13207 (Note 2)
800 (Note 1)
120 (Note 1)
100 (Note 1)
500 (Note 1)
50 (Note 1)
S4/S5
ON
OFF
ON
OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
ON
OFF
OFF
OFF
OFF
S3
ON
OFF
ON
ON
OFF
OFF
OFF
OFF
ON
ON
OFF
ON
S0
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
1.0V
1.8V
1.2-1.6V
1.05V
0.5V-1.2V
0.5V-1.2V
1.8V
3.3V
3.3V
3.3V
1.24V
1.8V or 3.3V
1.24V
VDDQ/2 V
1.35V
Bay
Trail
LDO5
LDO6
LDO7
LDO8
20 (Note 1)
OFF
OFF
OFF
OFF
50 (Note 1)
530 (Note 1)
500 (Note 1)
VSFR
Note 1 Do not exceed Pd.
Note 2 Iomax depends on the external component.
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1.3 Power Management Diagram for Jarrell Cove PMIC
RSMRST_B(Open Drain)
DRAMPWROK(Open Drain)
COREPWROK(Open Drain)
RTEST_B (Open Drain)
PWRBTN_B(Open Drain)
SLP_S3_B (1.8V)
SLP_S4_B (1.8V)
SRTC_RST_B (3.3V)
Bay Trail
SUSPWRDNACK(1.8V)
SDMMC3_1P8_EN_B(1.8V)
SDMMC3_PWREN_B(1.8V)
Jarrell Cove
PMIC
SVID_DATA (1.0V)
SVID_CLK(1.0V)
SVID_ALERT_B(Open Drain)
ERROR (3.3V)
POWER_ON (3.3V)
SYNC (3.3V)
ICM
Interface
SUS_STAT_B (3.3V)
Figure 5. Power Management Diagram for Jarrell Cove PMIC
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1.4 Power Rail Diagram for Jarrell Cove PMIC
V1P0A (1.0V)
V1P24A(1.24V)
V1P8A (1.8V)
V3P3A (3.3V)
V1P0S (1.0V)
V1P05S(1.05V)
V1P24S(1.24V)
V1P8S (1.8V)
Bay Trail
V3P3S (3.3V)
VNN (0.5V – 1.2V)
VCC (0.5V – 1.2V)
VSDIO (1.8Vor 3.3V)
VSFR (1.35V)
Jarrell Cove
PMIC
VDDQ (1.2－1.6V)
VTT (VDDQ/2 V)
DDR3
VRTC (3.3V)
Figure 6. Power Rail Diagram for Jarrell Cove PMIC
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2. Application
2.1 Power-up Sequence
(Note)
It is not allowed to move a rail to other rail group and select a signal of other rail group for the trigger.
Figure 7. Power-up Sequence
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Table 5: Power-up Sequence Wait Time
No.
Register Name
PON_WAIT_SRTCRST
PON_WAIT_RTEST
PON_WAIT_V1P8A
PON_WAIT_V1P0A
PON_WAIT_V1P24A
PON_WAIT_V3P3A
PON_WAIT_RSMRST
PON_WAIT_VDDQ
PON_WAIT_DRAMPWROK
PON_WAIT_VNN
Description
Default Setting
Specific
Specific
Short
Min
9
Typ
Max
11
11
16
16
16
16
16
16
16
16
5
Units
ms
ms
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ms
1
VRTC stable to SRTCRST_B high
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
VRTC stable to RTEST_B high
9
3
POWER_ON asserted to first A rail turn-on delay
Voltage rail to subsequent rail delay
Voltage rail to subsequent rail delay
Voltage rail to subsequent rail delay
A rails valid to RSMRST_B de-assertion
SLP_S4_B de-assertion to VDDQ turn-on delay
VDDQ valid to DRAMPWROK assertion
SLP_S3_B de-assertion to first S rail turn-on delay
Voltage rail to subsequent rail delay
Voltage rail to subsequent rail delay
Voltage rail to subsequent rail delay
Voltage rail to subsequent rail delay
Voltage rail to subsequent rail delay
Voltage rail to subsequent rail delay
Voltage rail to subsequent rail delay
Voltage rail to subsequent rail delay
S rails valid to COREPWROK assertion
10
10
10
10
10
10
10
10
0
4
Short
5
Short
6
Short
7
Short
8
Short
9
Short
10
11
12
13
14
15
16
17
18
19
Short
PON_WAIT_VCC
Immediately
Immediately
Short
PON_WAIT_V1P0S
PON_WAIT_V1P05S
PON_WAIT_VSFR
0
5
10
10
10
10
10
10
100
16
16
16
16
16
16
140
Short
PON_WAIT_V1P8S
PON_WAIT_V1P24S
PON_WAIT_V3P3S
PON_WAIT_VTT
Short
Short
Short
Short
PON_WAIT_COREPWROK
Specific
(Note) Values in the logic block are guaranteed by design
(Note) Values exclude the delay time from “enable-on” to “turn-on”
[No.3,8,10]
[No.4 to 6,11 to 18]
assertion
Control Signal
(Note1)
Power-rail
Enable of
WAIT
WAIT
Enable of power-rail
Power-rail
enable on
turn-on
Subsequent power-rail
enable on
turn-on
Subsequent power-rail
[No.7,9,19]
Power-rail
(Note 1) Power-Good Level
100% : VCC,VNN
90% : VDDQ
(Note1)
WAIT
80% : V1P0A,V1P8A,V1P0S,V1P05S,VTT
70% : V1P24A,V3P3A,V1P8S,V1P24S,V3P3S,VSFR
Control Signal
assertion
[No.1,2]
VRTC
Reset of Logic
Control Signal
WAIT
assertion
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2.2 Power-down Sequence
(Note)
It is not allowed to move a rail to other rail groups and select a signal of other rail groups as the trigger.
Figure 8. Power Down Sequence
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Table 6: Power-down Sequence Wait Time
No.
Register Name
POFF_WAIT_COREPWROK
POFF_WAIT_VTT
Description
Default Setting
Short
Short
Long
Min
10
Typ
Max
16
16
1
Units
µs
1
SLP_S3_B assertion to COREPWROK de-assertion
COREPWROK de-assertion to first S rail starts to turn-off
Voltage rail to subsequent rail delay
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
10
µs
3
POFF_WAIT_V3P3S
POFF_WAIT_V1P24S
POFF_WAIT_V1P8S
POFF_WAIT_VSFR
POFF_WAIT_V1P05S
POFF_WAIT_V1P0S
POFF_WAIT_VCC
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
10
ms
ms
ms
ms
ms
ms
ms
ms
µs
4
Voltage rail to subsequent rail delay
Long
1
5
Voltage rail to subsequent rail delay
Long
1
6
Voltage rail to subsequent rail delay
Long
1
7
Voltage rail to subsequent rail delay
Long
1
8
Voltage rail to subsequent rail delay
Long
1
9
Voltage rail to subsequent rail delay
Long
1
10
11
12
13
14
15
16
17
POFF_WAIT_VNN
Voltage rail to subsequent rail delay
Long
1
POFF_WAIT_DRAMPWROK
POFF_WAIT_VDDQ
POFF_WAIT_RSMRST
POFF_WAIT_V3P3A
POFF_WAIT_V1P24A
POFF_WAIT_V1P0A
POFF_WAIT_V1P8A
SLP_S4_B assertion to DRAMPWROK de-assertion
DRAMPWROK de-assertion to VDDQ starts to turn-off
VDDQ down to RSMRST_B assertion
RSMRST_B de-assertion to first A rail starts to turn-off
Voltage rail to subsequent rail delay
Short
Short
Short
Short
Long
16
16
16
16
1
10
µs
10
µs
10
µs
0.5
0.5
0.5
ms
ms
ms
Voltage rail to subsequent rail delay
Long
1
Voltage rail to subsequent rail delay
Long
1
(Note) Values in the logic block are guaranteed by design
(Note) Values exclude the delay time from “enable-off” to “turn-off”
[No.2,12,14]
[No.3 to 10,15 to 17]
assertion
Control Signal
(Note1)
WAIT
Power-rail
Enable of
WAIT
Enable of power-rail
Power-rail
enable off
turn-off
Subsequent power-rail
enable off
turn-off
Subsequent power-rail
[No.13]
(Note 1) Shut-down Level
(Note1)
WAIT
0.2V : VCC,VNN,VDDQ
0.5V : other power rails
Power-rail
Control Signal
assertion
[No.1,11]
assertion
Control Signal
Control Signal
WAIT
assertion
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2.3 Logic Block Diagram
LOGIC BLOCK
SVID
I/F
VID_VCC
VID_VNN
VCC DAC
VNN DAC
Register
SVID
VID
Control
Register
PON_**
POFF_**
PON_WAIT**
POFF_WAIT**
PON_TGL
POFF_TGL
from ANALOG block
(PGD,SHDN,SCP)
PGD/SHDN
Select
Power Rails
Enable Signals
Retiming
Sequencing
State Machine
Control Signals
from VLV2 or ICM interface
OSC Clock
Clock
Control
Error Output
Error
Gen.
Figure 9. Logic Block Diagram
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2.4 Input Capacitor Selection
The input capacitor reduces the input voltage ripple caused by the switching current on VDD1, VDD2 and VDD3. Place the input
capacitor as close as possible to the VDD1, VDD2 and VDD3 pin. A 22uF or 47uF ceramic capacitor is recommended. To prevent
large voltage transients from occurring, a low ESR input capacitor sized for the maximum RMS current should be used. The
maximum RMS current is given by the following formula.
VOUT
VIN
VIN
IRMS IOUT (MAX )
1
1
VOUT
2.5 Bootstrap Capacitor
A 0.1uF ceramic capacitor must be connected between the BOOT and SW pins to provide the gate drive voltage for the high-side
MOSFET. The capacitor should have 10V or higher voltage rating.
2.6 Inductor Current Sensing
VIN
The inductor current is sensed by current sense amplifier through resistor R.
Current sense amplifier monitors difference voltage (=R*IL) and controls DCDC
system. R should be above 5mΩ.
L
R
VOUT
When the inductor current is sensed by inductor DC resistance (=RL), use the r, C
and rb.
IL
Co
The resistor r calculated from following formula. ∆Vs to be about 12mV, set the
value of resistor r.
VIN VOUT
C r 1MHz VIN
VOUT
Vs
Current Sense Amplifier
VIN
Current Limit is determined by the value of rb and Temp_comp Voltage.
Over Current Protection (OCP) operate when Vs larger than Vocp. Vocp and Vs
are calculated from following formula.
IL
Vocp 0.091VTEMP _ COMP
L
r
RL
Vs
2
rb
VOUT
Vs
RL IOUT
r rb
OCP temp coefficiency which is caused by DCR of inductor can be compensated
by changing TEMP_COMP voltage with the external temperature. Thermistor can
be used to it.
Co
C
rb
Vs
Current Sense Amplifier
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2.7 SYNC function
The SYNC pin is used to synchronize the DC/DC switching frequency with external clock. SYNC input frequency range is from
1.8MHz to 2.2MHz, and SYNC input pulse duty range is from 45% to 55%. SYNC input clock is divided to half frequency
internally for DC/DC switching clock. Thus DC/DC switching frequency will be 0.9MHz to 1.1MHz. The clock input can be applied
at anytime. This pin can be remained open if synchronization is not need. (Default frequency is 1MHz.)
SW_V1P0A
(2V/div)
SW_V1P0A
(2V/div)
Frequency: 1MHz
No SYNC signal
Frequency: 1MHz
SYNC: 2MHz
SYNC
(2V/div)
SYNC
(2V/div)
SW_V1P0A
(2V/div)
SW_V1P0A
(2V/div)
Frequency: 0.9MHz
SYNC: 1.8MHz
Frequency: 1.1MHz
SYNC: 2.2MHz
SYNC
(2V/div)
SYNC
(2V/div)
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3. Electrical Characteristics
3.1 Absolute Maximum Ratings (Ta=25ºC)
Table 7: Absolute Maximum Ratings
Parameter
Symbol
V5IN_D, V5IN_A
1.8VIN
Rating
7 (Note 1)
4.5 (Note 1)
4.5 (Note 1)
7 (Note 1)
4.5
Unit
V
Input Voltage1
Input Voltage2
Input Voltage3
Input Voltage4
Input Voltage5
V
VDDQIN
V
VDD1, VDD2, VDD3
V3P3DIN
V
V
BOOT_V1P0S-SW_V1P0S,
BOOT_VNN-SW_VNN,
BOOT_VCC-SW_VCC,
BOOT_VDDQ-SW_ VDDQ
SW_V1P0A,
BOOT to SW Voltage
7 (Note 1)
V
V
SW_V1P0S,
SW_V1P8A,
SW_VNN,
SW to GND Voltage
7 (Note 1)
SW_VCC,
SW_VDDQ
SLP_S3_B, SLP_S4_B, SUSPWRDNACK,
SDMMC3_PWREN_B, SDMMC3_1P8_EN,
SVID_CLK, SVID_DATA, POWER_ON, SYNC,
DATA
RSMRST_B, DRAMPWROK, COREPWROK,
RTEST_B, PWRBTN_B, SUS_STAT_B,
SVID_ALERT_B, CLK, DATA, SRTC_RSR_B,
ERROR, SPARE OUTPUT, SVID_DATA
RSMRST_B, DRAMPWROK, COREPWROK,
RTEST_B, PWRBTN_B, SUS_STAT_B, CLK,
DATA, SRTC_RSR_B, ERROR, SPARE
OUTPUT
Logic Input Voltage
4.5
4.5
-3
V
V
Logic Output Voltage
Logic Output Pin Current Low1
mA
Logic Output Pin Current Low2
Logic Output Pin Current High
Power Dissipation
SVID_ALERT_B, SVID_DATA
-20
3
mA
mA
W
SUS_STAT_B, SRTC_RSR_B, ERROR
Pd
9.5(Note 2)
Operating Temperature Range
Storage Temperature Range
Topr
Tstg
-40 to +95
°C
-55 to +150
°C
(Note 3)
Junction Temperature Range
Tjmax
+150
°C
(Note 1) Do not exceed Pd.
(Note 2) A measure value at mounting on 8 layers board of 95mm*95mm*1.6mm.
(Surface: product pattern + 7 layers: all copper foil area)
In the case of exceeding Ta=25°C, 75.7 W should be reduced per 1 °C.
(Note 3) Operation is not guaranteed.
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3.2 Recommended Operating Conditions (Ta=25ºC)
Table 8: Recommended Operating Conditions
Parameter
Symbol
V5IN_D, V5IN_A
1.8VIN
MIN
TYP
5.0
MAX
Unit
Power Supply Voltage1
Power Supply Voltage2
Power Supply Voltage3
Power Supply Voltage4
Power Supply Voltage5
3.5
5.5
V
V
V
V
V
-
-
V1P8A
VDDQ
5.0
-
-
VDDQIN
VDD1, VDD2, VDD3
V3P3DIN
3.5
-
5.5
-
VRTC
BOOT_V1P0S-SW_V1P0S,
BOOT_VNN-SW_VNN,
BOOT_VCC-SW_VCC,
BOOT_VDDQ-SW_ VDDQ
BOOT to SW Voltage
3.5
-
5.5
V
Logic Input Voltage Low1
(3.3V Input)
Logic Input Voltage High1
(3.3V Input)
Logic Input Voltage Low2
(1.8V Input)
Logic Input Voltage High2
(1.8V Input)
Logic Input Voltage Low3
(1.8V Input)
Logic Input Voltage High3
(1.8V Input)
Logic Input Voltage Low4
(1.0V Input)
Logic Input Voltage High4
(1.0V Input)
POWER_ON, SYNC, DATA
POWER_ON, SYNC, DATA
-0.3
VRTC-0.7
-0.3
-
-
-
-
-
-
-
-
0.7
V
V
V
V
V
V
V
V
VRTC+0.3
V1P8A*1/3
V1P8A+0.3
V1P8S*1/3
V1P8S+0.3
0.45
SLP_S3_B, SLP_S4_B,
SUSPWRDNACK
SLP_S3_B, SLP_S4_B,
SUSPWRDNACK
SDMMC3_PWREN_B,
SDMMC3_1P8_EN
SDMMC3_PWREN_B,
SDMMC3_1P8_EN
V1P8A*2/3
-0.3
V1P8S*2/3
-0.3
SVID_CLK, SVID_DATA
SVID_CLK, SVID_DATA
0.65
1.0
TEMP_COMP Voltage
TEMP_COMP
SYNC
0.28
1.8
45
-
2
1.0
2.2
55
V
MHz
%
SYNC Input Frequency Range
SYNC Input Pulse Duty Range
SYNC
50
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BD9596BMWV-M
3.3 DC Characteristics
Table 9: DC Characteristics
(Unless otherwise noted, Ta=25°C, V5IN_D=V5IN_A=5V, POWER_ON=3.3V)
Standard value
Parameter
Symbol
Unit
Conditions
MIN
TYP
MAX
[Total Block]
S4/S5 state, non-switching
FB1=1.15V, FB2=1.9V,
IS-3=1.2V, IS-5=1V, FB4=3.4V
S3 state, non-switching
FB1=1.15V, FB2=1.9V,
IS-3=1.2V, IS-5=1V, FB4=3.4V
S0 state, non-switching
FB1=1.15V, FB2=1.9V,
IS-3=1.2V, IS-5=1V, FB4=3.4V
Bias Current1
Bias Current2
Bias Current3
ICC_V5IN_A_1
ICC_V5IN_A_2
ICC_V5IN_A_3
-
-
-
6.5
9.0
9.5
mA
mA
mA
12.6
30.5
22.0
[Under Voltage Lock-Out Block]
V5IN_A Threshold Voltage
V5IN_A Hysterics Voltage
V5IN_A_UVLO
dV5IN_A_UVLO
3.1
50
3.3
100
3.5
150
V
mV
V5IN_A: Sweep up
V5IN_A: Sweep down
(S4/S5 State)
[VRTC Block]
Output Voltage
On Resistance
Over Current Protection
SCP Detecting Voltage
VRTC
Ronvrtc
OCP_vrtc
SCP_vrtc
3.168
-
140
3.300
-
-
3.432
1.4
-
V
Ω
mA
V
Io=0mA
Ids=50mA
VRTCx0.55 VRTCx0.7 VRTCx0.85
[Reference Clock Block]
Reference Clock Frequency
FRTC
31.130
32.768
34.406
KHz
[V3P3A Block]
Output Voltage
On Resistance
Over Current Protection
SCP Detecting Voltage
V3P3A
3.234
-
140
3.300
-
-
3.366
1.4
-
V
Ω
mA
V
Io=0mA
Ids=50mA
Ronv3p3a
OCP_v3p3a
SCP_v3p3a
V3P3Ax0.55 V3P3Ax0.7 V3P3Ax0.85
[V1P24A Block]
Output Voltage
On Resistance
Over Current Protection
SCP Detecting Voltage
V1P24A
1.215
-
60
1.240
-
-
1.265
10
-
V
Ω
mA
V
Io=0mA
Ids=50mA
Ronv1p24a
OCP_v1p24a
SCP_v1p24a
V1P24Ax0.55 V1P24Ax0.7 V1P24Ax0.85
[V1P0A Block]
Output Voltage
V1P0A
Foscv1p0a
Fsync
Tss_v1p0a
Ronh_ v1p0a
Rohnl_v1p0a
OCP_v1p0a
SCP_v1p0a
OVP_v1p0a
0.980
900
-
-
-
-
1.000
1000
1.0
1
120
120
-
1.020
1100
V
KHz
MHz
ms
mΩ
mΩ
mA
V
Io=0mA
Switching Frequency
Synchronization Frequency
Soft Start Time
Upper Side On Resistance
Lower Side On Resistance
Over Current Protection
SCP Detecting Voltage
OVP Detecting Voltage
-
-
-
-
-
SYNC=2MHz
900
V1P0Ax0.55 V1P0Ax0.7 V1P0Ax0.85
V1P0Ax1.1 V1P0Ax1.2 V1P0Ax1.3
V
[V1P8A Block]
Output Voltage
V1P8A
Foscv1p8a
Fsync
Tss_v1p8a
Ronh_ v1p8a
Rohl_v1p8a
OCP_v1p8a
SCP_v1p8a
OVP_v1p8a
1.764
900
-
-
-
-
1.800
1000
1.0
1
120
120
-
1.836
1100
V
KHz
MHz
ms
mΩ
mΩ
mA
V
Io=0mA
Switching Frequency
Synchronization Frequency
Soft-Start Time
Upper-Side On Resistance
Lower-Side On Resistance
Over-Current Protection
SCP Detecting Voltage
OVP Detecting Voltage
-
-
-
-
-
SYNC=2MHz
2800
V1P8Ax0.55 V1P8Ax0.7 V1P8Ax0.85
V1P8Ax1.1 V1P8Ax1.2 V1P8Ax1.3
V
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BD9596BMWV-M
(S3 state)
[VDDQ Block for DDR]
Reference Voltage
Switching Frequency
Synchronization Frequency
Soft-Start Time
HG High-Side ON Resistance
HG Low-Side ON Resistance
LG High-Side ON Resistance
LG Low-Side ON Resistance
Over-Current Setting Voltage
SCP Detecting Voltage
OVP Detecting Voltage
VREF_DDR
Fosc_DDR
Fsync
0.784
900
-
-
-
-
-
-
45
0.8
1000
1.0
1
-
-
-
-
50
0.816
1100
-
-
7
5
8
1.5
55
V
KHz
MHz
ms
Ω
Ω
Ω
Ω
mV
V
Io=0mA
SYNC=2MHz
Tss_DDR
HGHRON
HGLRON
LGHRON
LGLRON
OCP_DDR
SCP_DDR
OVP_DDR
(Note 1)
(Note 1)
(Note 2)
(Note 2)
TEMP_COMP=0.55V
VDDQx0.55 VDDQx0.7 VDDQx0.85
VDDQx1.1
VDDQx1.2
VDDQx1.3
V
(S0 state)
[VCC Block]
Output Setting Voltage Range
Output Voltage Accuracy
Switching Frequency
Synchronization Frequency
Soft-Start Time
HG High-Side ON Resistance
HG Low-Side ON Resistance
LG High-Side ON Resistance
LG Low-Side ON Resistance
Over-Current Setting Voltage
SCP Detecting Voltage
OVP Detecting Voltage
VCC
dVCC
Foscvcc
Fsync
Tss_vcc
HGHRON
HGLRON
LGHRON
LGLRON
OCP_vcc
SCP_vcc
OVP_vcc
0.5
SVIDx0.97
-
1.2
SVIDx1.03
V
V
KHz
MHz
ms
Ω
Ω
Ω
Ω
mV
V
SVID
1000
1.0
1
-
-
-
-
50
Io=0mA
900
-
-
-
-
-
-
45
1100
-
-
7
5
8
1.5
SYNC=2MHz
(Note 1)
(Note 1)
(Note 2)
(Note 2)
55
TEMP_COMP=0.55V
SVIDx0.55
1.40
SVIDx0.7
1.56
SVIDx0.85
1.72
V
[VNN Block]
Output Setting Voltage Range
Output Voltage Accuracy
Switching Frequency
Synchronization Frequency
Soft-Start Time
HG High-Side ON Resistance
HG Low-Side ON Resistance
LG High-Side ON Resistance
LG Low-Side ON Resistance
Over-Current Setting Voltage
SCP Detecting Voltage
OVP Detecting Voltage
VNN
dVNN
Foscvnn
Fsync
Tss_vnn
HGHRON
HGLRON
LGHRON
LGLRON
OCP_vnn
SCP_vnn
OVP_vnn
0.5
SVIDx0.97
-
1.2
SVIDx1.03
V
V
KHz
MHz
ms
Ω
Ω
Ω
Ω
mV
V
SVID
1000
1.0
1
-
-
-
-
50
Io=0mA
900
-
-
-
-
-
-
45
1100
-
-
7
5
8
1.5
SYNC=2MHz
(Note 1)
(Note 1)
(Note 2)
(Note 2)
55
TEMP_COMP=0.55V
SVIDx0.55
1.40
SVIDx0.7
1.56
SVIDx0.85
1.72
V
[V3P3S Block]
Output Voltage
On Resistance
Over-Current Protection
SCP Detecting Voltage
V3P3S
3.234
-
600
3.300
-
-
3.366
250
-
V
mΩ
mA
V
Io=0mA
Ids=50mA
Ronv3p3s
OCP_v3p3s
SCP_v3p3s
V3P3Sx0.55 V3P3Sx0.7 V3P3Sx0.85
[V1P8S Block]
On Resistance
Over-Current Protection
Ron_v1p8s
OCP_v1p8s
-
-
-
85
-
mΩ
mA
Ids=50mA
[V1P24S Block]
Output Voltage
On Resistance
Over-Current Protection
SCP Detecting Voltage
V1P24S
1.215
-
700
1.240
-
-
1.265
700
-
V
mΩ
mA
V
Io=0mA
Ids=50mA
Ronv1p24s
OCP_v1p24s
SCP_v1p24s
V1P24Sx0.55 V1P24Sx0.7 V1P24Sx0.85
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BD9596BMWV-M
[VTT Block]
1/2×
VDDQ-5%
1/2×
VDDQ+5%
500
500
VTTx0.85
Output Voltage
VTT
1/2×VDDQ
V
Io=0mA
High-Side On Resistance
Low-Side On Resistance
SCP Detecting Voltage
[VSDIO Block]
Hron_VTT
Lron_VTT
SCP_VTT
-
-
-
-
mΩ
mΩ
V
Ids=50mA
Ids=50mA
VTTx0.55
VTTx0.7
Io=0mA
SDMMC3_PWR_EN_B=0
SDMMC3_1P8_EN=1
Output Voltage 1
Output Voltage 2
VSDIO18
VSDIO33
1.764
3.234
1.800
3.300
1.836
3.366
V
V
Io=0mA
SDMMC3_PWR_EN_B=0
SDMMC3_1P8_EN=0
Ids=50mA
On Resistance
Over-Current Protection
SCP Detecting Voltage
Ronvsdio
OCP_vsdio
SCP_vsdio
-
40
-
-
5
-
Ω
mA
V
VSDIOx0.55 VSDIOx0.7 VSDIOx0.85
[VSFR Block]
Output Voltage
On Resistance
Over-Current Protection
SCP Detecting Voltage
VSFR
Ronvsfr
OCP_vsfr
SCP_vsfr
1.323
-
700
1.350
-
-
1.377
700
-
V
mΩ
mA
V
Ids=50mA
VSFRx0.55 VSFRx0.7 VSFRx0.85
[V1P0S Block]
Output Voltage
Switching Frequency
Synchronization Frequency
Soft-Start Time
HG High-Side ON Resistance
HG Low-Side ON Resistance
LG High-Side ON Resistance
LG Low-Side ON Resistance
Over-Current Setting Voltage
SCP Detecting Voltage
OVP Detecting Voltage
V1P0S
Foscv1p0s
Fsync
0.980
900
-
-
-
-
-
-
45
1.000
1000
1.0
1
-
-
-
-
50
1.020
1100
-
-
7
5
8
1.5
55
V
KHz
MHz
ms
Ω
Ω
Ω
Ω
mV
V
Io=0mA
SYNC=2MHz
Tss_v1p0s
HGHRON
HGLRON
LGHRON
LGLRON
OCP_v1p0s
SCP_v1p0s
OVP_v1p0s
(Note 1)
(Note 2)
(Note 2)
(Note 2)
TEMP_COMP=0.55V
V1P0Ax0.55 V1P0Ax0.7 V1P0Ax0.85
V1P0Ax1.1 V1P0Ax1.2 V1P0Ax1.3
V
[V1P05S Block]
Output Voltage
V1P05S
Foscv1p05s
Fsync
Tss_v1p05s
Ronh_ v1p05s
Ronl_v1p05s
OCP_v1p05s
SCP_v1p05s
OVP_v1p05s
1.029
900
-
-
-
-
1.050
1000
1.0
1
120
120
-
1.071
1100
V
KHz
MHz
ms
mΩ
mΩ
mA
V
Io=0mA
Switching Frequency
Synchronization Frequency
Soft-Start Time
Upper-Side On Resistance
Lower-Side On Resistance
Over-Current Protection
SCP Detecting Voltage
-
-
-
-
-
SYNC=2MHz
2000
V1P05S x0.55 V1P05S x0.7 V1P05S x0.85
V1P05S x1.1 V1P05S x1.2 V1P05S x1.3
OVP Detecting Voltage
(Note 1) HG swings from SW to BOOT.
(Note 2) LG swings from VDD to PGND.
V
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BD9596BMWV-M
Table 10: Logic Characteristics
(Unless otherwise noted, Ta=25°C, V5IN_D=V5IN_A=5V, POWER_ON=3.3V)
Standard Value
Parameter
Symbol
Unit
V
Conditions
MIN
TYP
-
MAX
[Logic Block]
[Logic Output Voltage High1] (3.3V output)
SRTC_RST_B
SUS_STAT_B
Logic_out_high1 VRTC-0.7
VRTC+0.3
Iload=3mA
RTCCLK
ERROR
[Logic Output Voltage Low1] (3.3V output)
SRTC_RST_B
SUS_STAT_B
Logic_out_low1
-0.3
-
0.7
V
Iload=-3mA
RTCCLK
ERROR
[Logic Output Voltage Low2] (open drain output)
RSMRST_B
DRAM_PWROK
COREPWROK
RTEST_B
PWRBTN_B
SPAREOUTPUT
CLK,DATA
Logic_out_low2
-0.3
-0.3
-
-
0.5
0.3
V
V
Iload=-3mA
[Logic Output Voltage Low3] (SVID output)
SVID_ALERT_B
SVID_DATA
Logic_out_low3
Iload=-20mA
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BD9596BMWV-M
3.4 Protection Mode (Under Voltage Lock Out)
All power supplies will be shut down at the same time when the UVLO signal is detected. There is no sequence in this
shutdown mode and BD9596BMWV-M cannot receive any external signals during this time.
3.5 Protection Mode (Thermal Shut Down)
A built-in internal shutdown (TSD) circuit is provided to protect the IC from heat destruction. Operation has to be done within the
allowable loss range, and continuous use beyond the range will cause chip temperature Tj to increase and reach threshold
consequently activating the TSD circuit to shut down all power supplies at the same time and latch OFF. There is no sequence
in this shutdown mode and BD9596BMWV-M cannot receive any external signals during this time. It will reboot, if 5V supply
or POWER_ON is toggled OFF and ON.
Hence, make absolutely certain not to use the TSD function in set design.
3.6 Protection Mode
Table 11 : Protection Mode (DC/DC)
Protection Mode
UVLO Protection
Short Circuit Protection
Thermal Protection
Over Voltage Protection
HG
Low
Low
Low
Low
LG
Function
Hysteresys
Timer latch (1ms)
Timer latch (10us)
Timer latch (10us)
Low
Low
Low
Low
Table 12 : Protection mode (LDO)
Protection Mode
Output
Low
Function
Hysteresys
UVLO Protection
Short Circuit Protection
Thermal Protection
Low
Low
Timer latch (1ms)
Timer latch (10us)
Table 13 : Protection mode (SW)
Protection Mode
Output
Low
Function
Hysteresys
UVLO Protection
Short Circuit Protection
Thermal Protection
Low
Low
Timer latch (1ms)
Timer latch (10us)
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BD9596BMWV-M
3.7 DAC Code for VCC and VNN
BD9596BMWV-M supports 2 SVID voltage regulators – VCC and VNN.
[Address Index]
0h : VCC
1h : VNN
Table 14: DAC Code Table (VCC / VNN)
DAC Set point
Accuracy
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage
(Design
guarantee)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OFF
0.5
NA
+- 8mV
+- 8mV
+- 8mV
+- 8mV
+- 8mV
+- 8mV
+- 8mV
+- 8mV
+- 8mV
+- 8mV
+- 8mV
+- 8mV
+- 8mV
+- 8mV
+- 8mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
0.51
0.52
0.53
0.54
0.55
0.56
0.57
0.58
0.59
0.6
0.61
0.62
0.63
0.64
0.65
0.66
0.67
0.68
0.69
0.7
0.71
0.72
0.73
0.74
0.75
0.76
0.77
0.78
0.79
0.8
0.81
0.82
0.83
0.84
0.85
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BD9596BMWV-M
DAC Set point
Accuracy
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage
(Design
guarantee)
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0.86
0.87
0.88
0.89
0.9
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
0.91
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 5mV
+- 0.5% VID
+- 0.5% VID
+- 0.5% VID
+- 0.5% VID
+- 0.5% VID
+- 0.5% VID
+- 0.5% VID
+- 0.5% VID
+- 0.5% VID
+- 0.5% VID
+- 0.5% VID
+- 0.5% VID
+- 0.5% VID
+- 0.5% VID
+- 0.5% VID
+- 0.5% VID
+- 0.5% VID
+- 0.5% VID
+- 0.5% VID
+- 0.5% VID
+- 0.5% VID
1.01
1.02
1.03
1.04
1.05
1.06
1.07
1.08
1.09
1.1
1.11
1.12
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.2
*00h is off code that makes SVID bus idle, waiting for next instruction.
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3.8 Serial VID Command
Table 15: Serial VID Command Table
Master
Slave
#
Command
payload
contents
Extended
command
index
payload
contents
Description
00h
Extended
This command is not supported. The PMIC will respond with Reject
acknowledge (11b).
01h
02h
SetVID-fast
(Individual
address &
VID code
NA
NA
Applicable for VCC & VNN. Upon setting new VID target, VR changes to
reach new VID target with controlled (up or down) slew rate programmed by
the VR. When VR receives VID moving up command it will exit all low power
states and proceed to the normal state. VR sets VR_settled bit and issues
alert when VR has reached new VID target. Note that only one slew rate is
supported (SR-fast=SR-slow). (see registers 24h, 25h)
Applicable for VCC & VNN. Upon setting new VID target, VR changes to
reach new VID target with controlled (up or down) slew rate programmed by
the VR. When VR receives VID moving up command it will exit all low power
states and proceed to the normal state. VR sets VR_settled bit and issues
alert when VR has reached new VID target. Note that only one slew rate is
supported (SR-fast=SR-slow). (see registers 24h, 25h)
Applicable for VCC & VNN. Upon setting the VID target, VR changes to reach
new VID target with controlled slew rate (mV/us).
The SetVID_decay is only used in VID down direction.
VR sets VR_settled bit but Alert line is not asserted for SetVID-decay.
This command is not supported. Executing this command has no effect to
the function of the PMIC. However PMIC responds with ACK=10b for
SetPS(00h..03h). SetPS(04h..FFh) should be rejected with ACK=11b as
these states are not supported or defined.
all call address)
SetVID-slow
(Individual
address &
VID code
VID code
all call address)
03h
04h
SetVID-decay
(Individual
address &
all call address)
SetPS
NA
NA
Byte
indicating
power status
of voltage
rail
05h
06h
07h
SetRegADR
(Individual
address only.
NAK all call
address)
SetRegDAT
(Individual
address only.
NAK all call
address)
Address of
the index
in the data
table
NA
NA
Sets the address pointer in the data register table. Typically the next
command SetRegDAT is the payload that gets loaded into this address.
However for multiple writes to the same address, only one SetRegADR is
needed.
New data
register
contents
Writes the contents to the data register that was previously identified by the
address pointer with SetRegADR.
GetReg
Define
which
register
Specified
register
contents
Slave returns the contents of the specified register as the payload; see 3.9
Register Code for list of registers. The majority of the VR monitoring data is
accessed through the GetReg command.
(Individual
address only.
NAK all call
address)
For the details of command transaction structure, please refer to VR12/ IMVP7 SVID Protocol (Document number: 456098).
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3.9 Register Code
Table 16: Register Code Table
Access
(SOC)
#
Register
Description
Default
00h
Vendor ID
Required:
RO
Vendor
Note 1
1Fh
Uniquely identifies the VR vendor. The
vendor ID is assigned by Intel. This register
is mandatory and the VR must return the
assigned vendor ID.
01h
02h
Product ID
Required:
RO
Vendor
Note 1
20h
Uniquely identifies the VR product. The VR
vendor assigns this number.
Required:
Uniquely identifies the revision or stepping
of the VR control IC. The vendor assigns
this data.
Product Revision
RO
Vendor
Note 1
06h
03h
04h
05h
06h
Product date
Code
Optional:
RO
Note 1,3
Note 1,3
Note 1
This function is not supported. The PMIC Vendor
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Required:
PMIC response is ACK=10b. Content of Vendor
payload is 01h.
Lot Code
RO
Protocol ID
Capability
RO
Required:
RO
00h
Bit mapped register, identifies the SVID VR Vendor
capabilities and which of the optional
telemetry registers are supported. PMIC
responds with ACK=10b, content of
payload is 00h indicating none of the
functions listed below are supported.
Bit0= Iout ADC (15h)
Note 2
bit1= Vout ADC (16h)
bit2= Pout ADC (18h)
bit3= I input ADC (19h)
Bit4= V input ADC (1Ah)
bit5= P input ADC (1Bh)
bit6= Temperature ADC (17h)
bit7= 0 if (15h) is formatted 1A per LSB,
Legacy for Servers Only bit7= 1 if (15h) is
formatted FFh=Icc_max for Client and
optional for server ADC formatting.
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Optional:
RO
RO
RO
RO
RO
RO
RO
RO
RO
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
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10h
Status_1
Required:
R-M
00h
Data register read after the alert# signal is W-PWM
asserted. Conveying the status of the VR.
See 6.2.1 in the IMVP7 SVID protocol.
In Jarrell Cove, bit2 alerts SCP(OVP) and
bit1 alerts TSD.
Note 2
11h
12h
Status_2
Required:
R-M
00h
Note 2
Data Register showing status_2 data. W-PWM
Conveying the status of the SVID bus.
See 6.2.1 in the IMVP7 SVID protocol.
Required, but not supported:
This function is not supported. The PMIC
responds with ACK=10b. Content of
payload is 00h.
Temperature Zone
RO
00h
Note 2
13h
14h
15h
Current Zones
reserved
Optional:
RO
RO
RO
Note 3
Note 3
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Required but not supported:
This function is not supported. The PMIC
responds with ACK=10b. Content of
payload is 00h.
Output Current
00h
Note 2
16h
17h
18h
19h
1Ah
1Bh
1Ch
Output Voltage
Optional:
RO
RO
RO
RO
RO
RO
R-M
Note 2,3
Note 2,3
Note 2,3
Note 2,3
Note 2,3
Note 2,3
Note 2
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Required:
VR
Temperature
Output Power
(Pout)
Input current
Input Voltage
Input Power
Status2_last read
This register contains a copy of the status2 W-PWM
data that was last read with the GetReg
(status2) command. In the case of
a
communications error or parity error, when
the VR is sending the payload back to the
master, the master can read the
Status2_lastread register so the alert data
is not lost.
1Dh
1Eh
1Fh
20h
21h
22h
V1P0A/VDDQ Output
Current, Imon (H)
Required but not supported:
RO
RO
RO
RO
RO
RO
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
This function is not supported. The PMIC
responds with ACK=10b. Content of
payload is 00h.
V1P0A/VDDQ Output
Current, Imon (L)
Required but not supported:
This function is not supported. The PMIC
responds with ACK=10b. Content of
payload is 00h.
V1P05S Output Current, Required but not supported:
Imon (H) This function is not supported. The PMIC
responds with ACK=10b. Content of
payload is 00h.
V1P05S Output Current, Required but not supported:
Imon (L)
This function is not supported. The PMIC
responds with ACK=10b. Content of
payload is 00h.
ICC_MAX
Required but not supported:
This function is not supported. The PMIC
responds with ACK=10b. Content of
payload is 00h.
Temp max
Required but not supported:
This function is not supported. The PMIC
responds with ACK=10b. Content of
payload is 00h.
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23h
24h
DC_LL
SR-fast
Optional:
RO
RO
Note 2,3
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Required:
The PMIC supports only one slew rate.
Fast slew rate is equal to slow slew rate.
The PMIC responds with ACK=10b.
Content of payload is 0Ah.
0Ah = 10 mV/us
Note 2
25h
26h
SR-slow
Vboot
Required:
RO
RO
0Ah = 10 mV/us
Note 2
The PMIC supports only one slew rate.
Fast slew rate is equal to slow slew rate.
The PMIC responds with ACK=10b.
Content of payload is 0Ah.
Required:
Note 2
Vboot=1.00V fix for VNN and VCC. No Pin
programming is needed. PMIC responds
with ACK=10b.Content of payload is 97h.
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Required but not supported:
27h
28h
29h
2Ah
VR tolerance
RO
RO
RO
RO
Note 3
Note 3
Note 3
Note 2
Current-offset
Temperature offset
VCC/VNN Imon
Accuracy
This function is not supported. The PMIC
responds with ACK=10b. Content of
payload is FFh.
2Bh
2Ch
V1P0A/VDDQ Imon
Accuracy
Required but not supported:
RO
RO
Note 2
Note 2
This function is not supported. The PMIC
responds with ACK=10b. Content of
payload is FFh.
V1P05S Imon Accuracy
Required but not supported:
This function is not supported. The PMIC
responds with ACK=10b. Content of
payload is FFh.
2Dh
2Eh
2Fh
30h
reserved
reserved
reserved
Vout max
Optional:
RO
RO
RO
Note 3
Note 3
Note 3
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Required:
RW
D3h
This register is programmable by the
master and sets the maximum VID the VR
will be able to support. If a higher VID code
is received, the VR will respond with
“Reject, not supported” acknowledgement.
VR12 VID data format. Must be
programmed by MASTER during boot up
sequence if a value other than default is
desired. Offset (33h) does not affect
master
Note 2
Vout_max IE VID
>Vout_max
+
offset can be
31h
32h
VID setting
Pwr state
Required:
RW
00h
Note 2
Data
register
containing
currently Master
programmed VID voltage.
VID data format: Default is 00h, zero volts
out, VR off.
Required but not supported:
PMIC responds with ACK=10b. Content of
payload is 00h.
RO
Note 2
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33h
Offset
Required:
RW
00h
Sets offset in VID steps added to the VID Master
setting for voltage margining.
Bit7 is sign bit,
Note 2
0=positive margin
1= negative margin.
Remaining 7 BITS are the number of VID
steps for the margin 2s complement.
00h= no margin.
01h=+1 VID step,
02h=+2 VID steps
FFh=-1 VID step…
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
40h
Multi VR config
SetRegADR
Trim code 1 revision
Trim code 2 revision
reserved
Required but not supported:
PMIC responds with ACK=10b. Content of
payload is 00h.
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Note 2
Note 3
Note 2
Note 2
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Required but not supported:
PMIC responds with ACK=10b. Content of
payload is 00h.
Required but not supported:
PMIC responds with ACK=10b. Content of
payload is 00h.
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Optional:
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
This function is not supported. The PMIC
responds with Reject acknowledge (11b).
Notes:
1.
2.
3.
These registers only appear in 00h voltage rail. (“Reject” for 01h voltage rail.)
These registers are per address and not shared.
Optional register response – VR should respond with a
Reject (11b) ACK if a GetReg command is issued to an optional data register.
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Status1 Register bit[2], bit[1] (10h)
In Jarrell Cove, the function of the Status1 Register bit[2] and bit[1] are different from the original SVID Protocol. Bit[2] alerts
SCP/OVP while bit[1] alerts TSD, and the ALERT# line is not asserted.
Bit[2] of 00h voltage rail (VCC) shows the status of SCP/OVP for VCC.
Bit[2] of 01h voltage rail (VNN) shows the status of SCP/OVP for VNN.
Bit[1] of both VCC and VNN show the same status of TSD.
The status of SCP/OVP for the power rails other than VCC and VNN are not shown in Status1 Register.
When POWER_ON=0, the timer-latch is reset and the ERROR output is disabled. But the Status1 Register bit[2] and bit[1] are
latched until they are read by GetReg command.
POWER_ON
Occured
Timer
Removed
SCP/OVP/TSD
Timer-latch
Detective
Latch
Reset
State-machine
G3_P
G3
power-on-sequence
S0
GetReg Status1
Reset
Status1 bit2/bit1
ALERT#
(de-assertion)
ERROR
・・・・
Figure 10. Status1 Timing Chart
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4. Typical Performance Curves
4.1 Load Regulation
3.5
3.4
3.3
3.2
3.1
3.5
3.4
3.3
3.2
3.1
V5IN=5V
Ta=25 C
V5IN=5V
Ta=25 C
˚
˚
0.0
20.0 40.0 60.0 80.0 100.0 120.0
Output Current IVRTC[mA]
0.0
20.0
40.0
60.0
80.0
100.0
Output Current IV3P3A[mA]
Figure 11. Output Voltage VRTC vs Output
Current IVRTC
Figure 12. Output Voltage V3P3A vs Output
Current IV3P3A
1.02
1.01
1.00
0.99
0.98
1.30
1.28
1.26
1.24
1.22
1.20
V5IN=5V
V5IN=5V
Ta=25˚C
Ta=25 C
˚
0.0
20.0
40.0
60.0
80.0
100.0
0.0
0.2
0.4
0.6
0.8
1.0
Output Current IV1P24A[mA]
Output Current IV1P0A[A]
Figure 13. Output Voltage V1P24A vs Output
Current IV1P24A
Figure 14. Output Voltage V1P0A vs Output
Current IV1P0A
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Typical Performance Curves - Continued
1.84
1.83
1.82
1.81
1.80
1.79
1.78
1.38
1.37
1.36
1.35
1.34
1.33
1.32
V5IN=5V
Ta=25˚C
V5IN=5V
Ta=25˚C
1.77
1.76
0.0
0.5
1.0
1.5
2.0
0.0
1.0
2.0
3.0
4.0
5.0
Output Current IV1P8A[A]
Output Current IVDDQ[A]
Figure 15. Output Voltage V1P8A vs Output
Current IV1P8A
Figure 16. Output Voltage VDDQ vs Output
Current IVDDQ
1.03
1.02
1.01
1.00
0.99
0.98
0.97
1.03
1.02
1.01
1.00
0.99
0.98
0.97
V5IN=5V
Ta=25˚C
V5IN=5V
Ta=25˚C
0.0
2.0
4.0
6.0
8.0
10.0
0.0
2.0
4.0
6.0
8.0
10.0
Output Current IVCC[A]
Output Current IVNN[A]
Figure 17. Output Voltage VCC vs Output Current
IVCC
Figure 18. Output Voltage VNN vs Output Current
IVNN
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Typical Performance Curves - Continued
3.5
3.4
3.3
3.2
1.90
1.85
1.80
1.75
1.70
V5IN=5V
V5IN=5V
Ta=25 C
Ta=25 C
˚
˚
3.1
0.0
100.0 200.0 300.0 400.0 500.0
Output Current IV3P3S[mA]
0.0
200.0
400.0
600.0
800.0
Output Current IV1P8S[mA]
Figure 19. Output Voltage V3P3S vs Output
Current IV3P3S
Figure 20. Output Voltage V1P8S vs Output
Current IV1P8S
0.71
0.70
0.69
0.68
0.67
0.66
0.65
0.64
1.30
1.28
1.26
1.24
1.22
1.20
V5IN=5V
V5IN=5V
Ta=25˚C
Ta=25 C
˚
0.0
10.0
20.0
30.0
40.0
50.0
-600.0
-300.0
0.0
300.0
600.0
Output Current IV1P24S[mA]
Output Current IVTT[mA]
Figure 21. Output Voltage V1P24S vs Output
Current IV1P24S
Figure 22. Output Voltage VTT vs Output Current
IVTT
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Typical Performance Curves - Continued
3.5
3.4
3.3
3.2
1.90
1.85
1.80
1.75
1.70
V5IN=5V
V5IN=5V
Ta=25 C
Ta=25 C
˚
˚
3.1
0.0
10.0
20.0
30.0
40.0
50.0
0.0
10.0
20.0
30.0
40.0
50.0
Output Current IVSDIO[mA]
Output Current IVSDIO[mA]
Figure 24. Output Voltage VSDIO vs Output
Current IVSDIO
Figure 23. Output Voltage VSDIO vs Output
Current IVSDIO
(SDMMC3_1P8_EN = 3.3V)
(SDMMC3_1P8_EN = 0V)
1.020
1.40
1.38
1.36
1.34
1.32
1.30
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
V5IN=5V
V5IN=5V
Ta=25˚C
Ta=25 C
˚
0.0
100.0 200.0 300.0 400.0 500.0
Output Current IVSFR[mA]
0.0
1.0
2.0
3.0
4.0
Output Current IV1P0S[A]
Figure 25. Output Voltage VSFR vs Output
Current IVSFR
Figure 26. Output Voltage V1P0S vs Output
Current IV1P0S
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Typical Performance Curves - Continued
1.07
1.06
1.05
1.04
V5IN=5V
Ta=25˚C
1.03
0.0
0.5
1.0
1.5
2.0
Output Current IV1P05S[A]
Figure 27. Output Voltage V1P05S vs Output
Current IV1P05S
4.2 Temperature Characteristics
3.5
3.5
3.4
3.3
3.2
3.1
3.4
3.3
3.2
3.1
V5IN=5V
IOUT=0A
V5IN=5V
IOUT=0A
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
Temperature [ C]
Temperature [ C]
˚
˚
Figure 28. Output Voltage VSFR vs Temperature
Figure 29. Output Voltage V3P3A vs Temperature
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Typical Performance Curves - Continued
1.30
1.28
1.26
1.24
1.22
1.02
1.01
1.00
0.99
0.98
V5IN=5V
IOUT=0A
V5IN=5V
IOUT=0A
1.20
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
Temperature [˚C]
Temperature [˚C]
Figure 30. Output Voltage V1P24A vs
Temperature
Figure 31. Output Voltage V1P0A vs Temperature
1.84
1.83
1.82
1.81
1.80
1.79
1.78
1.77
1.76
1.40
1.38
1.36
1.34
1.32
1.30
V5IN=5V
IOUT=0A
V5IN=5V
IOUT=0A
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
Temperature [˚C]
Temperature [˚C]
Figure 32. Output Voltage V1P8A vs Temperature
Figure 33. Output Voltage VDDQ vs Temperature
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Typical Performance Curves - Continued
1.03
1.02
1.01
1.00
0.99
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.98
0.97
V5IN=5V
IOUT=0A
V5IN=5V
IOUT=0A
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
Temperature [˚C]
Temperature [˚C]
Figure 34. Output Voltage VCC vs Temperature
Figure 35. Output Voltage VNN vs Temperature
3.5
3.4
3.3
3.2
3.1
1.30
1.28
1.26
1.24
1.22
V5IN=5V
IOUT=0A
V5IN=5V
IOUT=0A
1.20
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
Temperature [˚C]
Temperature [˚C]
Figure 36. Output Voltage V3P3S vs Temperature
Figure 37. Output Voltage V1P24S vs
Temperature
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Typical Performance Curves - Continued
0.71
0.70
0.69
0.68
0.67
0.66
3.5
3.4
3.3
3.2
3.1
V5IN=5V
IOUT=0A
V5IN=5V
IOUT=0A
0.65
0.64
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
Temperature [˚C]
Temperature [˚C]
Figure 38. Output Voltage VTT vs Temperature
Figure 39. Output Voltage VSDIO vs Temperature
(SDMMC3_1P8_EN = 0V)
1.87
1.85
1.83
1.81
1.79
1.77
1.75
1.73
1.40
1.38
1.36
1.34
1.32
1.30
V5IN=5V
IOUT=0A
V5IN=5V
IOUT=0A
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
Temperature [˚C]
Temperature [˚C]
Figure 40. Output Voltage VSDIO vs Temperature
(SDMMC3_1P8_EN = 3.3V)
Figure 41. Output Voltage VSFR vs Temperature
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Typical Performance Curves - Continued
1.020
1.015
1.010
1.005
1.000
0.995
0.990
1.08
1.07
1.06
1.05
1.04
1.03
1.02
V5IN=5V
IOUT=0A
V5IN=5V
IOUT=0A
0.985
0.980
-40 -20
0
20
40
60
80
-40
-20
0
20
40
60
80
Temperature [˚C]
Temperature [˚C]
Figure 42. Output Voltage V1P0S vs Temperature
Figure 43. Output Voltage V1P05S vs
Temperature
4.3 Efficiency
100%
80%
60%
40%
20%
0%
100%
80%
60%
40%
S3/S4
S0
20%
V5IN=5V
V5IN=5V
Ta=25˚C
Ta=25 C
˚
0%
0.01
0.10
1.00
10.00
0.01
0.10
1.00
10.00
Output Current IV1P0A[A]
Output Current IV1P8A[A]
Figure 45. Efficiency V1P8A vs Output Current
IV1P8A
Figure 44. Efficiency V1P0A vs Output Current
IV1P0A
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Typical Performance Curves - Continued
100%
80%
100%
80%
60%
40%
20%
0%
60%
S3/S4
40%
S0
20%
V5IN=5V
Ta=25 C
V5IN=5V
Ta=25˚C
˚
0%
0.01
0.10
1.00
10.00
0.01
0.10
1.00
10.00
Output Current IVCC[A]
Output Current IVDDQ[A]
Figure 47. Efficiency VCC vs Output Current IVCC
Figure 46. Efficiency VDDQ vs Output Current
IVDDQ
100%
100%
80%
60%
40%
80%
60%
40%
20%
0%
20%
V5IN=5V
Ta=25 C
V5IN=5V
Ta=25 C
˚
˚
0%
0.01
0.10
1.00
10.00
0.01
0.10
1.00
10.00
Output Current IVNN[A]
Output Current IV1P0S[A]
Figure 48. Efficiency VNN vs Output Current IVNN
Figure 49. Efficiency V1P0S vs Output Current
IV1P0S
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Typical Performance Curves - Continued
100%
80%
60%
40%
20%
V5IN=5V
Ta=25 C
˚
0%
0.01
0.10
1.00
10.00
Output Current IV1P05S[A]
Figure 50. Efficiency V1P05S vs Output Current
IV1P05S
4.4 Transient Response
V1P0A: 20mV/div
V1P0A: 20mV/div
I
V1P0A: 0.2A/div
IV1P0A: 0.2A/div
Figure 51. Transient Response V1P0A
Figure 52. Transient Response V1P0A
(V5INA=5V Ta=25˚C IV1P0A = 160mA to 600mA)
(V5INA=5V Ta=25˚C IV1P0A = 600mA to 160mA)
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Typical Performance Curves - Continued
V1P8A: 50mV/div
V1P8A: 50mV/div
IV1P8A: 1A/div
IV1P8A: 1A/div
Figure 53. Transient Response V1P8A
Figure 54. Transient Response V1P8A
(V5INA=5V Ta=25˚C IV1P8A = 360mA to 1440mA)
(V5INA=5V Ta=25˚C IV1P8A = 1440mA to 360mA)
VDDQ: 50mV/div
VDDQ: 50mV/div
IVDDQ: 2A/div
I
VDDQ: 2A/div
Figure 55. Transient Response VDDQ
Figure 56. Transient Response VDDQ
(V5INA=5V Ta=25˚C IVDDQ = 800mA to 3800mA)
(V5INA=5V Ta=25˚C IVDDQ = 3800mA to 800mA)
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Typical Performance Curves - Continued
VCC: 50mV/div
VCC: 50mV/div
I
VCC: 5A/div
I
VCC: 5A/div
Figure 57. Transient Response VCC
Figure 58. Transient Response VCC
(V5INA=5V Ta=25˚C IVCC = 2.7A to 11A)
(V5INA=5V Ta=25˚C IVCC = 11A to 2.7A)
VNN: 50mV/div
VNN: 50mV/div
I
VNN: 5A/div
I
VNN: 5A/div
Figure 59. Transient Response VNN
Figure 60. Transient Response VNN
(V5INA=5V Ta=25˚C IVNN = 2.7A to 11A)
(V5INA=5V Ta=25˚C IVNN = 11A to 2.7A)
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Typical Performance Curves - Continued
V1P0S: 20mV/div
V1P0S: 20mV/div
IV1P0S: 1A/div
IV1P0S: 1A/div
Figure 61. Transient Response V1P0S
Figure 62. Transient Response V1P0S
(V5INA=5V Ta=25˚C IV1P0S = 533mA to 2135mA)
(V5INA=5V Ta=25˚C IV1P0S = 2135mA to 533mA)
V1P05S: 20mV/div
V1P05S: 20mV/div
I1P05S: 0.5A/div
I1P05S: 0.5A/div
Figure 63. Transient Response V1P05S
Figure 64. Transient Response V1P05S
(V5INA=5V Ta=25˚C IV1P05S = 264mA to 1058mA)
(V5INA=5V Ta=25˚C IV1P05S = 1058mA to 264mA)
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5. Sequence
5.1 State Machine
V5IN_A,V5IN_D = 5V
When the state goes into an irregular state,
it goes to "SOC G3_P" immediately.
INI_SET:
SRTCRST_B = 1
RTEST_B = 1
OTHERS
INI_SET
SOC G3
(1)
(1)
else
(2) POWER_ON = 0
else
SOC G3_P
(1)
(2) POWER_ON = 1
PLA_RST:
RSMRST_B = 0
1st Power A rail OFF
SUS_STAT_B = 0 @ Cold Off
other Power A rails OFF
PLA_SET:
Power A rails ON
RSMRST_B = 1
SUS_STAT_B = 1 @ Cold Boot
else
else
PLA_RST
PLA_SET
(1)
(1)
SUSPWRDNACK = 1 and SLP_S4_B = 0 and RSMRST_B = 1
(3)
else
SOC S4
(1)
(2) SLP_S4_B = 1 and RSMRST_B = 1 and SLP_S3_B = 0
PLU_RST:
DRAMPWROK = 0
Power U rails OFF
PLU_SET:
(SUS_STAT_B = 1 @ Exit SOC S4)
Power U rails ON
else
else
PLU_RST
(1)
PLU_SET
(1)
(SUS_STAT_B = 0 @ Enter SOC S4)
DRAMPWROK = 1
SLP_S4_B = 0 and RSMRST_B = 1 and SLP_S3_B = 0
(3)
else
SOC S3
(1)
(2) SLP_S3_B = 1 and RSMRST_B = 1
PLS_RST:
COREPWROK = 0
Power S rails OFF
PLS_SET:
(SUS_STAT_B = 1 @ Exit SOC S3)
Power S rails ON
else
else
PLS_RST
PLS_SET
(1)
(1)
(SUS_STAT_B = 0 @ Enter SOC S3)
COREPWROK = 1
SLP_S3_B = 0 and RSMRST_B = 1
(2)
else
SOC S0
(1)
- The arrows (1) in the figure show SCP, OVP or TSD.
When SCP, OVP or TSD is detected in any state, the state goes to "SOC G3_P" immediately.
- (1), (2) and (3) in the figure show priority when events occur simultaneously.
Figure 65. State Machine
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5.2 Cold Boot Timing Chart
Figure 66. Cold Boot Timing Chart
(*) SRTCRST_B and RTEST_B remain High once they become High at INI_SET state, even when SCP, OVP, or TSD is detected.
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5.3 Cold Off Timing Chart
Figure 67. Cold Off Timing Chart
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5.4 Enter SOC S4 Timing Chart
Figure 68. Enter SOC S4 Timing Chart
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5.5 Exit SOC S4 Timing Chart
Figure 69. Exit SOC S4 Timing Chart
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5.6 Enter SOC S3 Timing Chart
Figure 70. Enter SOC S3 Timing Chart
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5.7 Exit SOC S3 Timing Chart
Figure 71. Exit SOC S3 Timing Chart
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5.8 I/O Interface Signals
Table 17: I/O Interface Signals Table
Pin Name
Connect to
Description
I/O
Valid while
Sleep S3 trigger
0=enter S3; 1=exit S3
SLP_S3_B
SOC
I
RSMRST_B=1
Sleep S4 trigger
0=enter S4; 1=exit S4
RSMRST_B=1
SLP_S3_B=0
SLP_S4_B
SOC
I
tells the PMIC to turn off the SUS rails
in junction with assertion of SLP_S4_B
RSMRST_B=1
SLP_S4_B=0
SUSPWRDNACK
SRTCRST_B
RSMRST_B
DRAMPWROK
COREPWROK
RTEST_B
SOC
I
de-asserted when VRTC is stable,
allows to detect when VRTC has been switched off
SOC
O
VRTC ON
SOC
Resume reset, de-asserted after all SUS rails turned on
asserted after VDDQ turned on
O (OD)
-
SOC
O (OD)
-
SOC
asserted after all core rails turned on
O (OD)
-
Test and debug,
de-asserted when VRTC is stable
SOC
O (OD)
-
PWRBTN_B
POWER_ON
SUS_STAT_B
SYNC
SOC
level shifted copy of POWER_ON
O (OD)
RSMRST_B=1
Platform
Platform
Platform
SOC
tells the PMIC to switch on the SUS rails
I
-
-
-
Suspend status, informs platform that the desired suspend
state has been reached
O
DCDC synchronization clock
I
select 1.8V or 3.3V for SD card
0=3.3V; 1=1.8V
RSMRST_B=1
COREPWROK=1
SDMMC3_1P8EN
SDMMC3_PWREN_B
RTCCLK
I
SD card power (VSDIO) enable
0=ON; 1=OFF
RSMRST_B=1
COREPWROK=1
SOC
I
SOC
32kHz clock output
O
-
asserted when the PMIC state machine has reached an error
state, over current or over temperature condition occurred
ERROR
-
O
I
-
SVID_CLK
SOC
SVID clock
SVID data
SVID alert
State='S0'
State='S0'
-
SVID_DATA
SVID_ALERT_B
SOC
I/O (OD)
O (OD)
SOC
OD=Open-drain
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PWRBTN_B
V1P8A
VRTC
POWER_ON
Re-timing
PWRBTN_B
RSMRST_B
Power A rails ON
Power A rails OFF
POWER_ON
V1P8A
RSMRST_B
PWRBTN_B
PWRBTN_B is copy of POWER_ON.
(PWRBTN_B is valid while RSMRST_B=1.)
Figure 72. PWRBTN_B Timing Chart
ERROR
Error Detective
Type
Error Output
High
C1:
C2:
C3:
Error state
SCP, OVP
TSD
Latch
1ms Timer Latch (SCP)
10μs Timer Latch (OVP)
10μs Timer Latch
Oscillating (0.5sec period)
Oscillating (12.5sec period)
* Latch is reset by POR(Power-on-reset) or POWER_ON=0.
* In any case, the PMIC state machine goes to "SOC G3_P".
[ERROR Output]
C1 (Error state)
Error Detective
ERROR
C2 (SCP,OVP), C3 (TSD)
Error Detective
Timer Latch
ERROR
Figure 73. ERROR Timing Chart
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ALERT_B
Voltage change by SVID
Setting voltage 4VID
Setting voltage 4VID
VNN / VCC
Voltage change by SVID
ALERT_B
ALERT_B is asserted if VCC/VNN output voltage is within ±4VID of setting voltage.
Figure 74. ALERT_B Timing Chart
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6. I/O Equivalent Circuit
Table 18: Pin Equivalent Circuit
REMOTE_P_VNN (PIN1)
REMOTE_P_VCC(PIN86)
100kΩ
1kΩ
1kΩ
AGND
100kΩ
AGND
AGND
AGND
AGND
IS_M_VNN (PIN2)
IS_M_VCC (PIN85)
IS_P_VNN (PIN3)
IS_P_VCC (PIN84)
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I/O Equivalent Circuit – continued
LG_VNN (PIN5)
LG_VDDQ (PIN60)
V5INA
LG_V1P0S (PIN70)
LG_VCC (PIN82)
1kΩ
PGND
10kΩ
SW_VNN (PIN6)
SW_VCC (PIN81)
HG_VNN (PIN7)
BOOT_VNN
HG_VDDQ (PIN62)
HG_V1P0S (PIN68)
HG_VCC (PIN80)
BOOT_VCC
BOOT_V1P0S
BOOT_VDDQ
100kΩ
100kΩ
SW_VNN
SW_VCC
SW_V1P0S
SW_VDDQ
PGND
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I/O Equivalent Circuit – continued
BOOT_VNN (PIN8)
BOOT_VDDQ (PIN63)
BOOT_V1P0S (PIN67)
BOOT_VCC (PIN79)
SW_V1P8A (PIN10)
SW_V1P0A (PIN58)
V1P8S (PIN13,14)
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I/O Equivalent Circuit – continued
VSFR (PIN17)
V1P8A_IN
V1P24S (PIN19)
20k
48k
10k
200k
1k
67k (V1P24S)
58k (VSFR)
AGND
AGND
AGND AGND
SRTC_RST_B (PIN20)
SUS_STAT_B (PIN21)
ERROR (PIN22)
RTCCLK (PIN33)
SLP_S4_B (PIN23)
SLP_S3_B (PIN24)
SDMMC3_V1P8_EN (PIN25)
SDMMC3_PWREN_B (PIN26)
SUSPWRDNACK (PIN32)
POWER_ON (PIN44)
10k
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I/O Equivalent Circuit – continued
SYNC (PIN27)
VRTC
10k
300k
SPARE (PIN28)
SVID_CLK (PIN29)
SVID_DATA (PIN30)
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I/O Equivalent Circuit – continued
SVID_ALERT_B (PIN31)
PWRBTN_B (PIN45)
OPEN DRAIN
CLK (PIN46)
COREPWROK (PIN48)
DRAMPWROK (PIN49)
RSMRST_B (PIN50)
RTEST_B (PIN51)
V3P3S (PIN37)
V3P3A (PIN39)
VRTC (PIN40)
V1P24A (PIN41)
VSDIO (PIN42)
V5IN_D
10k
20k
1k
200k
AGND
AGND
10k
20k (V3P3S, V3P3A, VRTC, VSDIO)
64k (V1P24A)
AGND
AGND
DATA (PIN47)
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I/O Equivalent Circuit – continued
VTT (PIN53)
FB_VDDQ (PIN64)
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I/O Equivalent Circuit – continued
IS_M_VDDQ (PIN65)
IS_M_V1P0S (PIN73)
IS_P_VDDQ (PIN66)
IS_P_V1P0S (PIN72)
1kΩ
AGND
AGND
SW_VDDQ (PIN61)
SW_V1P0S (PIN69)
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I/O Equivalent Circuit – continued
FB_V1P0S (PIN74)
FB_V1P05S (PIN75)
SW_V1P05S (PIN77)
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I/O Equivalent Circuit – continued
REMOTE_M_VCC (PIN87)
REMOTE_M_VNN (PIN88)
V5INA
V5INA
2.5kΩ
100kΩ
1kΩ
AGND
AGND AGND
100kΩ
AGND
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7. Operational Notes
(1) Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when connecting
the power supply, such as mounting an external diode between the power supply and the IC’s power supply terminals.
(2) Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the digital and
analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog block. Furthermore,
connect a capacitor to ground at all power supply pins. Consider the effect of temperature and aging on the capacitance value
when using electrolytic capacitors.
(3) Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. However, pins that
drive inductive loads (e.g. motor driver outputs, DC-DC converter outputs) may inevitably go below ground due to back EMF or
electromotive force. In such cases, the user should make sure that such voltages going below ground will not cause the IC and
the system to malfunction by examining carefully all relevant factors and conditions such as motor characteristics, supply voltage,
operating frequency and PCB wiring to name a few.
(4) Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but connected
to a single ground at the reference point of the application board to avoid fluctuations in the small-signal ground caused by large
currents. Also ensure that the ground traces of external components do not cause variations on the ground voltage. The ground
lines must be as short and thick as possible to reduce line impedance.
(5) Thermal Consideration
Should by any chance the power dissipation rating be exceeded, the rise in temperature of the chip may result in deterioration of
the properties of the chip. The absolute maximum rating of the Pd stated in this specification is when the IC is mounted on a
70mm x 70mm x 1.6mm glass epoxy board. In case of exceeding this absolute maximum rating, increase the board size and
copper area to prevent exceeding the Pd rating.
(6) Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately obtained. The
electrical characteristics are guaranteed under the conditions of each parameter.
(7) Rush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.
Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of
connections.
(8) Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
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(9) Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject the IC to
stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always be turned off
completely before connecting or removing it from the test setup during the inspection process. To prevent damage from static
discharge, ground the IC during assembly and use similar precautions during transport and storage.
(10) Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in damaging
the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin. Inter-pin shorts could be
due to many reasons such as metal particles, water droplets (in very humid environment) and unintentional solder bridge
deposited in between pins during assembly to name a few.
(11) Unused Input Terminals
Input terminals of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge acquired
in this way is enough to produce a significant effect on the conduction through the transistor and cause unexpected operation of
the IC. So, unless otherwise specified, unused input terminals should be connected to the power supply or ground line.
(12) Regarding Input Pins of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N
junctions are formed at the intersection of the P layers with the N layers of other elements, creating a parasitic diode or transistor.
For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual interference
among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to operate, such as
applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be avoided.
Figure 75. Example of monolithic IC structure
(13) Area of Safe Operation (ASO)
Operate the IC such that the output voltage, output current, and power dissipation are all within the Area of Safe Operation
(ASO).
(14) Thermal Shutdown Circuit (TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always be within the
IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction temperature (Tj) will rise which
will activate the TSD circuit that will turn OFF all output pins. When the Tj falls below the TSD threshold, the circuits are
automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat damage.
(15) Over Current Protection Circuit (OCP)
This IC has a built-in overcurrent protection circuit that activates when the output is accidentally shorted. However, it is strongly
advised not to subject the IC to prolonged shorting of the output.
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8. Power Dissipation
Use of a heat sink may be necessary depending on the environmental condition.
UQFN88MV0100
Measurement machine: TH-156 (Kuwano Denki)
Measurement condition: mounted on a user’s specified board size
Board size: 95mm×95mm×1.6mmt
(With thermal via)
Board (1): 8 layered board
(Surface: product pattern + 7 layers: all copper foil area)
Board (2): 8 layered board
(Surface: product pattern + 2 layers: all copper foil area
+ 5 layer: wiring pattern copper foil 70% occupied)
Board (3): 8 layered board
(Surface: product pattern + 2 layers: all copper foil area
+ 5 layer: wiring pattern copper foil 50% occupied)
(Note) This is a measured value, not guaranteed.
Figure 76. Power Dissipation
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9. Soldering Condition
Recommended temperature profile for reflow
260°C MAX
Preheating temperature :
130°C to 190°C
Preheating zone
Soldering temperature
Soldering zone
: 120sec MAX
ꢀ
255°C
:
2
2
0
°C t
o
2
4
0°C
ꢀ
Soldering temperature
: 75sec MAX
ꢀ
1 to 4°C/sec
(Notice)
Preheating
Maximum 2-times soldering
temperature
Time
10secMAX
Preheating
zone
Soldering zone
The wave soldering method is not supported.
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10. History
Table 19: Revision History
Rev.
Date
Notes
Rev.001
2015/01/07
First release
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Notice
Precaution on using ROHM Products
(Note 1)
1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment
,
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
Rev.004
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Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
Rev.004
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General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3. The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
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