BH3810 [ROHM]
Vocal fader IC with input selector; 声乐推子IC的输入选择器
| 型号： | BH3810 |
| 厂家： | 
ROHM |
| 描述： | Vocal fader IC with input selector |
| 文件： | 总9页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Multimedia ICs
Vocal fader IC with input selector
BH3810FS
The BH3810FS is a vocal fader IC that is serial control compatible. It has mode switching that also includes a voice
multiplexing mode, a five-input selector, a gain selector and other such features, which can all be controlled serially.
Eight open-collector terminals and two tri-state terminals are provided on the chip to facilitate control by other ICs.
Applications
•
Component stereo systems, CD radio cassette players, TVs and car stereos.
Features
•
1) Built-in low-pass filter can perform vocal fader func-
tion (erasing of vocals from commercially available
music software) using just one chip.
4) Five-channel input selector.
5) Mic. mixing amplifier with mute function. Key con-
troller input also provided.
2) Serial control can be used to switch between vocal
fader, through, multiplex, and mute modes.
3) Built-in gain selector allows selection of gain from
6dB to 20dB in 2dB steps.
6) SSOP-A32 pin package.
Absolute maximum ratings (Ta = 25°C)
•
Parameter
Symbol
VDD
Limits
+ 5.5
– 4.5
850
Unit
V
Applied voltages
VEE
Power dissipation
Pd
mW
Operating temperature
Storage temperature
Topr
Tstg
VOP
– 40 ~ + 85
– 55 ~ + 125
14
°C
°C
V
Maximum open collector voltage
Reduced by 8.5mW for each increase in Ta of 1°C over 25°C ,
when mounted on a 50mm × 50mm × 1.6mm board.
Recommended operating conditions (Ta = 25°C)
•
Parameter
Symbol
VDD
Limits
Unit
4.0 ~ 5.3
V
V
Power supply voltage
VEE
– 4.3 ~ – 3.0
1
Multimedia ICs
BH3810FS
Block diagram
•
2
Multimedia ICs
BH3810FS
Electrical characteristics (unless otherwise notes, Ta = 25°C, VDD = 5V, VEE = – 4V, G = 14dB, f =1kHz,
•
Rg = 600Ω, VIN = 150mV, and RL = 100kΩ)
Parameter
Symbol
Min.
—
—
—
—
1.5
11
8
Typ.
4.5
4.1
10.0
7.6
2.2
14
Max.
10.0
10.0
20.0
20.0
—
Unit
mA
mA
mA
mA
Conditions
I
Q1
Q1
Q2
Q2
+
–
+
–
Through mode VDD current
Through mode VEE current
Through mode D9 to D16 data1
Through mode D9 to D16 data1
I
Quiescent current
I
I
Vom
V
rms
THD = 1%, through mode
Maximum output voltage
L, R gain
G
G
VT
17
dB
dB
dB
dB
Through mode
Low-frequency gain
Microphone gain
Crosstalk
VF
11
14
Vocal fader mode, f = 100Hz
—
G
VM
5
8
11
CT
MU
SV
54
64
—
f
=
1kHz, through mode
Mute attenuation
60
80
—
dB
dB
%
f
= 1kHz, mute mode or input mute
Vocal suppression ratio
Total harmonic distortion
Noise level
15
—
—
—
20
0.004
15
—
0.05
22
Vocal fader mode, f
1Vrms, through mode, BW 400Hz
to 30kHz
0, DIN AUDIO
= 1kHz
VO =
THD
V
N
µV
rms
Rg =
Mode switch output DC
differential
∆
DCB
0
18
mV
Between each mode with key controller on
Pins 1 to 5, pins 26, pins 28 to 32
Input impedance
R
IN
35
80
50
—
65
—
kΩ
Input selector crosstalk
CTIN
dB
mA
V
f = 1kHz
Pins 17 to 24, 0.5V between PORT
terminal and GND voltage = 0.5V
Port output current
IPMax.
5.0
12
—
"L" output voltage
V
OL
—
—
4.5
—
—
—
0.15
0
0.5
2.0
—
Pins 17 to 27, IOL
= 5mA
"H" output leakage current
Tri-state "H" output voltage
Tri-state "L" output voltage
SI pin source current (pin 13)
SCK pin source current (pin 14)
I
OH
µA
Pins 17 to 24, 13V applied to collector
V
SOH
4.85
0.05
0.4
V
Pins 15 to 16, Io
Pins 15 to 16, Io
=
=
1mA
1mA
V
SOL
SI
SCK
0.5
10
V
I
µA
When SI pin is at DGND potential
When SCK pin is at DGND potential
I
0.2
10
µA
Measured using a Matsushita VP-9690A (average value detector, effective value display) DIN AUDIO filter.
Operating specifications: same phase for the input and output signals.
᭺ Not designed for radiation resistance.
3
Multimedia ICs
BH3810FS
Measurement circuit
•
C L O C K
L A T C H
D A T A
Fig. 1
4
Multimedia ICs
BH3810FS
Circuit operation
•
(1) About the data format
Data format
MSB
24 bits total
LSB
Data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23
17pin 18pin 19pin 20pin 21pin 22pin 23pin 24pin
15pin
16pin
Input
selector
Input
selector
Mode
selector
Mic.
Chip
mute select
Descri-
ption
Tri-state
port
Tri-state
port
Open collector port
8bit
3bit
3bit
3bit
2bit
2bit
1bit
2bit
Bit number
Fig.2
• Address is "00"
D22
0
D23
0
At power on
Output port: current attraction OFF
Tri-state port: Low
Gain selector
Mode selector
Mic
6dB
Through mode
Mute OFF
OFF
Key controller
Input selector
LA, RA
Output port: open collector
Data
D16
D15
D14
D13
D12
D11
D10
D9
PORT PORT PORT PORT PORT PORT PORT PORT
Pin
name
1
2
3
4
5
6
7
8
(24pin) (23pin) (22pin) (21pin) (20pin) (19pin) (18pin) (17pin)
0
1
Current sink OFF
Current sink ON
Tri-state
PORT9 (16pin)
PORT10 (15pin)
D19
0
D20
Mode
LOW
D17
0
D18
0
Mode
LOW
0
1
0
1
0
OPEN
OPEN
HI
0
1
OPEN
OPEN
HI
1
1
0
1
1
1
D19, D20
D17, D18
Mic. mute
D21
0
Mode
Mic. ON
1
Mic. MUTE
5
Multimedia ICs
BH3810FS
Input selector 3 bits D0 to D2
D0
0
D1
0
D2
0
Mode
MUTE
MUTE
MUTE
0
0
1
0
1
0
0
1
1
INPUT—LA, INPUT—RA
INPUT—LB, INPUT—RB
INPUT—LC, INPUT—RC
INPUT—LD, INPUT—RD
INPUT—LE, INPUT—RE
1
0
0
1
0
1
1
1
0
1
1
1
Gain selector 3 bits D3 to D5
The gain is the total gain from input to output.
D3
0
D4
0
D5
0
Gain select
6dB
0
0
1
8dB
0
1
0
10dB
12dB
14dB
16dB
18dB
20dB
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Mode selector 3 bits D6 to D8
D6
0
D7
0
D8
0
LOUT
MUTE
ROUT
MUTE
TK
Mode
MUTE
Mute
0
0
1
VOCALFADE
VOCALFADE
VOCALFADE
Vocal fader
L channel
Through
0
1
0
L
L
L
0
1
1
L
R
L
1
0
0
FK
FK
FK
FK
FK
FK
FK
FK
L + R
Key controller, L + R
1
0
1
R
Key controller, R channel
Key controller, L channel
Key controller, vocal fader
1
1
0
L
1
1
1
VOCALFADE
6
Multimedia ICs
BH3810FS
(2) Timing chart
Serial data timing (timing for the IC terminals)
90%
tw
tw
SCK
(clock signal)
10%
tsu
th
ts
tw (LATCH)
90%
tw (DATA)
SI
90%
10%
(DATA signal,
LATCH signal)
D22
D23
10%
When LATCH is "H", the DATA signal is forced "L" internally.
The read decision for the DATA signal (SI) is made by the signal when the CLOCK signal rises.
The read decision for the LATCH signal (SI) is made by the signal when the LATCH signal itself rises.
A "L" must follow at the end of each signal to wait for the next signal.
Fig.3
Timing chart constants (Ta = 25°C, VDD = 5V and VEE = – 4V)
•
Parameter
H input voltage
Symbol
Min.
4.0
Typ.
5.0
2.5
0
Max.
6.0
3.0
1.0
—
Unit
V
VIH
M input voltage
VIM
2.0
V
L input voltage
VIL
– 0.3
2.0
V
Minimum clock width
Minimum data width
Minimum latch width
Setup time (DATA to CLK)
Hold time (CLK to DATA)
tw
tw (DATA)
tw (LATCH)
tsu
—
µs
µs
µs
µs
µs
4.0
—
—
2.0
—
—
1.0
—
—
th
1.0
—
—
Setup time (DATA, CLK to LATCH)
ts
1.0
—
—
µs
If the voltage between VDD and DGND changes, the values above will change.
7
Multimedia ICs
BH3810FS
Application circuit
•
+
Fig. 4
8
Multimedia ICs
BH3810FS
Operation notes
•
(1) We guarantee the application circuit design, but recommend that you thoroughly check its characteristics in actu-
al use.
If you change any of the external component values, check both the static and transient characteristics of the circuit,
and allow sufficient margin in your selections to take into account variations in the components and ICs.
Note that Rohm has not fully investigated patent rights regarding this product.
(2) The vocal fader function
The effect of the vocal fader is realized by negating the same-phase components. In the bass region, the first-stage
low-pass filter leaves the source sound as is, even for the same-phase components. Therefore, depending on the
music, the effect may be small.
(3) The low-pass filter that leaves the vocal fader bass
The low-pass filter is formed by connecting a capacitor to pin 6. A 20kΩ resistor (design value) and this capacitor set
the cutoff frequency.
1
fc =
(Hz)
2πCR
The optional attenuation of the first-stage low-pass filter frequency is:
f: frequency
1
A (f) = 20 log
(dB)
C: external capacitor
1 + (2πfCR) 2
R: 20kΩ (design value)
(4) AGND (pin 10) and DGND (pin 12)
AGND is the ground for the IC's internal analog circuits, and DGND is the ground for the internal ports 1 to 10.
Connect the two grounds externally.
(5) Switching noise
If you are troubled by switching noise that occurs when the input selector, gain selector, or mode selector are
switched, use muting, or some other appropriate countermeasure.
(6) Serial control
The LATCH and DATA serial signals are received on the same terminal, and the signals are differentiated by voltage
level. A diode and resistor are connected to perform a conversion to logic voltage (0 to 5V). The threshold values
will change depending on the external components, so select them carefully.
If the signals are not being received very well, connect a capacitor of about 100pF between the SI terminal (pin 13),
and the DGND terminal (pin 12).
External dimensions (Units: mm)
•
13.6 ± 0.2
32
17
16
1
0.8
0.36 ± 0.1
0.3Min.
0.15
SSOP-A32
9
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