BM6101FV-C [ROHM]
Isolation voltage 2500Vrms 1ch Gate Driver Providing Galvanic Isolation; 隔离电压2500Vrms的1通道栅极驱动器提供电流隔离
| 型号： | BM6101FV-C |
| 厂家： | 
ROHM |
| 描述： | Isolation voltage 2500Vrms 1ch Gate Driver Providing Galvanic Isolation |
| 文件： | 总34页 (文件大小：888K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
Gate Driver Providing Galvanic isolation Series
Isolation voltage 2500Vrms
1ch Gate Driver Providing Galvanic Isolation
BM6101FV-C
●General Description
●Key Specifications
The BM6101FV-C is a gate driver with isolation voltage
2500Vrms, I/O delay time of 350ns, and minimum input
pulse width of 180ns, and incorporates the fault signal
output functions, undervoltage lockout (UVLO) function,
thermal protection function, and short current protection
(SCP, DESAT) function.
Isolation voltage:
Maximum gate drive voltage:
I/O delay time:
2500Vrms(Max.)
24V(Max.)
350ns(Max.)
180ns(Max.)
Minimum input pulse width:
●Package
SSOP-B20W
W(Typ.) x D(Typ.) x H(Max.)
6.50mm x 8.10mm x 2.01mm
●Features
Providing Galvanic Isolation
Active Miller Clamping
Fault signal output function
(Adjustable output holding time)
Undervoltage lockout function
Thermal protection function
Short current protection function
(Adjustable reset time)
Soft turn-off function for short current protection
(Adjustable turn-off time)
●Applications
Supporting Negative VEE2
■
■
■
■
Automotive isolated IGBT/MOSFET inverter gate drive
Automotive DC-DC converter
Industrial inverters system
UPS system
●Typical Application Circuits
GND1
PROOUT
S
R
NC
VEE2
PRE
LOGIC
DRIVER
Q
INB
OUT1
MASK
FLTRLS
VCC2
LOGIC
VEE2
VCC1
FLT
VREG
UVLO
MASK
FB
TIMER
TIMER
UVLO
OUT2
SCPIN
GND2
VEE2
MASK
MASK
MASK
INA
ECU
FLT
FLT
ENA
TEST
GND1
Input side
chip
Output side
chip
MASK
VTSIN
Temp Sensor
Figure 1. For using 4-pin IGBT (for using SCP function)
GND1
NC
PROOUT
S
R
VEE2
OUT1
VCC2
VREG
OUT2
SCPIN
GND2
PRE
DRIVER
LOGIC
Q
INB
MASK
FLTRLS
LOGIC
VEE2
VCC1
FLT
UVLO
MASK
FB
TIMER
TIMER
UVLO
MASK
MASK
INA
ECU
FLT
FLT
ENA
MASK
TEST
VEE2
Input side
chip
Output side
chip
MASK
GND1
VTSIN
Temp Sensor
Figure 2. For using 3-pin IGBT (for using DESAT function)
○Product structure：Silicon integrated circuit ○This product is not designed protection against radioactive rays
.
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●Recommended range of external constants
Recommended Value
Pin Name
Symbol
Unit
Min.
-
Typ.
0.01
200
3.3
1.0
-
Max.
0.47
1000
10.0
-
CFLTRLS
RFLTRLS
CVREG
CVCC1
uF
kΩ
uF
uF
uF
FLTRLS
50
VREG
VCC1
VCC2
1.0
0.1
0.33
CVCC2
-
●Pin Configuration
SSOP-B20W
(TOP VIEW)
1pin
Figure 3. Pin configuration
●Pin Description
Pin No.
1
Pin Name
VTSIN
VEE2
GND2
SCPIN
OUT2
VREG
VCC2
OUT1
VEE2
PROOUT
GND1
NC
Function
Thermal detection pin
2
Output-side negative power supply pin
Output-side ground pin
3
4
Short current detection pin
5
MOS FET control pin for Miller Clamp
6
Power supply pin for driving MOS FET for Miller Clamp
Output-side positive power supply pin
Output pin
7
8
9
Output-side negative power supply pin
Soft turn-off pin
10
11
12
13
14
15
16
17
18
19
20
Input-side ground pin
No Connect
INB
Invert / non-invert selection pin
Fault output holding time setting pin
Input-side power supply pin
Fault output pin
FLTRLS
VCC1
FLT
INA
Control input pin
ENA
Input enabling signal input pin
Test mode setting pin
TEST
GND1
Input-side ground pin
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●Description of pins and cautions on layout of board
1) VCC1 (Input-side power supply pin)
The VCC1 pin is a power supply pin on the input side. To suppress voltage fluctuations due to the current to drive
internal transformers, connect a bypass capacitor between the VCC1 and the GND1 pins.
2) GND1 (Input-side ground pin)
The GND1 pin is a ground pin on the input side.
3) VCC2 (Output-side positive power supply pin)
The VCC2 pin is a positive power supply pin on the output side. To reduce voltage fluctuations due to OUT1 pin output
current and due to the current to drive internal transformers, connect a bypass capacitor between the VCC2 and the
GND2 pins.
4) VEE2 (Output-side negative power supply pin)
The VEE2 pin is a power supply pin on the output side. To suppress voltage fluctuations due to OUT1 pin output current and
due to the current to drive internal transformers, connect a bypass capacitor between the VEE2 and the GND2 pins. To use
no negative power supply, connect the VEE2 pin to the GND2 pin.
5) GND2 (Output-side ground pin)
The GND2 pin is a ground pin on the output side. Connect the GND2 pin to the emitter / source of a power device.
6) IN (Control input terminal)
The IN pin is a pin used to determine output logic.
ENA
INB
X
L
L
H
INA
X
L
H
L
OUT1
L
L
H
H
L
H
L
L
L
L
H
H
7) FLT (Fault output pin)
The FLT pin is an open drain pin used to output a fault signal when a fault occurs (i.e., when the undervoltage lockout
function (UVLO), short current protection function (SCP) or thermal protection function is activated).
This pin is I/O pin and if L voltage is externally input, the output is set to L status regardless of other input logic.
Consequently, be sure to connect the pull-up resistor between VCC1 pin and the FLT pin even if this pin is not used.
Pin
FLT
While in normal operation
Hi-Z
When an Fault occurs
(When UVLO, SCP or thermal protection is activated)
L
8) FLTRLS (Fault output holding time setting pin)
The FLTRLS pin is a pin used to make setting of time to hold a Fault signal. Connect a capacitor between the FLTRLS
pin and the GND1 pin, and a resistor between it and the VCC1 pin.
The Fault signal is held until the FLTRLS pin voltage exceeds a voltage set with the VFLTRLS parameter. To set holding
time to 0 ms, do not connect the capacitor. Short-circuiting the FLTRLS pin to the VCC1 pin will cause a high current to
flow in the FLTRLS pin and, in an open state, may cause the IC to malfunction. To avoid such trouble, be sure to connect
a resistor between the FLTRLS and the VCC1 pins.
9) OUT1 (Output pin)
The OUT1 pin is a pin used to drive the gate of a power device.
10) OUT2 (MOS FET control pin for Miller Clamp)
The OUT2 pin is a pin for controlling the external MOS switch for preventing increase in gate voltage due to the miller
current of the power device connected to OUT1 pin.
11) VREG (Power supply pin for driving MOS FET for Miller Clamp)
The VREG pin is a power supply pin for driving MOS FET for Miller Clamp. Be sure to connect a capacitor between
VREG pin and VEE2 pin for preventing the oscillation and to reduce voltage fluctuations due to OUT2 pin output current.
12) PROOUT (Soft turn-off pin)
The PROOUT pin is a pin used to put the soft turn-off function of a power devise in operation when the SCP function is
activated. This pin combines with the gate voltage monitoring pin for Miller Clamp.
13) SCPIN (Short current detection pin)
The SCPIN pin is a pin used to detect current for short current protection. When the SCPIN pin voltage exceeds a
voltage set with the VSCDET parameter, the SCP function will be activated. This may cause the IC to malfunction in an
open state. To avoid such trouble, short-circuit the SCPIN pin to the GND2 pin if the short current protection is not used.
In order to prevent the wrong detection due to noise, the noise mask time tSCPMSK is set.
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14) VTSIN (Thermal detection pin)
The VTSIN pin is a temperature sensor voltage input pin, which can be used for thermal protection of an output device.
If VTSIN pin voltage becomes VTSDET or less, OUT pin is set to L. In the open status, the IC may malfunction, so be sure
to supply the VTSPIN more than VTSDET if the thermal protection function is not used. In order to prevent the wrong
detection due to noise, the noise mask time tTSMSK is set.
●Description of functions and examples of constant setting
1) Miller Clamp function
When OUT1=L and PROOUT pin voltage < VOUT2ON, H is output from OUT2 pin and the external MOS switch is turned
ON. When OUT1=H, L is output from OUT2 pin and the external MOS switch is turned OFF. While the short-circuit
protection function is activated, L is output from OUT2 pin and the external MOS switch is turned OFF.
Short current
Detected
SCPIN
IN
X
PROOUT
X
OUT2
L
Not less than
VSCDET
X
X
X
L
L
Not less than VOUT2ON
Not more than VOUT2ON
X
Hi-Z
H
Not detected
H
L
VCC2
PREDRIV ER
OUT1
PREDRIV ER
PROOUT
PREDRIV ER
REGULATOR
LOGIC
VREG
OUT2
PREDRIV ER
PREDRIV ER
+
-
GND2
VEE2
Figure 4. Block diagram of Miller Clamp function
tPOFF tPON
IN
OUT1
PROOUT
(Monitor the gate voltage)
VOUT2ON
tOUT2ON
OUT2
Figure 5. Timing chart of Miller Clamp function
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2) Fault status output
This function is used to output a fault signal from the FLT pin when a fault occurs (i.e., when the undervoltage lockout
function (UVLO), short current protection function (SCP) or thermal protection function is activated) and hold the Fault
signal until the set Fault output holding time is completed. The Fault output holding time tFLTRLS is given as the following
equation with the settings of capacitor CFLTRLS and resistor RFLTRLS connected to the FLTRLS pin. For example, when
CFLTRLS is set to 0.01F and RFLTRLS is set to 200k, the holding time will be set to 2 ms.
tFLTRLS [ms]= CFLTRLS [F]•RFLTRLS [k]
To set the fault output holding time to “0” ms, only connect the resistor RFLTRLS.
Status
Normal
FLT pin
Hi-Z
L
Fault occurs
Fault occurs
(The UVLO, SCP or thermal protection)
Status
UVLO MASK
S
R
MASK
MASK
SCP
VTS
FLT
VFLTRLS
FLTRLS
FLT
VCC1
Hi-Z
FLTRLS
FLT
-
+
L
H
MASK
OUT
L
LOGIC
ECU
GND1
Fault output holding time (tFLTRLS)
Figure 6. Fault Status Output Timing Chart
Figure 7. Fault Output Block Diagram
3) Undervoltage Lockout (UVLO) function
The BM6101FV-C incorporates the undervoltage lockout (UVLO) function both on the low and the high voltage sides.
When the power supply voltage drops to the UVLO ON voltage, the OUT pin and the FLT pin both will output the “L”
signal. When the power supply voltage rises to the UVLO OFF voltage, these pins will be reset. However, during the fault
output holding time set in “2) Fault status output” section, the OUT pin and the FLT pin will hold the “L” signal. In addition,
to prevent malfunctions due to noises, mask time tUVLO1MSK and tUVLO2MSK are set on both low and high voltage sides.
H
IN
L
VUVLO1H
VUVLO1L
VCC1
FLT
Hi-Z
L
H
OUT1
L
Figure 8. Input-side UVLO Function Operation Timing Chart
H
L
IN
VUVLO2H
VUVLO2L
VCC2
FLT
OUT1
Hi-Z
L
H
Hi-Z
L
Figure 9. Output-side UVLO Operation Timing Chart
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4) Short current protection function (SCP, DESAT)
When the SCPIN pin voltage exceeds a voltage set with the VSCDET parameter, the SCP function will be activated.
When the SCP function is activated, the OUT1 pin voltage will be set to the “Hi-Z” level first, and then the PROOUT pin
voltage to the “L” level (soft turn-off).Next, after tSTO has passed after the short-circuit current falls below the threshold
value, OUT pin becomes L and PROOUT pin becomes L. Finally, when the fault output holding time set in “2) fault status
output” section on page 5 is completed, the SCP function will be released.
When OUT1=L or Hi-Z, internal MOSFET connected to SCPIN pin turns ON to discharge CBLANK. When OUT1=H,
internal MOSFET connected to SCPIN turns OFF.
VCOLLECTOR/VDRAIN which Desaturation Protection starts operation (VDESAT) and the blanking time (tBLANK) can be
calculated by the formula below;
R3 R2
VDESAT
V
VSCDET
VSCDET
VF
D
R3
R3 R2 R1
R3
VCC 2
V
MIN
VSCDET
VCC 2
R2 R1
R3 R2 R1
R3 R2 R1
R3
tBLANKouternal
s
R3 (CBLANK 27 1012 ) ln(1
) 0.65106
Reference Value
R2
VDESAT
R1
R3
4.0V
4.5V
5.0V
5.5V
6.0V
6.5V
7.0V
7.5V
8.0V
8.5V
9.0V
9.5V
10.0V
15 kΩ
15 kΩ
15 kΩ
15 kΩ
15 kΩ
15 kΩ
15 kΩ
15 kΩ
15 kΩ
15 kΩ
15 kΩ
15 kΩ
15 kΩ
39 kΩ
43 kΩ
36 kΩ
39 kΩ
43 kΩ
62 kΩ
68 kΩ
82 kΩ
91 kΩ
82 kΩ
130 kΩ
91 kΩ
130 kΩ
6.8 kΩ
6.8 kΩ
5.1 kΩ
5.1 kΩ
5.1 kΩ
6.8 kΩ
6.8 kΩ
7.5 kΩ
8.2 kΩ
6.8 kΩ
10 kΩ
6.8 kΩ
9.1 kΩ
VCC2
VCC1
IN
PREDRIVER
OUT
LOGIC
LOGIC
PREDRIVER
PREDRIVER
PROOUT
STO
R
S
R
+
FLTRLS
FLT
-
V
TFLTRLS
+
-
SCPIN
SCPMSK
ECU
GND1
GND2
VEE2
Input Side
Output Side
Figure 10. Block Diagram for DESAT
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H
L
IN
VSCDET
SCPIN
H
OUT1
OUT2
Hi-Z
L
H
Hi-Z
L
Hi-Z
L
Hi-Z
PROOUT
FLT
L
tSTO
tSTO
Fault output holding time*7
Fault output holding time *7
*7: “2) Fault status output” section on page 5
Figure 11. SCP Operation Timing Chart
INA
OUT1
OUT2
tSCPMSK+tcomp_delay
(Typ. 0.95us)
tSCPMSK+tcomp_delay
PROOUT
SCPIN
FLT
VSCDET (Typ. 0.7V)
VSCDET
tBLANKouternal
tBLANK
tBLANKouternal
tBLANK
tcomp_delay : Detection delay time of internal comparator
Figure 12. DESAT sequence
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Start
OUT1=L, OUT2=H
No
No
VSCPIN>VSCDET
Yes
No
VFLTRLS>VTFLTRLS
Yes
Exceed mask time
Yes
FLT=Hi-Z
OUT1=Hi-Z, OUT2=L,
PROOUT=L, FLT=L
No
IN=H
No
No
Yes
VSCPIN<VSCDET
Yes
OUT1=H, OUT2=L, PROOUT=Hi-Z
Exceed tSTO
Yes
Figure 13. SCP Operation Status Transition Diagram
VCC2
OUT
VCC1
IN
PREDRIVER
LOGIC
LOGIC
PREDRIVER
PREDRIVER
PROOUT
STO
R
S
R
+
FLTRLS
FLT
-
V
TFLTRLS
+
-
SCPIN
SCPMSK
ECU
GND1
GND2
VEE2
Input Side
Output Side
Figure 14. Block Diagram for SCP
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5）I/O condition table
Input
Output
P
R
O
O
U
T
P
R
O
O
U
T
V
T
S
I
S
C
P
I
O
U
T
1
O
U
T
2
F
L
T
E
N
A
I
N
B
I
N
A
F
L
T
No.
Status
VCC1
VCC2
N
N
1
2
3
4
SCP
X
X
X
X
X
X
X
H
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
Hi-Z
L
L
L
L
L
L
L
L
L
L
UVLO
UVLO
X
Hi-Z Hi-Z
Hi-Z
Hi-Z Hi-Z
Hi-Z
Hi-Z Hi-Z
Hi-Z
VCC1UVLO
X
L
H
UVLO
H
L
VCC2UVLO
5
6
X
UVLO
○
X
L
L
L
L
L
L
L
L
L
L
X
X
X
L
X
X
X
X
X
H
H
L
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
L
H
L
L
L
L
L
L
L
L
L
L
H
○
○
○
○
○
○
○
○
Thermal protection
FLT external input
Disable
7
○
L
H
8
○
H
H
H
H
H
H
H
L
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
9
○
L
H
10
11
12
13
○
H
H
H
H
H
L
○
H
○
H
L
Non-invert operation
L input
○
L
L
L
H
Hi-Z Hi-Z
Non-invert operation
H input
14
15
○
○
○
○
H
H
L
L
H
H
L
L
L
H
L
X
X
H
H
L
Hi-Z Hi-Z
Invert operation L
input
H
L
Hi-Z Hi-Z
16
17
○
○
○
○
H
H
L
L
H
H
L
L
H
H
H
H
H
L
L
L
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z
Invert operation H
input
H
○: VCC1 or VCC2 > UVLO, X:Don't care
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6) Power supply startup / shutoff sequence
IN
H
L
VUVLO1L
VUVLO1L
VUVLO1L
VUVLO2H
VCC1
0V
VCC2
VEE2
OUT1
VUVLO2H
VUVLO2H
0V
0V
H
Hi-Z
L
H
Hi-Z
L
OUT2
PROOUT
FLT
Hi-Z
L
Hi-Z
L
H
L
IN
VCC1
VUVLO1L
VUVLO2H
VUVLO1H
VUVLO1H
0V
VUVLO2L
VUVLO2L
VCC2
0V
0V
VEE2
H
Hi-Z
OUT1
OUT2
PROOUT
FLT
L
H
Hi-Z
L
Hi-Z
L
Hi-Z
L
H
L
IN
VCC1
VCC2
VEE2
OUT1
OUT2
VUVLO1L
VUVLO1L
VUVLO1H
VUVLO2L
0V
VUVLO2H
VUVLO2H
0V
0V
H
Hi-Z
L
H
Hi-Z
L
Hi-Z
PROOUT
FLT
L
Hi-Z
L
H
L
IN
VCC1
VUVLO1H
VUVLO2L
VUVLO1H
VUVLO1H
0V
VCC2
VUVLO2L
VUVLO2L
0V
0V
VEE2
H
Hi-Z
L
OUT1
OUT2
PROOUT
FLT
H
Hi-Z
L
Hi-Z
L
Hi-Z
L
: Since the VCC2 to VEE2 pin voltage is low and the output MOS does not turn ON,
the output pins become Hi-Z conditions.
: Since the VCC1 pin voltage is low and the FLT output MOS does not turn ON, the
output pins become Hi-Z conditions.
Figure 15. Power supply startup / shutoff sequence
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●Absolute Maximum Ratings
Parameter
Symbol
VCC1
Limits
Unit
V
Input-side supply voltage
-0.3 to +7.0*1
-0.3 to +30.0*2
-15.0 to +0.3*2
Output-side positive supply voltage
Output-side negative supply voltage
VCC2
V
VEE2
V
Maximum difference
VMAX2
36.0
V
between output-side positive and negative voltages
INA, INB, ENA pin input voltage
FLT pin input voltage
VIN
VFLT
-0.3 to +VCC1+0.3 or 7.0*1
V
V
-0.3 to +VCC1+0.3 or 7.0*1
FLTRLS pin input voltage
VTSIN pin input voltage
VFLTRLS
VVTSIN
VSCPIN
IVREG
IOUT1
-0.3 to +VCC1+0.3 or 7.0*1
V
-0.3 to +10.0*2
V
SCPIN pin input voltage
-0.3 to +10.0*2
V
VREG pin output current
OUT1 pin output current (DC)
OUT1 pin output current (Peak 1us)
OUT2 pin output current (DC)
OUT2 pin output current (Peak 1us)
PROOUT pin output current
FLT output current
10
0.4*3
mA
A
IOUT1PEAK
IOUT2
5.0
A
0.1*3
A
IOUT2PEAK
IPROOUT
IFLT
1
A
0.2*3
A
10
mA
W
℃
℃
℃
Power dissipation
Pd
1.19*4
-40 to +125
-55 to +150
+150
Topr
Operating temperature range
Storage temperature range
Junction temperature
Tstg
Tjmax
*1 Relative to GND1.
*2 Relative to GND2.
*3 Should not exceed Pd and Tj=150C.
*4 Derate above Ta=25C at a rate of 9.5mW/C. Mounted on a glass epoxy of 70 mm 70 mm 1.6 mm.
●Recommended Operating Ratings
Parameter
Symbol
Min.
4.5
14
Max.
5.5
24
Units
V
*5
Input-side supply voltage
VCC1
*6
Output-side positive supply voltage
Output-side negative supply voltage
VCC2
V
*6
VEE2
-12
0
V
Maximum difference
VMAX2
14
0
32
5
V
V
between output-side positive and negative voltages
*6
VTSIN pin input voltage
VVTSIN
*5 Relative to GND1.
*6 Relative to GND2.
●Insulation related characteristics
Parameter
Symbol
RS
Characteristic
Units
Insulation Resistance (VIO=500V)
Insulation Withstand Voltage / 1min
Insulation Test Voltage / 1sec
>109
2500
3000
Ω
VISO
Vrms
Vrms
VISO
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●Electrical Characteristics
（Unless otherwise specified Ta=-40℃ to 125℃, V CC1=4.5V to 5.5V, VCC2=14V to 24V, VEE2=-12V to 0V）
Parameter
Symbol
Min.
Typ.
Max.
Unit
Conditions
General
Input side circuit current 1
Input side circuit current 2
Input side circuit current 3
Input side circuit current 4
Output side circuit current 1
Output side circuit current 2
Output side circuit current 3
Output side circuit current 4
Output side circuit current 5
ICC1
ICC12
ICC13
ICC14
ICC21
ICC22
ICC23
ICC24
ICC25
ICC26
0.20
0.20
1.2
2.1
1.9
1.3
2.1
1.4
2.4
1.6
0.45
0.45
2.0
3.5
3.2
2.1
3.5
2.4
4.0
2.7
0.70
0.70
2.8
4.9
4.5
2.9
4.9
3.4
5.6
3.8
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
OUT=L
OUT=H
INA=10kHz, Duty=50%
INA=20kHz, Duty=50%
VCC2=14V, OUT=L
VCC2=14V, OUT=H
VCC2=18V, OUT=L
VCC2=18V, OUT=H
VCC2=24V, OUT=H
VCC2=24V, OUT=L
Output side circuit current 6
Logic block
Logic high level input voltage
VINH
VINL
0.7×VCC1
-
-
VCC1
0.3×VCC1
100
V
INA, INB, ENA, FLT
INA, INB, ENA, FLT
INA, INB
Logic low level input voltage
Logic pull-down resistance
Logic pull-up resistance
Logic input mask time
ENA, FLT mask time
0
V
RIND
25
25
80
4
50
50
130
10
kΩ
kΩ
ns
RINU
100
ENA
tINMSK
tFLTMSK
180
INA, INB
20
μs
ENA, FLT
Output
IOUT=40mA
IOUT=40mA
OUT1 ON resistance (Source)
OUT1 ON resistance (Sink)
RONH
RONL
0.7
0.4
1.8
0.9
4.0
2.0
Ω
Ω
VCC2=18V
Design assurance
OUT1 maximum current
IOUTMAX
3.0
4.5
-
A
0.4
180
180
0.9
265
265
2.0
350
350
IPROOUT=40mA
PROOUT ON resistance
Turn ON time
RONPRO
tPON
Ω
ns
Turn OFF time
tPOFF
ns
Propagation distortion
Rise time
tPDIST
tRISE
-60
-
0
50
50
4.5
3.5
2
60
100
100
9.0
7.0
2.2
50
ns
ns
ns
Ω
Ω
tPOFF - tPON
10nF between OUT1-VEE2
10nF between OUT1-VEE2
IOUT2=40mA
Fall time
tFALL
-
OUT2 ON resistance (Source)
OUT2 ON resistance (Sink)
OUT2 ON threshold voltage
OUT2 output delay time
VREG output voltage
RON2H
RON2L
2.0
1.5
1.8
-
IOUT2=40mA
VOUT2ON
tOUT2ON
VREG
V
ns
V
Relative to VEE2
15
10
-
9
11
Relative to VEE2
Common Mode Transient Immunity
Protection functions
CM
100
-
kV/μs Design assurance
VCC1 UVLO OFF voltage
VCC1 UVLO ON voltage
VCC1 UVLO mask time
VCC2 UVLO OFF voltage
VCC2 UVLO ON voltage
VCC2 UVLO mask time
SCPIN Input voltage
VUVLO1H
VUVLO1L
tUVLO1MSK
VUVLO2H
VUVLO2L
tUVLO2MSK
VSCPIN
4.05
4.25
4.15
10
4.45
4.35
30
V
V
3.95
4
μs
V
11.5
12.5
11.5
10
13.5
12.5
30
10.5
V
4
μs
-
0.1
0.22
0.735
1.05
110
V
V
ISCPIN=1mA
SCP detection voltage
SCP detection mask time
Soft turn OFF release time
Thermal detection voltage
Thermal detection mask time
FLT output low voltage
VSCDET
tSCPMSK
tSTO
0.665
0.700
0.8
0.55
30
μs
V
VTSDET
tTSMSK
1.60
1.70
10
1.80
30
4
μs
V
VFLTL
-
0.18
0.40
0.64×VCC1
+0.1
IFLT=5mA
0.64×VCC1
-0.1
FLTRLS threshold
VTFLTRLS
0.64×VCC1
V
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© 2013 ROHM Co., Ltd. All rights reserved.
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TSZ02201-0717ABH00090-1-2
24.Jun.2013 Rev.001
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Daattaasshheeeett
BM6101FV-C
50%
50%
tPON
INA
tPOFF
90%
90%
50%
50%
10%
OUT1
10%
tFALL
tRISE
Figure 16. INA-OUT1 Timing Chart
●Typical Performance Curves
0.7
0.7
0.6
0.5
0.4
0.3
Ta=125℃
0.6
0.5
0.4
0.3
0.2
Vcc1=5.5V
Vcc1=5.0V
Vcc1=4.5V
Ta=25℃
Ta=-40℃
0.2
4.50
-40 -20
0
20
40
60
80 100 120
4.75
5.00
VCC1 [V]
5.25
5.50
℃
Ta [
]
Figure 17. Input side circuit current (at OUT1=L)
Figure 18. Input side circuit current (at OUT1=L)
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0.7
0.6
0.5
0.4
0.3
0.7
0.6
0.5
0.4
0.3
0.2
Ta=125℃
Vcc1=5.5V
Vcc1=5.0V
Ta=25℃
Vcc1=4.5V
Ta=-40℃
0.2
4.50
4.75
5.00
VCC1 [V]
5.25
5.50
-40 -20
0
20
40
Ta [
60
]
80 100 120
℃
Figure 19. Input side circuit current (at OUT1=H)
Figure 20. Input side circuit current (at OUT1=H)
2.8
2.4
2.0
1.6
1.2
2.8
2.4
2.0
1.6
1.2
Ta=-40℃
Vcc1=5.5V
Vcc1=5.0V
Vcc1=4.5V
Ta=25℃
Ta=125℃
4.50
4.75
5.00
5.25
5.50
-40 -20
0
20
40
60
80 100 120
VCC1 [V]
℃
Ta [
]
Figure 21. Input side circuit current
(at INA=10kHz and Duty=50%)
Figure 22. Input side circuit current
(at INA=10kHz and Duty=50%)
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BM6101FV-C
4.9
4.5
4.1
3.7
3.3
2.9
2.5
4.9
4.5
4.1
3.7
3.3
2.9
2.5
2.1
Ta=-40℃
Vcc1=5.5V
Vcc1=4.5V
Ta=25℃
Vcc1=5.0V
Ta=125℃
2.1
4.50
4.75
5.00
VCC1 [V]
5.25
5.50
-40 -20
0
20
40
Ta [
60
80 100 120
℃
]
Figure 23. Input side circuit current
(at INA=20kHz and Duty=50%)
Figure 24. Input side circuit current
(at INA=20kHz and Duty=50%)
5.6
5.2
4.8
4.4
4.0
3.6
3.2
2.8
2.4
2.0
1.6
1.2
5.6
5.2
4.8
4.4
4.0
3.6
3.2
2.8
2.4
2.0
1.6
Vcc2=24V
Ta=125℃
Vcc2=18V
Vcc2=14V
Ta=25℃
Ta=-40℃
1.2
14
-40 -20
0
20
40
Ta [
60
80 100 120
16
18
20
22
24
℃
]
VCC2 [V]
Figure 25. Output side circuit current (at
OUT1=L)
Figure 26. Output side circuit current (at OUT1=L)
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BM6101FV-C
5.6
5.2
4.8
4.4
4.0
3.6
3.2
2.8
2.4
2.0
1.6
1.2
5.6
5.2
4.8
4.4
4.0
3.6
3.2
2.8
2.4
2.0
1.6
Vcc2=24V
Ta=125℃
Ta=25℃
Vcc2=18V
Vcc2=14V
20 40
Ta=-40℃
1.2
14
-40 -20
0
60
]
80 100 120
16
18
20
22
24
℃
Ta [
VCC2 [V]
Figure 27. Output side circuit current (at OUT1=H)
Figure 28. Output side circuit current (at OUT1=H)
24
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Ta=125℃
Ta=25℃
Ta=-40℃
20
16
12
8
Vcc1=5V
H level
L level
Ta=-40℃
Ta=25℃
Ta=125℃
4
0
4.50
4.75
5.00
VCC1 [V]
5.25
5.50
0
1
2
3
4
5
INA [V]
Figure 29. Logic (INA/INB/ENA) High/Low level
input voltage
Figure 30. Logic (INA/INB/ENA) High/Low level
input voltage at Ta=25℃
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24.Jun.2013 Rev.001
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Daattaasshheeeett
BM6101FV-C
100.0
75.0
50.0
100.0
75.0
50.0
25.0
Ta=-40℃
Ta=-40℃
Ta=25℃
Ta=25℃
Ta=125℃
Ta=125℃
25.0
4.50
4.75
5.00
VCC1 [V]
5.25
5.50
4.50
4.75
5.00
VCC1 [V]
5.25
5.50
Figure 31. Logic pull-down resistance
Figure 32. Logic pull-up resistance
180.0
160.0
140.0
120.0
100.0
180.0
160.0
140.0
120.0
100.0
80.0
Ta=125℃
Ta=125℃
Ta=25℃
Ta=-40℃
Ta=25℃
Ta=-40℃
80.0
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
VCC1 [V]
VCC1 [V]
Figure 33. Logic (INA/INB) input mask time
(High pulse)
Figure 34. Logic (INA/INB) input mask time
(Low pulse)
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20
16
12
8
20
16
12
8
Ta=-40℃
Ta=-40℃
Ta=25℃
Ta=25℃
Ta=125℃
Ta=125℃
4
4
4.50
4.75
5.00
VCC1 [V]
5.25
5.50
4.50
4.75
5.00
VCC1 [V]
5.25
5.50
Figure 35. ENA input mask time
Figure 36. FLT input mask time
2.0
1.6
1.2
0.8
0.4
3.7
3.1
2.5
1.9
1.3
Ta=125℃
Ta=25℃
Ta=125℃
Ta=25℃
Ta=-40℃
Ta=-40℃
0.7
14
14
16
18
20
22
24
16
18
20
22
24
VCC2 [V]
VCC2 [V]
Figure 37. OUT1 ON resistance (Source)
Figure 38. OUT1 ON resistance (Sink)
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BM6101FV-C
2.0
1.6
1.2
0.8
340
300
260
220
180
Ta=125℃
Ta=-40℃
Ta=125℃
Ta=25℃
Ta=25℃
Ta=-40℃
0.4
14
16
18
20
22
24
14
16
18
20
22
24
VCC2 [V]
VCC2 [V]
Figure 39. PROOUT ON resistance
Figure 40. Turn ON time
400
350
300
250
200
100
90
80
70
60
50
40
30
20
10
0
Ta=125℃
Ta=-40℃
Ta=125℃
Ta=25℃
Ta=25℃
Ta=-40℃
150
14
16
18
20
22
24
14
16
18
20
22
24
VCC2 [V]
VCC2 [V]
Figure 41. Turn OFF time
Figure 42. Rise time (10nF between OUT1-VEE2)
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BM6101FV-C
100
90
80
70
60
50
40
30
20
10
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
Ta=125℃
Ta=125℃
Ta=25℃
Ta=-40℃
Ta=25℃
Ta=-40℃
0
14
16
18
20
22
24
14
16
18
20
22
24
VCC2 [V]
VCC2 [V]
Figure 44. OUT2 ON resistance (Source)
Figure 43. Fall time (10nF between OUT1-VEE2)
2.2
2.1
2.0
1.9
1.8
6.5
5.5
4.5
3.5
2.5
1.5
Ta=125℃
Ta=125℃
Ta=25℃
Ta=-40℃
Ta=25℃
Ta=-40℃
14
16
18
20
22
24
14
16
18
20
22
24
VCC2 [V]
VCC2 [V]
Figure 45. OUT2 ON resistance (Sink)
Figure 46. OUT2 ON threshold voltage
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BM6101FV-C
11.0
10.5
10.0
9.5
50
40
30
20
10
0
Ta=-40℃
Ta=125℃
Ta=25℃
Ta=125℃
Ta=25℃
Ta=-40℃
9.0
14
16
18
20
22
24
14
16
18
20
22
24
VCC2 [V]
VCC2 [V]
Figure 47. OUT2 output delay time
Figure 48. VREG output voltage
5
4
3
2
1
0
11.0
Vcc2=24V
Vcc2=18V
Vcc2=14V
10.5
10.0
9.5
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
9.0
-40 -20
0
20 40 60
80 100 120
3.95
4.05
4.15
4.25
4.35
4.45
℃
Ta [
]
VCC1 [V]
Figure 49. VREG output voltage
Figure 50. VCC1 UVLO ON/OFF voltage
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BM6101FV-C
6
5
4
3
2
1
0
28
24
20
16
12
8
Ta=125℃
Ta=25℃
Ta=125℃
Ta=25℃
Ta=-40℃
Ta=-40℃
4
-40 -20
0
20
40
Ta [
60
80 100 120
10.5
11.5
12.5
13.5
℃
]
VCC2 [V]
Figure 51. VCC1 UVLO mask time
Figure 52. VCC2 UVLO ON/OFF voltage
(at VCC1=5V)
0.22
0.11
0.00
28
24
20
16
12
8
Ta=125℃
Ta=25℃
Ta=-40℃
4
14
16
18
VCC2 [V]
20
22
24
-40 -20
0
20
40
Ta [
60
80 100 120
℃
]
Figure 53. VCC2 UVLO mask time
Figure 54. SCPIN input voltage (at ISCPIN=1mA)
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0.73
1.05
0.95
0.85
0.75
0.65
0.55
Ta=-40℃
Ta=25℃
0.70
Ta=-40℃
Ta=25℃ Ta=125℃
Ta=125℃
0.67
14
16
18
20
22
24
14
16
18
20
22
24
VCC2 [V]
VCC2 [V]
Figure 55. SCP detection voltage
Figure 56. SCP detection mask time
110
90
1.8
1.7
1.6
Ta=25℃
Ta=125℃
Vcc2=14V
Vcc2=18V
Vcc2=24V
Ta=-40℃
Vcc2=14V
Vcc2=18V
Vcc2=24V
70
Max.
Min.
50
30
-40 -20
0
20 40
Ta [
60
80 100 120
14
16
18
VCC2 [V]
20
22
24
℃
]
Figure 57. Soft turn OFF release time
Figure 58. Thermal detection voltage
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0.4
0.3
0.2
0.1
0.0
28.0
24.0
20.0
16.0
12.0
8.0
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=25℃
Ta=125℃
Ta=-40℃
4.0
14
16
18
20
VCC2 [V]
22
24
4.50
4.75
5.00
VCC2 [V]
5.25
5.50
Figure 59. Thermal detection mask time
Figure 60. FLT output low voltage (IFLT=5mA)
3.62
3.41
3.20
2.99
2.78
Ta=-40℃
Ta=25℃
Ta=125℃
4.50
4.75
5.00
5.25
5.50
VCC1 [V]
Figure 61. FLTRLS threshold
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BM6101FV-C
●Selection of Components Externally Connected
Recommended
ROHM
RSR025N3
RSS065N03
Recommended
ROHM
MCR03EZP
GND1
PROOUT
S
R
NC
PRE
DRIVER
VEE2
OUT1
VCC2
LOGIC
Q
INB
MASK
FLTRLS
LOGIC
VEE2
UVLO
MASK
VCC1
FLT
VREG
OUT2
SCPIN
GND2
VEE2
TIMER
TIMER
FB
UVLO
MASK
MASK
MASK
INA
ECU
FLT
FLT
ENA
TEST
GND1
Input side
chip
Output side
chip
MASK
Temp Sensor
VTSIN
Figure 62. For using 4-pin IGBT (for using SCP function)
Recommended
ROHM
MCR03EZP
Recommended
ROHM
RSR025N3
RSS065N03
Recommended
ROHM
MCR03EZP
GND1
NC
PROOUT
S
VEE2
OUT1
VCC2
VREG
OUT2
SCPIN
GND2
PRE
DRIVER
LOGIC
Q
INB
R
MASK
FLTRLS
LOGIC
VEE2
VCC1
FLT
UVLO
MASK
FB
TIMER
TIMER
UVLO
MASK
MASK
INA
ECU
FLT
FLT
ENA
MASK
TEST
VEE2
Input side
chip
Output side
chip
MASK
GND1
VTSIN
Temp Sensor
Figure 63. For using 3-pin IGBT (for using DESAT function)
Recommended
ROHM
MCR03EZP
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TSZ02201-0717ABH00090-1-2
24.Jun.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
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●Power Dissipation
Measurement machine：TH156（Kuwano Electric）
Measurement condition：ROHM board
Board size：70×70×1.6mm3
1.5
1.19W
1-layer board：θja=105.3℃/W
1.0
0.5
0
0
25
50
75
100
125
150
Ambient Temperature:Ta[℃]
Figure 64. SSOP-B20W Derating Curve
●Thermal design
Please design that the IC’s chip temperature Tj is not over 150℃, while considering the IC’s power consumption (W),
package power (Pd) and ambient temperature (Ta). When Tj=150℃ is exceeded the functions as a semiconductor do not
operate and some problems (ex. Abnormal operation of various parasitic elements and increasing of leak current) occur.
Constant use under these circumstances leads to deterioration and eventually IC may destruct. Tjmax=150℃ must be strictly
obeyed under all circumstances.
The IC’s consumed power (P) can be estimated roughly with following equation.
2
2
P＝VCC1・ICC1 + VCC2・IGND2 +（VCC2 + VEE2）・（ICC2-IGND2）+ ION ・RONH・tON・fPWM + IOFF ・RONL・tOFF・fPWM
fPWM : PWM frequency
ION : OUT pin outflow current when OUT is H state.
tON : Current outflow time from OUT pin when OUT is H state.
IOFF : OUT pin inflow current when OUT is L state.
tOFF : Current inflow time to OUT pin when OUT is L state.
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●I/O equivalence circuits
Name
Pin No.
I/O equivalence circuits
Function
VTSIN
VCC2
Internal pow er supply
1
Thermal detection pin
SCPIN
SCPIN
VTSIN
GND2
4
5
6
Short current detection pin
VEE2
VCC2
OUT2
MOS FET control pin for Miller Clamp
VREG
Internal pow er supply
VREG
OUT2
Power supply pin for driving MOS FET
for Miller Clamp
VEE2
VCC2
OUT
8
OUT1
VEE2
Output pin
VCC2
VREG
PROOUT
10
PROOUT
VEE2
Soft turn-off pin
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TSZ02201-0717ABH00090-1-2
24.Jun.2013 Rev.001
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Name
Pin No.
I/O equivalence circuits
Function
VCC1
FLTRLS
FLTRLS
14
Fault output holding time setting pin
GND1
VCC1
FLT
FLT
16
Fault output pin
GND1
VCC1
INB
Invert / non-invert selection pin
INA
13
17
INA, INB
Control input pin
GND1
VCC1
ENA
18
ENA
Input enabling signal input pin
GND1
VCC1
TEST
19
TEST
GND1
Test mode setting pin
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TSZ02201-0717ABH00090-1-2
24.Jun.2013 Rev.001
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●Operational Notes
(1) Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc.,
can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open
circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection
devices, such as fuses.
(2) Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power
supply lines. An external direction diode can be added.
(3) Power supply Lines
Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply
line, separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply
terminals to ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic
capacitors in the circuit, not that capacitance characteristic values are reduced at low temperatures.
(4) GND1 Potential
The potential of GND1 pin must be minimum potential in all operating conditions. (Input side ; 11pin to 20pin)
(5) VEE2 Potential
The potential of VEE2 pin must be minimum potential in all operating conditions. (Output side ; 1pin to 10pin)
(6) Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
(7) Inter-pin shorts and mounting errors
When attaching to a printed circuit board, pay close attention to the direction of the IC and displacement. Improper
attachment may lead to destruction of the IC. There is also possibility of destruction from short circuits which can be
caused by foreign matter entering between outputs or an output and the power supply or GND.
(8) Operation in a strong electric field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to
malfunction.
(9) Inspection of the application board
During inspection of the application board, if a capacitor is connected to a pin with low impedance there is a possibility
that it could cause stress to the IC, therefore an electrical discharge should be performed after each process. Also, as a
measure again electrostatic discharge, it should be earthed during the assembly process and special care should be
taken during transport or storage. Furthermore, when connecting to the jig during the inspection process, the power
supply should first be turned off and then removed before the inspection.
(10) Input terminal of IC
Between each element there is a P+ isolation for element partition and a P substrate. This P layer and each element’s
N layer make up the P-N junction, and various parasitic elements are made up.
For example, when the resistance and transistor are connected to the terminal as shown in figure 65,
○When GND＞(Terminal A) at the resistance and GND＞(Terminal B) at the transistor (NPN), the P-N
junction operates as a parasitic diode.
○Also, when GND＞(Terminal B) at the transistor (NPN), The parasitic NPN transistor operates with the
N layers of other elements close to the aforementioned parasitic diode.
Because of the IC’s structure, the creation of parasitic elements is inevitable from the electrical potential relationship.
The operation of parasitic elements causes interference in circuit operation, and can lead to malfunction and
destruction. Therefore, be careful not to use it in a way which causes the parasitic elements to operate, such as by
applying voltage that is lower than the GND (P substrate) to the input terminal.
Resistor
Transistor (NPN)
Terminal A
Terminal B
Terminal B
B
C
E
Terminal A
C
B
N
N
N
P+
P+
N
P+
P+
N
P
P
N
Parasitic
element
E
Parasitic
element
P substrate
P substrate
GND
GND
GND
GND
Parasitic element
Parasitic
element
Other adjacent elements
Figure 65. Pattern Diagram of Parasitic Element
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TSZ02201-0717ABH00090-1-2
24.Jun.2013 Rev.001
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(11) Ground Wiring Patterns
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change
the GND wiring pattern potential of any external components, either.
●Ordering Information
F
V
B M 6
1
0
1
-
CE 2
Package
FV:SSOP-B20W
Packaging and forming specification
E2: Embossed tape and reel
Part Number
●Physical Dimension Tape and Reel Information
SSOP-B20W
<Tape and Reel information>
6.5 0.2
Tape
Embossed carrier tape
2000pcs
20
11
Quantity
E2
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
(
)
1
10
0.15 0.1
0.1
0.65
Direction of feed
1pin
0.22 0.1
Reel
Order quantity needs to be multiple of the minimum quantity.
(Unit : mm)
∗
●Marking Diagram
SSOP-B20W(TOP VIEW)
B M 6 1 0 1
Part Number Marking
LOT Number
1PIN MARK
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TSZ02201-0717ABH00090-1-2
24.Jun.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
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●Revision History
Date
Revision
Changes
24.Jun.2013
001
New Release
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TSZ02201-0717ABH00090-1-2
24.Jun.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
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Notice
●General Precaution
1) Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2) All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
●Precaution on using ROHM Products
1) Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
intend to use our Products in devices requiring extremely high reliability (such as medical equipment, transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
2) ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3) Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4) The Products are not subject to radiation-proof design.
5) Please verify and confirm characteristics of the final or mounted products in using the Products.
6) In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse) is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7) De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8) Confirm that operation temperature is within the specified range described in the product specification.
9) ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Notice - Rev.004
© 2013 ROHM Co., Ltd. All rights reserved.
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●Precaution for Mounting / Circuit board design
1) When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2) In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
ROHM representative in advance.
For details, please refer to ROHM Mounting specification
●Precautions Regarding Application Examples and External Circuits
1) If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2) You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
●Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
●Precaution for Storage / Transportation
1) Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2) Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3) Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4) Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
●Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
●Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
●Precaution for Foreign Exchange and Foreign Trade act
Since our Products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act,
please consult with ROHM representative in case of export.
●Precaution Regarding Intellectual Property Rights
1) All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data. ROHM shall not be in any way responsible or liable
for infringement of any intellectual property rights or other damages arising from use of such information or data.:
2) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the information contained in this document.
Notice - Rev.004
© 2013 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
●Other Precaution
1) The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
2) This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
3) The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
4) In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
5) The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice - Rev.004
© 2013 ROHM Co., Ltd. All rights reserved.
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