BR24G128FVT-3GTE2 [ROHM]
EEPROM;
| 型号： | BR24G128FVT-3GTE2 |
| 厂家： | 
ROHM |
| 描述： | EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总19页 (文件大小：3580K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Reliability Series Serial EEPROM Series
I2C BUS
Serial EEPROMs
BR24G□□□-3 Series
BR24G01-3, BR24G02-3, BR24G04-3, BR24G08-3, BR24G16-3, BR24G32-3,
BR24G64-3, BR24G128-3, BR24G256-3
ROHM's series of serial EEPROMs represent the highest level of reliability on the market. A double cell structure provides a
failsafe method of data reliability, while a double reset function prevents data miswriting, pushing the boundaries of reliability
to the limit.
Contents
BR24G□□□ꢀ3 Series
BR24G01-3, BR24G02-3, BR24G04-3, BR24G08-3,
BR24G16-3, BR24G32-3, BR24G64-3, BR24G128-3,
BR24G256-3
www.rohm.com
2011.9 - Rev.A
1/19
© 2011 ROHM Co., Ltd. All rights reserved.
Technical Note
BR24G□□□-3 Series
I2C BUS Serial EEPROMs
BR24G□□□-3 Series
BR24G01-3, BR24G02-3, BR24G04-3, BR24G08-3, BR24G16-3, BR24G32-3,
BR24G64-3, BR24G128-3, BR24G256-3
●Description
BR24G□□□-3 series is a serial EEPROM of I2C BUS interface method
●Features
・ Completely conforming to the world standard I2C BUS. All controls available by 2 ports of serial clock(SCL) and serial
data(SDA)
・ Other devices than EEPROM can be connected to the same port, saving microcontroller port
・ 1.7V～5.5V single power source action most suitable for battery use
・ 1.7V～5.5Ｖwide limit of action voltage, possible FAST MODE 400KHz action
・ Page write mode useful for initial value write at factory shipment
・ Auto erase and auto end function at data write
・ Low current consumption
・ Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
・ DIPꢀT8/SOP8/SOPꢀJ8/SSOPꢀB8/TSSOPꢀB8/TSSOPꢀB8J/MSOP8/VSON008X2030 various package
・ Data rewrite up to 1,000,000 times
・ Data kept for 40 years
・ Noise filter built in SCL / SDA terminal
・ Shipment data all address FFh
●BR24G series
Power source
Capacity Bit format
Type
SOP8
SOPꢀJ8
SSOPꢀB8 TSSOPꢀB8 TSSOPꢀB8J
MSOP8
Voltage
1Kbit
2Kbit
128×8 BR24G01ꢀ3
256×8 BR24G02ꢀ3
512×8 BR24G04ꢀ3
1.7～5.5V
1.7～5.5V
1.7～5.5V
1.7～5.5V
1.7～5.5V
1.7～5.5V
1.7～5.5V
●
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●
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●
●
●
●
●
●
●
●
4Kbit
8Kbit
1K×8
2K×8
4K×8
8K×8
BR24G08ꢀ3
BR24G16ꢀ3
BR24G32ꢀ3
BR24G64ꢀ3
16Kbit
32Kbit
64Kbit
128Kbit
256Kbit
16K×8 BR24G128ꢀ3 1.7～5.5V
32K×8 BR24G256ꢀ3 1.7～5.5V
www.rohm.com
2011.9 - Rev.A
2/19
© 2011 ROHM Co., Ltd. All rights reserved.
Technical Note
BR24G□□□-3 Series
●Absolute maximum ratings (Ta=25℃)
●Memory cell characteristics (Ta=25℃, Vcc=1.7～5.5V)
Parameter
symbol
Limits
Unit
V
Limits
Impressed voltage
VCC
ꢀ0.3～+6.5
Parameter
Unit
450 (SOP8) *1
Min.
1,000,000
40
Typ.
－
Max
－
450 (SOPꢀJ8) *2
300 (SSOPꢀB8) *3
330 (TSSOPꢀB8) *4
310 (TSSOPꢀB8J) *5
310 (MSOP8) *6
300 (VSON008X2030) *7
800 (DIPꢀT8) *8
－65～+150
Number of data rewrite times *1
Data hold years *1
Times
Years
－
－
Permissible
dissipation
Pd
mW
*1
Not 100% TESTED
●Recommended operating conditions
Storage temperature range
Action temperature range
Terminal voltage
Tstg
Topr
‐
℃
℃
V
－40～+85
Parameter
Power source voltage
Input voltage
Symbol
Vcc
Limits
1.7～5.5
0～Vcc
Unit
V
－0.3～Vcc+1.0*9
Junction Temperature *10
Tjmax
150
℃
When using at Ta=25℃ or higher, 8.0mW(*8), 4.5mW(*1,*2),
3.0mW(*3,*7), 3.3mW(*4), 3.1mW(*5, *6) to be reduced per 1℃.
VIN
*9 The Max value of Terminal Voltage is not over 6.5V. When the pulse width is 50ns or less,
the Min value of Terminal Voltage is not under ꢀ1.0V. (BR24G16/32/64/128/256ꢀ3)
the Min value of Terminal Voltage is not under ꢀ0.8V. (BR24G01/02/04/08ꢀ3)
*10 Junction temperature at the storage condition.
●Action timing characteristics
●Electrical characteristics
(Unless otherwise specified, Ta=－40～+85℃, VCC=1.7～5.5V)
(
Unless otherwise specified, Ta=－40～+85℃、VCC=1.7～5.5V)
Limit
Limits
Parameter
Symbol
Unit
Parameter
Symbol
Unit
Conditions
Min.
0.7Vcc
－0.3*1
－
Typ.
－
Max.
Vcc+1.0
0.3Vcc
0.4
Min.
－
Typ.
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
Max.
400
－
“H” input voltage 1
“L” input voltage 1
“L” output voltage 1
“L” output voltage 2
Input leak current
Output leak current
VIH1
VIL1
VOL1
VOL2
ILI
V
V
SCL frequency
fSCL
tHIGH
tLOW
tR
kHz
μs
μs
μs
μs
μs
μs
ns
－
Data clock “HIGH“ time
Data clock “LOW“ time
SDA, SCL rise time *1
0.6
1.2
－
－
V
IOL=3.0mA, 2.5V≦Vcc≦5.5V (SDA)
IOL=0.7mA, 1.7V≦Vcc＜2.5V (SDA)
VIN=0～Vcc
－
－
－
0.2
V
1.0
1.0
－
SDA, SCL fall time *1
tF
－
－1
－
1
ꢁA
ꢁA
ILO
－1
－
1
VOUT=0～Vcc (SDA)
Start condition hold time
Start condition setup time
Input data hold time
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
0.6
0.6
0
Vcc=5.5V,fSCL=400kHz, tWR=5ms,
Byte write, Page write
－
－
－
－
－
2.0
2.5
－
BR24G01/02/04/08/16/32/64ꢀ3
Vcc=5.5V,fSCL=400kHz, tWR=5ms,
Byte write, Page write
ICC1
mA
Input data setup time
100
0.1
0.1
0.6
1.2
－
－
ns
0.9
－
Output data delay time
Output data hold time
μs
μs
μs
μs
ms
μs
μs
μs
μs
Current consumption
at action
tDH
BR24G128/256ꢀ3
－
Stop condition setup time
Bus release time before transfer start
Internal write cycle time
Noise removal valid period (SDA, SCL terminal)
WP hold time
tSU:STO
tBUF
Vcc=5.5V,fSCL=400kHz
－
mA
ꢁA
Random read, current read,
sequential read
ICC2
－
－
－
－
0.5
2.0
tWR
5
BR24G01/02/04/08/16/32/64/128/256ꢀ3
Vcc=5.5V, SDA・SCL=Vcc
A0,A1,A2=GND,WP=GND
BR24G01/02/04/08/16/32/64/128/256ꢀ3
－
0.1
－
tI
tHD:WP
tSU:WP
tHIGH:WP
1.0
0.1
1.0
Standby current
ISB
－
WP setup time
－
WP valid time
○Radiation resistance design is not made.
*1 Not 100% TESTED.
*1 When the pulse width is 50ns or less, it is ꢀ1.0V. (BR24G16/32/64/128/256ꢀ3)
When the pulse width is 50ns or less, it is ꢀ0.8V. (BR24G01/02/04/08ꢀ3)
Condition
Input data level:VIL=0.2×Vcc VIH=0.8×Vcc
Input data timing reference level: 0.3×Vcc/0.7×Vcc
Output data timing reference level: 0.3×Vcc/0.7×Vcc
Rise/Fall time : ≦20ns
●Sync data input / output timing
tR
tF
tHIGH
70%
70%
30%
70%
SCL
70% 70%
30%
30%
30%
tLOW
tHD:DAT
DATA(n)
DATA(1)
D0 ACK
tSU:DAT
70%
70%
70%
70%
ACK
D1
70%
30%
tWR
SDA
(input)
tPD
tDH
tBUF
30%
30%
70%
30%
70%
30%
SDA
(output)
tSU:WP
tHD:WP
STOP CONDITION
○
Input read at the rise edge of SCL
Data output in sync with the fall of SCL
○
Fig.1ꢀ(a) Sync data input / output timing
Fig.1ꢀ(d) WP timing at write execution
70%
70%
70%
tSU:STA
tHD:STA
DATA(n)
tSU:STO
DATA(1)
70%
70%
D1
ACK
ACK
D0
30%
30%
tWR
tHIGH:WP
STOP CONDITION
START CONDITION
70%
70%
Fig.1ꢀ(b) Startꢀstop bit timing
Fig.1ꢀ(e) WP timing at write cancel
70%
70%
ACK
D0
write data
(nꢀth address)
tWR
STOP CONDITION START CONDITION
Fig.1ꢀ(c) Write cycle timing
www.rohm.com
2011.9 - Rev.A
3/19
© 2011 ROHM Co., Ltd. All rights reserved.
Technical Note
BR24G□□□-3 Series
●Block diagram
*2
A0
1
8
Vcc
1Kbit 256 Kbit EEPROM array
～
*1
Vcc
8
1
2
3
A0
A1
BR24G01ꢀ3
BR24G02ꢀ3
BR24G04ꢀ3
BR24G08ꢀ3
BR24G16ꢀ3
BR24G32ꢀ3
BR24G64ꢀ3
BR24G128ꢀ3
BR24G256ꢀ3
8bit
*17bit
13bit
8bit 14bit
9bit 15bit
10bit
WP
7
6
Address
decoder
Word
address register
Data
register
*2 A1
*2 A2
GND
2
3
4
7
6
5
WP
SCL
SDA
11bit
12bit
SCL
A2
START
STOP
Control circuit
4
5
SDA
GND
ACK
High voltage
generating circuit
Power source
voltage detection
＊1
7bit: BR24G01ꢀ3
8bit: BR24G02ꢀ3
9bit: BR24G04ꢀ3
10bit: BR24G08ꢀ3
11bit: BR24G16ꢀ3
12bit: BR24G32ꢀ3
13bit: BR24G64ꢀ3
14bit: BR24G128ꢀ3
15bit: BR24G256ꢀ3
*2 A0= Don't use : BR24G04ꢀ3
A0, A1=Don't use : BR24G08ꢀ3
A0, A1, A2=Don't use : BR24G16ꢀ3
Fig.2 Block diagram
●Pin assignment and description
Terminal
Name
Input/
BR24G01ꢀ3
BR24G02ꢀ3
BR24G04ꢀ3
BR24G08ꢀ3
BR24G16ꢀ3
BR24G32/64/128/256ꢀ3
Output
Slave address setting
Slave address setting
Slave address setting
Slave address setting
Don’t use＊
A0
A1
Input
Input
Input
－
Don’t use＊
Don’t use＊
Slave address setting
Slave address setting
A2
GND
Reference voltage of all input / output, 0V
Serial data input serial data output
Input/
output
SDA
SCL
WP
Vcc
Input
Input
－
Serial clock input
Write protect terminal
Connect the power source.
＊Pins not used as device address may be set to any of ‘H’, 'L', and 'HiꢀZ'.
●Characteristic data (The following values are Typ. ones.)
1
0.8
0.6
0.4
0.2
0
6
6
Ta=-40℃
Ta=25℃
Ta=85℃
5
4
3
2
1
0
Ta=-40℃
Ta=25℃
Ta=85℃
5
4
3
2
1
0
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
SPEC
SPEC
4
0
1
2
3
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
L OUTPUT CURRENT : IOL(mA)
Fig.4ꢀ'L' input voltage VIL1
Fig.5 'L' output voltage VOL1ꢀIOL(Vcc=1.7V)
Fig.3ꢀ'H' input voltage VIH1
(A0,A1,A2,SCL,SDA,WP)
(A0,A1,A2,SCL,SDA,WP)
1.2
1
0.8
0.6
0.4
0.2
0
1.2
1
SPEC
SPEC
1
0.8
0.6
0.4
0.2
0
Ta=-40℃
Ta=25℃
Ta=85℃
0.8
0.6
0.4
0.2
0
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLYVOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
L OUTPUT CURRENT : IOL(mA)
Fig.7ꢀInput leak current ILI
Fig.8ꢀOutput leak current ILO(SDA)
Fig.6ꢀ'L' output voltage VOL2ꢀIOL(Vcc=2.5V)
(A0,A1,A2,SCL,WP)
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
2011.9 - Rev.A
4/19
Technical Note
BR24G□□□-3 Series
●Characteristic data (The following values are Typ. ones.)
3.5
0.6
0.5
0.4
0.3
0.2
0.1
0
2.5
SPEC
3
SPEC
2
SPEC
2.5
1.5
1
2
1.5
1
Ta=-40℃ꢀ
Ta=25℃
Ta=85℃
Ta=-40℃ꢀ
Ta=25℃
Ta=85℃
Ta=-40℃ꢀ
Ta=25℃
Ta=85℃
0.5
0
0.5
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.11 Current consumption at READ operation ICC
SUPPLY VOLTAGE : Vcc(V)
Fig.9 Current consumption at WRITE operation ICC
(fscl=400kHz BR24G01/02/04/08/16/32/64ꢀ3)
1
Fig.10ꢀCurrent consumption at WRITE operation Icc1
2
(fscl=400kHz BR24G128/256ꢀ3)
(fscl=400kHz BR24G01/02/04/08/16/32/64/128/256ꢀ3)
2.5
1
10000
SPEC
2
0.8
1000
100
10
SPEC
SPEC
1.5
0.6
Ta=-40℃ꢀ
Ta=25℃
Ta=85℃
Ta=-40℃ꢀ
Ta=25℃
Ta=85℃
1
0.5
0
0.4
0.2
0
Ta=-40℃ꢀ
Ta=25℃
Ta=85℃
1
0.1
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.12ꢀStandby operation ISB
Fig.13ꢀSCL frequency fSCL
Fig.14 Data clock High Period tHIGH
(fscl=400kHz BR24G01/02/04/08/16/32/64/128/256ꢀ3)
1.1
1
1.5
SPEC
0.9
0.7
1.2
0.8
0.6
0.4
0.2
0
SPEC
SPEC
0.9
Ta=-40℃ꢀ
0.5
Ta=25℃
Ta=85℃
Ta=-40℃ꢀ
Ta=25℃
0.6
Ta=-40℃ꢀ
Ta=25℃
0.3
Ta=85℃
Ta=85℃
0.3
0
0.1
-0.1
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
Fig.17ꢀStart Condition Setup TimeꢀtSU : STA
SUPPLY VOLTAGE : Vcc（V）
SUPPLY VOLTAGE : Vcc(V)
Fig.15 Data clock Low PeriodꢀtLOW
Fig.16 Start Condition Hold Time tHD : STA
300
50
50
0
SPEC
SPEC
200
100
0
0
-50
SPEC
-50
-100
-150
-200
Ta=-40℃ꢀ
Ta=25℃
Ta=85℃
-100
-150
-200
Ta=-40℃ꢀ
Ta=25℃
Ta=85℃
Ta=-40℃ꢀ
Ta=25℃
-100
-200
Ta=85℃
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.18ꢀInput Data Hold Time tHD : DAT（HIGH）
Fig.19ꢀInput Data Hold Time tHD : DAT(LOW）
Fig.20ꢀInput Data Setup Time tSU: DAT(HIGH)
300
200
2.0
1.5
1.0
0.5
0.0
2.0
Ta=-40℃ꢀ
Ta=25℃
Ta=85℃
Ta=-40℃ꢀ
Ta=25℃
Ta=85℃
1.5
SPEC
100
SPEC
SPEC
1.0
0
Ta=-40℃ꢀ
Ta=25℃
Ta=85℃
0.5
-100
-200
SPEC
0.0
SPEC
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
Fig.23 'H' Data output delay time tPD
SUPPLY VOLTAGE : Vcc(V)
Fig.21ꢀInput Data setup time tSU : DAT(LOW)
SUPPLY VOLTAGE : Vcc(V)
Fig.22ꢀ'L' Data output delay time tPD
0
1
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
2011.9 - Rev.A
5/19
Technical Note
BR24G□□□-3 Series
●Characteristic data (The following values are Typ. ones.)
2.0
1.5
2
1.5
1
6
5
4
3
2
1
0
SPEC
Ta=-40℃ꢀ
Ta=25℃
Ta=85℃
SPEC
1.0
SPEC
Ta=-40℃ꢀ
Ta=25℃
Ta=85℃
0.5
Ta=-40℃ꢀ
Ta=25℃
Ta=85℃
0.5
0
0.0
0
1
2
3
4
5
6
-0.5
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.26 Internal writing cycle timeꢀtWR
Fig.24 Stop condition setup timeｔSU:STO
Fig.25 BUS open time before transmissionꢀtBUF
0.6
0.6
0.6
Ta=-40℃ꢀ
Ta=25℃
0.5
0.5
0.5
Ta=-40℃ꢀ
Ta=-40℃ꢀ
Ta=25℃
Ta=85℃
Ta=85℃
Ta=25℃
Ta=85℃
0.4
0.4
0.4
0.3
0.2
0.3
0.2
0.3
0.2
0.1
0.1
0.1
SPEC
SPEC
SPEC
0
0
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.28ꢀNoise reduction effective timeꢀtl（SCL L）
SUPPLY VOLATGE : Vcc(V)
Fig.29ꢀNoise reduction effective timeꢀtｌ（SDA H）
Fig.27 Noise reduction effective time tl（SCL H）
1.2
0.6
0.2
SPEC
0.1
1.0
0.8
0.6
0.4
0.2
0.0
0.5
SPEC
Ta=-40℃ꢀ
Ta=25℃
Ta=85℃
0.0
Ta=-40℃ꢀ
Ta=25℃
Ta=85℃
Ta=-40℃ꢀ
Ta=25℃
Ta=85℃
0.4
-0.1
-0.2
0.3
0.2
0.1
-0.3
-0.4
-0.5
-0.6
SPEC
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
Fig.32 WP setup time tSU : WP
SUPPLYVOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.31 WP data hold time tHD:WP
Fig.30 Noise reduction effective time tl（SDA L）
1.2
SPEC
1.0
0.8
Ta=-40℃ꢀ
Ta=25℃
0.6
Ta=85℃
0.4
0.2
0.0
0
1
2
3
4
5
6
SUPPLYVOLTAGE : Vcc(V)
Fig.33 WP effective time tHIGH : WP
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.9 - Rev.A
6/19
Technical Note
BR24G□□□-3 Series
●I2C BUS communication
○I2C BUS data communication
I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and
acknowledge is always required after each byte. I2C BUS carries out data transmission with plural devices connected by 2
communication lines of serial data (SDA) and serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by address peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bus during data
communication is called “transmitter”, and the device that receives data is called “receiver”.
SDA
1-7
1-7
1-7
8
9
8
9
8
9
SCL
S
P
START ADDRESS R/W
ACK
DATA
ACK
DATA
ACK
STOP
condition
condition
Fig.34 Data transfer timing
○Start condition (Start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is
'HIGH' is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is
satisfied, any command is executed.
○Stop condition (stop bit recongnition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
master and slave, the device (μꢀCOM at slave address input of write command, read command, and this IC at data
output of read command) at the transmitter (sending) side releases the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and μꢀCOM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'. When acknowledge
signal (ACK signal) is detected, and stop condition is not sent from the master (μꢀCOM) side, this IC continues data
output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes stop condition
(stop bit), and ends read action. And this IC gets in status.
○Device addressing
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type.
The device code of this IC is fixed to '1010'.
・Next slave addresses (A2 A1 A0 ꢀꢀꢀ device address) are for selecting devices, and plural ones can be used on a same
bus according to the number of device addresses.
・ The most insignificant bit (R/W ꢀꢀꢀ READ / WRITE) of slave address is used for designating write or read action, and is
as shown below.
――
Setting R /
Setting R /
W
to 0 ꢀꢀꢀꢀꢀꢀꢀ write (setting 0 to word address setting of random read)
to 1 ꢀꢀꢀꢀꢀꢀꢀ read
――
W
Maximum number of
Slave address
Type
Connected buses
BR24G01ꢀ3,BR24G02ꢀ3
BR24G04ꢀ3
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
A2 A1 A0 R/――
A2 A1 P0 R/――
A2 P1 P0 R/――
P2 P1 P0 R/――
A2 A1 A0 R/――
W
8
4
2
1
W
BR24G08ꢀ3
W
BR24G16ꢀ3
BR24G32ꢀ3,BR24G64ꢀ3,
BR24G128ꢀ3, BR24G256ꢀ3,
W
1
0
1
0
W
8
P0～P2 are page select bits.
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.9 - Rev.A
7/19
Technical Note
BR24G□□□-3 Series
●Write Command
○Write cycle
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous data of 2 bytes or
more, simultaneous write is possible by page write cycle. The maximum number of write bytes is specified per device of each capacity.
S
T
A
R
T
W
R
I
T
E
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS
DATA
SDA
LINE
As for WA7, BR24G01ꢀ3 becomes Don't care.
WA
7
WA
0
1
0
1
0 A2A1A0
Note)
D7
D0
A
C
K
A
C
K
R
/
W
A
C
K
Fig.35 Byte write cycle (BR24G01/02/04/08/16ꢀ3)
S
T
A
R
T
W
R
I
S
T
O
P
SLAVE
T
E
1st WORD
ADDRESS
2nd WORD
ADDRESS
DATA
ADDRESS
*1 As for WA12, BR24G32ꢀ3 becomes Don't care.
As for WA13, BR24G32/64ꢀ3 becomes Don't care.
As for WA14, BR24G32/64/128ꢀ3 becomes Don't care.
As for WA15, BR24G32/64/128/256ꢀ3 becomes Don't care.
SDA
LINE
WAWAWAWAWA
15 14 13 12 11
WA
0
1
0
1
0 A2A1A0
Note)
D7
D0
A
C
K
A
C
K
A
C
K
R
/
W
A
C
K
*1
Fig.36 Byte write cycle (BR24G32/64/128/256ꢀ3)
S
T
A
R
T
W
R
I
T
E
S
T
O
P
*2
DATA(n+15)
SLAVE
ADDRESS
WORD
ADDRESS(n)
DATA(n)
SDA
LINE
*1 As for WA7, BR24G01ꢀ3 becomes Don't care.
*2 As for BR24G01/02ꢀ3 becomes (n+7)
WA
7
WA
0
1
0
0
1
0
A2A1A0
D7
D0
D0
0
A
C
K
R
/
W
A
C
K
A
C
K
A
C
K
*1
Note)
Fig.37 Page write cycle (BR24G01/02/04/08/16ꢀ3)
S
T
A
R
T
W
R
I
T
E
*1 As for WA12, BR24G32ꢀ3 becomes Don't care.
As for WA13, BR24G32/64ꢀ3 becomes Don't care.
As for WA14, BR24G32/64/128ꢀ3 becomes Don't care.
As for WA15, BR24G32/64/128/256ꢀ3 becomes Don't care.
S
T
O
*2
DATA(n+31)
SLAVE
ADDRESS
1st WORD
ADDRESS(n)
2nd WORD
ADDRESS(n)
DATA(n)
P
SDA
LINE
WAWA WA WA WA
15 14 13 12 11
WA
0
1
0
0
1
0
A2 A1 A0
D7
D0
D0
0
*2 As for BR24G128/256ꢀ3 becomes (n+63)
A
C
K
R
/
W
A
C
K
A
C
K
A
C
K
A
C
K
*1
Note)
Fig.38 Page write cycle (BR24G32/64/128/256ꢀ3)
Note)
*1 In BR24G16ꢀ3, A2 becomes P2.
*2 In BR24G08/16ꢀ3, A1 becomes P1.
*3 In BR24G04/08/16ꢀ3 A0 becomes P0.
*1 *2 *3
A1
0
A2 A0
1 0 1
Fig.39 Difference of slave address of each type
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2011.9 - Rev.A
8/19
Technical Note
BR24G□□□-3 Series
・During internal write execution, all input commands are ignored, therefore ACK is not sent back.
・Data is written to the address designated by word address (nꢀth address)
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, the following can be written in bulk :
Up to 8Byte (BR24G01ꢀ3, BR24G02ꢀ3）
Up to 16Byte (BR24G04ꢀ3, BR24G08ꢀ3, BR24G16ꢀ3）
Up to 32Byte (BR24G32ꢀ3, BR24G64ꢀ3）
Up to 64Byte (BR24G128ꢀ3, BR24G256ꢀ3）
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment" of "Notes on page write cycle" in P10.)
・
・
As for page write cycle of BR24G01ꢀ3 and BR24G02ꢀ3, after the significant 4 bits (in the case of BR24G01ꢀ3) of word address, or
the significant 5 bits (in the case of BR24G02ꢀ3) of word address are designated arbitrarily, by continuing data input of 2 bytes or
more, the address of insignificant 3 bits is incremented internally, and data up to 8 bytes can be written.
As for page write command of BR24G04ꢀ3, BR24G08ꢀ3 and BR24G16ꢀ3, after page select bit ’P0’(in the case of BR24G04ꢀ3),
after page select bit ’P0,P1’(in the case of BR24G08ꢀ3), after page select bit ’P0,P1,P2’(in the case of BR24G16ꢀ3) of slave
address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 4 bits is incremented
internally, and data up to 16 bytes can be written.
・
・
As for page write cycle of BR24G32ꢀ3 and BR24G64ꢀ3, after the significant 7 bits (in the case of BR24G32ꢀ3) of word address, or
the significant 8 bits (in the case of BR24G64ꢀ3) of word address are designated arbitrarily, by continuing data input of 2 bytes or
more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written.
As for page write cycle of BR24G128ꢀ3 and BR24G256ꢀ3, after the significant 8 bits (in the case of BR24G128ꢀ3) of word address,
or the significant 9 bits (in the case of BR24G256ꢀ3) of word address are designated arbitrarily, by continuing data input of 2 bytes
or more, the address of insignificant 6 bits is incremented internally, and data up to 64 bytes can be written.
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2011.9 - Rev.A
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© 2011 ROHM Co., Ltd. All rights reserved.
Technical Note
BR24G□□□-3 Series
○Notes on page write cycle
List of numbers of page write
Number of
8Byte
16Byte
32Byte
64Byte
Pages
BR24G04ꢀ3
BR24G08ꢀ3
BR24G16ꢀ3
Product
number
BR24G01ꢀ3
BR24G02ꢀ3
BR24G32ꢀ3
BR24G64ꢀ3
BR24G128ꢀ3
BR24G256ꢀ3
The above numbers are maximum bytes for respective types.
Any bytes below these can be written.
In the case BR24G256ꢀ3, 1 page=64bytes, but the page
write cycle time is 5ms at maximum for 64byte bulk write.
It does not stand 5ms at maximum × 64byte=320ms(Max.)
○Internal address increment
Page write mode (in the case of BR24G16ꢀ3）
WA7
0
0
WA4 WA3 WA2 WA1 WA0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
Increment
0
0
0
0
0
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0Eh
For example, when it is started from address 0Eh,
therefore, increment is made as below,
0Eh→0Fh→00h→01h･･･ which please note.
※0Eh･･･0E in hexadecimal, therefore, 00001110 becomes a
Significant bit is fixed.
No digit up
binary number.
○Write protect (WP) terminal
・Write protect (WP) function
When WP terminal is set Vcc (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data rewrite of all
address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not use it open.
In the case of use it as an ROM, it is recommended to connect it to pull up or Vcc.
At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', mistake write can be prevented.
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2011.9 - Rev.A
10/19
Technical Note
BR24G□□□-3 Series
●Read Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when to verify just
after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be read in succession.
W
R
I
T
E
S
T
A
R
T
S
T
A
R
T
R
E
A
D
S
T
O
SLAVE
ADDRESS
SLAVE
ADDRESS
W ORD
ADDRESS(n)
DATA(n)
P
SDA
LINE
W A
7
W A
0
*1 As for WA7,BR24G01ꢀ3 become Don’t care.
1
0
1
0 A2A1A0
1
0
1
0 A2A1A0
D7
D0
A
C
K
*1
R
/
W
A
C
K
A
C
K
R
/
W
A
C
K
Note)
Fig.40 Random read cycle (BR24G01/02/04/08/16ꢀ3)
S
T
A
R
T
W
R
I
T
E
S
T
A
R
T
R
E
A
D
S
T
O
P
SLAVE
ADDRESS
1st WORD
ADDRESS（ｎ）
2nd WORD
ADDRESS（ｎ）
SLAVE
ADDRESS
DATA(n)
*1 As for WA12, BR24G32ꢀ3 become Don’t care.
As for WA13, BR24G32/64ꢀ3 become Don’t care.
As for WA14, BR24G32/64/128ꢀ3 become Don’t care.
As for WA15, BR24G32/64/128/256ꢀ3 become Don’t care.
SDA
LINE
WA
0
WAWAWAWAWA
15 14 13 12 11
A2
1 0 1 0
A1A0
1
0
1 0
A1A0
D7
D0
A2
R
/
W
A
C
K
A
C
K
A
C
K
R
A
C
K
A
C
K
*1
/
Note)
W
Fig.41 Random read cycle (BR24G32/64/128/256ꢀ3)
S
R
E
A
D
S
T
O
T
A
R
T
SLAVE
ADDRESS
DATA(n)
P
SDA
LINE
1
0
1
0 A2A1A0
D7
D0
A
C
K
R
/
W K
A
C
Note)
Fig.42 Current read cycle
S
R
E
A
D
S
T
O
P
T
A
R
T
SLAVE
ADDRESS
DATA(n)
DATA(n+x)
SDA
LINE
A2 A1A0
1
0
1
0
D7
D0
D7
D0
R
/
W
A
C
K
A
C
K
A
C
K
A
C
K
Note）
Fig.43 Sequential read cycle (in the case of current read cycle)
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of
incremented last read address (n)ꢀth address, i.e., data of the (n+1)ꢀth address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μꢀCOM) side, the next address data can be
read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H' .
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input 'H' to ACK
signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL signal 'H'.
Note)
*1 In BR24G16ꢀ3, A2 becomes P2.
*1 *2 *3
*2 In BR24G08/16ꢀ3, A1 becomes P1.
*3 In BR24G08/16ꢀ3, A0 becomes P0.
A1
0
1 A2 A0
0
1
Fig.44 Difference of slave address of each type
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2011.9 - Rev.A
11/19
Technical Note
BR24G□□□-3 Series
●Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset has several kinds,
and 3 kinds of them are shown in the figure below. (Refer to Fig.45ꢀ(a), Fig.45ꢀ(b), Fig.45ꢀ(c).) In dummy clock input area, release the
SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L' level) may be output from EEPROM, therefore, if 'H' is
input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence
upon devices.
Dummy clock×14
Start×2
SCL
SDA
Normal command
Normal command
1
2
13
14
Fig.45ꢀ(a) The case of dummy clock +START+START+ command input
Start
Dummy clock×9
Start
SCL
SDA
Normal command
Normal command
1
2
8
9
Fig.45ꢀ(b) The case of START +9 dummy clocks +START+ command input
Start×9
SCL
Normal command
Normal command
1
2
3
7
8
9
SDA
Fig.45ꢀ(c) START×9+ command input
※Start command from START input.
●Acknowledge polling
During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic write execution
after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it means end of write action,
while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command can be executed without waiting for tWR =
5ms.
When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if ACK signal
sends back 'L', then execute word address input and data output and so forth.
During internal write,
ACK = HIGH is sent back.
First write command
S
T
A
R
T
S
T
A
R
T
S
S
T
A
C
K
H
A
T
A
R
T
Slave
Slave
C
K
H
Write command
O
…
address
address
P
tWR
Second write command
S
T
A
R
T
S
T
A
R
T
S
T
O
P
A
C
K
L
A
C
K
L
A
A
C
K
L
Slave
Word
Slave
C
…
Data
K
address
address
address
H
tWR
After completion of internal write,
ACK=LOW is sent back, so input
next word address and data in
succession.
Fig.46 Case to continuously write by acknowledge polling
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2011.9 - Rev.A
12/19
Technical Note
BR24G□□□-3 Series
●WP valid timing (write cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid timing. During
write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte write cycle and page write cycle, the
area from the first start condition of command to the rise of clock to taken in D0 of data(in page write cycle, the first byte data) is cancel
invalid area.
WP input in this area becomes Don't care. The area from the rise of SCL to take in D0 to input the stop condition is cancel valid area. And,
after execution of forced end by WP, standby status gets in.
・
Rise of D0 taken clock
SCL
SDA
・Rise of SDA
SCL
D1
D0 ACK
SDA D0
ACK
Enlarged view
Enlarged view
S
A
A
C
K
L
A
C
K
L
A
C
K
L
S
T
O
P
tWR
T
A
R
T
Slave
Word
SDA
WP
D7 D6
D2
D3 D1 D0
C
K
L
D5
D4
Data
address
address
WP cancel invalid area
WP cancel valid area
Data is not written.
WP cancel invalid area
Fig.47 WP valid timing
●
Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Fig.48)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop condition cannot be
input, so reset is not available. Therefore, execute software reset. And when command is cancelled by start, stop condition, during random
read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out
current read cycle in succession. When to carry out read cycle in succession, carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition
Stop condition
Fig.48 Case of cancel by start, stop condition during slave address input
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2011.9 - Rev.A
13/19
Technical Note
BR24G□□□-3 Series
●
I/O peripheral circuit
○Pull up resistance of SDA terminal
SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to this resistance
value from microcontroller VIL, IL, and VOLꢀIOL characteristics of this IC. If RPU is large, action frequency is limited. The smaller the RPU, the
larger the consumption current at action.
○Maximum value of RPU
The maximum value of RPU is determined by the following factors.
①SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
②The bus electric potential
A to be determined by input leak total (IL) of device connected to bus at output of 'H' to SDA bus and RPU
should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended noise margin 0.2Vcc.
V
CC－ILRPU－0.2 VCC ≧ VIH
0.8VCC－
V
IH
Microcontroller
BR24GXX
∴
R
PU
≦
I
L
Ex.) VCC =3V
IL=10ꢁA VIH=0.7 VCC
RPU
from②
SDA terminal
A
0.8×3－0.7×3
RPU
≦
≦
10×10ꢀ6
I
L
I
L
Bus line
capacity
CBUS
［k
］
Ω
300
○ Minimum value of RPU
The minimum value of RPU is determined by the following factors.
When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA.
Fig.49 I/O circuit diagram
V
CC－
VOL
≦ IOL
RPU
V
CC－
VOL
∴ RPU
≧
I
OL
②VOLMAX= should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1Vcc.
0.1 VCC
V
OLMAX ≦ VIL－
Ex.) VCC =3V、VOL=0.4V、IOL=3mA、microcontroller, EEPROM VIL=0.3Vcc
3－0.4
from①
R
PU
≧
≧
-3
3×10
867
［
］
Ω
And
V
OL=0.4［V］
IL=0.3×3
=0.9［V］
Therefore, the condition ② is satisfied.
V
○Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes 'HiꢀZ', add a pull
up resistance. As for the pull up resistance, one of several kΩ ~ several ten kΩ is recommended in consideration of drive performance
of output port of microcontroller.
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2011.9 - Rev.A
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© 2011 ROHM Co., Ltd. All rights reserved.
Technical Note
BR24G□□□-3 Series
●
Cautions on microcontroller connection
○RS
In I2C BUS, it is recommended that SDA port is of open drain input/output. However, when using CMOS input / output of tri state to SDA
port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM. This controls over current that
occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON simultaneously. Rs also plays the role of protection of
SDA terminal against surge. Therefore, even when SDA port is open drain input/output, Rs can be used.
ACK
SCL
RPU
RS
SDA
'H' output of microcontroller
'L' output of EEPROM
Over current flows to SDA line by 'H'
output of microcontroller and 'L'
output of EEPROM.
EEPROM
Microcontroller
Fig.50 I/O circuit diagram
Fig.51 Input / output collision timing
○
Maximum value of Rs
The maximum value of Rs is determined by the following relations.
①
SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
②
The bus electric potential A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus sufficiently secure
the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc.
(VCC－
V
OL)×R
S
VCC
+
V
OL+0.1VCC≦VIL
R
PU+R
S
A
RPU
RS
V
IL－
V
OL－0.1VCC
VOL
R
S
≦
×
R
PU
∴
1.1VCCꢀVIL
IOL
CC
IL
CC
OL
PU
Bus line
capacity
CBUS
Ex.）V =3VꢀV =0.3V ꢀV =0.4VꢀR =20kΩ
0.3×3－0.4－0.1×3
20×103
R
S
×
≦
≦
VIL
1.1×3－0.3×3
1.67［kΩ］
EEPROM
Micro controller
Fig.52 I/O Circuit Diagram
○
Minimum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source line, and
instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be
satisfied. Determine the allowable current in consideration of impedance of power source line in set and so forth. Set the over current to
EEPROM 10mA or below.
CC
V
≦
≧
I
RS
RPU
RS
'L'output
VCC
I
RS
∴
Over current I
Ex.) VCC=3V, I=10mA
'H' output
3
RS
≧
≧
10×10ꢀ3
EEPROM
Microcontroller
300［Ω］
Fig.53 I/O circuit diagram
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.9 - Rev.A
15/19
Technical Note
BR24G□□□-3 Series
●
I2C BUS input / output circuit
○
Input (A0, A1, A2, SCL, WP)
Fig.54 Input pin circuit diagram
○Input / output (SDA)
Fig.55 Input / output pin circuit diagram
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.9 - Rev.A
16/19
Technical Note
BR24G□□□-3 Series
●
Notes on power ON
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset, and
malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action, observe the following
conditions at power on.
1. Set SDA = 'H' and SCL ='L' or 'H’
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
tR
CC
V
Recommended conditions of tR, tOFF,Vbot
tR
tOFF
Vbot
10ms or below 10ms or larger 0.3V or below
100 or below 10ms or larger 0.2V or below
tOFF
Vbot
0
Fig.56 Rise waveform diagram
3. Set SDA and SCL so as not to become 'HiꢀZ'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above condition 1 cannot be observed. When SDA becomes 'L' at power on .
→
Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
Fig.57 When SCL=’H’ and SDA=’L’
) In the case when the above condition 2 cannot be observed.
After power source becomes stable, execute software reset(P12).
) In the case when the above conditions 1 and 2 cannot be observed.
Carry out a), and then carry out b).
Fig.58 When SCL=’L’ and SDA=’L’
ｂ
ｃ
→
→
●
Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it prevent data
rewrite.
●Vcc noise countermeasures
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a by
pass capacitor (0.1ꢁF) between IC Vcc and GND. At that moment, attach it as close to IC as possible.
And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
●
Cautions on use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the
case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static
characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be
destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute
maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum
ratings should not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal.
(5) Terminal design
In consideration of permissible loss in actual usecondition, carry out heat design with sufficient margin.
(6) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in
the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be
destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
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2011.9 - Rev.A
17/19
© 2011 ROHM Co., Ltd. All rights reserved.
Technical Note
BR24G□□□-3 Series
●Order part number
E
2
3
B R
2 4
G
2 5
G T
F
6
ROHM type
name
Operating
BUS type
24：I2C
Capacity
64 64K
Package
Halogen Free
temperature/
Power source
Voltage
G:ꢀ40℃～+85℃/
1.7V～5.5V
01=1K
＝
F
:SOP8
Sn 100
FJ
FV
:SOPꢀJ8
: SSOPꢀB8
02=2K
04=4K
08=8K
16=16K
128=128K
256=256K
Process Code
FVT : TSSOPꢀB8
FVJ : TSSOPꢀB8J
FVM : MSOP8
Package specifications
32
＝32K
E2：reel shape emboss taping
TR：reel shape emboss taping
●Package specifications
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2011.9 - Rev.A
18/19
© 2011 ROHM Co., Ltd. All rights reserved.
Technical Note
BR24G□□□-3 Series
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2011.9 - Rev.A
19/19
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相关型号：
BR24G128NUX-3ATTR
EEPROM, 16KX8, Serial, CMOS, PDSO8, 2 X 3 MM, 0.60 MM HEIGHT, HALOGEN FREE, VSON-8
ROHM
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