BR93LC56FV [ROHM]
2,048-Bit Serial Electrically Erasable PROM; 2048位串行电可擦除PROM型号: | BR93LC56FV |
厂家: | ROHM |
描述: | 2,048-Bit Serial Electrically Erasable PROM |
文件: | 总12页 (文件大小:128K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Memory ICs
2,048-Bit Serial Electrically Erasable PROM
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
Features
Pin assignments
•
•
• Low power CMOS technology
CS
SK
DI
VCC
N.C.
GND
DO
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
N.C.
VCC
CS
• 128 × 16 bit configuration
N.C.
N.C.
GND
• 2.7V to 5.5V operation
BR93LC56F /
BR93LC56FV
BR93LC56 /
BR93LC56RF
• Low power dissipation
– 3mA (max.) active current: 5V
– 5µA (max.) standby current: 5V
• Auto increment for efficient data bump
• Automatic erase-before-write
DO
DI
SK
• Hardware and software write protection
– Default to write-disabled state at power up
– Software instructions for write-enable / disable
– Vcc lock out inadvertent write protection
• 8-pin SOP / 8-pin SSOP-B / 8-pin DIP packages
• Device status signal during write cycle
• TTL compatible Input / Output
Pin descriptions
•
Pin
name
Function
Chip select input
Serial clock input
CS
SK
Start bit, operating code, address, and serial
data input
DI
• 100,000 ERASE / write cycles
• 10 years Data Retention
Serial data output, READY / BUSY internal
status display output
DO
Ground
GND
N.C.
N.C.
VCC
Not connected
Not connected
Power supply
Overview
•
The BR93LC56 is CMOS serial input / output-type memory circuits (EEPROMs) that can be programmed electrically.
Each is configured of 128 words × 16 bits (2,048 bits), and each word can be accessed individually and data read
from it and written to it.
Operation control is performed using five types of commands. The commands, addresses, and data are input
through the DI pin under the control of the CS and SK pins. In a write operation, the internal status signal (READY or
BUSY) can be output from the DO pin.
The only difference between the BR93LC56 / F / RF / FV is the write disable voltage and its accompanying write
enable voltage. All other functions and characteristics are the same.
1
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
Block diagram
•
Power supply
CS
SK
DI
voltage detector
Command decode
Control
High voltage
generator
Write
Clock generation
disable
Address
buffer
Address
decoder
7bit
Command
register
7bit
2,048-bit
EEPROM array
Data
R / W
16bit
16bit
register
amplifier
DO
Dummy bit
Absolute maximum ratings (Ta = 25°C)
•
Parameter
Applied voltage
BR93LC56
Symbol
VCC
Limits
Unit
– 0.3 ~ + 6.5
V
1
500
Power
dissipation
2
BR93LC56F / RF
BR93LC56FV
Pd
mW
350
3
300
Storage temperature
Operating temperature
Terminal voltage
Tstg
Topr
—
– 65 ~ + 125
– 40 ~ + 85
°C
°C
V
– 0.3 ~ VCC + 0.3
1 Reduced by 5.0mW for each increase in Ta of 1°C over 25°C.
2 Reduced by 3.5mW for each increase in Ta of 1°C over 25°C.
3 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C.
Recommended operating conditions (Ta = 25°C)
•
Parameter
Symbol
VCC
Min.
2.7
2.0
0
Typ.
—
Max.
5.5
Unit
Writing
V
V
V
Power supply
voltage
—
5.5
Reading
Input voltage
VIN
—
VCC
2
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
Electrical characteristics (unless otherwise noted, Ta = – 40 to + 85°C, VCC = 5V ± 10%)
•
Parameter
Symbol
VIL
Min.
– 0.3
2.0
Typ.
—
Max.
0.8
Unit
V
Conditions
—
—
Input low level voltage
Input high level voltage
Output low level voltage 1
Output high level voltage 1
Output low level voltage 2
Output high level voltage 2
Input leakage current
Output leakage current
Operating current
VIH
—
VCC + 0.3
0.4
V
VOL1
VOH1
VOL2
VOH2
ILI
—
—
V
IOL = 2.1mA
2.4
—
—
V
IOH = – 0.4mA
—
—
0.2
V
IOL = 10µA
VCC – 0.4
– 1.0
– 1.0
—
—
V
IOH = – 10µA
—
1.0
µA
µA
VIN = 0V ~ VCC
VOUT = 0V ~ VCC, CS = GND
ILO
—
1.0
VIN = VIH / VIL, DO = OPEN
f = 1MHz, WRITE
ICC1
—
1.5
3
mA
dissipation 1
Operating current
VIN = VIH / VIL, DO = OPEN
f = 1MHz, READ
ICC2
ISB
—
—
0.7
1.0
1.5
5
mA
dissipation 2
Standby current
µA
CS = SK = DI = GND, DO = OPEN
(unless otherwise noted, Ta = – 40 to + 85°C, VCC = 3V ± 10%)
Parameter
Symbol
VIL
Min.
– 0.3
Typ.
—
Max.
0.15 × VCC
VCC + 0.3
0.2
Unit
V
Conditions
—
—
Input low level voltage
Input high level voltage
Output low level voltage
Output high level voltage
Input leakage current
Output leakage current
Operating current
VIH
0.7 × VCC
—
—
V
VOL
VOH
ILI
—
V
IOL = 10µA
VCC – 0.4
– 1.0
—
—
V
IOH = – 10µA
—
1.0
µA
µA
VIN = 0V ~ VCC
VOUT = 0V ~ VCC, CS = GND
ILO
– 1.0
—
1.0
VIN = VIH / VIL, DO = OPEN,
f = 250kHz, WRITE
ICC1
—
0.5
2
mA
dissipation 1
Operating current
VIN = VIH / VIL, DO = OPEN,
f = 250kHz, READ
ICC2
ISB
—
—
0.2
0.4
1
3
mA
dissipation 2
Standby current
µA
CS = SK = DI = GND, DO = OPEN
Electrical characteristics (unless otherwise noted, Ta = – 40 to + 85°C, VCC = 2.0V ± 10%)
•
Parameter
Symbol
VIL
Min.
– 0.3
Typ.
—
Max.
0.15 × VCC
VCC + 0.3
0.2
Unit
V
Conditions
Input low level voltage
Input high level voltage
Output low level voltage
Output high level voltage
Input leakage current
Output leakage current
Operating current
—
—
VIH
0.7 × VCC
—
—
V
VOL
VOH
ILI
—
V
IOL = 10µA
VCC – 0.4
– 1.0
—
—
V
IOH = – 10µA
—
1.0
µA
µA
VIN = 0V ~ VCC
ILO
– 1.0
—
1.0
VOUT = 0V ~ VCC, CS = 0V
VIN = VIH / VIL, DO = OPEN
f = 200kHz, READ
ICC2
ISB
—
—
0.2
0.4
1
3
mA
dissipation 2
Standby current
µA
CS = SK = DI = 0V, DO = OPEN
3
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
Circuit operation
•
Start Operating
Command
Address
Data
(1) Command mode
bit
code
With these ICs, commands are not rec-
ognized or acted upon until the start bit
is received. The start bit is taken as the
first “1” that is received after the CS pin
rises.
1
Read (READ)
1
10
0A6 ~ A0
—
—
Write enabled (WEN)
1
00
11XXXXXX
2
Write (WRITE)
1
01
0A6 ~ A0 D15 ~ D0
01XXXXXX D15 ~ D0
2
Write all addresses (WRAL)
Write disabled (WDS)
1
00
1 After setting of the read command
and input of the SK clock, data corre-
sponding to the specified address is
output, with data corresponding to up-
per addresses then output in se-
quence. (Auto increment function)
1
00
00XXXXXX
0A6 ~ A0
—
—
—
3
Erase (ERASE)
1
11
3
1
00
10XXXXXX
Chip erase (ERAL)
X: Either VIH or VIL
2 When the write or write all addresses command is executed, all data in the selected memory cell is erased auto-
matically, and the input data is written to the cell.
3 These modes are optional modes. Please contact Rohm for information on operation timing.
(2) Operation timing characteristics
(unless otherwise noted, Ta = – 40 to + 85°C, VCC = 5V ± 10%)
Parameter
SK clock frequency
Symbol Min.
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
1
Unit
MHz
ns
fSK
tSKH
tSKL
tCS
—
450
450
450
50
—
SK "H" time
—
ns
SK "L" time
—
ns
CS "L" time
tCSS
tDIS
tCSH
tDIH
tPD1
tPD0
tSV
—
ns
CS setup time
100
0
—
ns
DI setup time
—
ns
CS hold time
100
—
—
ns
DI hold time
500
500
500
100
10
ns
Data "1" output delay time
Data "0" output delay time
Time from CS to output confirmation
Time from CS to output High impedance
Write cycle time
—
ns
—
ns
tDF
—
ns
tE / W
—
ms
4
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
For low voltage operation (unless otherwise noted, Ta = – 40 to + 85°C, VCC = 3V ± 10%)
Parameter
SK clock frequency
Symbol Min.
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
250
—
—
—
—
—
—
—
2
Unit
kHz
µs
µs
µs
ns
fSK
tSKH
tSKL
tCS
—
1
SK "H" time
SK "L" time
1
CS "L" time
1
CS setup time
tCSS
tDIS
tCSH
tDIH
tPD1
tPD0
tSV
200
400
0
DI setup time
ns
CS hold time
ns
DI hold time
400
—
—
—
—
—
ns
Data "1" output delay time
Data "0" output delay time
Time from CS to output confirmation
Time from CS to output High impedance
Write cycle time
µs
µs
µs
ns
2
2
tDF
400
25
tE / W
ms
When reading at low voltage (unless otherwise noted, Ta = – 40 to + 85°C, VCC = 2.0V)
Parameter
SK clock frequency
Symbol Min.
Typ.
—
—
—
—
—
—
—
—
—
—
—
Max.
200
—
Unit
kHz
µs
µs
µs
ns
fSK
tSKH
tSKL
tCS
—
2
SK "H" time
SK "L" time
2
—
CS "L" time
2
—
CS setup time
tCSS
tDIS
tCSH
tDIH
tPD1
tPD0
tDF
400
800
0
—
—
ns
DI setup time
—
ns
CS hold time
800
—
—
—
—
ns
DI hold time
4
µs
µs
ns
Data "1" output delay time
Data "0" output delay time
Time from CS to output High impedance
᭺ Not designed for radioactive rays.
4
800
5
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
(3) Timing chart
CS
tCSS
tSKH
tSKL
tCSH
SK
DI
tDIS
tDIH
tPD0
tPD1
tDF
DO (READ)
tDF
STATUS VALID
DO (WRITE)
• Data is acquired from DI in synchronization with the SK rise.
• During a reading operation, data is output from DO in synchronization with the SK rise.
• During a writing operation, a Status Valid (READY or BUSY) is valid from the time CS is HIGH until time tCS after CS falls following the input of a write
command and before the output of the next command start bit. Also, DO must be in a HIGH-Z state when CS is LOW.
• After the completion of each mode, make sure that CS is set to LOW, to reset the internal circuit, before changing modes.
Fig. 1 Synchronized data timing
6
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
(4) Reading (Figure 2)
When the read command is acknowledged, the data
(16 bits) for the input address is output serially. The
data is synchronized with the SK rise during A0 acqui-
sition and a “0” (dummy bit) is output. All further data is
output in synchronization with the SK pulse rises.
(5) Write enable (Figure 3)
off. However, read commands can be used in either
the write enable or write disable state.
(6) Write (Figure 4)
This command writes the input 16-bit data (D15 to D0)
to the specified address (A6 to A0). Actual writing of
the data begins after CS falls (following the 27th clock
pulse after the start bit input), and the SK clock which
reads D0 falls.
These ICs are set to the write disabled state by the in-
ternal reset circuit when the power is turned on.
Therefore, before performing a write command, the
write enable command must be executed. When this
command is executed, it remains valid until a write
disable command is issued or the power supply is cut
If STATUS is not detected (CS is fixed at LOW), or if
STATUS is detected (CS = HIGH) at a maximum of 10
ms, in accordance with the time tE / W, no commands
are accepted while DO is LOW (BUSY). Therefore, no
commands should be input during this period.
CS
1
1
2
4
0
11
A0
12
27 28
SK
DI
1
1
0
A6
A5
A1
2
D15 D14
D1 D0 D15 D14
DO
0
High-Z
1 If the first data input following the rise of the start bit CS is "1", the start bit is acknowledged. Also, if a "1" is input following several zeroes in
succession, the "1" is recognized as the start bit, and subsequent operation commences. This applies also to all commands described subsequently.
2 Address auto increment function: These ICs are equipped with an address auto increment function which is effective only during reading operations.
With this function, if the SK clock is input following execution of one of the above reading commands, data is read from upper addresses in succession.
CS is held in HIGH state during automatic incrementing.
Fig. 2 Read cycle timing (READ)
CS
SK
DI
1
0
0
1
1
DO
High-Z
Fig. 3 Write enable cycle timing
7
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
CS
tCS
27
STATUS
1
2
0
4
0
11
12
SK
DI
A6 A5
A1 A0 D15 D14
D1
D0
1
1
tSV
DO
BUSY READY
High-Z
tE / W
Fig. 4 Write cycle timing (WRITE)
CS
STATUS
tCS
1
2
5
12
27
SK
DI
D0
D15 D14
D1
1
0
0
0
1
tSV
DO
BUSY READY
High-Z
tE / W
Fig. 5 Write all address cycle timing (WRAL)
(STATUS)
After time tCS following the fall of CS, after input of the
write command), if CS is set to HIGH, the write execute
= BUSY (LOW) and the command wait status READY
(HIGH) are output.
Rather than writing one word at a time, in succession,
data is written all at one time, enabling a write time of
tE / W.
(8) Write disable (Figure 6)
If in the command wait status (STATUS = READY), the
next command can be performed within the time tE / W.
Thus, if data is input via SK and DI with CS = HIGH in
the tE / W period, erroneous operations may be per-
formed. To avoid this, make sure that DI = LOW when
CS = HIGH. (Caution is especially important when
common input ports are used.) This applies to all of the
write commands.
When the power supply is turned on, the IC enters the
write disable status when a write enable command is
issued. If a write disable command is issued at this
point, however, the IC enters the write disabled status,
just as when the power is first turned on. Subsequent
write commands are cancelled by the software, but
read commands may be executed. In the write enable
status, writing begins even if a write command is
entered accidentally. To prevent errors of this type, we
recommend executing a write disable command after
writing has been completed.
(7) All address write (Figure 5)
With this command, the input 16-bit data is written
simultaneously to all of the addresses (128 words).
CS
SK
DI
1
0
0
0
0
DO
High-Z
Fig. 6 Write disable cycle timing (WDS)
8
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
Operation notes
•
(1) Cancelling modes
READ
Operating code
2 bits
Start bit
1 bit
Address
8 bits
Data
16 bits
Cancel can be performed for the entire read mode space
Cancellation method: CS LOW
WRITE, WRAL
Operating code
2 bits
Address
8 bits
tE / W
Start bit
1 bit
Data
16 bits
a
b
a: Canceled by setting CS LOW or VCC OFF (
)
b: Cannot be canceled by any method. If VCC is set to OFF during this time, the data
in the designated address is not secured.
: VCC OFF (VCC is turned off after CS is set to LOW)
Fig.7
9
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
(2) Timing in the standby mode
To prevent erroneous writing, these ICs are equipped
As shown in Figure 8, during standby, if CS rises when
SK is HIGH, the DI state may be read on the rising
edge. If this happens, and DI is HIGH, this is taken to
be the start bit, causing a bit error (see point “a” in
Figure 8).
with a POR (Power On Reset) circuit, but in order to
achieve operation at a low power supply, VCC is set to
operate at approximately 1.3V. After the POR has been
activated, writing is disabled, but if CS is set to HIGH,
writing may be enabled because of noise or other fac-
tors. However, the POR circuit is effective only when
the power supply is on, and will not operate when the
power is off.
Make sure all inputs are LOW during standby or when
turning the power supply on or off (see Figure 9).
Point a: Start bit position during erroneous operation
Point b: Timing during normal operation
Also, to prevent erroneous writing at low voltages,
these ICs are equipped with a built-in circuit (VCC-lock-
out circuit) which resets the write command if VCC
drops to approximately 2V or lower (typ.) ( ).
SK
CS
+ 5V
VCC
GND
0
1
DI
+ 5V
CS
a
b
GND
Fig. 8 Erroneous operation timing
Bad example
Good example
(Bad example) Here, the CS pin is pulled up to VCC. In this case, CS is
HIGH (active state). Please be aware that the EEPROM
may perform erroneous operations or write erroneous
data because of noise or other factors. This can occur
even if the CS input is high-Z.
SK
(Good example) In this case, CS is LOW when the power supply is
turned on or off.
CS
DI
Fig. 10
0
1
(4) Clock (SK) rise conditions
b
If the clock pin (SK) signal of the BR93LC56 / F / FV
has a long rise time (tr) and if noise on the signal line
exceeds a certain level, erroneous operation can occur
due to erroneous counts in the clock. To prevent this, a
Schmitt trigger is built into the SK input of the BR93-
LC56 / F / FV. The hysteresis amplitude of this circuit is
set to approximately 0.2V, so if the noise exceeds the
SK input, the noise amplitude should be set to 0.2VP-P
or lower. Furthermore, rises and falls in the clock input
should be accelerated as much as possible.
Fig. 9 Normal operation timing
(3) Precautions when turning power on and off
When turning the power supply on and off, make sure
CS is set to LOW (see Figure 10).
When CS is HIGH, the EEPROM enters the active
state. To avoid this, make sure CS is set to LOW (dis-
able mode) when turning on the power supply.
(When CS is LOW, all input is cancelled.)
When the power supply is turned off, the low power
state can continue for a long time because of the
capacity of the power supply line. Erroneous opera-
tions and erroneous writing can occur at such times for
the same reasons as described above. To avoid this,
make sure CS is set to LOW before turning off the
power supply.
(5) Power supply noise
The BR93LC56 / F / FV discharge high volumes of high
voltage when a write is completed. The power supply
may fluctuate at such times. Therefore, make sure a
capacitor of 1000pF or greater is connected between
VCC (Pin 8) and GND (Pin 5).
10
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
(6) Connecting DI and DO directly
The BR93LC56 / F / FV have an independent input pin
(DI) and output pin (DO). These are treated as individ-
ual signals on the timing chart but can be controlled
through one control line.Control can be initiated on a
single control line by inserting a resistor R betweeen
the [DI] pin and [DO] pin.
The resistor R is the only resistance which limits this
current. Therefore, a resistor with a value which satis-
fies the µ-COM and the BR93LC56 / F / FV current
capacity is required. When using a single control line,
when a dummy bit “0” is output to the DO, the µ-COM
I / O address data A0 is also output. Therefore, the
dummy bit cannot be detected.
µ-COM
BR93LC56
2) Feedback to the DI input from the DO output
Data is output from the DO pin and then feeds back
into the DI input through the resistor R. This happens
when:
I / O PORT
DI
· DO data is output during a read operation
· A READY / BUSY signal is output during WRITE or
WRAL operation
R
DO
Such feedback does not cause problems in the basic
operation of the BR93LC56 / F / FV.
The µ-COM input level must be adequately maintained
for the voltage drop at R which is caused by the total
input leakage current for the µ-COM and the BR93-
LC56 / F / FV.
Fig. 11 Common connections for
the DI and DO control line
1) Data collision between the µ-COM output and the
DO output
Within the input and output timing of the BR93LC56 / F
/ FV, the drive from the µ-COM output to the DI input
and a signal output from the DO output can be emitted
at the same time. This happens only for the 1 clock
cycle (a dummy bit “0” is output to the DO pin) which
acquires the A0 address data during a read cycle.
When the address data A0 = 1, the µ-COM output
becomes a direct current source for the DO pin.
In the state in which SK is input, when the READY /
BUSY function is used, make sure that CS is dropped
to LOW within four clock pulses of the output of the
READY signal HIGH and the standby mode is restored.
For input after the fifth clock pulse, the READY HIGH
will be taken as the start bit and WDS or some other
mode will be activated, depending on the DI state.
11
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
External dimension (Units: mm)
•
BR93LC56
BR93LC56F / RF
9.3 ± 0.3
5.0 ± 0.2
8
5
8
5
1
4
7.62
1
4
1.27
0.4 ± 0.1
0.3Min.
2.54
0.5 ± 0.1 0° ~ 15°
0.15
DIP8
SOP8
BR93LC56FV
3.0 ± 0.2
8
5
1
4
(0.52)
0.65 0.22 ± 0.1
0.3Min.
0.1
SSOP-B8
12
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