BRCB016GWL-3U_技术文档

Datasheet

Serial EEPROM Series Standard EEPROM

WLCSP EEPROM

BRCB016GWL-3U

General Description

BRCB016GWL-3U is a serial EEPROM of I²C BUS Interface Method

Features

Package W(Typ) x D(Typ) x H(Max)

UCSP50L1 1.10mm x 1.15mm x 0.55mm

◼ Completely conforming to the world standard I²C BUS.

All controls available by 2 ports of serial clock (SCL)

and serial data (SDA)

◼ 1.7V to 3.6V single power source operation most

suitable for battery use

◼ 1.7V to 3.6V wide limit of operating voltage, possible

FAST MODE 400KHz operation

◼ 16byte Page Write Mode useful for initial value write

at factory shipment

◼ Self-timed Programming Cycle

◼ Low Current Consumption

◼ Prevention of Write Mistake at Low Voltage

◼ More than 1 million write cycles

◼ More than 40 years of data retention

◼ Noise Filter built in SCL / SDA terminal

◼ Initial delivery state FFh

BRCB016GWL-3U

Capacity Bit Format

Type

Power Source Voltage

1.7V to 3.6V

Package

16Kbit 2K×8

BRCB016GWL-3U

UCSP50L1

○Product structure：Silicon monolithic integrated circuit ○This product has no designed protection against radioactive rays

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Absolute Maximum Ratings (Ta=25°C)

Parameter

Symbol

Rating

-0.3 to +6.5

220 (UCSP50L1)

-65 to +125

-40 to +85

Unit

V

Remark

Supply Voltage

V_CC

Power Dissipation

Pd

mW

°C

Derate by 2.2mW/°C when operating above Ta=25°C

Storage Temperature

Operating Temperature

Tstg

Topr

°C

The Max value of Input Voltage / Output Voltage is not over 6.5V.

When the pulse width is 50ns or less, the Min value of Input Voltage

/ Output Voltage is not below -1.0V.

Input Voltage/

Output Voltage

‐

-0.3 to Vcc+1.0

150

V

Junction Temperature

Tjmax

°C

Junction temperature at the storage condition

Memory Cell Characteristics (Ta=25°C, Vcc=1.7V to 3.6V)

Limit

Parameter

Unit

Min

1,000,000

40

Typ

Max

Write Cycles ⁽¹⁾

-

Times

Years

Data Retention ⁽¹⁾

(1) Not 100% TESTED

Recommended Operating Ratings

Parameter

Power Source Voltage

Input Voltage

Symbol

Rating

1.7 to 3.6

0 to Vcc

Unit

V

Vcc

V_IN

DC Characteristics

(

Unless otherwise specified, Ta=-40

℃

to +85

Max

℃, Vcc=1.7V to 3.6V)

Limit

Parameter

Symbol

Unit

Conditions

Min

Typ

Input High Voltage

Input Low Voltage

Output Low Voltage1

Output Low Voltage2

V_IH

V_IL

0.7Vcc

-

Vcc+1.0

+0.3Vcc

0.4

V

1.7V≦Vcc≦3.6V

-0.3⁽²⁾

1.7V≦Vcc≦3.6V

V_OL1

V_OL2

I_LI

-

V

I_OL=3.0mA, 2.5V≦Vcc≦3.6V (SDA)

I_OL=0.7mA, 1.7V≦Vcc＜2.5V (SDA)

V_IN=0 to Vcc

0.2

V

Input Leakage Current

Output Leakage Current

Supply Current (Write)

-1

-

+1

µA

mA

I_LO

+1

V_OUT=0 to Vcc (SDA)

Vcc=3.6V, f_SCL=400kHz, t_WR=5ms,

Byte Write, Page Write

I_CC1

2.0

Vcc=3.6V, f_SCL=400kHz

Random Read, Current Read, Sequential

Read

Supply Current (Read)

Standby Current

I_CC2

I_SB

-

0.5

2.0

mA

µA

Vcc=3.6V, SDA・SCL=Vcc, WP=GND

(2) When the pulse width is 50ns or less, it is -1.0V.

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Datasheet

BRCB016GWL-3U

AC Characteristics (Unless otherwise specified, Ta=-40℃ to +85℃, Vcc=1.7V to 3.6V)

Limits

Parameter

Symbol

Unit

Min

-

Typ

Max

Clock Frequency

f_SCL

t_HIGH

t_LOW

t_R

-

400

kHz

µs

ns

µs

ms

µs

Data Clock High Period

Data Clock Low Period

SDA and SCL Rise Time ⁽¹⁾

SDA and SCL Fall Time ⁽¹⁾

Start Condition Hold Time

Start Condition Setup Time

Input Data Hold Time

Input Data Setup Time

Output Data Delay Time

Output Data Hold Time

Stop Condition Setup Time

Bus Free Time

0.6

1.2

-

0.3

t_F

-

0.3

t_HD:STA

t_SU:STA

t_HD:DAT

t_SU:DAT

t_PD

0.6

0

-

100

0.1

0.6

1.2

-

0.9

t_DH

-

t_SU:STO

t_BUF

-

Write Cycle Time

t_WR

5

0.1

-

Noise Spike Width (SDA and SCL)

WP Hold Time

t_I

-

t_HD:WP

t_SU:WP

t_HIGH:WP

1.0

0.1

1.0

WP Setup Time

-

WP High Period

-

(1) Not 100% TESTED.

Condition: Input Data Level: V_IL=0.2×Vcc V_IH=0.8×Vcc

Input Data Timing Reference Level: 0.3×Vcc/0.7×Vcc

Output Data Timing Reference Level: 0.3×Vcc/0.7×Vcc

Rise/Fall Time : ≦20ns

Serial Input / Output Timing

tR

tF

tHIGH

70%

30%

SCL

70% 70%

30%

SCL

SDA

30%

DATA(n)

DATA(1)

D0 ACK

tLOW

tHD:DAT

70%

tSU:DAT

ACK

D1

(input)

70%

tWR

30%

SDA

(input)

tPD

tDH

tBUF

WP

30%

70%

30%

70%

30%

SDA

(output)

tSU:WP

tHD:WP

STOP CONDITION

○Input Read at the rise edge of SCL

○Data Output in sync with the fall of SCL

Figure 1-(d). WP Timing at Write Execution

Figure 1-(a).Serial Input / Output Timing

70%

SCL

SDA

70%

DATA(n)

DATA(1)

D0

SCL

70%

D1

ACK

tSU:STA

tHD:STA

tSU:STO

(input)

SDA

(input)

tWR

tHIGH:WP

70%

30%

70%

STOP CONDITION

START CONDITION

WP

Figure 1-(b). Start-Stop Bit Timing

Figure 1-(e). WP Timing at Write Cancel

SCL

SDA

(input)

70%

ACK

D0

write data

(n-th address)

tWR

STOP CONDITION START CONDITION

Figure 1-(c). Write Cycle Timing

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Block Diagram

GND

16Kbit EEPROM ARRAY

VCC

Vcc

8bit

11bit

ADDRESS

DECODER

SLAVE WORD

DATA

REGISTER

11bit

ADDRESS REGISTER

WP

START

STOP

SCL

CONTROL LOGIC

ACK

VCC LEVEL DETECT

SDA

HIGH VOLTAGE GEN.

Figure 2. Block Diagram

Pin Configuration

C3

C1

C

B

A

○

SCL

WP

B2

○

SDA

A3

A1

○

GND

VCC

3

2

1

BOTTOM VIEW

Pin Descriptions

Land No. Terminal Name Input / Output

Descriptions

-

Power supply

A1

A3

B2

C1

C3

VCC

GND

SDA

WP

-

Input / Output

Input

Reference voltage of all input / output, 0V

Slave and word address

Serial data input serial data output

Write protect terminal

Serial clock input

Input

SCL

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Typical Performance Curves

6

5

4

3

2

1

0

Ta=-40℃

Ta= 25℃

Ta=-40℃

Ta= 25℃

5

Ta= 85℃

4

3

SPEC

2

1

0

SPEC

4

0

1

2

3

4

5

6

0

1

2

3

5

6

SupplyVoltage: Vcc(V)

Figure 4. Input Low Voltage vs Supply Voltage

(SCL,SDA)

Figure 3. Input High Voltage vs Supply Voltage

(SCL,SDA)

0.6

1

0.8

0.6

0.4

0.2

0

Ta=-40℃

Ta= 25℃

Ta=-40℃

Ta= 25℃

0.5

0.4

0.3

0.2

0.1

0

Ta= 85℃

SPEC

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

Output Low Current : IOL(mA)

Output Low Current : I_OL(mA)

Figure 5. Output Low Voltage1 vs Output Low Current

(Vcc=2.5V)

Figure 6. Output Low Voltage2 vs Output Low Current

(Vcc=1.7V)

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Typical Performance Curves‐Continued

1.2

1

1.2

SPEC

1

0.8

0.6

0.4

0.2

0

0.8

Ta=-40℃

Ta= 25℃

Ta=-40℃

Ta= 25℃

0.6

Ta= 85℃

0.4

0.2

0

1

2

3

4

5

6

0

1

2

3

4

5

6

SupplyVoltage : Vcc(V)

Figure 7. Input Leakage Current vs Supply Voltage

(SCL)

Figure 8. Output Leakage Current vs Supply Voltage

(SDA)

0.6

2.5

2

SPEC

0.5

0.4

Ta=-40℃

Ta= 25℃

Ta=-40℃

Ta= 25℃

1.5

1

0.3

Ta= 85℃

0.2

0.1

0

0.5

0

1

2

3

4

5

6

0

1

2

3

4

5

6

SupplyVoltage : Vcc(V)

Figure 9. Supply Current (Write) vs Supply Voltage

(f_SCL=400kHz)

Figure 10. Supply Current (Read) vs Supply Voltage

(f_SCL=400kHz)

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Typical Performance Curves‐Continued

10000

1000

100

10

2.5

SPEC

2

SPEC

1.5

Ta=-40℃

Ta= 25℃

1

Ta= 85℃

Ta=-40℃

Ta= 25℃

Ta= 85℃

1

0.5

0

0.1

0

1

2

3

4

5

6

0

1

2

3

4

5

6

SupplyVoltage : Vcc(V)

Figure 12. Clock Frequency vs Supply Voltage

Figure 11. Standby Current vs Supply Voltage

5

4

3

2

1

0

6

5

4

3

2

1

0

Ta=-40℃

Ta= 25℃

Ta=-40℃

Ta= 25℃

Ta= 85℃

SPEC

0

1

2

3

4

5

6

0

1

2

3

4

5

6

SupplyVoltage: Vcc(V)

Figure 14. Data Clock Low Period vs Supply Voltage

Figure 13. Data Clock High Period vs Supply Voltage

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Typical Performance Curves‐Continued

6

5

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

SPEC

Ta=-40℃

Ta= 25℃

4

Ta= 85℃

3

2

Ta=-40℃

Ta= 25℃

Ta= 85℃

1

SPEC

0

-0.1

0

1

2

3

4

5

6

0

1

2

3

4

5

6

SupplyVoltage: Vcc(V)

SupplyVoltage : Vcc(V)

Figure 15. Start Condition Hold Time vs Supply Voltage

Figure 16. Start Condition Setup Time vs Supply Voltage

300

50

SPEC

200

100

0

-50

SPEC

-100

-150

-200

Ta=-40℃

Ta= 25℃

Ta=-40℃

Ta= 25℃

Ta= 85℃

-100

-200

Ta= 85℃

0

1

2

3

4

5

6

0

1

2

3

4

5

6

SupplyVoltage: Vcc(V)

Figure 17. Input Data Hold Time vs Supply Voltage

Figure 18. Input Data Setup Time vs Supply Voltage

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Typical Performance Curves‐Continued

4

3

2

1

0

4

Ta=-40℃

Ta= 25℃

Ta=-40℃

Ta= 25℃

3

Ta= 85℃

2

SPEC

1

0

1

2

3

4

5

6

0

1

2

3

4

5

6

SupplyVoltage: Vcc(V)

Figure 20. Output Data Delay Time vs Supply Voltage

(HIGH)

Figure 19. Output Data Delay Time vs Supply Voltage

(LOW)

5

2

Ta=-40℃

Ta= 25℃

Ta= 85℃

Ta=-40℃

Ta= 25℃

Ta= 85℃

4

1.5

3

2

1

SPEC

0.5

SPEC

1

0

-0.5

0

1

2

3

4

5

6

0

1

2

3

4

5

6

SupplyVoltage: Vcc(V)

Figure 21. Stop Condition Setup Time

vs Supply Voltage

Figure 22. Bus Free Time

vs Supply Voltage

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Typical Performance Curves‐Continued

6

1

0.8

0.6

0.4

0.2

0

SPEC

5

Ta=-40℃

Ta= 25℃

4

3

Ta= 85℃

Ta=-40℃

Ta= 25℃

2

Ta= 85℃

1

SPEC

0

1

2

3

4

5

6

0

1

2

3

4

5

6

SupplyVoltage: Vcc(V)

SupplyVoltage : Vcc(V)

Figure 23. Write Cycle Time vs Supply Voltage

Figure 24. Noise Spike Width vs Supply Voltage

(SCL HIGH)

1.2

1

0.6

SPEC

0.5

Ta=-40℃

Ta= 25℃

Ta=-40℃

Ta= 25℃

0.8

0.6

0.4

0.2

0

0.4

0.3

0.2

0.1

0

Ta= 85℃

SPEC

0

1

2

3

4

5

6

0

1

2

3

4

5

6

SupplyVoltage: Vcc(V)

Figure 25. Noise Spike Width vs Supply Voltage

(SDA HIGH)

Figure 26. WP Hold Time vs Supply Voltage

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Typical Performance Curves‐Continued

1.2

1

0.2

SPEC

0.1

SPEC

Ta=-40℃

Ta= 25℃

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

Ta=-40℃

Ta= 25℃

0.8

0.6

0.4

0.2

0

Ta= 85℃

0

1

2

3

4

5

6

0

1

2

3

4

5

6

SupplyVoltage: Vcc(V)

SupplyVoltage : Vcc(V)

Figure 28. WP High Period vs Supply Voltage

Figure 27. WP Setup Time vs Supply Voltage

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Timing Chart

1. I²C BUS Data Communication

I²C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and

acknowledge is always required after each byte. I²C BUS data communication with several devices is possible by connecting

with 2 communication lines; serial data (SDA) and serial clock (SCL).

Among the devices, there should be a “master” that generates clock and control communication start and end. The rest

become “slave” which are controlled by an address peculiar to each device, like this EEPROM. The device that outputs data

to the bus during data communication is called “transmitter”, and the device that receives data is called “receiver”.

SDA

1-7

8

9

8

9

8

9

SCL

S

P

START ADDRESS R/W

condition

ACK

DATA

ACK

DATA

ACK

STOP

condition

Figure 29. Data Transfer Timing

2. Start Condition (Start Bit Recognition)

(1) Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is

'HIGH' is necessary.

(2) This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is

satisfied, any command cannot be executed.

3. Stop Condition (Stop Bit Recognition)

(1) Each command can be ended by a stop condition (stop bit) where SDA goes from 'LOW' to 'HIGH' while SCL is 'HIGH'.

4. Acknowledge (ACK) Signal

(1) The acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In a

master-slave communication, the device (Ex. µ-COM sends slave address input for write or read command to this IC)

at the transmitter (sending) side releases the bus after output of 8bit data.

(2) The device (Ex. This IC receives the slave address input for write or read command from the µ-COM) at the receiver

(receiving) side sets SDA 'LOW' during the 9th clock cycle, and outputs acknowledge signal (ACK signal) showing that

it has received the 8bit data.

(3) This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.

(4) After receiving 8bit data (word adress and write data) during each write operation, this IC outputs acknowledge signal

(ACK signal) 'LOW'.

(5) During read operation, this IC outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'. When

acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this IC

continues to output data. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and

recognizes stop condition (stop bit), and ends read operation. Then this IC becomes ready for another transmission.

5. Device Addressing

(1) Slave address comes after start condition from master.

(2) The significant 4 bits of slave address are used for recognizing a device type.

The device code of this IC is fixed to '1010'.

(3) Next slave addresses (P2, P1, P0 --- page select) are for selecting page addresses.

(4) The most insignificant bit (R / W --- READ / WRITE ) of slave address is used for designating write or read action,

and is as shown below.

Setting R/ W to 0 ------- write (setting 0 to word address setting of Random Read)

Setting R/ W to 1 ------- read

Type

BRCB016GWL-3U

Slave Address

P2 P1 P0 R/W

― ―

1

0

1

0

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Write Command

1. Write Cycle

(1) Arbitrary data can be written to this EEPROM. When writing only 1 byte, Byte Write is normally used, and when

writing continuous data of 2 bytes or more, simultaneous write is possible by Page Write cycle. Up to 16 arbitrary

bytes can be written.

S

T

A

R

T

W

R

I

T

E

S

T

O

SLAVE

ADDRESS

WORD

ADDRESS

DATA

P

SDA

LINE

WA

7

WA

0

1

0

1

0 P2P1P0

D7

D0

A

C

K

A

C

K

R

/

W

A

C

K

Figure 30. Byte Write Cycle

S

W

R

I

T

E

S

T

O

P

T

A

R

T

SLAVE

ADDRESS

WORD

ADDRESS(n)

DATA(n)

DATA(n+15)

SDA

LINE

WA

7

WA

0

1

0

1

P2P1P0

D7

D0

0

A

C

K

R

/

W

A

C

K

A

C

K

A

C

K

Figure 31. Page Write Cycle

(2)

(3)

(4)

(5)

(6)

During internal write execution, all input commands are ignored, therefore ACK is not returned.

Data is written to the address designated by word address (n-th address)

By issuing stop bit after 8bit data input, internal write to memory cell starts.

When internal write is started, command is not accepted for t_WR(5ms at maximum).

Using page write cycle, writing in bulk is done as follows: When data of more than 16 bytes is sent, the bytes in

excess overwrites the data already sent first.

(Refer to "Internal Address Increment")

(7)

As for page write command, where 2 or more bytes of data is intended to be written, after page select bit

‘P0,P1,P2’ of slave address are designated arbitrarily, only the value of 4 least significant bits in the address is

incremented internally, so that data up to 16 addresses of memory only can be written.

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2. Notes on Page Write Cycle

1 page=16bytes, but the page

Write Cycle Time is 5ms at maximum for 16byte bulk write.

It does not stand 5ms at maximum × 16byte=80ms (Max)

3. Internal Address Increment

Page Write Mode

WA7

0

WA4 WA3 WA2 WA1 WA0

0

1

0

1

0

Increment

0

For example, when it is started from address 0Eh, then, increment

is made as below, 0Eh→0Fh→00h→01h･･･ please take note.

0

1

0

1

0

1

0

1

0

0Eh

※0Eh･･･0E in hexadecimal, therefore,

00001110 becomes a binary number.

Significant bit is fixed.

No digit up

4. Write Protect (WP) Terminal

Write Protect (WP) Function

When WP terminal is set at Vcc (H level), data rewrite of all addresses is prohibited. When it is set at GND (L level), data

rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not

use it open.

In case of using it as a ROM, it is recommended to connect it to pull up or Vcc.

At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', write error can be prevented.

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Read Command

1. Read Cycle

Read cycle is when data of EEPROM is read. Read cycle could be random read cycle or current read cycle. Random

read cycle is a command to read data by designating a specific address, and is used generally. Current read cycle is a

command to read data of internal address register without designating an address, and is used when to verify just after

write cycle. In both the read cycles, sequential read cycle is available where the next address data can be read in

succession.

W

R

I

T

E

S

T

A

R

T

S

T

A

R

T

R

E

A

D

S

T

O

SLAVE

ADDRESS

SLAVE

ADDRESS

WORD

ADDRESS(n)

DATA(n)

P

SDA

LINE

WA

7

WA

0

1 0 1 0P2P1P0

1

0 1 0 P2P1P0

D7

D0

A

C

K

R A

/ C

W K

A

C

K

R A

/ C

W K

Figure 32. Random Read Cycle

S

T

A

R

T

R

E

A

S

T

O

SLAVE

ADDRESS

D

DATA(n)

P

SDA

LINE

1 0 1 0 P2P1P0

D7

D0

A

C

K

R A

/ C

W K

Figure 33. Current Read Cycle

S

T

A

R

T

R

E

A

D

S

T

SLAVE

ADDRESS

O

P

DATA(n)

DATA(n+x)

SDA

LINE

P1

P2 P0

1

0

1

0

D7

D0

D7

D0

R A

A

C

K

A

C

K

A

C

K

/

C

W K

Figure 34. Sequential Read Cycle (in the case of Current Read Cycle)

(1) In Random Read Cycle, data of designated word address can be read.

(2) When the command just before current read cycle is random read cycle, current read cycle (each including sequential

read cycle), data of incremented last read address (n)-th, i.e., data of the (n+1)-th address is output.

(3) When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (µ-COM) side, the next

address data can be read in succession.

(4) Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal goes from ‘L’ to ‘H’

while SCL signal is 'H' .

(5) When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.

Therefore, read command cycle cannot be ended. To end the read command cycle, be sure to input 'H' to ACK signal

after D0, and the stop condition where SDA goes from ‘L’ to ‘H’ while SCL signal is 'H'.

(6) Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is asserted from

‘L’ to ‘H’ while SCL signal is 'H'.

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Software Reset

Software reset is executed to avoid malfunction after power on, and during command input. Software reset has several

kinds, and 3 kinds of them are shown in the figure below. (Refer to Figure 35-(a), Figure 35-(b), and Figure 35-(c).) Within

the dummy clock input area, the SDA bus is released ('H' by pull up) and ACK output and read data '0' (both 'L' level) may

be output from EEPROM. Therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to

instantaneous power failure of system power source or influence upon devices.

Dummy clock×14

Start×2

SCL

SDA

Normal command

1

2

13

14

Figure 35-(a). The case of dummy clock×14 + START+START+ command input

Start

Dummy clock×9

Start

SCL

SDA

Normal command

1

2

8

9

Figure 35-(b). The case of START + dummy clock×9 + START + command input

Start×9

SCL

SDA

Normal command

1

2

3

7

8

9

Normal command

Figure 35-(c). START×9 + command input

※Start command from START input.

Acknowledge Polling

During internal write execution, all input commands are ignored, therefore ACK is not returned. During internal automatic

write execution after write cycle input, next command (slave address) is sent. If the first ACK signal sends back 'L', then it

means end of write operation, else 'H' is returned, which means writing is still on progress. By the use of acknowledge

polling, next command can be executed without waiting for t_WR= 5ms.

To write continuously,R/ W = 0, then to carry out current read cycle after write, slave address with R/ W = 1 is sent. If

ACK signal sends back 'L', then execute word address input and data output and so forth.

During internal write,

ACK = HIGH is returned.

First write command

S

T

A

R

T

S

T

A

R

T

S

T

A

C

K

H

A

T

A

R

T

Slave

C

K

H

Write command

O

…

address

P

t_WR

Second Write Command

S

T

A

R

T

S

T

A

R

T

S

T

O

P

A

C

K

L

A

C

K

L

A

C

K

L

Slave

Word

Slave

C

…

Data

K

address

H

t_WR

After completion of internal write,

ACK=LOW is returned, so input next

word address and data in succession.

Figure 36. Case of continuous write by Acknowledge Polling

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WP Valid Timing (Write Cancel)

WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so on, pay attention to the following WP valid

timing. During write cycle execution, inside cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte

write cycle and page write cycle, the area from the first start condition of command to the rise of clock to take in D0 of

data(in page write cycle, the first byte data) is the cancel invalid area.

WP input in this area becomes Don't care. The area from the rise of SCL to take in D0 to the stop condition input is the

cancel valid area. Furthermore, after the execution of forced end by WP, the IC enters standby status.

・Rise of SDA

・Rise of D0 taken clock

SCL

SDA

D1

D0 ACK

SDA D0

ACK

Enlarged View

S

A

C

K

L

A

C

K

L

A

C

K

L

S

T

O

P

t_WR

T

A

R

T

Slave

Word

SDA

WP

D7 D6 D5

D2

D1 D0

D4 D3

C

K

L

Data

address

WP cancel invalid area

WP cancel valid area

Data is not written.

WP cancel invalid area

Figure 37. WP Valid Timing

Command Cancel by Start Condition and Stop Condition

During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Figure 38)

However, within ACK output area and during data read, SDA bus may output 'L'. In this case, start condition and stop

condition cannot be input, so reset is not available. Therefore, execute software reset. When command is cancelled by

start-stop condition during random read cycle, sequential read cycle, or current read cycle, internal setting address is not

determined. Therefore, it is not possible to carry out current read cycle in succession. To carry out read cycle in succession,

carry out random read cycle.

SCL

SDA

1

0

1

0

Start Condition

Stop Condition

Figure 38. Case of Cancel by Start, Stop Condition during Slave Address Input

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I/O Peripheral Circuit

1. Pull-up Resistance of SDA Terminal

SDA is NMOS open drain, so it requires a pull up resistor. As for this resistance value (R_PU), select an appropriate value

from microcontroller V_IL, I_L, and V_OL-I_OLcharacteristics of this IC. If R_PUis large, operating frequency is limited. The smaller

the R_PU, the larger is the supply current (Read).

2. Maximum Value of R_PU

The maximum value of R_PUis determined by the following factors:

(1) SDA rise time to be determined by the capacitance (C_BUS) of bus line and R_PUof SDA should be t_Ror lower.

Furthermore, AC timing should be satisfied even when SDA rise time is slow.

(2)The bus electric potential

A to be determined by the input current leak total (I_L) of the device connected to the bus

○

with output of 'H' to the SDA line and R_PUshould sufficiently secure the input 'H' level (V_IH) of microcontroller and

EEPROM including recommended noise margin of 0.2Vcc.

Vcc-I_LR_PU-0.2 Vcc ≧ V_IH

0.8Vcc-V_IH

I_L

Microcontroller

BRCB016GWL-3U

SDA terminal

∴

R_PU≦

RPU

Ex.) Vcc =3V I_L=10µA V_IH=0.7 Vcc

From(2)

A

0.8×3-0.7×3

R_PU≦

10×10^-6

IL

≦ 30 [kΩ]

Bus line

Capacity

C_BUS

Figure 39. I/O circuit diagram

3. Minimum Value of R_PU

The minimum value of R_PUis determined by the following factors.

(1) When IC outputs LOW, it should be satisfied that V_OLMAX=0.4V and I_OLMAX=3mA.

Vcc-V_OL

≦I_OL

R_PU

Vcc-V_OL

∴

R_PU≧

I_OL

(2)VOLMAX=0.4V should secure the input 'L' level (V_IL) of microcontroller and EEPROM

including the recommended noise margin of 0.1Vcc.

VOLMAX ≦ V_IL-0.1 Vcc

Ex.) Vcc =3V, V_OL=0.4V, I_OL=3mA, microcontroller, EEPROM V_IL=0.3Vcc

from (1)

3-0.4

R_PU

≧

3×10^-3

867[Ω]

And

V_OL=0.4［V］

V_IL=0.3×3

=0.9［V］

Therefore, the condition (2) is satisfied.

4. Pull-up Resistance of SCL Terminal

When SCL control is made at the CMOS output port, there is no need for a pull up resistor. But when there is a time

where SCL becomes 'Hi-Z', add a pull up resistor. As for the pull up resistor value, one of several kΩ to several ten kΩ

is recommended in consideration of drive performance of output port of microcontroller.

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Cautions on Microcontroller Connection

1. RS

In I²C BUS, it is recommended that SDA port is of open drain input/output. However, when using CMOS input / output of

tri state to SDA port, insert a series resistance R_Sbetween the pull up resistor R_PUand the SDA terminal of EEPROM.

This is to control over current that may occur when PMOS of the microcontroller and NMOS of EEPROM are turned ON

simultaneously. R_Salso plays the role of protecting the SDA terminal against surge. Therefore, even when SDA port is

open drain input/output, Rs can be used.

ACK

SCL

R_PU

R_S

SDA

'H' output of microcontroller

'L' output of EEPROM

EEPROM

Microcontroller

Over current flows to SDA line by 'H'

output of microcontroller and 'L'

output of EEPROM.

Figure 40. I/O Circuit Diagram

Figure 41. Input / Output Collision Timing

2. Maximum Value of R_S

The maximum value of Rs is determined by the following relations:

(1) SDA rise time to be determined by the capacitance (C_BUS) of bus line and R_PUof SDA should be t_Ror lower.

Furthermore And AC timing should be satisfied even when SDA rise time is slow.

(2) The bus electric potential

should sufficiently secure the input 'L' level (V_IL) of microcontroller including recommended noise margin of 0.1Vcc.

A to be determined by R_PUand R_Sthe moment when EEPROM outputs 'L' to SDA bus

○

(Vcc-V_OL)×R_S

+V_OL+0.1Vcc≦V_IL

VCC

R_PU+R_S

A

RPU

RS

V_IL-V_OL-0.1Vcc

1.1Vcc-V_IL

×R_PU

∴

R_S≦

VOL

IOL

Ex)Vcc=3V V_IL=0.3V_CCV_OL=0.4V R_PU=20kΩ

Bus line

capacity

C_BUS

0.3×3-0.4-0.1×3

1.1×3-0.3×3

×20×10³

R_S≦

VIL

EEPROM

Micro controller

≦1.67[kΩ]

Figure 42. I/O Circuit Diagram

3. Minimum Value of R_S

The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source

line and instantaneous power failure of power source may occur. When allowable over current is defined as I, the

following relation must be satisfied. Determine the allowable current in consideration of the impedance of power source

line in set and so forth. Set the over current to EEPROM at 10mA or lower.

Vcc

R_S

≦I

R_PU

R_S

Vcc

I

∴

R_S≧

'L'output

EX) V_CC=3V I=10mA

Over current I

3

R_S≧

10×10^-3

'H' output

≧300[Ω]

EEPROM

Microcontroller

Figure 43. I/O Circuit Diagram

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I/O Equivalence Circuit

1. Input (SCL, WP)

Figure 44. Input Pin Circuit Diagram

2. Input / Output (SDA)

Figure 45. Input / Output Pin Circuit Diagram

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Power-Up/Down Conditions

At power on, the IC’s internal circuits may go through unstable low voltage area as the Vcc rises, making the IC’s internal

logic circuit not completely reset, hence malfunction may occur. To prevent this, the IC is equipped with POR circuit and

LVCC circuit. To assure the operation, observe the following conditions at power on.

1. Set SDA = 'H' and SCL ='L' or 'H’

2. Start power source so as to satisfy the recommended conditions of t_R, t_OFF, and V_botfor operating POR circuit.

t_R

Recommended conditions of t_R, t_OFF,V_bot

VCC

t_R

t_OFF

V_bot

10ms or below

100ms or below

10ms or larger

0.3V or below

0.2V or below

t_OFF

V_bot

0

Figure 46. Rise Waveform Diagram

3. Set SDA and SCL so as not to become 'Hi-Z'.

When the above conditions 1 and 2 cannot be observed, take the following countermeasures.

(1) In the case when the above condition 1 cannot be observed such that SDA becomes 'L' at power on.

→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.

V^CC

t_LOW

SCL

SDA

After Vcc becomes stable

t_DH

t_SU:DAT

Figure 48. When SCL='L' and SDA='L'

Figure 47. When SCL= 'H' and SDA= 'L'

(2) In the case when the above condition 2 cannot be observed.

→After power source becomes stable, execute software reset(Page 16).

(3) In the case when the above conditions 1 and 2 cannot be observed.

→Carry out (1), and then carry out (2).

Low Voltage Malfunction Prevention Function

LVCC circuit prevents data rewrite operation at low power and prevents write error.. At LVCC voltage (Typ =1.2V) or below,

data rewrite is prevented.

Noise Countermeasures

1. Bypass Capacitor

When noise or surge gets in the power source line, malfunction may occur, therefore, it is recommended to connect a

bypass capacitor (0.1µF) between the IC’s Vcc and GND pins. Connect the capacitor as close to the IC as possible. In

addition, it is also recommended to attach a bypass capacitor between the board’s Vcc and GND.

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Operational Notes

1. Described numeric values and data are design representative values only and the values are not guaranteed.

2. We believe that the application circuit examples in this document are recommendable. However, in actual use, confirm

characteristics further sufficiently. If changing the fixed number of external parts is desired, make your decision with

sufficient margin in consideration of static characteristics, transient characteristics, and fluctuations of external parts

and our LSI.

3. Absolute maximum ratings

If the absolute maximum ratings such as supply voltage, operating temperature range and so on are exceeded, LSI

may be destroyed. Do not supply voltage or subject the IC to temperatures exceeding the absolute maximum ratings.

In the case of fear of exceeding the absolute maximum ratings, take physical safety countermeasures such as adding

fuses, and see to it that conditions exceeding the absolute maximum ratings should not be supplied to the LSI.

4. GND electric potential

Set the voltage of GND terminal lowest at any operating condition. Make sure that each terminal voltage is not lower

than that of GND terminal.

5. Thermal design

Use a thermal design that allows for a sufficient margin by taking into account the permissible power dissipation (Pd) in

actual operating conditions.

6. Short between pins and mounting errors

Be careful when mounting the IC on printed circuit boards. The IC may be damaged if it is mounted in a wrong

orientation or if pins are shorted together. Short circuit may be caused by conductive particles caught between the pins.

7. Operating the IC in the presence of strong electromagnetic field may cause malfunction, therefore, evaluate design

sufficiently.

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Part Numbering

E 2

B R C B 0 1 6 G W L - 3 U

BUS type

C：I²C

Revision

Capacity

016=16K

Package

GWL：UCSP50L1

Process Code

Resin change model

Packaging and forming specification

E2：: Embossed tape and reel

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Physical Dimensions Tape and Reel Information

UCSP50L1

1PIN MARK

A

B

Vcc

GND

SCL

5

0

SDA

(top view)

0

1

C

WP

1

2

3

1.10±0.05

5

0

5

1

S

0.06

S

5

0

5-φ0.25±0.05

0.05

±

A

B

2

3

C

B

WP

SCL

B

(bottom view)

0.

0±

6.

SDA

A

Vcc

GND

1

3

2

0.35±0.05

P = 0.4 × 1

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Marking Diagram

UCSP50L1(TOP VIEW)

1PIN MARK

Part Number Marking

B 9

LOT NO.

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Revision History

Date

Revision

001

Changes

05.Feb.2021

New Release

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Notice

Precaution on using ROHM Products

1. Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment,

OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you

intend to use our Products in devices requiring extremely high reliability (such as medical equipment ^{(Note 1)}, transport

equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car

accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or

serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.

Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any

damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific

Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are designed and manufactured for use under standard conditions and not under any special or

extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any

special or extraordinary environments or conditions. If you intend to use our Products under any special or

extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of

product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.

However, recommend sufficiently about the residue.) ; or Washing our Products by using water or water-soluble

cleaning agents for cleaning residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PGA-E

Rev.004

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl₂, H₂S, NH₃, SO₂, and NO₂

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PGA-E

Rev.004


型号：	BRCB016GWL-3U
厂家：	ROHM
描述：	BRCB016GWL-3U是一款WL-CSP型的I²C　EEPROM。可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总29页 (文件大小：1060K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BRCB016GWL-3U [ROHM]

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