BU1424K [ROHM]
NTSC / PAL digital RGB encoder; NTSC / PAL数字RGB编码器
| 型号： | BU1424K |
| 厂家： | 
ROHM |
| 描述： | NTSC / PAL digital RGB encoder |
| 文件： | 总30页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Multimedia ICs
NTSC / PAL digital RGB encoder
BU1424K
The BU1424K is an IC that converts digital RGB / YUV input to composite (NTSC / PAL / PAL60), luminance (Y),
and chrominance (C) signals, and outputs the results.
Applications
•
Video interfaces for VIDEO-CDs and CD-G decoders
Features
•
1) Input clocks supported.
5) Internal 8-color OSD output function is provided.
6) FSC-TRAP on the Y channel can be turned on and
off.
27.0 / 13.5MHz
28.636 / 14.318MHz
28.375 / 14.1875MHz
7) C channel is equipped with an internal chrominance
band-pass filter in addition to the U,V. low-pass filter.
8) 5V single power supply, low power consumption.
(0.4W typ.)
35.4695 / 17.73475MHz
2) 24-bit RGB and 16-bit YUV input signals are sup-
ported.
3) Both master and slave systems are supported.
4) 9-bit high-speed DAC is used for DAC output of
composite VIDEO, Y, and C signals.
9) Y and C output can be turned off (the power con-
sumption with Y and C off is 0.25W typ.).
1
Multimedia ICs
BU1424K
Block diagram
•
RGB 24BITS
OSD PALLET
DAC
V
Y-FILTER
C-FILTER
MIX SIG
and
sync
LATCH
RGB
to
YUV
Y-LEVEL SHIFT
CHROMA GEN
RD
VOUT
YOUT
COUT
burst
GD / Y
BD / UV
Y
C
UV
FILTER
VOLK
RSTB
PIXCLK
HSY
VIDEO TIMING CONTROL
SYNC BLANK
SUB CARRIER BURST GENERATOR
BURST
VSY
BCLK
MODE CONTROL FIELD / FLAME CONTROL
2
Multimedia ICs
BU1424K
Pin descriptions
•
Pin No. Pin name
Function
Pin No. Pin name
SLABEB SELECT MASTER / SLAVE
ADDH + 0.5 / – 0.5LINE at NON-INTER
VREF-C DAC BIAS
Function
1
BOSD
OSD BLUE DATA INPUT
1
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
1
2
GD0 / Y0 GREEN DATA Bit0 (LSB)
GD1 / Y1 GREEN DATA Bit1
GD2 / Y2 GREEN DATA Bit2
GD3 / Y3 GREEN DATA Bit3
GD4 / Y4 GREEN DATA Bit4
GD5 / Y5 GREEN DATA Bit5
GD6 / Y6 GREEN DATA Bit6
3
4
CGND
COUT
VGND
VOUT
AVSS
CHROMA OUTPUT GROUND
5
CHROMA OUTPUT
6
Composite Output Ground
COMPOSITE OUTPUT
Analog Ground (DAC. VREF)
ANALOG (DAC) VDD
7
8
9
GND
DIGITAL GROUND
AVDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GD7 / Y7 GREEN DATA Bit7 (MSB)
BD0 / UV0 BLUE DATA Bit0 (LSB)
BD1 / UV1 BLUE DATA Bit1
IR
REFERENCE RESISTOR
ANALOG (VREF) VDD
Luminance Output Ground
Luminance Output
AVDD
YGND
YOUT
BD2 / UV2 BLUE DATA Bit2
BD3 / UV3 BLUE DATA Bit3
C4FSC 4FSC / 3.2FSC at PALCD-G
47 YFILON2B Y-FILSEL THROU / FILON2
48 YCOFF DAC (YOUT. COUT) OFF
49 YFILON1B Y-FILSEL THROU / FILON1
PAL60B NORMAL / PAL60 at PALMODE
1
2
OSDSW OSD ENABLE / DISABLE
CDGSWB SELECT Video-CD / CD-G
BD4 / UV4 BLUE DATA Bit4
1
2
2
BD5 / UV5 BLUE DATA Bit5
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
BD6 / UV6 BLUE DATA Bit6
VCLK
RSTB
Video Clock Input
NORMAL / RESET
BD7 / UV7 BLUE DATA Bit7 (MSB)
2
GND
NTB
DIGITAL GROUND
CLKSW SEL × 1CLK / × 2CLK
SELECT NTSC / PAL MODE
SELECT YUV / RGB
RD0
RD1
RD2
ROSD
RD3
RD4
RD5
VDD
RED DATA Bit0 (LSB)
RED DATA Bit1
1
1
1
1
1
1
1
IM0
1
1
1
1
IM1
SELECT DAC / NORMAL
Normally pull down to GND
SELECT U / V TIMING
RED DATA Bit2
TEST1
TEST2
VSY
OSD RED DATA INPUT
RED DATA Bit3
V-SYNC INPUT or OUTPUT
H-SYNC INPUT or OUTPUT
RED DATA Bit4
HSY
RED DATA Bit5
PIXCLK 1 / 2freq. of BCLK
DIGITAL VDD
BCLK
VDD
INTERNAL CLOCK OUTPUT
RD6
RD7
GOSD
RED DATA Bit6
1
1
1
DIGITAL VDD
RED DATA Bit7
INT
Interlace / Non-Interlace
OSD GREEN DATA INPUT
1 Internal pull-down resistor
2 Internal pull-up resistor
3
Multimedia ICs
BU1424K
Absolute maximum ratings (Ta = 25°C)
•
Parameter
Symbol
Limits
Unit
V
Applied voltage
V
DD, AVDD
– 0.5 ~ + 7.0
– 0.5 ~ VDD + 0.5
– 55 ~ + 150
Input voltage
VIN
V
Storage temperature
Power dissipation
Tstg
Pd
°C
mW
1
1350
1 Reduced by 11mW for each increase in Ta of 1°C over 25°C.
When mounted on a 120mm × 140mm × 1.0mm glass epoxy board.
Operation is not guaranteed at this value.
᭺ Not designed for radiation resistance.
Recommended operating conditions (Ta = 25°C)
•
Parameter
Symbol
Limits
+ 4.75 ~ + 5.25
+ 2.1 ~ VDD
0 ~ + 0.8
Unit
V
Power supply voltage
Input high level voltage
Input low level voltage
Analog input voltage
Operating temperature
Should be used at VDD = AVDD
V
DD = AVDD
V
IH
IL
AIN
V
V
V
V
0 ~ AVDD
V
Topr
– 25 ~ + 60
°C
.
Electrical characteristics (unless otherwise noted, Ta = 25°C, VDD = AVDD = 5.0V, GND = AVSS = VGND = CGND =
YGND)
•
Digital block
Parameter
Symbol
fBST1
fBST2
CBST
Idd1
Min.
—
Typ.
3.57954
4.43361
9
Max.
—
Unit
MHz
MHz
CYC
mA
mA
V
Conditions
Burst frequency 1
—
—
—
Burst frequency 2
—
—
Burst cycle
—
—
Operating circuit current 1
Operating circuit current 2
Output high level voltage
Output low level voltage
Input high level voltage
Input low level voltage
Input high level current
Input low level current
—
80
—
27MHz color bar
27MHz color bar PD mode
Idd2
—
40
—
V
OH
OL
IH
IL
IH
4.0
—
4.5
—
I
I
OH = – 2.0mA
OH = 2.0mA
V
0.5
1.0
—
V
V
2.1
—
—
V
—
—
—
—
V
—
0.8
10.0
10.0
V
I
I
0.0
µA
µA
– 10
– 10
IL
0.0
DAC block
Parameter
DAC resolution
Symbol
RES
EL
Min.
—
Typ.
9
Max.
—
Unit
BITS
LSB
mA
mA
µA
Conditions
—
Linearity error
—
± 0.5
25.14
7.24
0.0
± 3.0
—
IR = 1.2kΩ
Y white level current
Y black level current
Y zero level current
V white level current
V black level current
V zero level current
IYW
IYB
—
—
—
—
—
—
—
—
—
IYZ
– 10
—
10.0
—
IYW
IYB
25.14
7.24
0.0
mA
mA
µA
—
—
IYZ
– 10
10.0
4
Multimedia ICs
BU1424K
Application example
•
(1) Example in Master mode: Doubled clock is input and 24-bit RGB input is used
YFILON1B
49
50
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
INT
VDD
PAL GOB
51 VCLK
52 RSTB
BCLK
PIXCLK
HSY
CLKSW
53
54 RD0
55 RD1
56 RD2
57 ROSD
VSY
0
1
2
TEST2
TEST1
IM1
BU1424K
RD3
59 RD4
58
IM0
3
4
5
NTB
RD5
VDD
60
61
GND
BD7
7
6
5
4
62 RD6
63 RD7
64 GOSD
BD6
6
7
BD5
BD4
0
1
2
3
4
5
6
7
0
1
2
3
Fig.1
5
Multimedia ICs
BU1424K
(2) Example in Slave mode: Doubled clock is input and 16-bit YUV input is used
49 YFILON1B
50 PALGOB
51 YCLK
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
INT
VDD
BCLK
PIXCLK
HSY
52
RSTB
53 CLKSW
54
55
56
RD0
RD1
RD2
VSY
0
1
2
TEST2
TEST1
IM1
BU1424K
57 ROSD
58 RD3
59 RD4
60 RD5
IM0
3
4
5
NTB
GND
BD7
61
62
63
64
VDD
7
6
5
4
RD6
RD7
GOSD
BD6
6
7
BD5
BD4
0
1
2
3
4
5
6
7
0
1
2
3
Fig.2
6
Multimedia ICs
BU1424K
Equivalent circuits
•
Pin No.
Pin name
GD (7: 0)
I / O
Equivalent circuit
Function
2 ~ 8
10
G data input pin for 24-bit RGB input.
Y data input pin for 16-bit YUV input.
I
B data input pin for 24-bit RGB input.
U, V data input pins for 16-bit YUV
input.
11 ~ 14
17 ~ 20
BD (7: 0)
RD (7: 0)
I
I
I
I
54 ~ 56
58 ~ 60
62.63
R data input pin for 24-bit RGB input.
OSD data input pin when using the
OSD function.
When the OSDSW pin is HIGH, input
to the ROSD, GOSD, and BOSD pins
takes precedence over RGB, and the
data is converted.
1
ROSD
GOSD
BOSD
57
64
15
OSDSW
Control pins used to select RGB (24-
bit), YUV (16-bit) or DAC Through as
the input mode.
23
24
IM0
IM1
Switches the mode between Video-
CD (HIGH) and CD-G (LOW).
16
22
CDGSWB
I
I
Switches the mode between NTSC
(LOW) and PAL (HIGH).
NTB
This is the horizontal synchronization
signal pin. Negative polarity HSYNC
signals are input (when SLABEB =
LOW) or output (when SLABEB =
HIGH) here. This is also used as the
synchronization signal for fixing the
PIXCLK output phase.
28
HSY
I / O
7
Multimedia ICs
BU1424K
Pin No.
Pin name
VSY
I / O
Equivalent circuit
Function
Vertical synchronization signals
(VSYNC) are input (when SLABEB =
LOW) or output (when SLABEB =
HIGH) here.
27
I
The internal processing clock is divid-
ed in half and then output. Data is
read at the point at which the edge of
this clock changes. This can also be
used as the clock for the OSD IC.
29
PIXCLK
O
This pin switches between interlace
(when HIGH) and non-interlace
(when LOW) modes. This pin is effec-
tive in both the VIDEO-CD and CD-G
modes.
32
INT
I
This pin switches between the Master
(when HIGH) and Slave (when LOW)
modes. It is effective in the non-
interlace mode, and it switches bet-
ween – 0.5 lines (when LOW) and +
0.5 lines (when HIGH) for the number
of lines in an interlace field.
33
34
SLABEB
ADDH
I
I
This is the reference voltage generator
circuit monitoring pin which deter-
mines the output amplitude (output cur-
rent for 1 LSB) of the DAC.
35
Vref-C
I
8
Multimedia ICs
BU1424K
Pin No.
Pin name
I / O
Equivalent circuit
Function
This is the chrominance output pin for
the S pin.
37
COUT
O
39
45
42
48
30
VOUT
O
O
I
Composite output pin.
YOUT
Luminance output pin for the S pin.
The output amplitude (output current
for 1 LSB) of the DAC is specified
using an external resistor, and this pin
controls the value of the current flow-
ing per bit.
IR
When there is HIGH input at the signal
input pin, which switches to and from
the low power consumption mode, this
turns off the output from the YOUT
and COUT pins.
YCOFF
I
Output for the internal clock.
When CLKSW is HIGH, the VCLK buff-
er output.
BCLK
O
When CLKSW is LOW, the VCLK 1 / 2
cycle output.
9
Multimedia ICs
BU1424K
Pin No.
51
Pin name
VCLK
I / O
Equivalent circuit
Function
Input pin for the reference clock in the
Video-CD mode.
I
Reset input pin which initializes the
system.
52
49
RSTB
I
I
Selects the F characteristic of the
Y-FILTER. However, this is only effec-
tive when OSDSW is LOW.
YFILON1B
YFILON2B
Switches between the PAL and
PAL60 modes. This is effective only
when the NTB pin is HIGH. (PAL
mode only).
50
53
46
PAL60B
CLKSW
G4FSC
I
I
I
I
This switches between dividing the
VCLK input in half and using it as an
internal clock (when LOW), and using
it as an internal clock without dividing
it in half (when HIGH).
Switching pin for CDG mode input fre-
quency 14.1875 / 4fsc.
Normally, this is connected to the
GND pin. However, when 16-bit YUV
input is used, the TEST2 pin can be
used as the U and V timing control
pins.
25
26
TEST1
TEST2
10
Multimedia ICs
BU1424K
Pin No.
Pin name
I / O
Equivalent circuit
Function
31
61
41
43
VDD
AVDD
Power supply pin for the digital, the
analog and blocks.
—
—
9
GND
CGND
VGND
AVSS
21
36
38
40
44
Ground for digital and analog blocks.
—
—
YGND
11
Multimedia ICs
BU1424K
Circuit operation
•
(1) Overview
including black) chrominance data. At the same time, a
clock with a frequency half that of the internal clock is
output from the PIXCLK pin. As a result, the PIXCLK
pin can easily be directly connected to the OSD IC
clock input pin, and the OSDSW pin can be directly
connected to the BLK output pin. Thus, the BU1424K
and the OSD IC can be synchronized, and OSD text
with a burster trimmer stacker feature can be used.
If the input data is in the RGB format, it is converted to
YUV. If it is in the YUV format, it is converted from the
CCIR-601 format to level-shifted YUV data. The YUV
data is then adjusted to the 100IRE level in the NTSC,
PAL, and PAL60 modes, and U and V data is phase-
adjusted by a sub-carrier generated internally, and is
modulated to chrominance signals.
The BU1424K converts digital images and video data
with an 8-bit configuration to 9-bit composite signals
(VOUT), luminance signals (YOUT), and chrominance
signals (COUT) for the NTSC, PAL, and PAL60 for-
mats, and outputs the converted data as analog TV
signals.
The user may select whether VOUT consists of chromi-
nance signals that have passed through a chrominance
band pass and luminance signals that have been
mixed, or luminance signals that have passed through
a chrominance trap and luminance signals that have
not passed through a chrominance trap. The F charac-
teristic of this chrominance trap may be selected from
among three available types. Since YOUT normally
does not pass through the trap, it is optimum for the S
pin. COUT normally passes through the chrominance
band pass, and is thus highly resistance to dot interfer-
ence. In addition, when used in the doubled clock
mode, it passes through an interpolator filter, and for
that reason is able to reproduce even cleaner image
quality.
Ultimately, elements such as the necessary synchro-
nization level, the color blanking level, and burst sig-
nals are mixed, and pass through the 9-bit DAC to be
output as NTSC or PAL composite signals, luminance
signals, and chrominance signals (conforming to RS-
170A). At this point, the DAC is operating at twice the
internal clock, making it possible to reduce the number
of attachments.
A correspondence can be set up between input digital
image data and Video-CD and CD-G decoder output.
Output TV signals, in addition to switching among the
NTSC, PAL, and PAL60 modes, can be switched be-
tween the interlace and non-interlace modes.
Furthermore, luminance signal output and chrominance
signal output can be turned off. At this point, it is possi-
ble to reduce the level of power consumption.
The DAC output is current output. If a resistor of a
specified value is connected to the IR pin, 2.0VP-P out-
put can be obtained by connecting 75Ω to the VOUT
pin as an external resistor. As a result, normally, when
a video input pin (75Ω terminus) is connected, the out-
put is approximately 1.0VP-P voltage output at a white
100% level.
The data clock input to the VCLK pin can also be input
as a doubled clock for the data rate (in doubled clock
modes). In doubled clock modes, data is read and
processed at the rising edge of an internal clock that
has been divided in half. In ordinary clock modes, data
is read and processed at the rising edge of the clock
that has the same phase as the input clock. Two input
data formats are supported: 24-bit RGB (4: 4: 4) and
16-bit YUV (4: 2: 2). These are input to RD0 to 7, GD0
to 7, and BD0 to 7, respectively. The selected input for-
mat can be switched using the IM0 and IM1 pin input.
When the OSDSW pin is set to the "Enabled" (H) state,
data input to the ROSD, GOSD, and BOSD pins be-
comes effective, making it possible to input 7-color (8
(2) Specifying the mode
1) Power saving mode
With the BU1424K, setting the YCOFF pin to HIGH
turns off the output from the YOUT and COUT pins of
the DAC output, enabling use in the low power con-
sumption mode.
Table 1: Low power consumption mode with the YCOFF pin
Pin No.
Pin name
YCOFF
LOW
Output mode and power consumption
VOUT pin
YOUT pin
COUT pin
Power consumption (Typ.)
0.45W
48
Composite signal
Composite signal
Luminance signal
No output (0V)
Chrominance signal
No output (0V)
HIGH
0.25W
12
Multimedia ICs
BU1424K
2) Output modes
as the output TV modes. The output TV mode is
switched using the NTB and PAL60 pin input. Setting
the NTB pin input to LOW sets the NTSC mode, and
setting it HIGH with the PAL60 pin also HIGH sets the
PAL mode. Setting the NTB pin HIGH and the PAL60
pin LOW, sets the PAL60 mode.
The "Video-CD" and "CD-G" modes can be supported
by both digital image and video data, with the mode
being switched by the CDGSWB pin input. When the
CDGSWB pin input is LOW, the CD-G mode is set, and
when HIGH, the Video-CD mode is set. Also, the
"NTSC", "PAL", and "PAL60" modes may be selected
Table 2: Specifying modes
NTB
PAL60
GDGSWB
Decoder mode
CD-G
TV mode
NTSC
NTSC
PAL60
PAL60
PAL
0
0
1
1
1
1
0
1
0
1
0
1
Video-CD
CD-G
0
0
1
1
Video-CD
CD-G
Video-CD
PAL
Also, INT pin input can be used to switch between "in-
terlace output" and "non-interlace output."
ADDH pin is LOW, the number of lines in one field is
set to the number of interlace output lines minus 0.5
lines, and when HIGH, the number of lines in one field
is set to the number of interlace output lines plus 0.5
lines.
Setting the input to LOW enables non-interlace output,
and setting it to HIGH enables interlace output. When
non-interlace output is used, the number of lines in one
field can be controlled using the ADDH pin. If the
Table 3: Pin settings for interlace / non-interlace modes
No. of Lines / Field
INT
ADDH
Scan Mode
NTSC / PAL60
PAL
312
0
0
1
0
1
Non-interlace
Non-interlace
Interlace
262
263
313
262.5
312.5
3) Input formats
RGB (4: 4: 4) and 16-bit YUV (4: 2: 2) are supported. In
addition, digital RGB input can be output as analog
RGB output (RGB Through mode).
The digital data input format can be set as shown in the
table below, using the IM1 and IM0 pins. Both 24-bit
Table 4: Input format settings
IM1
0
IM0
0
Input format
Output signal
TV signals (9-bit resolution)
TV signals (9-bit resolution)
—
R (8 bits), G (8 bits), B (8 bits)
YUV16bit (4: 2: 2)
0
1
1
0
—
1
1
ROSD, GOSD, BOSD expanded to RGB input
RGB analog signals (9 bits)
13
Multimedia ICs
BU1424K
Table 5: Bit assignments in RGB Through mode
Output Pin
YOUT (45)
VOUT (39)
COUT (37)
BIT8
RD7
GD7
BD7
BIT7
RD6
GD6
BD6
BIT6
RD5
GD5
BD5
BIT5
RD4
GD4
BD4
BIT4
RD3
GD3
BD3
BIT3
RD2
GD2
BD2
BIT2
RD1
GD1
BD1
BIT1
BIT0
RD0
GD0
BD0
ROSD
GOSD
BOSD
The BU1424K has an internal OSD switch and chromi-
nance data generating function. Consequently, joint
usage of an OSD-IC with blanking and R, G, and B out-
put can be easily supported by the OSD. Moreover, a
clock with half the internal processing frequency of the
BU1424K is output from the PIXCLK pin, and can be
connected to the OSD-IC clock input, enabling the tim-
ing to be captured.
ROSD, GOSD, and BOSD pin input is effective as long
as the OSDSW pin input is HIGH. The relationship be-
tween OSD data and chrominance data is as shown in
Table 6 below.
Table 6: Correspondence between OSD function, input data and chrominance output
OSDSW
ROSD
GOSD
BOSD
Output chrominance signal
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Black (blanking)
Blue
Green
Cyan
Red
Magenta
Yellow
White
Based on input specified by IM0 and IM1
4) Clock modes
Fig. 3, with the HSY pin input serving as a reference. In
the Master mode, in which data from the HSY pin is
output and used, HSY is output at the timing shown in
Fig. 3. With the BU1424K, data (RD, GD, BD, etc.) is
read at the rising edge of the internal clock (BCLK), so
data should be input to the BU1424K as shown in Fig.
3.
With the BU1424K, clock input is available at the VCLK
pin.
Clocks supplied from an external source should basi-
cally be input at a frequency double that of clocks used
internally (basic clock: BCLK) (when the CLKSW pin is
LOW). The phase relationship between the internal
clock and the external clock at this time is as shown in
HSY
VCLK
Internal clock
(BCLK)
Input data
Fig.3 Illustration of clock timing (CLKSW is LOW)
14
Multimedia ICs
BU1424K
Also, setting the CLKSW pin to HIGH enables the fre-
quency of the external clock to be used as BCLK, the
internal clock, just as it is. Since the data is read to the
BU1424K at the rising edge of BCLK at this time as
well, data should be input as shown in Fig. 4. The rela-
tionship with HSY is also as shown in Fig. 4.
HSY
VCLK
Internal clock
(BCLK)
Input data
Fig.4 Illustration of clock timing (CLKSW is HIGH)
With the BU1424K, the sub-carrier (burst) frequency is
generated using the internal clock. For this reason, the
frequencies used in the various modes are limited, so
those frequencies should be input (see Table 7 below).
Table 7: BU1424K clock input frequency settings
Video-CD mode
CD-G mode
CLKSW
pin
G4FSC
pin
Same for NTSC / PAL / PAL60
27.000MHz
NTSC
PAL / PAL60
28.3750MHz
35.4695MHz
14.1875MHz
17.73475MHz
0
0
1
1
0
1
0
1
28.636MHz
28.636MHz
14.318MHz
14.318MHz
27.000MHz
13.500MHz
13.500MHz
5) Synchronization signals
output only under "Odd" field conditions (the falling
edges of HSY and VSY are the same).
The BU1424K has an "Encoder Master" mode in which
synchronization signals are output, and an "Encoder
Slave" mode in which synchronization signals are input
from an external source and used to achieve synchro-
nization. These modes are switched at the SLABEB
pin. When the SLABEB pin is LOW, the Slave mode is
in effect, and when HIGH, the Master mode is in effect.
In the Master mode, the HSY and VSY pins serve as
output, with horizontal synchronization signals
(HSYNC) being output from the HSY pin and vertical
synchronization signals (VSYNC) from the VSY pin. At
this time, the reference timing for synchronization sig-
nal output is determined at the rising edge of the RSTB
pin. Output is obtained in accordance with the specified
mode (NTSC, PAL, or PAL60, interlace or non-inter-
lace). Output in the non-interlace mode, however, is
In the Slave mode, the HSY and VSY pins serve as
input, and horizontal synchronization signals (HSYNC)
should be input to the HSY pin and vertical synchro-
nization signals (VSYNC) to the VSY pin. The input
synchronization signals at this time should be input in
accordance with the specified mode. With the
BU1424K, field distinction between odd and even fields
is made automatically for each field when interlace
input is used. With the BU1424K, all synchronization
signals are treated as negative polarity signals (signals
for which the sync interval goes LOW). When using the
non-interlace mode, operation is normally carried out
under odd field conditions (the falling edges of HSY
and VSY are simultaneous).
15
Multimedia ICs
BU1424K
6) Y filter
it can be selected using the YFILON1 and 2 pins. A
through filter is normally used on the YOUT pin output,
so that it is not limited to this method.
With the BU1424K, the frequency characteristic of Y,
which is mixed with the VOUT pin output, is set so that
Table 8: Frequency characteristic of the Y channel
YFILON2B
H
YFILON1B
H
Frequency characteristic of the Y channel
TRAP filter through
(same signal as YOUT pin output is mixed with VOUT)
L
H
L
H
L
L
chart1
chart2
chart3
10
10
5
5
0
180
135
90
180
135
90
0
– 5
– 5
– 10
– 15
– 20
– 25
– 30
45
– 10
– 15
– 20
– 25
– 30
45
0
0
– 45
– 90
– 135
– 180
– 45
– 90
– 135
– 180
– 35
– 40
– 35
– 40
100
1000
10000 20000
100
1000
10000 20000
FREQUENCY (kHz) CONT (c), END (e), COPY (Shift + Prt Sc)
FREQUENCY (kHz) CONT (c), END (e), COPY (Shift + Prt Sc)
Gain-Phase Graphic
Gain-Phase Graphic
Fig.6 Chart2 (BCLK = 13.5MHz)
Fig.5 Chart1 (BCLK = 13.5MHz)
10
5
0
180
135
90
– 5
– 10
– 15
– 20
– 25
– 30
45
0
– 45
– 90
– 135
– 180
– 35
– 40
100
1000
10000 20000
FREQUENCY (kHz) CONT (c), END (e), COPY (Shift + Prt Sc)
Gain-Phase Graphic
Fig.7 Chart3 (BCLK = 14.318MHz)
16
Multimedia ICs
BU1424K
(3) Output level
Figures 8 to 10 indicate the digital data values for the DAC output when the color bars from the various pins are re-
produced.
WHITE
YELLOW
CYAN
GREEN
MAGEN
RED
BLUE
BLACK
BLACK LEVEL
= PEDESTAL LEVEL
SYNC TIP LEVEL
Fig.8 YOUT output
B
L
A
C
K
W
H
I
T
E
M
A
G
E
N
T
Y
E
L
G
R
E
E
N
C
Y
A
N
B
L
U
E
R
E
D
BLACK LEVEL
L
O
W
A
COLOR
BURST
Fig.9 COUT output
Y
E
W
L
H
L
O
W
C
Y
A
N
I
T
E
G
R
E
E
N
M
A
G
E
N
T
R
E
D
B
L
U
E
B
L
A
C
K
A
BLACK LEVEL
= PEDESTAL LEVEL
SYNC TIP LEVEL
Fig.10 VOUT output
17
Multimedia ICs
BU1424K
Table 9: BU1424K color bar input / output data
Input (8-bit hexadecimal for each)
Output (9-bit hexadecimal for each)
RGB24bit
GD
—
YUV (4: 2: 2)
NAME&COLOR
SYNC TIP
YOUT
COUT
VOUT
RD
—
BD
—
YD
UD
—
VD
—
—
—
000
—
—
± 039
± 03D
100
000
± 039
± 03D
—
—
—
—
—
—
Color Burst NTSC
Color Burst PAL
BLANK LEVEL
BLACK (Pedestal)
BLUE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
00
00
00
00
FF
FF
FF
FF
00
00
FF
00
FF
00
FF
00
FF
10
28
90
A9
51
6A
D2
EB
80
F1
36
A5
5A
C9
0E
80
80
6D
22
10
F0
DD
92
80
072
092
117
138
0C6
0E6
16C
18C
000
072
00
± 064
± 085
± 08E
± 08E
± 085
± 064
000
± 064
± 085
± 08E
± 08E
± 085
± 064
000
FF
GREEN
FF
CYAN
00
RED
00
MAGENTA
YELLOW
FF
FF
WHITE
COUT and VOUT display the chrominance amplitude. COUT is 100H ± XXXH.
VOUT is YOUT ± XXXH.
(4) Timing
Table 10 below shows the input and output pins related to timing.
Table 10: BU1424K timing-related input / output pins
Pin No.
52
Pin name
RSTB
I / O
Function
I
System reset input pin
Clock input pin
51
VCLK
I
53
CLKSW
VSY
I
Clock input mode setting pin
27
I / O
Vertical synchronization signal I / O pin
Horizontal synchronization signal I / O pin
Video-CD / CD-G mode switching pin
NTSC / PAL mode switching pin
28
HSY
I / O
16
CDGSWB
NTB
I
I
22
50
PAL60B
INT
I
PAL / PAL60 mode switching pin
32
I
Interlace / Non-interlace mode switching pin
Master / Slave mode switching pin
33
SLABEB
ADDH
PIXCLK
I
34
I
Pin which adds 1 line in non-interlace mode
29
O
1 / 2 divider output for internal clock (OSD clock)
1) Input clocks and input data timings in the various
operation modes
What is shared by all modes is that, with the BU1424K,
data is read and discharged at the rising edge of the in-
ternal clock. The illustration below shows the input con-
ditions in the various modes.
There are slight differences in the input data and the
clock timing, depending on which mode is being used.
18
Multimedia ICs
BU1424K
1. Master mode, clock mode
Encoder master (pin 33 = H)
Internal clock = input clock (pin 53 = H)
VCLK (53pin)
BCLK
(Internal clock)
Input data
Output data
(HSY, VSY)
Tds1
Fig.11
In this mode, the internal clock (BCLK) begins to operate at the same phase as the VCLK input, following the rise
of the RSTB pin (pin 52).
Table 11
Parameter
Data setup time 1
Symbol
Tds1
Min.
10
Typ.
—
Max.
—
2. Master mode, doubled clock mode
Encoder master (pin 33 = H)
Internal clock = 2 input clock (pin 53 = H)
VCLK (53pin)
BCLK
(Internal clock)
Input data
Output data
(HSY, VSY)
Tds2
Fig.12
In this mode, the internal clock (BCLK) begins to operate at a halved frequency at the rise of the VCLK input, fol-
lowing the rise of the RSTB pin (pin 52).
Table 12
Parameter
Data setup time 2
Symbol
Tds2
Min.
10
Typ.
—
Max.
—
19
Multimedia ICs
BU1424K
3. Slave mode, single clock mode
Encoder slave (pin 33 = L)
Internal clock = input clock (pin 53 = L)
VCLK (53pin)
BCLK
(Internal clock)
Input data
output data
(HSY, VSY)
Tds3
Tsh1
Tsd1
Fig.13
In this mode, the internal clock (BCLK) begins to operate at the same phase as the VCLK input, following the rise
of the RSTB pin (pin 52).
Table 13
Parameter
Symbol
Tds3
Min.
10
Typ.
—
Max.
—
Data setup time 3
Sync signal hold time
Sync signal hold time
Tsh1
10
—
—
Tsd1
10
—
—
4. Slave mode, doubled clock mode
Encoder slave (pin 33 = L)
Internal clock = 2 input clock (pin 53 = L)
VCLK (53pin)
BCLK
(Internal clock)
Input data
Input data
(HSY, VSY)
Tds4
Tsh2
Tsd2
Fig.14
20
Multimedia ICs
BU1424K
In this mode, the internal clock (BCLK) begins to operate at a halved frequency at the rise of the VCLK input, fol-
lowing the rise of the RSTB pin (pin 52). When HSY is input, phase correction is carried out at the falling edge, as
shown in Fig. 14. (In other words, the phase of the internal clock (BCLK) is not determined until HSY is input.)
Table 14
Parameter
Symbol
Tds4
Min.
10
Typ.
—
Max.
—
Data setup time 4
Sync signal hold time 2
Sync signal setup time 2
Tsh2
10
—
—
Tsd2
10
—
—
BCLK (Internal clock)
HSY (IN / OUT)
PIXCLK
OSDSW
ROSD.GOSD
V,Y,C,OUT
VIDEO-DATA
BLACK YELLOW
VIDEO-DATA
Fig.15 Clock timing with the OSD function
The frequency of the PIXCLK pin output is one-half that of the internal clock. This phase is determined at the rising
edge of HSY, as shown in Fig. 15. (In the Encoder Master mode, phase correction is implemented using the HSY
output of the BU1424K itself.) The OSD function is effective only during the time that video output is enabled.
21
Multimedia ICs
BU1424K
2) Output timing
1. Master mode, doubled clock mode
Encoder master (pin 33 = H)
Internal clock = input clock 1 / 2 (pin 53 = L)
VCLK
BCLK (Internal clock)
Thdr
Thdf
HSY (OUT)
VSY (OUT)
Tvdr
Thdv
PIXCLK (OUT)
Tpdr
Fig.16 Output timing with a doubled clock
Table 15
Parameter
HSY output delay
Symbol
Thdr Thdf
Tvdr Tvdf
Tpdr Tpdf
Min.
—
Typ.
14
Max.
—
VSY output delay
—
14
—
PIXCLK output delay
—
14
—
2. Master mode, regular clock mode
Encoder master (pin 33 = H)
Internal clock = input clock (pin 53 = L)
VCLK
BCLK (Internal clock)
Thdr
Tvdr
Thdf
Tvdf
HSY (OUT)
VSY (OUT)
PIXCLK (OUT)
Tpdr
Fig.17 Output timing with a clock at the regular frequency
22
Multimedia ICs
BU1424K
Table 16
Parameter
HSY output delay
Symbol
Thdr Thdf
Tvdr Tvdf
Tpdr Tpdf
Min.
—
Typ.
10
Max.
—
VSY output delay
—
10
—
PIXCLK output delay
—
10
—
3) Odd / even recognition timing in Slave mode
to the specified mode, enabling regulated output for the
first time. Odd input conditions are indicated below.
Timing that does not match these conditions is recog-
nized as an even field.
The BU1424K distinguishes whether the conditions of
each field (each time that VSY is input) are odd or oth-
erwise, and internal operation is carried out based on
that recognition after the data is input. As a result, HSY
and VSY are input under input conditions appropriate
HSY
VSY
Tvl
Expanded view
HSY
VSY
Thvdiff
Fig.18 ODD recognition conditions
Table 17: Odd recognition conditions
Parameter
Symbol
Tvl
Min.
128
Typ.
—
Max.
—
Unit
VSY input L interval
BCLK
HSY falling edge
– 1clk
HSY Rising edge
– 2clk
VSY Delay from HSY
Thvdiff
—
BCLK
BCLK = One cycle of internal clock
23
Multimedia ICs
BU1424K
4) TV signal timing diagram
VOUT
(39)
BURST
BURST
YOUT
(45)
COUT
BURST
BURST
(37)
Td1
Td2
Td3
Td4
Td5
Fig.19
Table 18
Parameter
NTSC
PAL
PAL60
Symbol
Unit
V-CD
CD-G
67
V-CD CDG2 CDG1 V-CD CDG2 CDG1
SYNC rise
Burst start
Burst end
Td1
Td2
Td3
Td4
Td5
BCLK
BCLK
BCLK
BCLK
BCLK
64
71
64
76
83
100
140
186
1135
67
79
64
71
83
94
67
75
76
106
128
858
112
135
910
106
142
864
112
149
908
106
128
858
139
166
1127
111
135
902
Data start
1-line interval
24
Multimedia ICs
BU1424K
Frame timing in Video-CD mode
(NTSC / PAL60: Interlace)
Fig.20
25
Multimedia ICs
BU1424K
Frame timing in Video-CD mode
(PAL: Interlace)
Fig.21
26
Multimedia ICs
BU1424K
Frame timing in CD-G mode
(NTSC / PAL60: Non-interlace)
Fig.22
27
Multimedia ICs
BU1424K
Frame timing in CD-G mode
(PAL: Non-interlace)
Fig.23
28
Multimedia ICs
BU1424K
(5) Adjustment of the DAC output level
current of 67.71µA per 1LSB is output. Because the
white level of Y is a digital value of 396 (decimal value),
the following results:
The voltage level of the DAC output is determined by
the DAC internal output current and the DAC output ex-
ternal resistor. The output current per 1 DAC bit is de-
termined by the external resistor of the IR pin (pin 42),
as shown below.
V (Y white) = 0.0677 × 396 = 26.81[mA]
At this point, if the DAC output external resistance is
37.5Ω, an amplitude of 1.005[VP-P] is obtained.
I (1LSB) = VVREF / RIR 1 / 16 [A]······ (equation 6-1)
(6) YUV input mode
With the BU1424K, setting the IM0 pin (pin 23) to HIGH
enables a 16-bit YUV input format to be supported. At
that time, the timing of U and V can be reversed when
data is input, using the H / L state of the Test2 pin.
The input conditions for this mode are shown below.
VREF······Voltage generated by the regulator circuit in
the BU1424K [V]
RIR·········External resistor for the IR pin 1200 [Ω]
Consequently, when VREF = 1.3V and RIR = 1200Ω, a
0
1
2
2n 2n + 1
Internal clock (BCLK)
HSY
Y1
U1
Y2
V1
Y3
U3
Y4
V3
Y5
U5
Y-Data
U.V-Data
Fig.24 YUV input timing when TEST [2] = L
0
1
2
2n 2n + 1
Internal clock (BCLK)
HSY
Y1
U1
Y2
V1
Y3
U3
Y4
V3
Y5
U5
Y-Data
U.V-Data
Fig.25 YUV input timing when TEST [2] = H
Reversal of the U and V timing using the H / L state of TEST[2] can be controlled regardless of whether CLKSW is
HIGH or LOW (the input clock is a doubled clock or not).
29
Multimedia ICs
BU1424K
When using the RGB input mode, TEST[2] should be fixed at LOW.
In the Master mode, HSYNC is output at the timing shown on the previous page. For that reason, the timing of U
and V should be determined by counting from that falling edge. In the Slave mode, the HSY, U, and V data should
be input at the timing shown on the previous page.
Table 19
TEST2
CLKSW
(53pin)
(26pin)
0
0
0
1
In a doubled clock mode, the timing of U and V is as shown in Fig. 24
In a regular clock mode, the timing of U and V is as shown in Fig. 24
1
1
0
1
In a doubled clock mode, the timing of U and V is as shown in Fig. 25
In a regular clock mode, the timing of U and V is as shown in Fig. 25
External dimensions (Units: mm)
•
12.0 ± 0.3
10.0 ± 0.2
16.4 ± 0.3
14.0 ± 0.2
48
33
48
33
32
17
49
64
49
64
32
17
1
16
1
16
0.15 ± 0.1
0.125 ± 0.1
0.5
0.2 ± 0.1
0.8
0.35 ± 0.1
0.1
0.15
QFP-A64
VQFP64
30
相关型号：
©2020 ICPDF网 联系我们和版权申明