BU2050F-TL [ROHM]
SIPO Based Peripheral Driver, 0.025A, PDSO14, ROHS COMPLIANT, SOP-14;
| 型号： | BU2050F-TL |
| 厂家： | 
ROHM |
| 描述： | SIPO Based Peripheral Driver, 0.025A, PDSO14, ROHS COMPLIANT, SOP-14 光电二极管 |
| 文件： | 总25页 (文件大小：1047K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL NOTE
Serial-in / Parallel-out Driver Series
Serial / Parallel
4-input Drivers
BU2050F, BU2092F/FV, BU2099FV, BD7851FP, BU2152FS
●Description
Serial-in-parallel-out driver incorporates a built-in shift register and a latch circuit to control a maximum of 24 LED by a 4-line
interface, linked to a microcontroller.
A single external resistor can set the output current value of the constant current up to a maximum of 50mA.
(BD7851FP only)
CMOS open drain output type products can drive the maximum current of 25mA.
●Features
1) LED can be driven directly.
2) Parallel output of a maximum of 24 bit
3) Operational on low voltage (2.7V～5.5V)
4) Cascade connection is possible (BU2050F and BU2092F/FV are not acceptable)
●Application
For AV equipment such as, audio stereo sets, videos and TV sets, PCs, control microcontroller mounted equipment.
●Product line-up
Parameter
Output current
Output line
BU2050F
BU2092F
BU2092FV BU2099FV BD7851FP BU2152FS
Unit
mA
line
25
8
25
12
25
12
25
12
50
25
24
16
Constant
current
HSOP25
CMOS
SOP14
Open drain
CMOS
-
-
Output type
Package
SOP18
SSOP-B20 SSOP-B20
SSOP-A32
Mar. 2008
●Thermal derating curve
700
700
600
500
600
500
BU2050F
BU2092F
400
300
200
400
300
200
BU2092FV
BU2099FV
100
100
0
85℃
0
75 100
175
75 100
Ambient temperature Ta [℃]
175
25
50
125 150
25
50
125 150
Ambient temperature Ta [℃]
1600
1400
1200
BD7851FP
BU2152FS
1000
800
600
400
200
85℃
0
75 100
Ambient temperature Ta [℃]
175
25
50
125 150
●Absolute maximum ratings (Ta=25℃)
Limits
Parameter
Symbol
Unit
BU2050F
-0.3～+7.0
450 *1
BU2092F
BU2092FV
Power Supply Voltage
Power dissipation 1
Power dissipation 2
Input Voltage
VDD
Pd1
Pd2
VIN
-0.3～+7.0
V
mW
mW
V
450 (SOP) *2
550 (SOP) *4
400 (SSOPB) *3
650 (SSOPB) *5
-
VSS-0.3～VDD+0.5
VSS-0.3～VDD+0.5
-40～+85
VSS-0.3～VDD+0.3
Output Voltage
Vo
VSS～+25.0
-25～+75
V
Operating Temperature
Storage Temperature
Topr
Tstg
℃
-55～+125
-55～+125
℃
*1 Reduced by 4.5mW/℃ over 25℃
*2 Reduced by 4.5mW/℃ over 25℃
*3 Reduced by 4.0mW/℃ over 25℃
*4 Reduced by 5.5mW/℃ for each increase in Ta of 1℃ over 25℃ (When mounted on a board 50mm×50mm×1.6mm Glass-epoxy PCB).
*5 Reduced by 6.5mW/℃ for each increase in Ta of 1℃ over 25℃ (When mounted on a board 70mm×70mm×1.6mm Glass-epoxy PCB).
Limits
Parameter
Symbol
Unit
BU2099FV
-0.3～+7.0
400 (SSOPB) *6
650 (SSOPB) *9
VSS-0.3～VDD+0.3
VSS～+25.0
BD7851FP
0～+7.0
1450 *7
BU2152FS
-0.3～+7.0
800 *8
Power Supply Voltage
Power dissipation 1
Power dissipation 2
Input Voltage
VDD
Pd1
Pd2
VIN
V
mW
mW
V
-
-
-0.3～VCC+0.3
0～+10
VSS-0.3～VDD+0.3
VSS-0.3～VDD+0.3
-25～+85
Output Voltage
Vo
V
Operating Temperature
Storage Temperature
Topr
Tstg
-40～+85
-30～+85
-55～+150
℃
-55～+125
-55～+125
℃
*6 Reduced by 4.5mW/℃ over 25℃
*7 Reduced by 11.6mW/℃ over 25℃
*8 Reduced by 8.0mW/℃ over 25℃
*9 Reduced by 6.5mW/℃ for each increase in Ta of 1℃ over 25℃ (When mounted on a board 70mm×70mm×1.6mm Glass-epoxy PCB).
2/24
●Electrical characteristics
BU2050F (Unless otherwise noted, Ta=25℃, VDD=4.5～5.5V)
Parameter
Power Supply Voltage
Input high-level Voltage
Input low-level Voltage
Input Hysteresis
Symbol
VDD
Min.
4.5
Typ.
Max.
5.5
Unit
V
Condition
-
VIH
0.7VDD
VSS
-
VDD
0.3VDD
-
V
VIL
-
V
VHYS
-
0.5
V
VDD-1.5
VDD-1.0
VDD-0.5
VSS
-
-
-
-
-
-
-
VDD
VDD
VDD
1.5
IOH=-25mA
Output high-level Voltage
VOHD
V
IOH=-15mA
IOH=-10mA
IOL=25mA
Output low-level Voltage
Quiescent Current
VOLD
IDD
VSS
0.8
V
IOL=15mA
VSS
0.4
IOL=10mA
-
0.1
mA
VIH=VDD, VIL=VSS
BU2092F/FV (Unless otherwise noted, Ta=25℃, VSS=0V, VDD=5.0V/3.0V)
Parameter
Power Supply Voltage
Input high-level Voltage
Input low-level Voltage
Symbol
VDD
Min.
2.7
Typ.
Max.
5.5
Unit
V
Condition
-
-
-
VIH
3.5 / 2.5
-
-
V
VDD=5V/3V
VDD=5V/3V
VIL
1.5 / 0.4
V
V
DD=5V/3V,
Output low-level Voltage
VOL
-
-
2.0 / 1.0
V
IOL=20mA/5mA
VO=25.0V
Output high-level disable Current
Output low-level disable Current
IOZH
IOZL
-
-
-
-
10.0
-5.0
μA
μA
VO=0V
VIN=VSS or VDD
(VDD=5V/3V)
OUTPUT:OPEN
Quiescent Current
IDD
-
-
5.0 / 3.0
μA
BU2099FV (Unless otherwise noted, Ta=25℃, VSS=0V, VDD=5.0V/3.0V)
Parameter
Power Supply Voltage
Input high-level Voltage
Input low-level Voltage
Symbol
VDD
Min.
2.7
Typ.
Max.
5.5
Unit
V
Condition
-
-
-
VIH
3.5 / 2.1
-
-
V
VDD=5V/3V
VDD=5V/3V
VDD=5V/3V,
VIL
1.5 / 0.9
V
VDD-0.5
/ VDD-0.3
Output high-level Voltage (SO)
Output low-level Voltage 1 (Qx)
Output low-level Voltage 2 (SO)
VOH
-
-
-
V
V
I
OH=-400μA/-100μA
VDD=5V/3V,
-
1.0
IOL1=10mA/5mA
VDD=5V, IOL1=15mA
VDD=5V, IOL1=20mA
VOL1
-
-
-
-
1.5
2.0
V
DD=5V/3V,
VOL2
IOZH
IOZL
-
-
-
-
-
-
0.4 / 0.3
10
V
IOL2=1.5mA/0.5mA
Output high-level disable Current
(Qx)
μA
μA
VO=25.0V
Output low-level disable Current
(Qx)
-5.0
VO=0V
IPULLDOWN (OE)
IPD
-
-
-
150 / 60
2.4
μA
OE= VDD, VDD=5V/3V
Low Voltage Reset
VCLR
1.1
V
VIN=VSS or VDD
,
Quiescent Current
IDD
-
-
200
μA
VDD=5V
OUTPUT:OPEN
3/24
●Electrical characteristics
BD7851FP (Unless otherwise noted, Ta=25℃, VCC=5.0V)
Parameter
Power Supply Voltage
Input high-level Voltage
Input low-level Voltage
Output high-level Voltage
Output low-level Voltage
Symbol
VDD
VIH
Min.
Typ.
Max.
Unit
V
Condition
4.5
-
-
-
-
-
5.5
0.8×VCC
-
V
VIL
-
0.2×VCC
V
VOH
VOL
VCC-0.5
-
-
V
IOH=-1mA
0.5
V
IOL=1mA
R=13kΩ
-
-
-
0.7
1.8
4.0
1.0
3.0
6.5
mA
mA
mA
OUT1～OUT16:OFF
R=1.3kΩ
OUT1～OUT16:OFF
R=13kΩ
Quiescent Current
ICC
OUT1～OUT16:ON
R=1.3kΩ
-
30
55
40
62
mA
mA
mA
OUT1～OUT16:ON
VOUT=2.0V, R=1.3kΩ
Reference Current Output Current
(including the equation between
each bit)
Iolc1
Iolc2
48
5.0
5.9
6.8
VOUT=2.0V, R=13kΩ
Equation between each bit of
Reference Current Output Current
Change rate of reference current
output current for output voltage
Output Leak Current
VOUTn=2.0V, R=1.3kΩ
(1bit : ON)
Δiolc
-
±1
±6
%
VOUT=2.0～3.0V,
R=1.3kΩ
IΔVCC
-
-
±1
±6
%/V
IOH
0.01
0.8
μA
VOUT=10V
BU2152FS (Unless otherwise noted, Ta=25℃, VDD=2.7～5.5V)
Parameter
Power Supply Voltage
Input high-level Voltage
Input low-level Voltage
Symbol
VDD
Min.
Typ.
Max.
5.5
-
Unit
V
Condition
2.7
-
-
-
-
-
-
-
-
-
-
-
-
VIH
2.0
V
VDD=5V
VIL
-
0.6
-
V
VDD=5V
VDD-1.5
IOH=-25mA
IOH=-15mA
IOH=-10mA
IOL=25mA
IOL=15mA
IOL=10mA
VIL=VSS, VIH=VDD
Output high-level Voltage
Output low-level Voltage
VOH
VDD-1.0
-
V
V
VDD-0.5
-
-
-
-
-
-
-
1.5
1.0
0.8
5
VOL
Quiescent Current
IDDST
IIH
μA
μA
μA
Input high-level Current
Input low-level Current
1
IIL
1
4/24
●Block diagram
BU2050F
STB
CLR
Controller
L
a
t
8bit
Write
Shift
c
h
Buffer
P1～P8
CLOCK
DATA
Register
BU2092F/FV
LCK
L
a
t
c
h
12bit
Write
Controller
CLOCK
DATA
Shift
Buffer
Q0～Q11
Register
OE
BU2099FV
LCK
LPF
L
a
t
c
h
12bit
Write
Controller
CLOCK
DATA
Shift
Buffer
Q0～Q11
Register
OE
BD7851FP
S_IN
L
a
t
c
h
16bit
Write
Shift
Register
Buffer
OUT1～OUT16
CLOCK
SOUT
LATCH
ENABLE
R_Iref
Current Adjustment
BU2152FS
STB
CLB
Controller
L
a
t
24bit
Write
Shift
c
h
Buffer
P1～P24
CLOCK
DATA
Register
SO
5/24
●Operating description
(1) Data clear
When the reset terminal (CLR, CLB) is set to “L”, the content of all latch circuits are set to “H”, and all parallel outputs are
initialised.
(For model with reset terminal only)
(2) Data transfer
Serial data is sequentially input to the shift register during the rise of the clock time (strobe signal is not active). When
the strobe signal is active, the content of the shift register are transferred to the latch circuit.
(3) Cascade connection
Serial input data is output from the serial output through the shift register, regardless of the strobe signal.
(except for BU2050F, BU2092F/FV)
●Application circuit
P1 P2
Pn-2 Pn-1 Pn
C1
(*)
VDD
VDD
Serial data input
Clock input
VSS
MPU
Strobe input
Latch input
Serial data output
VSS
P1 P2
Pn-2 Pn-1 Pn
VSS
VDD
Serial data input
Clock input
Strobe input
Latch input
Serial data output
Fig. 1
(*C1 must be placed as close to the terminal as possible.)
●Interfaces
BU2050F
BU2050F
BU2092F/FV
BU2092F/FV
DATA, CLOCK, STB, CLR
P1～P8
DATA, CLOCK, LCK, OE
Q0～Q11
VDD
VDD
VDD
VDD
OUT
INPUT
IN
OUTPUT
GND(VSS)
GND(VSS)
GND(VSS)
GND(VSS)
GND(VSS)
GND(VSS)
GND(VSS)
BU2099FV
DATA, CLOCK, LCK, OE
BU2099FV
Q0～Q11
BU2099FV
BU2152FS
SO
CLOCK, DATA, STB, CLB
VDD
VDD
VDD
VDD
VDD
VDD
VDD
OUT
IN
OUT
GND(VSS)
(only OE pin)
GND(VSS)
GND(VSS)
GND(VSS)
GND(VSS)
GND(VSS)
GND(VSS)
GND(VSS)
BU2152FS
BU2152FS
P1～P28
SO
VDD
VDD
VDD
VDD
VDD
GND(VSS)
GND(VSS) GND(VSS)
VSS
VSS
VSS
6/24
【BU2050F】
●Pin descriptions
Pin No.
Pin Name
P3
Function
1
2
3
4
5
6
7
8
9
P4
Parallel Data Output
GND
P5
VSS
P6
P7
Parallel Data Output
P8
DATA
CLK
Serial Data Input
Clock Signal Input
Strobe Signal Input
10
11
STB
CLR
In case of “L”, the data of shift register outputs.
In case of “H”, all parallel outputs and data of latch circuit do not change.
Reset Signal Input
In case of “L”, the data of latch circuit reset, and all parallel output (P1～P8) can be L.
Normally CLR=H
12
13
14
P1
P2
Parallel Data output
Power Supply
VDD
●Timing chart
CLK
DATA8
DATA7
DATA6
DATA2
DATA1
DATA
CLR
STB
Pn
Previous DATA
DATA
“L”
Fig. 2
1. After the power is turned on and the voltage is stabilized, STB should be activated, after clocking 8 data bits into
the DATA pin.
2. Pn parallel output data of the shift register is set after the 8th clock by the STB.
3. Since the STB is level latch, data is retained in the “L” section and renewed in the “H” section of the STB.
［Function explanation］
・
A latch circuit has the reset function, which is common in all bits. In case of CLR terminal is “L”, the latch
circuit is reset non-synchronously without the other input condition, and all parallel output can be “L”.
A serial data inputted from DATA terminal is read in shift register with synchronized rising of clock.
In case of STB is “L” (CLR is ”H”), transmit the data which read in the shift register to latch circuit, and
outputs from the parallel data output terminal (P1～P8).
・
In case of STB is “H”, all parallel outputs and the data of latch do not change.
7/24
●Switching characteristics (Unless otherwise specified, VDD=4.5～5.5V, Ta=25℃)
Limit
Parameter
Symbol
Unit
Condition
Min.
20
Typ.
-
Max.
-
Set up time (DATA-CLK)
Hold time (DATA-CLK)
tSD
tHD
ns
ns
-
20
30
30
-
-
-
-
-
-
-
-
-
-
-
tSSTB
tHSTB
tPDPCK
tPDPSTB
tPDPCLR
fMAX
ns
-
Set up time (STB − CLK)
Hold time (STB − CLK)
-
ns
-
100
80
80
-
ns
P1～P8 terminal load 20pF or less
P1～P8 terminal load 20pF or less
P1～P8 terminal load 20pF or less
-
Propagation (CLR − P1～P8)
Propagation (STB − P1～P8)
Propagation (CLR − P1～P8)
Maximum clock frequency
-
ns
-
ns
5
MHz
●Switching Time Test Waveform
fMAX
1
2
8
9
10
11
12
CLK
tSD
DATA
STB
tHD
tHSTB
tSSTB
CLR
P8
P1
tPDPSTB
tPDPCLR
tPDPCK
Fig. 3
8/24
【BU2092F/FV】
●Pin descriptions
Pin No.
Pin Name
I/O
Function
1
2
3
4
VSS
DATA
CLOCK
LCK
-
I
I
I
GND
Serial Data Input
Shift clock of DATA (Rising Edge Trigger)
Latch clock of DATA (Rising Edge Trigger)
Parallel Data Output (Nch Open Drain FET)
5～11,
Latch Data
Output FET
L
H
Q0～Q11
O
14～18
ON
OFF
12, 13
17
N.C.
OE
-
I
Non connected
Output Enable (“H” level : output FET is OFF)
Power Supply
18
VDD
-
●Timing chart
CLOCK
DATA11
DATA10
DATA9
DATA1
DATA0
DATA
LCK
OE
Qx
“H”
Previous DATA
DATA11～0
Note) Diagram shows a status where a pull-up resistor is connected to output.
Fig. 4
1. After the power is turned on and the voltage is stabilized, LCK should be activated, after clocking 12 data bits into
the DATA terminal.
2. Qx parallel output data of the shift register is set after the 12th clock by the LCK.
3. Since the LCK is a label latch, data is retained in the “L” section and renewed in the “H” section of the LCK.
4. Data retained in the internal latch circuit is output when the OE is in the “L” section.
［Truth Table］
Input
Function
CLOCK
×
DATA
×
LCK
×
OE
H
Output (Q0～Q11) Disable
×
×
×
L
Output (Q0～Q11) Enable
Store “L” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
Store “H” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
The data of shift register has no change.
L
×
×
×
H
×
×
×
×
×
×
×
×
×
×
The data of shift register is transferred to the storage register.
The data of storage register has no change.
9/24
●Switching characteristics (Unless otherwise specified, VDD=5V, VSS=0V, Ta=25℃)
Limit
Parameter
Symbol
tw
Unit
Condition
Min.
1000
500
1000
500
400
200
400
200
400
200
-
Typ.
-
Max.
VDD(V)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
Minimum Clock Pulse Width
-
-
-
-
-
-
-
Minimum Latch Pulse Width
(LCK)
tw
(LCK)
-
-
Setup Time
ts
tsu
tH
(LCK→CLOCK)
Setup Time
-
-
(DATA→CLOCK)
Hold Time
-
-
(CLOCK→DATA)
-
90
55
115
50
70
45
80
35
tPLZ
(LCK)
tPZL
RL=5kΩ
CL=10pF
RL=5kΩ
CL=10pF
RL=5kΩ
CL=10pF
RL=5kΩ
CL=10pF
-
Propagation
(LCK→OUTPUT QX)
-
(LCK)
-
-
tPLZ
-
Propagation
-
( OE →OUTPUT QX)
tPZL
-
●Switching Time Test Circuit
±25V
VDD
Pulse
Gen.
RL
Q0
CL
CLOCK
Pulse
Gen.
LCK
GND (Vss)
±25V
Pulse
Gen.
DATA
OE
RL
Q11
CL
Pulse
Gen.
GND (Vss)
GND (Vss)
Fig. 5
10/24
【BU2092F/FV】
●Switching Time Test Waveforms
tW
tW
VDD
90%
90%
90%
90%
CLOCK
10%
10%
10%
GND (VSS)
tSU
tH
VDD
90%
90%
tS
DATA
GND (VSS)
tW(CLK)
90%
VDD
90%
50%
50%
LCK
10%
GND (VSS)
tPLZ(LCK)
tPZL(LCK)
VDD
50%
50%
OE
Qx
GND (VSS)
tPZL
tPLZ
VDD
50%
50%
10%
10%
GND (VSS)
Fig. 6
11/24
【BU2099FV】
●Pin descriptions
Pin No.
Pin Name
I/O
Function
1
2
3
4
5
VSS
N.C.
-
-
I
I
I
GND
Non connected
DATA
CLOCK
LCK
Serial Data Input
Shift clock of Shift register (Rising Edge Trigger)
Latch clock of Storage register (Rising Edge Trigger)
Parallel Data Output (Nch Open Drain FET)
Q0～Q11
Latch Data
Output FET
L
H
6～17
O
(Qx)
ON
OFF
18
19
20
SO
OE
VDD
O
I
Serial Data Output
Output Enable Control Input ＊OE pin is pulled down to Vss.
-
Power Supply
●Timing chart
CLOCK
DATA12
DATA11
DATA10
DATA2
DATA1
DATA
LCK
OE
Qx
Previous DATA
DATA
“H”
DATA11
Previous
DATA 11
Previous
DATA 11
DATA12
SO
Fig. 7
1. After the power is turned on and the voltage is stabilized, LCK should be activates, after clocking 12 data bits into
the DATA terminal.
2. Qx parallel output data of the shift register is set after the 12th clock by the LCK.
3. Since the LCK is a label latch, data is retained in the “L” section and renewed in the “H” section of the LCK.
4. Data retained in the internal latch circuit is output when the OE is in the “L” section.
5. The final stage data of the shift register is output to the SO by synchronizing with the rise time of the CLOCK.
［Truth Table］
Input
Function
CLOCK
×
DATA
×
LCK
×
OE
H
All the output data output “H” with pull-up.
×
×
×
L
The Q0～Q11 output can be enable and output the data of storage register.
Store “L” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
Store “H” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
The data of shift register has no change.
L
×
×
×
×
H
×
×
×
SO outputs the final stage data of shift register with synchronized falling edge
of CLOCK, not controlled by OE.
×
×
×
×
×
×
The data of shift register is transferred to the storage register.
The data of storage register has no change.
＊The Q0～Q11 output have a Nch open drain Tr. The Tr is ON when data from shift register is “L”, and Tr is OFF when data is “H”.
12/24
【BU2099FV】
●Switching characteristics (Unless otherwise specified, VDD=5V, VSS=0V, Ta=25℃)
Limit
Parameter
Symbol
tW
Unit
Condition
Min.
Typ.
Max.
VDD(V)
1000
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
-
Minimum Clock Pulse Width
(CLOCK)
-
-
-
-
-
500
-
-
-
1000
-
Minimum Latch Pulse Width
(LCK)
tW
(LCK)
500
-
-
400
-
-
Setup Time
tS
tsu
tH
(LCK→CLOCK)
Setup Time
200
-
-
400
-
-
(DATA→CLOCK)
Hole Time
200
-
-
400
-
-
(CLOCK→DATA)
Propagation
200
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
500
-
-
tPLH
tPHL
(SO)
-
250
360
170
260
175
115
85
175
65
30
20
-
-
-
-
-
-
-
-
tPLZ
RL=5kΩ
(LCK)
tPZL
CL=10pF
RL=5kΩ
CL=10pF
RL=5kΩ
CL=10pF
RL=5kΩ
CL=10pF
Propagation
(LCK→QX) *
(LCK)
tPLZ
tPZL
tI
Propagation
( QE →QX) *
Noise Pulse Suppression
Time (LCK) *
-
-
*Reference value
●Input Voltage Test Circuit
RL =10kΩ
GND
(Vss)
P.G.
VIH
VIL
GND
Fig. 8
●Switching Time Test Circuit
+25V
VDD
RL =5kΩ
CL =10pF
GND
(Vss)
GND
(Vss)
+25V
P.G.
RL =5kΩ
CL =10pF
GND
(Vss)
Fig. 9
13/24
【BU2099FV】
●Output Voltage Test Circuit
VDD
±25V
12
SW4
2
1
SW3
1
SW2
3
1
2
SW1
GND
(Vss)
IOL1
IOH
IOL2
P.G.
GND
(Vss)
GND
(Vss)
GND
(Vss)
GND
(Vss)
GND
(Vss)
GND
(Vss)
Test condition
VOL1
VOL2
VOH
：Set all data “L”. SW1=”ON”, SW2=”3”, SW3=”1”～”12”.
：Set output data “L” to SO and SW4 is positioned to “2”, then voltage is measured at IOL2.
：Set output data “H” to SO and SW4 is positioned to “1”, then voltage is measured at IOH.
Fig. 10
●Switching Time Test Waveforms
tW
tW
VDD
90%
90%
50%
90%
90%
50%
50%
CLOCK
10%
10%
10%
GND (VSS
)
)
tH
tSU
VDD
90%
90%
tS
DATA
GND (VSS
tW (CLK)
90%
VDD
90%
50%
50%
LCK
OE
10%
GND (VSS
VDD
)
tS
2
tPLZ
tPLZ(LCK)
50%
50%
GND (VSS
)
tPZL
tPZL(LCK)
VEXT
50%
50%
Qx
10%
10%
GND (VSS
)
tPLH
tPHL
VDD
50%
50%
SO
GND (VSS
)
Fig. 11
14/24
【BD7851FP】
●Pin descriptions
Pin No.
Pin Name Function
1
2
3
4
GND
R_Iref
Ground
Reference Current Output Current setting
Latch Signal Input
LATCH
S_IN
Serial Data Input
OUT16
～OUT6
P_GND
OUT5
5～15
16
Reference Current Output
Ground for Driver
17～21
Reference Current Output
～OUT1
SOUT
22
23
24
25
Serial Data Output
Clock Input
ENABLE
CLOCK
ENABLE
VCC
VCC
●Timing chart
CLOCK
DATA16
DATA15
DATA14
DATA2
DATA1
S_IN
LATCH
ENABLE
Previous DATA
DATA
OUTn
SOUT
Previous
DATA15
Previous
DATA2
Previous
DATA14
Previous
DATA1
DATA16
DATA15
DATA14
Fig. 12
1. After the power is turned on and the voltage is stabilized, LATCH should be activated, after clocking 16 data bits
into the S_IN terminal.
2. OUTn parallel output data of the shift register is set after the 16th clock by the LATCH.
3. The final stage data of the shift register is outputted to the SOUT by synchronizing with the rise time of the
CLOCK.
4. Since the LATCH is a label latch, data is retained in the “L” section and renewed in the “H” section of the LATCH.
5. Data retained in the internal latch circuit is outputted when the ENABLE is in the “L” section. When the ENABLE
is in the “H” section, data is fixed in the “H” section.
15/24
【BD7851FP】
●Timing characteristics (Unless otherwise specified, VCC=5V, Ta=25℃)
Limit
Parameter
Symbol
Unit
Condition
Min.
-
Typ.
-
Max.
Frequency CLOCK
Pulse Width CLOCK
Pulse Width LATCH
Pulse Width ENABLE
Rise Time / Fall Time
fclk
twh
10
MHz
ns
20
40
30
-
50
50
-
-
CLOCK
LATCH
twh
-
ns
tw
-
ns
ENABLE
tr / tf
30
50
50
50
50
300
-
100
ns
CLOCK
30
30
30
30
-
-
-
S_IN-CLOCK
LATCH-CLOCK
S_IN-CLOCK
LATCH-CLOCK
OUTn
Setup Time
Hold Time
Rise Time
Fall Time
tSU
th
ns
ns
ns
ns
-
-
-
tr
-
50
-
SOUT
-
300
-
OUTn
tf
-
50
SOUT
CLK-SOUT, LATCH
ENABLE-OUTn
CLK-SOUT, LATCH
ENABLE-OUTn
tpLH
tpHL
-
-
400
300
650
400
Propagation
ns
●Reference Current of Output Current
250
[Condition]
Vcc=5.0V, Vo=5.0V, Ta=25℃
200
150
100
50
The reference current of output current is determined by the
external resistor.
(between 2pin and GND )
0
0.1
1
10
100
R_Iref [k ]
Ω
＊This is a data for the standard sample, not guaranteed the characteristic.
Fig. 13
●R_Iref-VOUT
1.6
[Condition]
Vcc=5.0V, Ta=27℃, all bit : ON
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1
10
100
R_Iref [k ]
Ω
＊Notes the increase of consumption current Icc, in case sets the voltage of VOUT lower. See the graph above.
Fig. 14
16/24
【BD7851FP】
●Test Circuit 1
Vcc
1
2
3
4
5
6
GND
Vcc 25
ENABLE 24
CLOCK 23
R
ENABLE
CLOCK
SOUT
R_Iref
LATCH
S_IN
LATCH
S_IN
SOUT
OUT1
22
21
OUT16
OUT15
VE
OUT2 20
7
8
9
OUT14
OUT13
OUT12
OUT3
OUT4
19
18
17
16
10 OUT11
11 OUT10
12 OUT9
13 OUT8
OUT5
P_GND
P_GND
OUT6 15
OUT7 14
Fig. 15
●Test Circuit 2
Vcc
GND
25
Vcc
1
2
3
4
5
6
R
ENABLE
CLOCK
SOUT
R_Iref
LATCH
S_IN
ENABLE 24
CLOCK 23
LATCH
S_IN
SOUT
OUT1
22
21
OUT16
OUT15
VE
OUT2 20
7
8
9
OUT14
OUT13
OUT12
OUT3
19
OUT4 18
17
16
10 OUT11
11 OUT10
12 OUT9
OUT5
P_GND
P_GND
OUT6 15
OUT7 14
13
OUT8
＊R=51Ω (note : R_Iref=1.3kΩ) , C=15pF
Fig. 16
17/24
【BD7851FP】
●Switching Time Test Waveforms
tWh
tf
tr
0.8×VCC 0.8×VCC
0.8×VCC
CLOCK
0.2×VCC
0.2×VCC
tSU
th
0.8×VCC
0.8×VCC
S_IN
twh
0.8×VCC
LATCH
0.2×VCC
tSU
tpHL
tpHL
th
90%
90%
10%
90%
10%
OUTn
10%
tf
tr
t
pHL・tpLH
0.8×VCC
0.2×VCC
ENABLE
tw
0.8×VCC
0.2×VCC
SOUT
t
pHL・tpLH
tf・tr
Fig. 17
18/24
【BU2152FS】
●Pin descriptions
Pin
Pin Name
I/O
Function
No.
1
VSS
CLK
-
I
Ground
2
Clock Input
3
VSS
-
Ground
4
DATA
P1～P24
SO
I
Serial Data Input
Parallel Data Output
Cascade Output
Strobe Signal Input active “L”
Clear Signal Input active “L”
Power Supply
5～28
29
30
31
32
O
O
I
STB
CLB
I
VDD
-
●Timing chart
CLK
DATA24
DATA23
DATA22
DATA2
DATA1
DATA
STB
Previous DATA
DATA
Pn
Previous
DATA24
Previous
DATA23
Previous
DATA2
Previous
DATA1
DATA24
DATA23
DATA22
SO
Fig. 18
1. After the power is turned on and the voltage is stabilized, STB should be activated, after clocking 24 data bits into
the DATA terminal.
2. Pn parallel output data of the shift register is set after the 24th clock by the LCK.
3. Since the STB is a label latch, data is retained in the “H” section and renewed in the “L” section of the STB.
4. The final stage data of the shift register is outputted to the SO by synchronizing with the rise time of the CLOCK.
［Truth Table］
Input
Function
CLK
STB
CLB
L
All the data of the latch circuit are set to “H” (data of shift register does not
change), all the parallel outputs are “H”.
×
×
Serial data of DATA pin are latched to the shift register.
At this time, the data of the latch circuit does not change.
The data of the shift register are transferred to the latch circuit, and the data of
the latch circuit are outputted from the parallel output pin.
The data of the shift register shifts 1bit, and the data of the latch circuit and
parallel output also change.
H
L
H
H
L
H
19/24
【BU2152FS】
●Switching characteristics (Unless otherwise specified, VDD=2.7～5.5V, VSS=0V, Ta=25℃)
Limit
Parameter
Symbol
Unit
Condition
Min.
5
Typ.
Max.
Maximum Clock Frequency
Setup Time 1
fMAX
tSU1
tHD1
tSU2
tHD2
tSU3
tHD3
tSU4
tHD4
tPD1
tPD2
tPD3.
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
30
30
30
30
30
30
-
-
DATA-CLK
Hold Time 1
-
CLK-DATA
STB-CLK
Setup Time 2
-
Hold Time 2
-
-
CLK-STB
Setup Time 3
CLB-CLK
Hold Time 3
-
CLK-CLB
Setup Time 4
-
STB-CLB
Hold Time 4
-
CLB-STB
Output Delay Time 1*
Output Delay Time 2*
Output Delay Time 3*
*50pF of load is attached.
100
80
80
CLK-P1～P24
STB-P1～P24
CLB-P1～P24
-
-
20/24
●Switching characteristic conditions
○Setup/Hold Time (DATA-CLOCK, STB-CLOCK, CLB-CLOCK)
tr
tr
90%
90%
50%
50%
CLOCK
DATA
10%
tSU1
10%
tHD1
50%
50%
STB
CLB
tSU2
tHD2
50%
50%
tSU3
tHD3
○Setup/Hold Time (STB-CLB)
50%
CLB
STB
tSU4
tHD4
Fig. 19 Switching characteristic conditions 1
○Output Delay Time (CLOCK-P1～P24)
CLOCK
50%
tPD1
P1～P24
○Output Delay Time (STB-P1～P24)
STB
50%
tPD2
P1～P24
○ Output Delay Time (CLB-P1～P24)
CLB
50%
tPD3
50%
Fig. 20 Switching characteristic conditions 2
21/24
●Operation Notes
1. Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can
break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any
over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as
fuses.
2. Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply
lines. An external direction diode can be added.
3. Power supply lines
Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line,
separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals to
ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the circuit,
not that capacitance characteristic values are reduced at low temperatures.
4. GND voltage
The potential of GND pin must be minimum potential in all operating conditions.
5. Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
6. Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.
7. Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.
8. Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure.
Use similar precaution when transporting or storing the IC.
9. Ground Wiring Pattern
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing
a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused
by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern
of any external components, either.
10. Unused input terminals
Connect all unused input terminals to VDD or VSS in order to prevent excessive current or oscillation.
Insertion of a resistor (100kΩ approx.) is also recommended.
22/24
●Order Type Selections
―
B
U
2
0
5
0
F
E
2
Package type
E1 : Emboss tape reel
Pin 1 on draw-out side
Product number
ROHM model name
F : SOP14, SOP18
FV : SSOP-B20
FP : HSOP25
BU
BD
2050
2092
2099
7851
2152
E2 :
Emboss tape reel
Pin 1 opposite draw-out side
TL :
FS : SSOP-A32
Emboss tape reel
Pin 1 on draw-out side
TR : Emboss tape reel
Pin 1 opposite draw-out side
●External Dimensions
<Dimension>
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
2500pcs
E2
8.7 0.2
Direction
of feed
8
14
1
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
7
0.15 0.1
0.1
1.27
0.4 0.1
1Pin
※When you order , please order in times the amount of package quantity.
Direction of feed
Reel
(Unit:mm)
<Dimension>
<Tape and Reel information>
Tape
Embossed carrier tape
2000pcs
Quantity
11.2 0.2
E2
Direction
of feed
18
10
9
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
1
0.15 0.1
0.1
1.27
0.4 0.1
1Pin
※When you order , please order in times the amount of package quantity.
Direction of feed
Reel
(Unit:mm)
SSOP-B20
<Dimension>
<Tape and Reel information>
Embossed carrier tape
Tape
Quantity
2500pcs
Direction
of feed
E2
6.5 0.2
20
11
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
1
10
0.15 0.1
0.1
0.65
0.22 0.1
Direction of feed
※When you order , please order in times the amount of package quantity.
1pin
Reel
（Unit:mm)
23/24
HSOP25
<Dimension>
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
2000pcs
13.6 0.2
2.75 0.1
E2
Direction
of feed
25
1
14
13
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
0.25 0.1
1.95 0.1
0.8
0.1
0.36 0.1
Direction of feed
1pin
Reel
(Unit:mm)
※When you order , please order in times the amount of package quantity.
SSOP-A32
<Dimension>
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
2000pcs
13.6 0.2
Direction
of feed
E2
32
17
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
1
16
0.15 0.1
0.1
0.8
0.36 0.1
Direction of feed
1pin
Reel
(Unit:mm)
※When you order , please order in times the amount of package quantity.
Catalog No.08T004A '08.3 ROHM © 1000 NZ
Appendix
Notes
No technical content pages of this document may be reproduced in any form or transmitted by any
means without prior permission of ROHM CO.,LTD.
The contents described herein are subject to change without notice. The specifications for the
product described in this document are for reference only. Upon actual use, therefore, please request
that specifications to be separately delivered.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard
use and operation. Please pay careful attention to the peripheral conditions when designing circuits
and deciding upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams information, described herein
are intended only as illustrations of such devices and not as the specifications for such devices. ROHM
CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any
third party's intellectual property rights or other proprietary rights, and further, assumes no liability of
whatsoever nature in the event of any such infringement, or arising from or connected with or related
to the use of such devices.
Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or
otherwise dispose of the same, no express or implied right or license to practice or commercially
exploit any intellectual property rights or other proprietary rights owned or controlled by
ROHM CO., LTD. is granted to any such buyer.
Products listed in this document are no antiradiation design.
The products listed in this document are designed to be used with ordinary electronic equipment or devices
(such as audio visual equipment, office-automation equipment, communications devices, electrical
appliances and electronic toys).
Should you intend to use these products with equipment or devices which require an extremely high level
of reliability and the malfunction of which would directly endanger human life (such as medical
instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers
and other safety devices), please be sure to consult with our sales representative in advance.
It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance
of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow
for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in
order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM
cannot be held responsible for any damages arising from the use of the products under conditions out of the
range of the specifications or due to non-compliance with the NOTES specified in this catalog.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact your nearest sales office.
THE AMERICAS / EUROPE / ASIA / JAPAN
ROHM Customer Support System
Contact us : webmaster@ rohm.co.jp
www.rohm.com
TEL : +81-75-311-2121
FAX : +81-75-315-0172
Copyright © 2008 ROHM CO.,LTD.
21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan
Appendix1-Rev2.0
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