BU2090F-E1 [ROHM]
SIPO Based Peripheral Driver, 0.02A, PDSO16, SOP-16;
| 型号： | BU2090F-E1 |
| 厂家： | 
ROHM |
| 描述： | SIPO Based Peripheral Driver, 0.02A, PDSO16, SOP-16 驱动 光电二极管 接口集成电路 |
| 文件： | 总16页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL NOTE
Serial-in / Parallel-out Driver Series
Serial / Parallel
2-input Driver
BU2098F, BU2090F/FS
●Description
Serial-in-parallel-out driver is a open drain output driver. It incorporates a built-in shift register and a latch circuit to turn on a
maximum of 12 LED by a 2-line interface, linked to a microcontroller.
A open drain output provides maximum of 25mA current.
●Features
1) LED can be driven directly. (Output current 25mA)
2) 8/12 Bit parallel output
3) This product can be operated on low voltage.
4) Compatible with I2C BUS. (BU2098)
* I2C BUS is a registered trademark of Phillips.
●Use
For AV equipment such as, audio stereo sets, videos and TV sets, PCs, control microcontroller mounted equipment.
ver.C Oct.2007
●Line up
Parameter
Output current
Output line
Package
BU2098F
BU2090F
SOP16
BU2090FS
SSOP-A16
Unit
mA
lines
－
25
8
25
12
SOP16
●Thermal derating curve
700
700
600
500
600
500
BU2090FS
400
300
200
400
300
200
BU2098F
BU2090F
100
0
100
0
85℃
75 100
Ambient temperature Ta [℃]
175
75 100
Ambient temperature Ta [℃]
175
25 50
125 150
25 50
125 150
●Electrical characteristics
BU2098F (unless otherwise noted, VDD=5V, Vss=0V, Ta=25℃)
Parameter
Symbol
VIH
Min.
Typ.
Max.
-
Unit
V
Condition
Input High-level voltage
Input Low-level voltage
Output Low-level voltage
Input Low-level current
Input High-level current
0.7ＸVDD
-
-
-
VIL
-
-
-
-
0.3ＸVDD
0.4
V
VOL
IIL
V
IOUT=10mA
VIN=0
2.0
μA
μA
IIH
-
-
-
-2.0
VIN=VDD
Output=High impedance
VOUT=VDD
Output leakage current
Static dissipation current
IOZ
IDD
-
-
±5.0
μA
μA
2.0
BU2090F/FS (unless otherwise noted,
VDD=5V/3V, VSS=0V, Ta=25℃)
Parameter
Symbol
Min.
Typ.
Max.
-
Unit
V
Condition
Input High-level voltage
Input Low-level voltage
Output Low-level voltage
“H” output disable current
“L” output disable current
Static dissipation current
VIH
VIL
3.5/2.5*
-
-
-
-
-
-
-
-
-
1.5/0.4*
2.0/1.0*
10
V
VOL
IOZH
IOZL
IDD
V
IOL=20mA
VO=25V
VO=0V
μA
μA
μA
-5.0
-
5.0/3.0*
(*the value at 5V /3V)
2/15
●Operating conditions (Ta=25℃, VSS=0V)
Limits
Parameter
Symbol
Unit
BU2098F
BU2090F/FS
+2.7～5.5
Power Supply Voltage
Output Voltage
VDD
Vo
V
V
0～+15
0～+25
●Absolute maximum ratings
BU2098F
Limits
Parameter
Symbol
Unit
BU2098F
-0.5～+7.0
Power supply voltage
Power dissipation
VDD
Pd
V
mW
℃
℃
V
300
*
Operating temperature range
Storage temperature range
Output voltage
Topr
Tstg
Vo
-40～+85
-55～+125
VSS～+18.0
-0.5～VDD+0.5
Input voltage
VIN
V
Allowable loss of single unit
* Reduced by 3mW/℃ over 25℃. (BU2098F)
BU2090F/FS
Parameter
Limits
Symbol
Unit
BU2090F
BU2090FS
Power supply voltage
Power dissipation 1
Power dissipation 2
Operating temperature range
Storage temperature range
Output voltage
VDD
Pd1
Pd2
Topr
Tstg
Vo
-0.3～+7.0
V
mW
mW
℃
300 *1
500 *3
500 *2
650 *4
-40～+85
-55～+125
℃
VSS-0.3～+25
VSS-0.3～VDD+0.3
V
Input voltage
VIN
V
Allowable loss of single unit
*1 Reduced by 3mW/℃ over 25℃.
*2 Reduced by 5mW/℃ over 25℃.
*3 Reduced by 5.0mW for each increase in Ta of 1℃ over 25℃.(When mounted on a board 70mm×70mm×1.6mm Glass-epoxy PCB)
*4 Reduced by 6.5mW for each increase in Ta of 1℃ over 25℃.(When mounted on a board 70mm×70mm×1.6mm Glass-epoxy PCB)
3/15
●Pin descriptions
BU2098F
PIN No.
Pin Name
A0
I/O
Function
Address input, internally pull-up
1
2
I
I
I
A1
3
A2
4
Q0
5
Q1
O
-
Open drain output
GND
6
Q2
7
Q3
8
VSS
Q4
9
10
11
12
13
14
15
16
Q5
O
Open drain output
Q6
Q7
N.C.
SCL
SDA
VDD
-
I
Non connected
Serial clock input
Serial data input/output
Power supply
I/O
-
BU2090F/FS
PIN No.
Pin Name
VSS
I/O
Function
1
2
-
I
GND
DATA
Serial data input
Data shift clock input
(rising edge trigger)
3
CLOCK
I
The shift data is transferred to the output when the input data logic
level is high during the falling transition of the clock pulse.
4
5
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
VDD
6
7
Parallel data output (Nch Open Drain FET)
8
9
O
Latch data
L
H
10
11
12
13
14
15
16
Output FET
ON
OFF
-
Power supply
4/15
●Block diagram
BU2098F
Power-On Reset
SDA
SCL
L
a
t
c
h
Write
I2C Bus
Buffer
8bit
A0
A1
A2
Q0～Q7
Controller
Shift
Register
BU2090F/FS
L
a
t
c
h
Write
CLOCK
DATA
12bit
Buffer
Controller
Q0～Q11
Shift
Register
5/15
●Interfaces
BU2090F/FS
BU2090F/FS
DATA, CLOCK
Q0～Q11
VDD
VDD
OUT
IN
GND (VSS
)
GND (VSS
)
GND (VSS
)
BU2098F
BU2098F
Q0～Q7
A0～A2
VDD
VDD
VDD
OUT
IN
GND (VSS
)
GND (VSS
)
GND (VSS
)
GND (VSS)
BU2098F
SDA
BU2098F
SCL
VDD
VDD
IN
IN
GND (VSS
)
GND (VSS
)
GND (VSS)
GND (VSS
)
GND (VSS
)
6/15
【BU2098F】
●AC characteristics (Unless otherwise noted, VDD=5V, VSS=0V, Ta=25℃)
Fast mode I2Cbus
Standard mode I2Cbus
Parameter
Symbol
Unit
Min.
Max.
Min.
0
Max.
SCL clock frequency
fSCL
tBUS
0
400
100
kHz
μs
μs
μs
μs
μs
μs
ns
Bus free time between start-stop condition
Hold time start condition
1.3
-
4.7
4.0
4.7
4.0
4.7
0
-
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
0.6
-
-
Low period of the SCL clock
High period of the SCL clock
Set up time Re-start condition
Data hold time
1.3
-
-
-
0.6
-
0.6
-
-
-
0
100
0.9
-
Data set up time
250
-
-
Rise time of SDA and SCL
Fall time of SDA and SCL
Set up time stop condition
Capacitive load for SDA line and SCL line
20+0.1Cb
20+0.1Cb
0.6
300
300
-
1000
300
-
ns
tF
-
ns
tSU:STO
Cb
4.0
-
μs
pF
-
400
400
●Timing chart
SDA
tBUS
tHD:STA
tf
tLOW
tr
SCL
tHD:STA
tSU:STO
Sr
S
tHD:DAT
tSU:DAT
tSU:STA
P
P
Fig.1 SDA, SCL timing chart
7/15
●Function
○Start condition
The start condition is a “HIGH” to “LOW” transition of the SDA line while SCL is “HIGH”.
○Stop condition
The stop condition is a “LOW” to “HIGH” transition of the SDA line while SCL is “HIGH”.
SDA
SCL
S
P
Start
condition
Stop
condition
Fig.2 Start / Stop condition
○Acknowledge
The master (μp) puts a resistive “HIGH” level on the SDA line during the acknowledge clock pulse. The peripheral
(audio processor) that acknowledge has to pull-down (“LOW”) the SDA line during the acknowledge clock pulse, so
that the SDA line is stable “LOW” during this clock pulse.
The slave which has been addressed has to generate an acknowledgement after the reception of each byte, otherwise
the SDA line remains at the “HIGH” level during the ninth clock pulse time. In this case the master transmitter can
generate the STOP information in order to abort the transfer.
clock for acknowledge
SCL
(from master)
1
8
9
SDA
(from master)
not confirm
confirm
SDA
(from slave)
S
ACK signal
Fig.3 Acknowledge
8/15
○Write DATA
Send the stave address from master following the start condition (S). This address consists of 7 bits. The left 1 bit (the
foot bit) is fixed “0”. The stop condition (P) is needed to finish the data transferred. But the re-send starting condition
(Sr) enables to transfer the data without STOP (P).
slave address
R/W
ACK
ACK
DATA
S
P
“0” (Write)
ACK
DATA
slave address
DATA
slave address
R/W
ACK Sr
R/W
ACK
ACK
P
S
“0” (Write)
“0” (Write)
Fig.4 DATA transmit
○Data format
The format is following.
S
A6
A5
A4
A3
A2
A1
A0 R/W ACK D7 D6
D5
D4
D3 D2
D1
D0 ACK
P
SLAVE ADDRESS
WRITE DATA
Table 1 for WRITE format
A0～A2
A3～A6
R/W
Each bit can be defined by the input levels of pins A0～A3.
Slave address
Write Data
These 4 bits are fixed.
“0”
Write “1” to D0 makes Q0 pin High-impedance. And write “0” makes Q0
pin LOW. D[1:7] and Q[1:7] are same as D0 and Q0.
D0～D7
Table 2 for (A2, A1, A0) to SLAVE ADDRESS
A6
0
A5
A4
1
A3
1
A2
0
A1
0
A0
0
Slave address
38H
1
1
1
1
1
1
1
1
0
1
1
0
0
1
39H
0
1
1
0
1
0
3AH
0
1
1
0
1
1
3BH
0
1
1
1
0
0
3CH
0
1
1
1
0
1
3DH
0
1
1
1
1
0
3EH
0
1
1
1
1
1
3FH
Fixed for BU2098F
Defined by external pin A0～A2
9/15
○Data transmission timing
SDA
S
A6
A5
A4
A3
A2
A1
A0 R/W ACK D7 D6
D5
D4
D3 D2
D1
D0 ACK
P
Slave address
Write data
Latch pulse
Output (Q7～Q0)
Output the write data to Q7～Q0 at the same time.
Fig.5 Timing chart for WRITE
Command sample for driving LEDs. These are all off. (terminal A0～A2 is open)
Power Supply ON
LEDs all-ON with power supply ON
SDA
S
0
1
1
1
1
1
1
0
ACK
1
1
1
1
1
1
1
1
ACK
P
Slave address
Write data
LEDs are all-off by this command.
・RESET CONDITION
After reset, Q0～Q7 pins are ON. (LEDs are all ON.)
・RISING TIME OF POWER SUPPLY
VDD must rise within 10ms. If the rise time would exceed 10ms, it is afraid not to reset the BU2098F.
VDD
GND
t≦10ms
Fig.6 Rising time of power supply
10/15
【BU2090F/FS】
●AC characteristics (unless otherwise noted, VDD=5V, VSS=0V, Ta=25℃)
Limit
Parameter
Minimum clock frequency
Data shift set up time
Data shift hold time
Symbol
tw
Unit
Condition
Min.
500
1000
200
300
200
400
50
Typ.
Max.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
DD=5V
VDD=3V
DD=5V
VDD=3V
DD=5V
VDD=3V
DD=5V
VDD=3V
DD=5V
VDD=3V
DD=5V
VDD=3V
DD=5V
V
tSU
V
tH
V
Data latch set up time
Data latch hold time
tLSUH
tLHH
tLSUL
tLHL
100
250
500
200
400
250
500
V
V
Data latch ”L”
set up time
Data latch ”L”
hold time
V
VDD=3V
●Switching time test circuit
±25V
RL 10kΩ
VDD
Q0
Pulse
Gen.
CLOCK
DATA
±25V
RL 10kΩ
Pulse
Gen.
Q11
GND (Vss)
Fig.7
●Switching time test waveforms
tW
tW
VDD
90%
90%
90%
10%
10%
tLHL
10%
10%
GND (Vss)
CLOCK
tSU
tH
tLSUL
tLSUH
tLHH
VDD
90%
90%
90%
90%
10%
10%
GND (Vss)
DATA
Fig.8
11/15
●Timing chart
【BU2098F】
Slave address
Device code
External terminal
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Start condition
Stop condition
SDA
VCC
A4
A6 A5
A3 A2 A1 A0 RW ACK D7
D5
D6
D4 D3 D2 D1 D0 ACK
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Note) Diagram shows a status where a pull-up resistor is connected to output.
12/15
●Timing chart
【BU2090F/FS】
CLOCK
DATA
D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Note1)
Indicates undefined output.
Note2) Output terminal is provided with a pull-up resistor.
13/15
●Operation Notes
1. Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can
break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any
over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as
fuses.
2. Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply
lines. An external direction diode can be added.
3. Power supply lines
Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line,
separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals to
ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the circuit,
not that capacitance characteristic values are reduced at low temperatures.
4. GND voltage
The potential of GND pin must be minimum potential in all operating conditions.
5. Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
6. Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.
7. Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.
8. Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure.
Use similar precaution when transporting or storing the IC.
9. Ground Wiring Pattern
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing
a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused
by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern
of any external components, either.
10. Unused input terminals
Connect all unused input terminals to VDD or VSS in order to prevent excessive current or oscillation.
Insertion of a resistor (100kΩ approx.) is also recommended.
14/15
●Type Designations (Selections) for Ordering
―
B
U
2
0
9
8
F
E
2
Product name
・BU2098
・BU2090
Package type
F : SOP16
FS : SSOP-A16
E1 Emboss tape reel Pin 1 on draw-out side
E2 Emboss tape reel Pin 1 opposite draw-out side
TL Emboss tape reel Pin 1 on draw-out side
TR Emboss tape reel Pin 1 opposite draw-out side
<Dimension>
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
2500pcs
10.0 0.2
E2
Direction
of feed
16
1
9
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
8
0.15 0.1
0.1
1.27
0.4 0.1
1Pin
Direction of feed
Reel
(Unit:mm)
※When you order , please order in times the amount of package quantity.
SSOP-A16
<Dimension>
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
2500pcs
E2
Direction
of feed
6.6 0.2
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
16
9
1
8
0.15 0.1
0.1
0.8
0.36 0.1
1Pin
Direction of feed
Reel
(Unit:mm)
※When you order , please order in times the amount of package quantity.
15/15
Appendix
Notes
No technical content pages of this document may be reproduced in any form or transmitted by any
means without prior permission of ROHM CO.,LTD.
The contents described herein are subject to change without notice. The specifications for the
product described in this document are for reference only. Upon actual use, therefore, please request
that specifications to be separately delivered.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard
use and operation. Please pay careful attention to the peripheral conditions when designing circuits
and deciding upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams information, described herein
are intended only as illustrations of such devices and not as the specifications for such devices. ROHM
CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any
third party's intellectual property rights or other proprietary rights, and further, assumes no liability of
whatsoever nature in the event of any such infringement, or arising from or connected with or related
to the use of such devices.
Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or
otherwise dispose of the same, no express or implied right or license to practice or commercially
exploit any intellectual property rights or other proprietary rights owned or controlled by
ROHM CO., LTD. is granted to any such buyer.
Products listed in this document are no antiradiation design.
The products listed in this document are designed to be used with ordinary electronic equipment or devices
(such as audio visual equipment, office-automation equipment, communications devices, electrical
appliances and electronic toys).
Should you intend to use these products with equipment or devices which require an extremely high level
of reliability and the malfunction of which would directly endanger human life (such as medical
instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers
and other safety devices), please be sure to consult with our sales representative in advance.
It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance
of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow
for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in
order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM
cannot be held responsible for any damages arising from the use of the products under conditions out of the
range of the specifications or due to non-compliance with the NOTES specified in this catalog.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact your nearest sales office.
THE AMERICAS / EUPOPE / ASIA / JAPAN
ROHM Customer Support System
Contact us : webmaster@ rohm.co.jp
www.rohm.com
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FAX : +81-75-315-0172
Copyright © 2007 ROHM CO.,LTD.
21, Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan
Appendix1-Rev2.0
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