BU26154MUV_技术文档

Datasheet

The 24bit Audio CODEC series

Monaural Audio CODEC

with Touch Panel Interface

BU26154MUV

General Description

Key Specifications

BU26154 is a low-power compact audio CODEC.

BU26154 also incorporates touch panel interface and

Cap-Less headphones amplifier, speaker amplifier which

is most suitable for digital still cameras, electronic

dictionaries. BU26154 has built-in voltage regulator for

the stability of CODEC characteristic that is sensitive to

the outside noise. Speaker amplifier that can change AB

/ D Class. Therefore, when the interference including the

FM radio influences it, BU26154 can prevent

interference by operating AB grade. As digital code

processing, it is equipped with the high-pass filter as the

noise cut use of the specific frequency band, Notch filter

and the Equalizer of 5 bands and P²Bass+, Noise gate,

and flexible sound quality effect processing is possible.

■



HVDD Power Supply:

SPVDD Power Supply:

CPDD Power Supply:

TVDD Power Supply:

MIC-ADC SNR:

2.7V to 3.6V

2.7V to 5.5V

2.7V to 3.6V

92dB(Typ)

DAC-SP SNR:

DAC-HP SNR:

95dB (Typ)

93dB (Typ)

Package(s)

W (Typ) x D (Typ) x H (Max)

6.00mm x 6.00mm x 1.00mm

VQFN040V6060

Features

■

Various sound processing functions



P²Bass+

Noise gate

Fast release ALC

5-band Equalizer/Notch Filter

■

High PSRR is attained by built-in regulator

Speaker amplifier can be switched to AB class and

D class.

■

Touch panel interface.

VQFN040V6060

Applications

■

Electronic Dictionary

Digital Still Camera

Digital Single-lens Reflex Camera

Digital Mirror-less Camera

Digital Video Camera, others

Typical Application Circuit(s)

VMID

HVDD1 HGND2 REGOUT

HGND1

HVDD

REGOUT IOVDD

Bias

LDO

MBIASCAP

MICBIAS

CSB/SCL

REGOUT

CPU

IO

I/F

SDATA/SDA

REGOUT

ADC

REGOUT

PGA

SCLK

REGOUT IOVDD

MIN1

MIN2

RESETB

RESET

IO

SPVDD

SPGND

Class AB or

Class D

REGOUT IOVDD

SPVDD

SPOUT+

SPOUT-

SP

VOL

SAI_LRCLK

Serial

Audio

InterFac

e

ALC

Filter

Sound Effect

HPVDD

REGOUT

IO

SAI_BCLK

VOL

HPL

HP

SAI_SDOUT

DAC

HPVSS

HPVDD

HPCOM

SAI_SDIN

REGOUT

HPR

DAC

REGOUT

IOVDD

IO

CPVDD

HPVDD

CPP

HPVSS

LDO

MCLKI

TSTO

TVDD

CLOCK

PLL

HPVDD

HPVSS

CHARGE

PUMP

CPN

TOUCH

PANEL I/F

HPVSS

CPGND

XP XN YP YN TVDD

TGND

IRQB

PLLC

Figure 1. Block Diagram

〇Product structure : Silicon monolithic integrated circuit 〇This product has no designed protection against radioactive rays

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Pin Configuration(s)

Top view

30

29

28

27 26 25

24

23 22 21

YP

XP

XN

31

32

33

34

35

36

37

38

39

40

20

RESETB

19 PLLC

18 REGOUT

17 HVDD

YN

TGND

TVDD

HPCOM

CPVDD

CPP

16

15 HGND1

NC

14

13

HGND2

MIN2

12 MIN1

11

MBIASCAP

HPR

1

2

3

4

5

6

8

9

10

7

Figure 2. Pin Configuration(s)

Pin Description(s)

Reset

(Note1) (Note3)

No use

No

17

6

Name

HVDD

SPVDD

I/O

P

Power

Function

High voltage power supply pin

A capacitor is connected between HVDD and HGND1.

Speaker power supply pin

A capacitor is connected between SPVDD and SPGND.

Voltage power supply pin for charge pump

A capacitor is connected between CPVDD and CPGND.

A no connect pin.

Voltage power supply for the touch panel

Please connect a capacitor between TVDD and TGND.

High voltage ground 1

-

P

38

16

36

CPVDD

N.C

P

-

TVDD

P

15

14

9

HGND1

HGND2

SPGND

CPGND

TGND

P

O

-

It is used on the same voltage as HGND2, SPGND,

CPGND, and TGND.

High voltage ground 2

It is used on the same voltage as HGND1, SPGND,

CPGND, and TGND.

Ground pin for Speaker

It is used on the same voltage as HGND1, HGND2,

CPGND, and TGND.

Ground pin for charge pump

It is used on the same voltage as HGND1, HGND2,

SPGND, and TGND.

Ground pin for touch panel interface

It is used on the same voltage as HGND1, HGND2,

CPGND, and SPGND.

-

3

-

35

18

Regulator output

REGOUT

HVDD

A capacitor is connected between REGOUT and HGND1. HGND2

Please connect as close as possible to the chip.

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A positive side voltage output pin for the headphones

driver.

A capacitor is connected between HPVDD and CPGND.

Please connect as close as possible to the chip.

A negative side voltage output pin for the headphones

driver.

A capacitor is connected between HPVSS and CPGND.

Please connect as close as possible to the chip.

Master Clock pin

Output pin for test-mode. Make it open.

Reset pin

(Note 2)

2

4

HPVDD

O

CPVDD

CPGND

(Note 2)

HPVSS

CPGND

22

21

MCLKI

TSTO

I

O

HVDD

(input)

HGND1

Open

20

RESETB

I

HVDD

"L" level: Reset enables.

"H" level: Reset disable.

(input)

-

3 wire interface: data input output pin

It is indicated as SDATA.

SDATA

/SDA

24

IO

HVDD

-

2 wire interface: data input output pin^{(Note 1)}

It is indicated as SDA.

3 wire interface: Serial clock input pin

It is indicated as SCLK.

SCLK

/SAD

2 wire interface: Slave address select input pin.

It is indicated as SAD.

SAD pin = "L" level slave address is "0011010"

SAD pin = "H" level slave address is "0011011"

3 wire interface: chip select input pin

It is indicated as CSB.

25

23

I

HVDD

(input)

HGND1

CSB

/SCL

-

2 wire interface: Serial clock input pin *1

It is indicated as SCL.

26

27

28

29

SAI_LRCLK

SAI_BCLK

SAI_SDIN

IO

I

HVDD

SAI LR clock input/output pin

SAI bit clock input/output pin

SAI serial data input pin

SAI serial data output pin

(input)

HGND1

Open

SAI_SDOUT

O

An interrupt output terminal. When an interrupt occurs,

chip outputs "L".

Analog reference voltage pin

30

10

IRQB

VMID

O

HVDD

HGND1

HGND2

Open

-

REGOUT

A capacitor is connected between VMID and HGND2.

Microphone bias voltage output pin

A capacitor is connected between HGND2.

Please connect as close as possible to the chip.

Analog microphone input 1

Single-end and differential can be chosen.

When differential is chosen, it connects with microphone

+ pin.

11

12

MBIASCAP

MIN1

O

I

HVDD

HGND2

Hi-Z

Open

REGOUT

Analog microphone input 2

Single-end and differential can be chosen.

When differential is chosen, it connects with microphone

- pin.

13

MIN2

I

REGOUT

Hi-Z

Open

8

7

1

40

39

5

SPOUT-

SPOUT+

HPL

HPR

CPP

O

SPVDD

speaker output - pin

speaker output + pin

Headphones output Lch terminal

Headphones output Rch terminal

SPGND

CPGND

Hi-Z

Open

CPVDD Charge pump flying capacitor, positive side output pin

CPVDD Charge pump flying capacitor, negative side output pin

PLL filter pin

CPN

Hi-Z

When clock of the MCLKI pin input is used, make it open.

When clock of the SAI_BCLK pin input is used, it is

19

PLLC

O

HVDD

HGND2

Open

necessary to connect resistors and a capacitor.

31

32

33

34

37

YP

XP

XN

O

I

TVDD

-

YP pin for the touch panel interface

XP pin for the touch panel interface

XN pin for the touch panel interface

YN pin for the touch panel interface

Headphones amplifier common pin

Hi-Z

(input)

Open

-

YN

HPCOM

(Note 1) In case of 2 wire serial, if this pin is used with external pull-up resistor, it possibly gets noise from power. Therefore, tamper noise design is required

in the noisy environment.

(Note 2) At the time of power down, in HPVDD and HPVSS, is short-circuited.

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Description of Block(s)

1μF

CPVDD

HVDD

TVDD SPVDD

CSB/SCL

option

4.7μF

MBIASCAP

SDATA/SDA

SCLK

2.2kohm

MIN1

MIN2

0.47μF

RESETB

CPU

and

DSP

IRQB

SAI_LRCLK

SAI_BCLK

SAI_SDOUT

SAI_SDIN

MCLKI

SPOUT+

SPOUT-

BU26154

option

PLLC

HPL

HPR

option

VMID

1μF

XP

REGOUT

HPVDD

2.2μF

XN

YP

Touch

2.2μF

1μF

Screen

CPP

CPN

YN

HPVSS

2.2μF

option

HPCOM

TSTO Open

SPGND

HGND1

CPGNDHGND2

TGND

Figure 3. BU26154 Application circuit

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Absolute Maximum Ratings (Ta = 25°C)

(HGND1=HGND2=SPGND=CPGND=TGND=0V)

Parameter

Symbol

HVDD

Condition

-

Rating

Unit

V

HVDD Supply Voltage

-0.3 to 4.5

SPVDD Supply Voltage

CPVDD Supply Voltage

SPVDD

CPVDD

-

-0.3 to 7.0

-0.3 to 4.5

V

MCLKI, SAI_LRCLK,

SAI_BCLK, SAI_SDIN,

SDATA/SDA, SCLK.

CSB/SCL pins

-0.3 to HVDD+0.3

V

Input Voltage

VIN

T_stg

MIN1, MIN2 pins

-0.3 to REGOUT+0.3

-55 to +150

V

Storage Temperature

-

℃

Ta=25°C ^{(Note 1)}

Ta=25°C ^{(Note 2)}

SPOUT+, SPOUT- pins

HPL, HPR pins

0.80

W

Power Dissipation^{(Note 1)}

Pd

3.01

W

Output Current 1

Output Current 2

Output Current 3

Output Current 4

IOSP

IOHP

-560 to +560

-100 to +100

-500 to +500

-30 to 0

mA

HPVSS,HPVDD,CP,CN

IOCP

IOREGO

REGOUT pin

Except SPOUT+,SPOUT-,

HPL,HPR,

REGOUT,HPVDD,HPVSS

pins

Output Current 5

IOO

-8 to +8

mA

Do not short the output pin to another output pin, power supply pin or GND pin.(Output pin includes an IO pin which is in output mode)

(Note 1) 74.2mm×74.2mm×1.6tmm FR4 1Layer Glass epoxy base Surface Copper foil 0%）Mounting

Above Ta=25℃,reduced by 8.0mW/℃. Thermal beer is on a base.

(Note 2) 74.2mm×74.2mm×1.6tmm FR4. 4 Layer Glass epoxy base（2,3layer Copper foil 100%）Mounting

Above Ta=25℃, reduced by 30.12mW/℃. Thermal beer is on a base.

Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over

the absolute maximum ratings.

Recommended Operating Conditions

(HGND1=HGND2=SPGND=CPGND=TGND=0V)

Parameter

Symbol

Condition

Rating

Unit

V

HVDD Supply Voltage

HVDD

HVDD=CPVDD=TVDD

2.7 to 3.6

SPVDD Supply Voltage

CPVDD Supply Voltage

TVDD Supply Voltage

Operating Temperature

SPVDD

CPVDD

TVDD

T_op

-

2.7 to 5.5

2.7 to 3.6

-20 to +85

V

HVDD=CPVDD=TVDD

-

V

℃

(Note 1) The radiation-proof design is not carried out.

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Electrical Characteristics

DC Characteristics

(HGND1= HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V, Ta=25℃)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Related Pin

All Digital

Input

"H" Input Voltage1

VIH1

HGND1=0V

HVDD *0.8

-

HVDD+0.3

V

All Digital

Input

All Digital

Input

All Digital

Input

"L" Input Voltage 1

VIL1

VIH2

VIL2

HGND1=0V

-0.3

HVDD-0.4

-0.3

-

HVDD *0.2

HVDD+0.3

0.4

V

"H" Input Voltage 2

"L" Input Voltage 2

"H" output Voltage

"L" output Voltage 1

"L" output Voltage 2

"H" Input Leakage

Current

"L" Input Leakage

Current

"Z" output Leakage

Current

VOH

VOL1

VOL2

IOH=-1mA

IOL=1mA

IOL=3mA

HVDD *0.85

-

V

Except SDA

SDA

All Digital

Input

-

HVDD *0.15

0.4

IIH

IIL

VIH= HVDD

VIL=HGND1

VOH=HVDD

VOL=HGND1

-

10

-

µ A

All Digital

Input

-10

-

IOZH

IOZL

10

-

SDA

"Z" output Leakage

Current

-10

Playback(fs48kHz)

no Load, Hp-amp

use

Sin1kHz-Full Scale

output

Playback(fs48kHz)

no Load, D-class,

Sp-amp use

Sin1kHz-Full Scale

output

Operating Current1

Operating Current2

Operating Current3

IDDO1

IDDO2

IDDO3

-

10

10.5

12

13

mA

-

13.7

15.6

Playback(fs48kHz)

no Load, AB-class,

Sp-amp use

Sin1kHz-Full Scale

output

Record(fs48kHz)

Sin1kHz-Full Scale

input

Touch Panel

Interface Operate

Operating Current4

Operating Current5

IDDO4

IDDO5

-

9.5

0.6

12.4

1

mA

-

Touch Panel

Interface Interrupt

Wait

Ta = -40 to 55 ℃

Operating Current6

IDDO6

IDDS

-

220

0.5

320

5

uA

-

(Note 3)

Standby Current

25 ℃

µ A

(Note 1) Touch Panel Interface Interrupt electric current at the time of the wait. Please refer to a touch panel interface clause for the movement setting

condition.

(Note 2) Standby current is total value for all power supply currents.

(Note 3) Standby current's condition is power off state by RESETB=L

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AC Characteristics

Clock

PLL not used

(HGND1= HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V, Ta=25℃)

Min

Max

Unit

MHz

ns

Parameter

MCLKI Frequency

Symbol

fC

4.096

1/fC

49.152

MCLKI Period

tC

1/fC

MCLKI “H” Length

MCLKI “L” Length

tCH

tCL

tC*0.4

-

ns

PLL used

(HGND1= HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V,Ta=25℃)

Min

6.75

Max

54

1/fC

-

Unit

MHz

ns

Parameter

MCLKI Frequency

Symbol

fC

MCLKI Period

tC

1/fC

MCLKI “H” Length

MCLKI “L” Length

tCH

tCL

tC*0.4

ns

-

ns

When PLL is use, clock from SAI_BCLK pin other than MCLKI pin could be inputted. Please refer to SAI slave clause about

the BCLK pin input frequency.

tC, fC

MCLKI

tCH

tCL

Figure 4

Reset

(HGND1= HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V, Ta=25℃)

Min

5

Max.

-

Unit

µ s

Parameter

RESETB pulse width

Symbol

tW_RST

RESETB

Figure 5

When Reset pin is made low-level, internal LDO goes to power mode.

1ms is necessary until REGOUT pin becomes low-level. The recommended tW_RST is over 1ms.

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2-Wire Serial Interface

(HGND1= HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V, Ta=25℃,

CL=30pF)

Standard Mode

Fast Mode

Unit

Parameter

Symbol

Min

-

Max

Min

Max

SCL Frequency

SCL "L" Length

SCL "H" Length

f_SCL

t_LOW

t_HIGH

100

-

400

kHz

µs

4.7

4.0

-

1.3

0.6

-

µs

Hold Time under Repeat [Start] Condition

Setup Time under Repeat [Start] Condition

t_HD:STA

t_SU:STA

4.0

-

0.6

-

µs

Data Hold Time

Data Setup Time

t_HD:DAT

t_SU:DAT

0

3.45

-

0

0.9

-

µs

ns

250

100

Setup Time under [Stop] Condition

t_SU:STO

4.0

-

0.6

-

µs

tHD:STA

SDA

tSU:DAT

tLOW

SCL

tHD:STA

tHD:DAT

tHIGH

tSU:STA

tSU:STO

Figure 6

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3-Wire Serial Interface

(HGND1= HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V, Ta=25℃,

CL=30pF)

Parameter

Symbol

tSLCL

Min

100

Max

-

Unit

ns

SCLK Low to Chip Select enable

Chip Select Enable to SCLK Low

Chip Select Enable to SCLK High

CLK High to Chip Select enable

SCLK High Pulse Width

tCLSL

tCLSH

tSHCL

tSH

100

50

-

ns

-

ns

SCLK Low Pulse Width

tSL

50

-

Input Data Setup time

tIDS

30

100

-

Input Data Hold time

tIDH

-

ns

SCLK last edge to Chip Select disable

Chip Select High Pulse Width

Output Data Valid

tCHS2

tCH

-

tODV

tCHDTS

40

Chip Select High to Data Transition

-

Two kinds of timing are supported depending on the SCLK pin level at data transfer start. Read or Write is selected by LSB

logic INDEX.

Figure 7

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Serial Audio Interface (Slave)

(HGND1= HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, VDD=3.3V, Ta=25℃,

CL=30pF)

Parameter

Symbol

tC_BCLK

Min

32fs

73

20

-

Max

Unit

Hz

ns

SAI_BCLK Period

128fs

SAI_BCLK "H" Length

SAI_BCLK "L" Length

SAI_LRCLK Hold Time

SAI_LRCLK Setup Time

tHW_BCLK

tLW_BCLK

tH_LRCLK

tSU_LRCLK

tD_SDO ^{(Note 1)}

tSU_SDI

-

SAI_SDOUT Delay Time

SAI_SDIN Setup Time

SAI_SDIN Hold Time

80

-

20

tH_SDI

-

(Note 1) tD_SDO is the delay time from previous SAI_BCLK transition and SAI_LRCLK transition.

SAI_LRCLK

tC_BCLK

tH_LRCLK

tSU_LRCLK

SAI_BCLK

tHW_BCLK tLW_BCLK

SAI_SDOUT

tD_SDO

SAI Transmit

Figure 8

SAI_LRCLK

SAI_BCLK

SAI_SDIN

tC_BCLK

tH_LRCLK

tSU_LRCLK

tH_SDI

tSU_SDI

tHW_BCLK tLW_BCLK

SAI Receive

Figure 9

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SAI (Master) - Serial Audio Interface (Master)

(HGND1= HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V, Ta=25℃,

CL=30pF)

Parameter

Symbol

tC_BCLK

tHW_BCLK

tLW_BCLK

tD_LRCLK

tD_SDO

Min

32fs

146

-

Max

Unit

Hz

ns

SAI_BCLK Period

64fs

SAI_BCLK "H" Length

SAI_BCLK "L" Length

SAI_LRCLK Delay time

-

ns

20

-

ns

SAI_SDOUT Delay Time

SAI_SDIN Setup Time

SAI_SDIN Hold Time

-

ns

tSU_SDI

50

0

ns

tH_SDI

-

ns

SAI_LRCLK

tC_BCLK

tD_LRCLK

SAI_BCLK

tHW_BCLK tLW_BCLK

SAI_SDOUT

tD_SDO

SAI Transmit

Figure 10

SAI_LRCLK

SAI_BCLK

SAI_SDIN

tC_BCLK

tD_LRCLK

tH_SDI

tSU_SDI

tHW_BCLK tLW_BCLK

SAI Receive

Figure 11

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Power Supply Sequence

Please power on/off the LSI with all kind of power at the same time.

Each power supply should power up/down in 50ms. Also, keep all power supply in the ON state or the OFF state.

Please avoid partial ON or partial OFF states.

Please keep RESETB pin “L” level until all power supply become ON state. The CPU I/F become available when all power

supply is powered on after t_{W_PURST}and t_{W_REGU}time exceeds.

HVDD must be powered on first, but HVDD must be powered off last. About SPVDD, there is no limitation above.

Parameter

Power On Delay Time

Symbol

Min

Typ Max Unit

t_{VDD_ON}

t_{VDD_OFF}

t_{w_PURST}

t_{w_REGU}

0

1

-

50

-

ms

μs

Power Off Delay Time

Reset Time after Power ON

Wait Time for Regulator Starting after Reset

Release

-

ms

PowerSupply*0.9

t_{VDD_ON}

HVDD

Power

supply

PowerSupply*0.1

t_{VDD_OFF}

Other

PowerSupply*0.9

t_{W_PURST}t_{W_REGU}

Power

supply

PowerSupply*0.1

REGOUT

RESETB

CPU I/F

not available

VDD OFF

available

not available

VDD OFF

STATUS

Wait

Regulator

PowerDown

Operation

Figure 12

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Analog Characteristics

(HGND1= HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V, Ta=25°C)

Parameter

Regulator Output

REGOUT Output Level

Symbol

Condition

Min

1.7

-

Typ

1.8

-

Max

Unit

V

VREGOUT

-

1.9

Mic Input (MIC Gain=18dB / Digital Volume=0.0dB / ALC=OFF)

Full Scale Input Signal Level

Input Resistance

VMINFS1

RMIN1

MIN1,MIN2

0.124

40

Vp-p

20

30

kΩ

Mic Input (MIC Gain=9.0dB / Digital Volume=0.0dB / ALC=OFF)

-

Full Scale Input Signal Level

Input Resistance

VMINFS2

RMIN2

MIN1,MIN2

0.454

40

Vp-p

20

30

kΩ

Analog Reference Level(VMID-pin)

0.9x

1.0x

1.1x

Analog Reference Voltage

VREF

-

V

REGOUT/2 REGOUT/2 REGOUT/2

Microphone Bias(MBIASCAP -pin)

IMIC = -1mA,

MICBCON=0

1.50x

1.67x

1.84x

V

REGOUT/2 REGOUT/2 REGOUT/2

IMIC = -1mA,

MICBCON=1

2.00x 2.22x 2.45x

REGOUT/2 REGOUT/2 REGOUT/2

Output Voltage

where, VMIC<HVDD*0.85

VMIC

IMIC

IMIC = -1mA,

MICBCON=2

2.50x 2.78x 3.06x

REGOUT/2 REGOUT/2 REGOUT/2

3.00x 3.33x 3.67x

IMIC = -1mA,

MICBCON=3

V

REGOUT/2 REGOUT/2 REGOUT/2

Output Current

-

2

mA

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(HGND1=HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V, Ta=25℃)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Analog Inputs to ADC out (MIC Gain=18dB / Digital Volume=0.0dB / ALC=OFF)

S/(N+D)

SND1

SNR1

-1dBFS/ A-weighted

A-weighted

-

78

89

90

-

dB

S/N

HVDD on 100mVp-p, 1kHz

noise, no signal input

Power Supply Rejection Ratio

PSRR1

dB

Analog Inputs to ADC out (MIC Gain=9.0dB / Digital Volume=0.0dB / ALC=OFF)

S/(N+D)

S/N

SND2

SNR2

-1dBFS/ A-weighted

A-weighted

-

80

92

-

dB

HVDD on 100mVp-p, 1kHz

noise, no signal input

Power Supply Rejection Ratio

PSRR2

-

90

-

dB

DAC to Headphone OUT(HPR/HPL, with 16Ω/50pF load)

Total Harmonic Distortion

Signal to Noise Ratio

THD+N3

SNR3

1kHz,input -12dBFS

A-weighted

-

75

93

-

dB

HVDD on

100mVp-p,1kHz noise, no

signal input

CPVDD on

100mVp-p,1kHz noise, no

signal input

-

90

-

dB

Power Supply Rejection Ratio

PSRR3

Output Offset Voltage

VOF

No signal input

-

±1

500

1.8

-

mV

kHz

V

Charge Pump Oscillator Frequency

HPVDD Port Output Voltage

HPVSS Port Output Voltage

CPOSC

HPVDO

HPVSO

-

-1.8

V

DAC to Speaker OUT D-class Mode (SPOUT+/-, with 8Ω/50pF load)

Output Power

Po4

THD=10%, SPVOL=6dB

Po=310mW

-

700

66

-

mW

dB

Total Harmonic Distortion

Signal to Noise Ratio

THD+N4

SNR4

A-weighted, THD+N=1%

95

dB

HVDD on

100mVp-p,1kHz noise

SPVDD on

100mVp-p,1kHz noise

-

90

60

-

dB

Power Supply Rejection Ratio

PSRR4

PWM frequency

Efficiency

PWMF

EFF

-

370

90

-

kHz

%

DAC to Speaker OUT AB-class Mode (SPOUT+/-, with 8Ω/50pF load)

Output Power

Po5

THD=10%, SPVOL=6dB

Po=310mW

-

700

62

-

mW

dB

Total Harmonic Distortion

Signal to Noise Ratio

THD+N5

SNR5

A-weighted, THD+N=1%

95

dB

HVDD on

100mVp-p,1kHz noise

SPVDD on

100mVp-p,1kHz noise

-

90

60

-

dB

Power Supply Rejection Ratio

PSRR5

Microphone Bias(MBIASCAP-pin) *1

Output Noise Voltage

22Hz to 22kHz,

MICBCON=1

HVDD on

100mVp-p,1kHz noise

VMICN6

PSRR6

-

5

-

μV

Power Supply Rejection Ratio

70

dB

Load=1mA

MICBCON=1

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(HGND1=HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V,Ta=25℃)

Parameter

Touch Panel Interface

ADC Resolution

Symbol

Conditions

Min

Typ

Max

Unit

N

-

-3

-4

-

12

3

Bit

LSB

Ω

Differential Non-Linearity Error

Integral Non-Linearity Error

Offset Error

DNL

-

INL

-

4

OFTERR

GAERR

SWONR

IRQR1

IRQR2

Tw_ADC1

Tw_ADC2

-

1

-

Gain Error

-

0.5

5

-

Touch Panel Driver Switch

-

RSEL=0

RSEL=1

40

70

-

50

90

-

70

120

35

43

kΩ

Interrupt Pull-up Resistance

ADC Conversion Timing

kΩ

μs

-

μs

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Function Description

Clock Control

Main modules that make sound path of the LSI inside operate with 1024fs Audio Clock.

Audio Clock can be selected whether divided clock of 256fs/512fs/1024fs from MCLKI or generated clock from Audio PLL.

When PLL is used, PLL generates internal clock. The input clock into PLL can be selected from either MCLKI port or

SAI_BCLK port by setting Clock Input / Output Control register. PLL generates 256fs clock of sampling frequency.

The registers about Audio Clock setting: Sampling Rate Setting Register, FPLLM, FPLLNL, FPLLNH, FPLLD, FPLLFL,

FPLLFH, FPLLFDL, FPLLFDH, Clock Input / Output Control register, Clock Input Select Register

・The sequence of PLL setting

1. Stop PLL output by setting PLLOE bit to “0”.

2. Disable PLL by setting PLLEN bit to “0”.

3. Set PFLLM, FPPNL, FPLLNH, FPLLD, FPLLFL, FPLLFH, FPLLFDL, FPLLFDH.

4. Set input port by PLLISEL bit.

5. Set PLLEN bit to “1”.

6. Wait for the PLL stabilizing time as the table “PLL Stabilizing Time”.

7. Set PLLOE bit to “1”.

8. Start recording or playback.

PLL Stabilizing Time

PLL stability time

10msec

- Related Register

Sampling Rate Setting Register

PLLNL, PLLNH Register

PLLML, PLLMH Register

PLLDIV Register

Clock Enable Register

Clock Input / Output Control Register

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When PLL is Used.

The LSI support audio PLL function that can generate precise audio clock from wide range of clock frequency. Then, it can

be realize audio function without external clock generator for audio. The LSI supports following cases.

The LSI generates audio clock with input clock provided from MCLKI port or BCLKI port.

■case1: PLLISEL (0x0e/0x0f)=0x1, MST(0x64/0x65)="0"

Audio clock is generated by the PLL BU26154 with MCLKI clock. SAI_LRCLK and SAI_BCLK are provided by the CPU.

B26154

SAI_LRCLK

SAI_BCLK

SAI_SDIN

CPU

SAI_SDOUT

MCLKI

CLOCK

Figure 13

■case2: PLLISEL (0x0e/0x0f)=0x1, MST(0x64/0x65)="1"

Audio clock is generated by the PLL in BU26154 from MCLKI clock. SAI_LRCLK and SAI_BCLK are provided from the LSI.

Figure 14

■case3: PLLISEL (0x0e/0x0f)=0x2, MST(0x64/0x65)="1"

Audio clock is generated by PLL in BU26154 form SAI clock.

Figure 15

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When PLL is not Used.

Audio clock is generated by the CPU and supplied to the LSI when PLL is not used. Then CPU and the LSI are

synchronized.

■case 5: MST (0x64/0x65) ="0"

Audio clock (256fs, 512fs, 1024fs) is generated by the CPU and supplied to MCLKI port of the LSI. LRCLK and BCLK are

also provided from the CPU.

Figure 16

■case6: MST (0x64/0x65)="1"

Audio clock (256fs, 512fs, 1024fs) is generated by the CPU and supplied to MCLKI port of the LSI. SAI_LRCLK and

SAI_BCLK are provided from the LSI.

Figure 17

Even when using the same sampling frequency, the setting condition is different depending on clock frequency.

When changing MCLKI input frequency, PLLOE should be set to “0”, then PLLOE should be set to “1” back.

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SAI (Serial Audio System Interface)

The LSI supports SAI formats.

WSLI="0", DLYI="0", FMTI="0"

SAI_

LRCLK

Right

Left

1 2 3 ……………16………… 1 2 3 ……………16…………

SAI_SDIN

SAI_SDOUT

3SB

MSB 2SB

Figure 18

LSB

SAI_BCLK

WSLI="1", DLYI="0", FMTI="0"

Left

Right

Left

SAI_

LRCLK

1 2 3 ……………16………… 1 2 3 ……………16…………

SAI_SDIN

SAI_SDOUT

3SB

MSB 2SB

LSB

SAI_BCLK

Figure 19

WSLI="0", DLYI="1", FMTI="0"

SAI_

LRCLK

Left

Right

1 2 3 ……………16………… 1 2 3 ……………16…………

SAI_SDIN

SAI_SDOUT

3SB

MSB 2SB

LSB

SAI_BCLK

Figure 20

WSLI="1", DLYI="1", FMTI="0"

SAI_

LRCLK

Right

Left

3SB

Left

1 2 3 ……………16………… 1 2 3 ……………16…………

SAI_SDIN

SAI_SDOUT

3SB

MSB 2SB

LSB

SAI_BCLK

Figure 21

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DLYI="0", FMTI="1"

Flame synchronous transfer mode: R channel data is transferred right after L channel data.

SAI_

LRCLK

Left

Right

Left

1 2 3 ……………16 1 2 3 ……………16…………

SAI_SDIN

SAI_SDOUT

3SB

MSB 2SB

LSB

SAI_BCLK

Figure 22

DLYI="1", FMTI="1"

Flame synchronous transfer mode: R channel data is transferred right after L channel data.

SAI_

LRCLK

Right

Left

1 2 3 ……………16 1 2 3 …………16…………

SAI_SDIN

SAI_SDOUT

3SB

MSB 2SB

LSB

SAI_BCLK

Figure 23

- Related Register

SAI Transmitter Control Register

SAI Receiver Control Register

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2 wire serial interface

This LSI has 2 wire serial interfaces. The LSI operates as a slave device. The address is fixed at “0011010”.

- Format

The followings are the protocol of the LSI.

Write (MSB first)

Start Condition (Set SDA level from “H” to “L” during SCL=“H”)

Slave Address (0011010) +W (0) (8bit)

Write Address (8bit)

Write Data (8bit)

…

Stop Condition (Set SDA level from “L” to “H” during SCL=“H”)

Read (MSB first)

Start Condition

Slave Address (0011010) +W (0) (8bit)

Read Address (8bit)

(Stop Condition) Start Condition

Slave Address (0011010) +R (1) (8bit)

Read Data (8bit)

The following shows the wave form of the LSI.

The yellow gridding shows that slave device drives the bus.

The symbol in the wave form means as following table.

Unit

W/R

Description

0: It is Read Write 1

A

0: ACK(Acknowledge) 1: NAK(Not Acknowledge)

A[7-0]

D[7-0]

Address (8bit)

Data(8bit)

Write

slave address reception

Access address reception

Write data reception

Start

0

1

2

3

4

0

5

1

6

0

7

8

SCL

SDA

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

A

0

1

A7 A6

A1 A0

A5 A4 A3 A2

W

D7 D6 D5 D4 D3 D2 D1 D0

Writedata reception

Write data reception

8

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

Stop

Continued

from the

above

A

D7 D6

D1 D0

A

D5 D4 D3 D2

D7 D6

D1 D0

D7 D6

D1 D0

D5 D4 D3 D2

Internal write

Figure 24

In case there is no Stop or Start condition after internal register is written (Above figure: Internal Write), the slave device

becomes continuous write mode and the next received 8 bits of data will be written into the internal register addressed by

incremented by two to the current address.

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Read

slave address reception

Access address reception

Start

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

S

SCL

SDA

A

0

1

0

1

0

W

A7 A6

A1 A0

A5 A4 A3 A2

slave address reception

Read data transmission

0

1

2

1

3

1

4

5

6

7

8

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

Continued

fromthe

above

A

D7 D6 D5 D4 D3 D2 D1 D0

0

A

D7 D6 D5 D4 D3 D2 D1 D0

R

A

0

1

Internal read

Figure 25

If the Master device returns ACK (acknowledge) after the 8 bit data transferred from the LSI becomes continuous read

mode. The next received 8 bits of data will be read from the internal register addressed by incremented by two to the

current address.

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State transition about sound control

The following shows state transition about sound control. A change state is carried out by RECPLAY bit setup.

Sound Stop

STATE

0x0

Play STATE

Rec STATE

0x2

0x1

BU26154MUV is changed

Rec and Play

STATE

Monitor STATE

0x7

status by setting RECPLAY

bit.

0x3

Figure 26

(1) Sound Stop STATE (RECPLAY=0x0)

Sound activity is stopped.

(2) Rec STATE (RECPLAY =0x1)

Recording is enabled through microphone.

(3) Play STATE (RECPLAY =0x2)

Playback is enabled from SAI.

(4) Monitor STATE (RECPLAY =0x7)

Monitoring recording via microphone is enabled. ALC function is only effective in recording path.

Only 2ch sound effects are available in Notch filter mode. In the time of transition Rec STATE to Monitor STATE, please

set off the register bits of EQ2EN-EQ3EN.

(5) Rec and Play STATE (RECPLAY =0x3)

Playback is enabled from SAI with recording via microphone. ALC function is only effective in recording path.

Only 2ch sound effects are available in Notch filter mode. In the time of transition Rec STATE to Monitor STATE, please

set off the register bits of EQ2EN-EQ3EN.

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Signal Flow

It uses signal flow Case1 or Case2 at the time of recording (analog microphone).

Case1:

DV

MUTE

Recording

ALC

AMIC

VOL

REC

LPF

REC

ALCVOL

Noise

Gate

REC

DATT

Digital

Interface

ADC

HPF1

HPF2

Filter

Filter Block

Case2:

DV

MUTE

Recording

ALC

AMIC

VOL

REC

LPF

REC

ALCVOL

Noise

Gate

REC

DATT

Digital

Interface

ADC

HPF1

HPF2

Filter

Filter Block

Figure 27

Name

AMICVOL

HPF1

Function

Related Register

Mic input volume control

DSP Filter Function Enable

Setting

Volume setting

Analog Microphone volume

9dB to +35.25dB

HPF Enable/Disable

order setting

Cut-off frequency setting

Sound Effect mode setting

Each filters Enable/Disable setting

Each filters gain setting

Each sound effects characteristics

setting

High path filter for record DC cut

HPF2

High pass Filter for Record

Notch filter is available

High Pass Filter2 Cut-off Control

Sound Effect Mode

DSP Filter Function Enable

EQ Band N Gain Setting

Programmable EQ Band N

Coeffeicient-a0/1

Filter

LPF Enable/Disable setting

order setting

Cut-off frequency setting

Rec Programmable LPF Setting

RECLPF

Low pass Filter for recording.

Rec Programmable LPF Cutoff

Coef

ALC use:ALC controls volume

ALC not use: It’s available as

Boost volume

REC

ALCVOL

Auto Level Controller Function.

ALC is processed to recording

data

refer to application note

ALC

The purpose is for reducing a floor

noise

Noise Gate

Record Digital Attenuator Control

Digital Volume Control Function Digital Volume Control Function

Enable

Record Digital Attenuator Control

Record Digital Attenuator.

It’s available fader function for

reducing a Pop-noise when

changing volume.

RECDATT

Enable

Mixer & Volume Control

Digital Volume Control Function Digital Volume Control Function

Enable Enable

DVMUTE

Record Digital Volume Mute

* Please refer to the Sound Effect Mode register for Filter Block. When Filter Block is connected with the reproduction route, nothing is processed in the

recording route.

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Signal flow at the time of the reproduction

Playback

To Speaker ampifier

SOFT

CLIP

PLAY

DATT

PLAY

ALCVOL

PLAY

LPF

Effect

Vol

LRM

CON

Digital

Interface

VOL

SPVOL

SPINSEL

AVOL

DAC

Filter

HPF2

H-BASS

Filter Block

DV

MUTE

To Headphone ampifier

ALC

HPINSEL

Figure 28

Name

Function

Related Register

Setting

Mixer of the Lch/Rch data input from

SAI.

It is digital before the sound is

processed Volume.

LRMCON

Mixer & Volume Control

Mixer setting

Volume setting

-71.5dB to 0dB (0.5dBstep)

Setting of P²Bass+

Effect Vol

P²Bass+

Playback Effect Volume

P²Bass+ Enable

Block for P²Bass + processing.

P²Bass+ Parameter*

Sound Effect Mode

Sound mode setting

DSP Filter Function Enable

EQ Band N Gain Setting

Programmable EQ Band

N Coeffeicient-a0/1

Enable/Disable of each filter

Gain setting of each filter

Characteristic setting of each

filter and acoustic treatment

Degree setting of LPF for

Enable/Disable reproduction of

LPF for reproduction

Filter

Notch filter is available

Play Programmable LPF Setting

It is programmable LPF for the

reproduction.

PLAYLPF

Play Programmable LPF Cutoff

Coef

Characteristic setting of LPF for

reproduction

When ALC is used It functions as

Volume that ALC controls.

When ALC unused: It functions as

Boost Volume.

PLAY

ALCVOL

Please refer to the application note for the ALC function.

It is an auto level controller.

ALC is processed to the reproduction

data.

ALC

Playback Digital Attenuator

Control

Digital Volume Control Function

Enable

Volume setting

Digital Attenuator of the reproduction

route.

Fader can be used for the noise

reduction at the Volume setting

change.

-71.5dB to 0dB (0.5dBstep)

Fader ON/OFF setting

(Synchronize with DVMUTE.)

Setting at Fade time

PLAYDATT

Mixer & Volume Control

(Synchronize with DVMUTE.)

Reproduction route (PLAYDATT) is

compulsorily put into the state of

Mute.

The value of PLAYDATT need not be

changed.

Digital Volume Control Function

Enable

DVMUTE

SPVOL

MUTE ON/ Turning off setting

The Analog Boost Volume of

Speaker amplifier setting.

Volume setting

0dB/6dB/12dB/18dB

Volume setting

-28dB to +18dB*At BTL

Fader ON/OFF setting

(Synchronize with AVMUTE.)

Speaker Amplifier Input Control

Analog volume control

The Analog Volume of reproduction

route setting.

Fader can be used for the Pop-noise Amplifier Volume Fader Control

reduction at the Volume setting

AVOL

Amplifier Volume Control Function Setting at Fade time

Enable

change.

(Synchronize with AVMUTE.)

Reproduction route (SPVOL) is

compulsorily put into the state of

Mute. The value of SPVOL need not

be changed.

Amplifier Volume Control Function

Enable

AVMUTE

MUTE ON/OFF setting

It selects the input path to speaker

amplifier.

It selects the input path to

headphone amplifier.

Selection of speaker amplifier

playback path

Selection of headphone amplifier

playback path

SPINSEL

HPINSEL

Speaker Amplifier Input Control

Headphone Amplifier Input Control

* Please refer to Sound Effect Mode Register for Filter Block. When Filter Block is connected with the recording route, nothing is processed in the

reproduction route.

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Filter (5bands-Programmable IIR Filter)

A five bands equalizer features a second-order IIR type Band Pass Filter. Volume control of MUTE, -71.5dB to +12dB

(0.5dB step) can be controlled at all paths.

Each channels of the filter can be selected parallel connection or serial connection

The followings are block diagrams at parallel connection and serial connection

Coefficient(a0, a1) X 5ch gain X 5ch

Input

Band0-IIR

Band1-IIR

Coefficient(a0, a1) X 5ch

gain X 5ch

Input

Output

Band2-IIR

Band4-IIR

Band0-IIR

Band1-IIR

Band2-IIR

Band3-IIR

Band4-IIR

Output

Parallel connection

Figure 29

Serial connection

Figure 30

The filter coefficient is programmable. From required center frequency and band width, Programmable Equalizer

Coefficient-a0 Control Register and Programmable Notch Filter Coefficient-a1 Control Register value is decided. Followings

are the setting formula.

a0 = (1 - tanπf_b/fs) / (1 + tanπf_b/fs)

a1 = - 2cos2πf₀/fs / (1 + tanπf_b/fs)

f0: Band center frequency [Hz]

fb: -3dB band width [Hz]

fs: Sampling frequency [Hz]

* Actual setting value is an integral number that the result of above formula multiplied by 2¹⁴then round up numbers of five

and above and round down anything under five to a integer.

DSP filtering function: ON / OFF

DSP Filter Function Enable register can set ON or OFF of each filter function. Please change this register when

RECPLAY bit is 0x0. If this register is changed on playback or recording, the noise may be generated.

ALC Auto Level Control

Please refer the application note “AutoLevelControlApplicationNote”.

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P²Bass+ (Perfect Pure Bass Plus)

Please refer the application note.

Soft clip limiter

Soft clip function is reduced power comsumption. If ALC cannot be responded to input waveform, soft clip function is

reduced input waveform. In case of input waveform is overed threshold level, soft clip reduce output waveform.

SCGAIN=2

SCGAIN=1

SCGAIN=1/2

SCGAIN=1/4

SCGAIN=1/64

Soft Clip Gain

(SCGAIN)

Soft Clip Threshold

(SCTHRH, SCHTRM, SCHTRL)

0xFFFFFF

0x000000

IN

Figure 31

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Low Power Consumption Operation

When PCM data is inputted into LSI consecutive "0" is detected, it will disable the output amplifier automatically and

perform low power consumption mode operation by stopping the internal clock. When data except “0” are inputted, it will

automatically return to original movement.

When "0" is detected in both LCHRCH, this function is effective. When you use only LCH, please input "0" data into the

RCH side. When you use only RCH, please input "0" data into the LCH side. This function is effective only at the time of the

playback of the speaker amplifier. At the time of headphones amplifier playback and the recording, please set it to disable.

In addition, set the enable function and "0" count level in Zero Detection Setting Register.

Low power operation

Normal operation

Normal

operation

Figure 32

Change of the SP/HP playback

When it changes of Speaker Amplifier and Headphone Amplifier, it prepares for COEFSEL bit because it does not perform

the re-setting of filter coefficients. A side register is used when COEFSEL bit is "0". B side register is used when COEFSEL

bit is "1". The target registers are as follows. Please be careful in setting addresses.

A side register

INDEX(R)

0x24/0x26/0x28

0x46

B side register

INDEX(R)

0x2a/0x2c/0x2e

0x46

Register

-

MAP

2

0

2

P²BASS+ Parameter0/1/2

Play HPF2 Setting

0x4c/0x4e

0x5c

0x4c/0x4e

0x5c

Play Programmable HPF2L/H Coef

Sound Effect Mode

0x66

0x70

0x3e

0x66

0x70

0x73

DSP Filter Function Enable

Playback Effect Volume Control

Playback Digital Attenuator Control

EQ Band0/1/2/3/4 Gain Setting

Programmable Equalizer Band0/1/2/3/4

Coefficient-a0/a1 L/H

0x74 to 0x7c

0

0x80 to 0xa6

2

0x7e to 0xa4

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Analog block

VMID is used as analog circuit reference voltage for both recording path and playback path. Therefore, both case for

recording and playback, VMID need to do power up. At the power up, the wait time in proportion to the capacitor value is

needed to charge external capacitor connected with VMID pin. If recording and playback start before completion of charge,

it may generate noise. The following is a sequence of recommendation. Refer to the Analog Reference Power Management

Register for the function of VMIDCON.

.

VMID Power UP/DOWN Sequence (External capacitor 1uF)

Power Up

Power Down

1/2 Regout Level

vmid

( 0V )

Power Down

0x0

Charge Time

Record or Playback Power Down

0x0

0x2

VMIDCON

0x1

Min 5ms

Figure 33

Playback Path

The LSI can be executed sound output from 4 paths bellow. The output can be selected by Speaker Amplifier Output

Control Resister and Analog Reference Power Management Register.

Digital Input (SAI) → DAC → D-class Speaker Amplifier

Digital Input (SAI) → DAC → AB-class Speaker Amplifier

Digital Input (SAI) → DAC → Headphone Amplifier

Analog Microphone Input (MIN pin) → ADC → DAC → Headphone Amplifier

No guaranty of record path sound quality during speaker amplifier active.

Speaker amplifier

The speaker amplifier of BU26154 can choose operation mode among one of D-class operation or the AB-class operation.

It can prevent interference with FM radio influence by making AB-class operation.

It performs the change of the enable / disable setting of the speaker amplifier and the AB-class/D-class operation in

Speaker Amplifier Power Management Register.

Headphones amplifier

The headphones amplifier of BU26154 operates in a ground reference. Therefore the LSI can delete the condenser for the

AC coupling to get outside. In addition, the LSI can suppress a POP noise when you want to suppress a POP noise by

connecting the optional resistance of the chart below outside.

Left

Headpphone Amplifier

BU26154

option

HPL

option

HPR

Right

Headpphone Amplifier

Figure 34

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In addition, it is necessary to operate LDO for headphone amplifier when operating headphones amplifier. The power up of

headphones amplifier and LDO for headphone set in Analog Reference Power Management Register. Please power up the

headphones amplifier after 1mS waiting time for LDO for headphones. At the time of the power down, please power down

HPVDD after the power down of the headphones amplifier.

HPVDD Power UP/DOWN Sequence

Power Up

HP Power Down

HPVDD Power Down

Regout Level

HPVDD

( 0V )

Power Down

HPVDD Power up

HP Power up and Playback

HP Power Down HPVDD Power Down

HPVDDEN

HPLEN or HPREN

Min 1ms

Min 0ms

Figure 35

About HPCOM pin

HPCOM pin is a signal ground pin of the headphones amplifier.

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Microphone amplifier

The microphone input can support two modes, a single-end and differential. When using it in single-end input, it writes "0" in

the MINDIF bit of the MIC Interface Control register. When using differential input, it writes "1".

In the case of single-end input, it can input from MINP pin or MINN pin. Please set of the input pin in MIC Select Control

Register.

Microphone bias

The Case of using Microphone bias, it shows a recommended connection diagram. By all means, please connect a

condenser (2.2uF at the minimum) to MBIASCAP outside pin. On this occasion, the LSI can improve noise characteristics

by connecting the option resistance on the chart below (the optional resistance is up to 50 Ω).

BU26154

MicBiasAmplifier

option

MBIASCAP

2.2uF

Figure 36

In addition, according to the capacity of the outside condenser, it is necessary to wait until microphone bias is stable.

In waiting time of MICBIAS, please set the value of the MICTIME bit at the MIC Input Charging Time register.

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Touch Screen Controller

SAR 12 bits ADC is integrated into this LSI and is available as 4 lines type touch screen controller.

There is the function of the X-axis, the position sensing of the Y-axis, the pen pressure detection and the pen interrupt

detection.

It becomes independent to Codec and is controllable without minding timing. But the hard reset (reset signal input by

RESETB pin) communizes it.

Clock control

When enabled clock is to be used for touch screen controller, set TCLKEN bit of Clock Enable Register to "1". The touch

screen controller function uses a built-in oscillator. Therefore it is not necessary to perform clock control listing in item

clock control when using only the touch screen controller.

Position sensing

This LSI is available for the position sensing of the touch screen. The twice measurement of the X-axis measurement, the

Y-axis measurement is necessary for position sensing.

BU26154

XP

YP

XP

YP

refp

refn

refp

refn

ainp

ainn

ainp

ainn

YN

XN

YN

XN

At the time of the X-axis plate measurement

The Pen Pressure Detection

At the time of the Y-axis plate measurement

Figure 37

The measurement of touch pressure is carried out to measure the resistance between X plate and Y plate. It is calculable

by two methods, from the location information by location determination, and the measurement result in touch pressure

measurement mode.

In case of X-Position and Y-Position are known

Touch pressure resistance = X-plate resistance*(X-position/4096)*[(4096/Z1)-1] - Y-plate resistance*[1-(Y-position/4096)]

In case of X-Position is known

Touch pressure resistance = X-plate resistance*(X-position/4096)*[(Z2/Z1)-1]

BU26154

XP

YP

XP

YP

refp

refn

refp

refn

ainp

ainn

ainp

ainn

YN

XN

YN

XN

At the time of Z1 point measurement

At the time of Z2 point measurement

Figure 38

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The Pen Interrupt Detection

Touch detect function outputs the X-plate and Y-plate contact from IRQB pin. Please refer to Description of Registers for

valid or invalid setup of Touch Detection. When X-plate and Y-plate do not contact, H level is outputted from IRQB pin by

internal pull-up resister (typical 10kohm). When X-plate and Y-plate contact, L level is outputted from IRQB pin by touch

plate resistance (about hundreds ohm). Please refer to Description of Registers for IRQB output selection. Touch Detect

schematic diagram is shown below.

BU26154

Typ.50koh

m

XP

YP

IRQB

YN

XN

Interrupt detect circuit

Figure 39

IRQB pin outputs "L" during RESETB "L"(RESET state) period. During this period, please mask interrupt.

RESETB

IRQB

Valid

Min: 1ms

Interrupt timing

Figure 40

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About Touch Panel Interface at Interrupt Wait

Touch panel interface can switch to low power consumption by stopping the operation of unnecessary circuits at interrupt

wait.

Setting of touch panel interface at interrupt wait

0x2d = 0x00, // Thermal detect circuit Disable

0x1d = 0x02, // MAPCON=2

0x05 = 0x22, // Level shifter for headphone OFF

0x13 = 0x00, // Reference current circuit for audio system OFF

0x1d = 0x00, // MAPCON=0

0x0d = 0x80, // Touch panel interface oscillation circuit Enable

0x1d = 0x01, // MAPCON=1

0x61 = 0x38, // Touch panel interface interrupt circuit Enable

0x1d = 0x00, // MAPCON=0

0x0d = 0x00, // Touch panel interface oscillation circuit Disable

This state is interrupt wait mode. Please use a touch panel interface after interrupt, setting enable oscillation circuit.

Please, set circuit from Disable to Enable in circuit when using of audio system function

Setting at using of audio system function

0x2d = 0x01, // Thermal detect circuit Enable

0x1d = 0x02, // MAPCON=2

0x05 = 0x26, // Level shifter for headphone ON

0x13 = 0x01, // Reference current circuit for audio system ON

0x1d = 0x00, // MAPCON=0

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Operating Mode

Normal operating mode

It becomes Normal operating mode by setting Touch ADC Control registerTCHA2=0x1. Next AD conversion starts by

reading register value of ADCR1 register (8Bit mode) or ADCR2 register (12Bit mode), at Normal operating mode.

TCLKEN Bit

Internal Clk

I2C Operation

Write Data reception

Slave address receptio Read Data reception

INDEX=0x64

INDEX=0x61,TCHEN="1"

SCL

SDA

D2

D1

D0 ACK

1

0

R

ACK D7

D6

D5

Internal ADC Start Sync

ADC Status

IDLE

Data Hold

AD Conversion1_1

AD Conversion1_2

Data Valid1_1

IDLE

Data Hold

AD Conversion2_1

AD Conversion2_2

Data Valid2_1

IDLE

ADCR1Register

ADCR2 Register

Data Valid1_2

Data Valid2_2

Tw_ADC1

Tw_ADC2

Tw_ADC1

Tw_ADC2

12Bit Normal Mode I2C Timing

TCLKEN Bit

Internal Clk

I2C Operation

Write Data reception

Slave address receptio Read Data reception

INDEX=0x62

INDEX=0x61,TCHEN="1"

SCL

SDA

D2

D1

D0 ACK

1

0

R

ACK D7

D6

D5

Internal ADC Start Sync

ADC Status

IDLE

Data Hold

AD Conversion1

IDLE

Data Hold

AD Conversion2

IDLE

ADCR1Register

ADCR2 Register

Data Valid1

Data Valid2

Tw_ADC1

8Bit Normal Mode I2C Timing

AD conversion starts by rising edge of CSB at using SPI. 12Bit timing mode chart is listed below. 8Bit mode start timing is

similar it.

TCLKEN Bit

Internal Clk

SPI Operation

Write Data

Read Data

INDEX=0x61,TCHEN="1"

INDEX = 0x64

SCLK

CSB

Internal ADC Start Sync

ADC Status

IDLE

Data Hold

AD Conversion1_1

AD Conversion1_2

Data Valid1_1

IDLE

Data Hold

AD Conversion2_1 AD Conversion2_2

Data Valid2_1

Idle

ADCR1Register

ADCR2 Register

Data Valid1_2

Data Valid2_2

Tw_ADC1

Tw_ADC2

Tw_ADC1

Tw_ADC2

8Bit Normal Mode SPI Timing

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Auto Operation Mode

When TCHA2 bit of Touch ADC Control register is set to "0", BU26154MUV is set to Auto Operation Mode. When is to set

in Auto Mode Operation, BU 26154 MUV is Interrupt mode by reading to ADCR2 register in 12 bit mode and BU 26154

MUV is Interrupt mode by reading to ADCR1 register in 8 bit mode.

TCLKEN Bit

Internal Clk

I2C Operation

Write Data reception

Slave address receptio Read Data reception

INDEX=0x64

INDEX=0x61,TCHEN="1"

SCL

SDA

D2

D1

D0 ACK

1

0

R

ACK D7

D6

D5

Internal ADC Start Sync

ADC Status

IDLE

Data Hold

AD Conversion1_1

AD Conversion1_2

Data Valid1_1

IDLE

Interrupt Mode

ADCR1Register

ADCR2 Register

Data Valid1_2

Tw_ADC1

Tw_ADC2

12Bit Auto Mode I2C Timing

TCLKEN Bit

Internal Clk

I2C Operation

Write Data reception

Slave address receptio Read Data reception

INDEX=0x62

INDEX=0x61,TCHEN="1"

SCL

SDA

D2

D1

D0 ACK

1

0

R

ACK D7

D6

D5

Internal ADC Start Sync

ADC Status

IDLE

Data Hold

AD Conversion1_1

IDLE

Interrupt Mode

ADCR1Register

ADCR2 Register

Data Valid1_1

Tw_ADC1

8Bit Auto Mode I2C Timing

TCLKEN Bit

Internal Clk

SPI Operation

Write Data

Read Data

INDEX=0x61,TCHEN="1"

INDEX = 0x64

SCLK

CSB

Internal ADC Start Sync

ADC Status

IDLE

Data Hold

AD Conversion1_1

AD Conversion1_2

Data Valid1_1

IDLE

Interrupt Mode

ADCR1Register

ADCR2 Register

Data Valid1_2

Tw_ADC1

Tw_ADC2

12Bit Auto Mode SPI Timing

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Register function explanation

Register map

Note: “-” indicates a reserved bit. They return “0” for read. Write “0” to the bit every time. If “1” is written to this bit, the

operations cannot be guaranteed.

Don’t write data to empty INDEX or register bit to guarantee normal operation.

A function with (*)bit doesn’t need internal clock to change state.

The following registers are accessible at the time of MAPCON=0x0 of the Register Map Control register (0x1c/0x1d).

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INDEX

b07

b06

b05

b04

b03

b02

b01

b00

Register Name

Note

R

W

(Initial)

SR

0x00

0x0c

0x0e

0x10

0x12

0x14

0x1c

0x20

0x22

0x24

0x26

0x2c

0x2e

0x30

0x3a

0x3e

0x46

0x48

0x4a

0x4c

0x4e

0x58

0x5a

0x5c

0x60

0x62

0x64

0x66

0x68

0x6a

0x6c

0x70

0x72

0x74

0x01

-

Sampling

-

0

PLLOE

0

MCLKEN

0

Rate Setting

Clock Enable

0x0d

0x0f

TCLKEN

-

MCLKOE

PLLEN

-

0

-

0

PLLISEL

CLKSEL

-

Clock Input/Output

Control

-

0

-

0

-

0

-

0

SOFTRST

0

0x11

0x13

0x15

0x1d

0x21

0x23

0x25

0x27

0x2d

0x2f

-

Software Reset

-

RECPLAY

0

-

Record/Playback

Running Control

Mic Input Charging

Time

-

0

MCTIME

-

0

MAPCON

-

Register MAP

Control

-

0

VMIDCON

HPREN

HPLEN

-

HPVDDEN

MICBEN

0

Analog Reference Power

Management

0

-

0

-

PGAATT

-

PGAEN

ADCREN

ADCEN

-

Analog Input Power

Management

-

0

-

0

-

0

-

DACREN

DACLEN

-

DAC Power

-

0

-

Management

SPMDSEL

AVREN

COEFSEL

-

SPEN

AVLEN

Speaker Amplifier Power

Management

0

-

0

-

0

-

1

0

-

TSDEN

Thermal Shutdown

Control

-

ZCEN

0

1

-

Zero Cross Cmparator

Power Management

MICBIAS

note1

-

MICBCON

0x31

0x3b

0x3f

-

AVVOL

0

1

0

1

Voltage Control

Analog Volume

Control

0

1

PDATT

Playback

1

-

1

-

1

Digital Attenuator Control

Play HPF2

PLHPF2CUT

0x47

0x49

0x4b

0x4d

0x4f

HPF2CSEL

PLHPF2OD PLHPF2EN

0

-

0

-

0

-

0

-

0

AVFADE

0

Setting

AVMUTE

Amplifier Volume Control

Function Enable

Amplifier Volume

Fader Control

0

AVFCON

0

PHPF2C0L

Play Programable HPF2

CoefL

0

-

0

-

0

PHPF2C0H

-

Play Programable HPF2

CoefH

0

-

0

-

OSRSEL

0x59

0x5b

0x5d

0x61

0x63

0x65

0x67

0x69

0x6b

0x6d

0x71

0x73

0x75

-

DAC Clock Setting

-

0

-

MINVOL

-

MINDIF

Mic Interface

Control

1

0

-

0

-

0

SEMODE[2:0]

SEMODE[7]

0

-

Sound Effect Mode

-

0

PCMFO24

FMTO

MSBO

ISSCKO

AFOO

DLYO

WSLO

SAI Transmitter

Control

1

0

PCMFI24

FMTI

MSBI

ISSCKI

AFOI

DLYI

WSLI

SAI Receiver

Control

1

0

-

BSWP

-

MST

SAI Mode

-

0

-

0

select

HPF2OD

EQ4EN

EQ3EN

EQ2EN

EQ1EN

EQ0EN

HPF2EN

HPF1EN

DSP Filter Function

Enable

0

-

0

-

0

-

0

DVMUTE

0

DVFADE

0

-

0

RALCEN

0

1

PALCEN

0

Digital Volume Control

Function Enable

Mixer & Volume

Control

DVFCON

RMCON

LMCON

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

RDVOL

Record

1

0

Digital Attenuator Control

Playback

Effect VOL

1

-

Effect Volume Control

RALCVOL

0

note1

Record ALC Volume Control

EQ Band0

EQGAIN0

1

0

Gain Setting

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INDEX

b07

b06

b05

b04

b03

b02

b01

b00

Register Name

Note

R

W

(Initial)

EQGAIN1

0x76

0x78

0x7a

0x7c

0x7e

0x80

0x82

0x84

0x86

0x88

0x8a

0x8c

0x8e

0x90

0x92

0x94

0x96

0x98

0x9a

0x9c

0x9e

0xa0

0xa2

0xa4

0xa6

0xb2

0xb4

0xb8

0xba

0xbc

0xbe

0xc0

0xc2

0x77

EQ Band1

Gain Setting

1

0

1

0

1

0

1

0

EQGAIN2

0x79

0x7b

0x7d

0x7f

EQ Band2

0

Gain Setting

EQGAIN3

EQGAIN4

EQ Band3

Gain Setting

EQ Band4

1

-

1

-

1

-

0

-

0

-

1

HPF2CUT

0

Gain Setting

High Pass Filter2

Cut-off Control

EQ0A0L

EQ0A0H

EQ0A1L

EQ0A1H

EQ1A0L

EQ1A0H

EQ1A1L

EQ1A1H

EQ2A0L

EQ2A0H

EQ2A1L

EQ2A1H

EQ3A0L

EQ3A0H

EQ3A1L

EQ3A1H

EQ4A0L

EQ4A0H

EQ4A1L

EQ4A1H

0x81

0x83

0x85

0x87

0x89

0x8b

0x8d

0x8f

Programable Equalizer Band0

Coefficient-a0 (L)

0

1

Programable Equalizer Band0

Coefficient-a0 (H)

Programable Equalizer Band0

Coefficient-a1 (L)

Programable Equalizer Band0

Coefficient-a1 (H)

Programable Equalizer Band1

Coefficient-a0 (L)

Programable Equalizer Band1

Coefficient-a0 (H)

Programable Equalizer Band1

Coefficient-a1 (L)

Programable Equalizer Band1

Coefficient-a1 (H)

0x91

0x93

0x95

0x97

0x99

0x9b

0x9d

0x9f

Programable Equalizer Band2

Coefficient-a0 (L)

Programable Equalizer Band2

Coefficient-a0 (H)

Programable Equalizer Band2

Coefficient-a1 (L)

Programable Equalizer Band2

Coefficient-a1 (H)

Programable Equalizer Band3

Coefficient-a0 (L)

Programable Equalizer Band3

Coefficient-a0 (H)

Programable Equalizer Band3

Coefficient-a1 (L)

Programable Equalizer Band3

Coefficient-a1 (H)

0xa1

0xa3

0xa5

0xa7

0xb3

0xb5

0xb9

0xbb

0xbd

0xbf

Programable Equalizer Band4

Coefficient-a0 (L)

Programable Equalizer Band4

Coefficient-a0 (H)

Programable Equalizer Band4

Coefficient-a1 (L)

Programable Equalizer Band4

Coefficient-a1 (H)

0

-

0

-

0

-

RALCATK

-

Record ALC

note1

-

0

Attack Time Control

Record ALC

RALCDCY

-

0

RALCLVL

1

Decay Time Control

Record ALC

-

1

-

0

-

1

Target Level Control

Record ALC

RALCMINGAIN

0

-

0

Min Gain Control

RSATMINGAIN

RSATEN

Record ALC

0

-

0

-

1

-

0

-

0

-

0

-

1

0

Satulation Detect Control

Record ALC Zero Cross

Time Out Control

RALCZCTM

note1

0

1

PALCATK

0xc1

0xc3

Playback ALC

0

1

Attack Time Control

Playback ALC

PALCDCY

0

Decay Time Control

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INDEX

b07

b06

b05

b04

b03

b02

b01

b00

Register Name

Note

R

W

(Initial)

PALCLVL

0

0xc4

0xc6

0xc8

0xca

0xcc

0xce

0xdc

0xe8

0xc5

-

Playback ALC

note1

1

-

1

0

Target Level Control

Playback ALC

Min Gain Control

Playback ALC

Volume Control

Playback ALC ZeroCross

TimeOut

PALCMINGAIN

0

0xc7

0xc9

0xcb

0xcd

0xcf

-

note1

-

0

PALCVOL

0

-

1

-

0

-

0

-

0

PALCZCTM

-

0

RALCFRTH

RALCFRSP

RALCFREN

ALC

0

1

0

1

Fast Release Setting

Playback Limiter

Fast Release Setting

Zero Detection

Setting

PALCFRTH

PALCFRSP

PALCFREN

0

-

0

ZDTIME

0xdd

0xe9

-

ZDEN

0

-

0

-

0

-

0

-

MIN2EN

0

MIN1EN

1

MIC select

Control

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The following registers are accessible at the time of MAPCON=0x1 of the Register Map Control register (0x1c/0x1d).

INDEX

b07

b06

b05

b04

b03

b02

b01

b00

Register Name

Note

R

W

(Initial)

FPLLM

0

0x02

0x04

0x06

0x08

0x0a

0x0c

0x0e

0x10

0x12

0x1c

0x20

0x22

0x24

0x26

0x28

0x60

0x62

0x64

0x82

0x84

0xa0

0xa2

0xa4

0xa6

0xa8

0xaa

0xda

0xde

0xe0

0xe2

0xe4

0xe6

0xe8

0x03

-

FPLL M setting

0

FPLLNL

0x05

0x07

0x09

0x0b

0x0d

0x0f

FPLL N Setting(L)

FPLL N Setting(H)

FPLL D Setting

0

-

0

-

0

-

0

-

0

-

0

-

0

FPLLNH

0

-

FPLLD

0

FPLLFL

FPLLFH

FPLL F Setting(L)

FPLL F Setting(H)

FPLL F_D Setting(L)

FPLL F_D Setting(H)

FPLL V setting

0

FPLLFDL

FPLLFDH

0

0x11

0x13

0x1d

0x21

0x23

0x25

0x27

0x29

0x61

0x63

0x65

0x83

0x85

0xa1

0xa3

0xa5

0xa7

0xa9

0xab

0xdb

0xdf

0

-

0

-

0

-

0

-

FPLLV

0

-

0

-

0

MAPCON

RegisterMAP

Control

0

-

0

SCEN

0

Soft Clip Enable

SCTHRH

0

Soft Clip Threshold H

Soft Clip Threshold M

Soft Clip Threshold L

Soft Clip Gain

0

SCTHRM

0

SCTHRL

0

-

0

-

1

0

SCGAIN

0

-

TCHSEN

0

-

TCHA2

1

-

TCHA1

1

-

TCHA0

1

TCHRSEL TCHMODE

Touch ADC Control

Touch ADC result1

Touch ADC result2

0

ADCR1

0

-

0

ADCR2

-

0

-

0

-

0

-

HPLIN1EN

0

HPRIN2EN HPRIN1EN

-

Headphone input

Select Control

0

-

0

-

SPVOL

SPIN2EN

SPIN1EN

SPAMP input Control

0

-

0

-

0

PLPFOD

0

PLPFEN

0

Play Programable LPF

Setting

PLPFC0L

Play Programable LPF

Coef (L)

0

PLPFC0H

Play Programable LPF

Coef (H)

0

-

0

-

0

-

0

-

0

-

0

-

0

RLPFOD

0

RLPFEN

0

Rec Programable LPF

Setting

RLPFC0L

RLPFC0H

Rec Programable LPF

Coef (L)

0

Rec Programable LPF

Coef (H)

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

NGEN

0

Noise GateꢀSetting

note1

NGMINGAIN

Noise Gate

Minimum Gain

Noise Gate

Threshold

1

-

1

-

0

1

0

1

0

NGTH

0xe1

0xe3

0xe5

0xe7

0xe9

0

-

1

-

0

1

NGTHHYS

1

-

Noise Gate

Threshold Hysteresis

Noise Gate

Slope

-

NGSLOPE

0

-

0

1

-

0

-

1

-

0

NGGAINSTEP

-

Noise Gate

Gain Step

-

1

NGZTIM

0

NGENVAVE

0

Noise Gate

Time Setting

0

1

0

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INDEX

b07

(Initial)

b06

b05

b04

b03

b02

b01

b00

Register Name

Note

note1

R

W

NGFDOUT

NGFDIN

0xea

0xec

0xee

0xf0

0xf2

0xf4

0xeb

Noise Gate

Fade Control

Noise Gate

0

1

0

1

0

1

0

NGENVMONL[7:0]

0xed

0xef

0xf1

0xf3

0xf5

0

Envelope Monitor Lch(L)

Noise Gate

NGENVMONL[15:8]

note1

0

Envelope Monitor Lch(H)

Noise Gate

NGENVMONR[7:0]

0

Envelope Monitor Rch(L)

Noise Gate

NGENVMONR[15:8]

0

Envelope Monitor Rch(H)

Noise Gate

NGGAINMON

0

Gain Monitor

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The following registers are accessible at the time of MAPCON=0x2 of the Register Map Control register (0x1c/0x1d).

INDEX

b07

b06

b05

b04

b03

b02

b01

b00

Register Name

Note

R

W

(Initial)

0x00

0x04

0x12

0x1c

0x24

0x26

0x28

0x2a

0x2c

0x2e

0x04

0x12

0x1c

0x46

0x4c

0x4e

0x5c

0x66

0x70

0x72

0x74

0x76

0x78

0x7a

0x7c

0x7e

0x80

0x82

0x84

0x86

0x88

0x8a

0x8c

0x8e

0x90

0x92

0x94

0x96

0x01

-

1

-

1

-

EXMODE

PLL External Components

Setting Register

Audio Analog

-

1

0x05

0x13

0x1d

0x25

0x27

0x29

0x2b

0x2d

0x2f

HPLSEN

-

1

-

AREFI1EN

1

Control2

Audio Analog

Contrl1

RegisterMAP

MAPCON

0

Control

P2BLPF1A

P2BHPF1A

P2 Bass+ Parameter0A

0

-

0

P2BGAINBSA

0

P2BLPF2A

P2 Bass+ Parameter1A

P2 Bass+ Parameter2A

P2 Bass+ Parameter0B

P2 Bass+ Parameter1B

P2 Bass+ Parameter2B

0

P2BGAINEVA

P2BGAINODA

0

P2BLPF1B

P2BHPF1B

0

-

0

P2BGAINBSB

0

P2BLPF2B

0

P2BGAINEVB

P2BGAINODB

0

-

0

-

0

-

0

-

0

-

0

HPLSEN

0

-

1

-

0

-

0x05

0x13

0x1d

0x47

0x4d

0x4f

Audio Analog

Control2

1

-

1

-

AREFI1EN

1

-

Audio Analog

Contrl1

RegisterMAP

Control

-

MAPCON

-

0

ＰＬHPF2CUTB

0

ＰＬHPF2ODB ＰＬHPF2ENB

HPF2CSELB

0

Play HPF2B

0

PHPF2C0LB

Play Programable HPF2

CoefL B

0

-

0

-

0

-

0

PHPF2C0HB

Play Programable HPF2

CoefH B

0

SEMODE[2:0]

0

0x5d SEMODE[7]

-

Sound Effect Mode B

0

-

EQ3ENB

0

-

EQ2ENB

0

-

EQ1ENB

0

EQ0ENB

0

0x67

0x71

0x73

0x75

0x77

0x79

0x7b

0x7d

0x7f

HPF2ODB EQ4ENB

HPF2ENB HPF1ENB

Filter Func

Enable B

0

1

0

1

0

1

0

1

0

Effect VOLB

Playback

1

0

1

0

1

0

Effect Volume Control B

Playback

PDATTB

1

0

Digital Attenuator Control B

EQ gain

EQGAIN0B

EQGAIN1B

EQGAIN2B

EQGAIN3B

EQGAIN4B

EQ0A0LB

EQ0A0HB

EQ0A1LB

EQ0A1HB

EQ1A0LB

EQ1A0HB

EQ1A1LB

EQ1A1HB

EQ2A0LB

EQ2A0HB

EQ2A1LB

EQ2A1HB

EQ3A0LB

Band0 B

EQ gain

Band1 B

EQ gain

Band2 B

EQ gain

Band3 B

EQ gain

Band4 B

EQ Band0

Coef0L B

EQ Band0

Coef0H B

EQ Band0

Coef1L B

EQ Band0

Coef1H B

EQ Band1

Coef0L B

EQ Band1

Coef0H B

EQ Band1

Coef1L B

EQ Band1

Coef1H B

EQ Band2

Coef0L B

EQ Band2

Coef0H B

EQ Band2

Coef1L B

EQ Band2

Coef1H B

EQ Band3

Coef0L B

0x81

0x83

0x85

0x87

0x89

0x8b

0x8d

0x8f

0x91

0x93

0x95

0x97

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INDEX

b07

b06

b05

b04

b03

b02

b01

b00

Register Name

Note

R

W

(Initial)

0x98

0x9a

0x9c

0x9e

0xa0

0xa2

0xa4

0x99

EQ3A0HB

EQ Band3

Coef0H B

EQ Band3

Coef1L B

EQ Band3

Coef1H B

EQ Band4

Coef0L B

EQ Band4

Coef0H B

EQ Band4

Coef1L B

EQ Band4

Coef1H B

0

0x9b

0x9d

0x9f

EQ3A1LB

0

EQ3A1HB

EQ4A0LB

EQ4A0HB

EQ4A1LB

EQ4A1HB

0xa1

0xa3

0xa5

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Register details explanation

Note: “-” indicates a reserved bit. They return “0” for read. Write “0” to the bit every time. If “1” is written to this bit, the

operations cannot be guaranteed.

Don’t write data to empty INDEX or register bit to guarantee normal operation.

A function with (*)bit doesn’t need internal clock to change state.

Sampling Rate Setting Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

0

b02

0

b01

0

b00

0

R

W

(Initial)

0x00

0x01

-

SR

This register sets the sampling rate of the recording/playback. Please perform the change of this register level in

RECPLAY=0x0) at a recording/playback stop.

SR [3:0]

Setting

Explanation

8kHz

11.025 kHz

12kHz

16kHz

22.05 kHz

24kHz

32kHz

44.1 kHz

48kHz

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

Clock Enable Register

INDEX

MAPCON

0x0

b07

(Initial)

TCLKEN

0

b06

b05

b04

b03

b02

b01

b00

R

W

0x0c

0x0d

-

PLLOE

0

PLLEN

0

MCLKEN

0

This register is a register to control the operation of the clock.

MCLKEN

This bit sets permission / stop of the input of the MCLKI terminal. The input logic of the MCLKI terminal becomes invalid at

the time of the stop and clock is not transmitted to the LSI inside.

Setting

Explanation

MCLKI terminal input stop

A clock stops at the input first grade of the terminal

MCLKI terminal input permission

0

1

PLLEN

This bit sets movement / stop of PLL.

Setting

Explanation

0

1

PLL stop

PLL movement

After setting the PLL Setting register, please set PLLEN bit to "1".

PLLOE

This bit is to set the status of PLL output. Set this bit to “1” after PLL operation has stabilized. Also, this bit must be set to

“1” if PLL is not used, otherwise internal clock cannot be provided.

Setting

Explanation

0

1

The PLL output is put under ban

PLL output permission

TCLKEN

This bit sets the clock for the touch panel interface circuit.

TCLKEN

Explanation

0

1

Disable clock for the touch panel interface.

Enable clock for the touch panel interface.

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Clock Input / Output Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

0

b02

0

b01

b00

0

R

W

(Initial)

0x0e

0x0f

-

PLLISEL

CLKSEL

0

This register is to select internal clock. It is to use or not use and to create MCLKI input or internal clock divided PLL.

CLKSEL[2:0]

Choose a clock to be use

Setting

Explanation

Using PLL lets you output 256fs clock from PLL.

The PLL output is just used inside this LSI.

0x0

Using PLL lets you output 512fs clock from PLL.

The clock that is divided by 1/2 the PLL output is used inside this LSI.

Using PLL lets you output 1024fs clock from PLL

The clock that is divided by 1/4 the PLL output is used inside this LSI.

Input 256fs clock to MCLKI terminal and PLL is not used.

MCLKI terminal input is just used in this LSI.

Input 512fs clock to MCLKI terminal and PLL is not used.

The clock that is divided by ½ the MCLKI terminal input is used inside this LSI.

Input 1024fs clock than MCLKI terminal and use it without using PLL.

The clock that is divided by 1/4 the MCLKI terminal input is used inside this LSI.

0x2

0x3

0x4

0x6

0x7

PLLISEL[1:0]

When this bit chooses to input clock into PLL and does not use PLL, please set register to 0x0.

Setting

Explanation

0x0

0x1

0x2

Prohibited from setting

Use MCLKI terminal input

Use BCLK terminal input

Software Reset Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x10

0x11

-

SOFTRST

0

This register is for software reset. CPU interface and this register are reset by writing SOFTRST bit to “1”. And then, write

“0” for releasing reset.

Record/Playback Running Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

0

b01

b00

0

R

W

(Initial)

0x12

0x13

-

RECPLAY

0

This register controls start / stop of the recording/playback operation of the LSI.

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RECPLAY [2:0]

This bit controls start / stop of the recording/playback operation of the LSI and it is feasible by recording and reproduction at

the same time and monitor recording data from the reproduction course, and please refer to "state transition item about the

recording reproduction control" for the transition between recording/playback states again. Transition between other states

is prohibited. Please move to the next movement once by all means after having let recording/playback movement make a

stop (RECPLAY=0x0).

TCLKEN

Explanation

Sound Stop STATE

Stop recording and playback.

Rec STATE

0x0

0x1

0x2

Recording start. Microphone input is converted from analog to digital, and transferred

through SAI.

Play STATE

Playback start. SAI received data is converted from digital to analog and output from

playback path.

Rec and Play STATE.

Simultaneously Recording and Playback start. Microphone input is converted from

analog to digital, and transferred through SAI and SAI received data is converted from

digital to analog and output from playback path.

0x3

0x7

Monitor STATE.

Monitoring the recording sound start. Microphone input is converted from analog to

digital, and transferred through SAI and this data is converted from digital to analog and

output from playback path.

MIC Input Charging Time Register

INDEX

MAPCON

0x0

b07

b06

b05

0

b04

0

b03

b02

MCTIME

b01

0

b00

0

R

W

(Initial)

0x14

0x15

-

0

This register is to select the wait time for microphone input load charge. The LSI work recording signal or playback signal

are mute when from RECPLAY is changed from 0x0 until MCTIME. This time contains required time of initializing DSP that

is 40/fs. It must be waited the setting time to start recording or playback.

MCTIME is valid at playback. If it is necessary to start up earlier on playback, please set MCTIME to 0x00. It is minimum

time.

.

MCTIME [5:0]

Setting

0x00

fs conversion

40/fs

Time (fs=48kHz)

0.8ms

0x01

128/fs

2.7ms

0x02

256/fs

5.3ms

0x03

384/fs

8.0ms

0x04 - 0x3D

0x3E

(128/fs / step)

7936/fs

:

165.3ms

168.0ms

0x3F

8064/fs

Note) the waiting time for microphone input load charge

It is a recommended value of MIN1 coupling capacitor at the charge time.

Charge waiting time

Capacitor

capacity

Charge waiting time (6 τ)

0.1µF

0.22µF

16ms

36ms

* Charge time is proportional to capacity of capacitor.

Register MAP Control Register

INDEX

MAPCON

ALL

b07

b06

b05

b04

b03

b02

b01

b00

0

R

W

(Initial)

0x1c

0x1d

-

MAPCON

0

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MAPCON

This register controls register MAP.

Setting

Explanation

0x0

0x1

0x2

0x3

It is accessible to register MAP0

It is accessible to register MAP1

It is accessible to register MAP2

This is prohibited from setting

Analog Reference Power Management Register

INDEX

MAPCON

0x0

b07

(Initial)

HPREN

0

b06

b05

b04

b03

b02

b01

b00

0

R

W

0x20

0x21

HPLEN

0

-

HPVDDEN MICBEN

VMIDCON

0

This register controls headphones amplifier, LDO for the charge pump, the power-up / down of the hole Rch standard

voltage generation circuit.

VMIDCON [1:0]

These bits control power up and down of the VMID generation circuit. Power up time can be reduced by using high speed

mode. VMID generation circuit should be changed to normal mode after high speed mode.

Setting

Explanation

0x0

power down

0x1

0x2

high speed mode power up

normal mode power up

MICBEN

It controls Microphone bias circuit.

Setting

Explanation

0

1

Power down

Power up

HPVDDEN

It controls HPAMP LDO for the charge pump.

Setting

0

1

Disables

Enables

HPLEN

It controls HPAMP. When using headphone, please set HPLEN/HPREN to "1".

Setting

Explanation

0

1

Disable(HPL)

Enable(HPL)

HPREN

It controls HPAMP. When using headphones , please set HPLEN/HPREN "1".

Setting

Explanation

0

1

Disable(HPR)

Enable(HPR)

Analog Input Power Management Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x22

0x23

-

PGAATT

0

-

PGAEN

0

-

ADCEN

0

-

This register controls the power-up / down of analog circuit.

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ADCEN

It controls power-up / down of the ADC.

Setting

Explanation

0

1

ADC power down

ADC power up

PGAEN

It controls the power-up / down of the microphone amplifier.

Setting

Explanation

Microphone amplifier power down

Microphone amplifier power up

0

1

PGAATT

It controls the gain of the microphone amplifier.

Setting

Explanation

0

1

Normal mode (0dB)

Attenuation mode (-9dB)

DAC Power Management Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x24

0x25

-

DACREN DACLEN

-

0

This register controls power-up / down of the DAC.

DACLEN

It controls the power-up / down of the DAC left.

Setting

Explanation

0

1

power down

power up

DACREN

It controls the power-up / down of the DAC right.

Setting

Explanation

0

1

power down

power up

Speaker Amplifier Power Management Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x26

0x27 SPMDSEL

0

-

AVREN COEFSEL

-

SPEN

0

AVLEN

0

1

This register controls speaker amplifier volume’s power-up / down.

b02 is H fix.

AVLEN

It controls power-up / down of the Lch analog volume.

AVLEN

0x0

0x1

Explanation

Lch analog volume power down

Lch analog volume power up

SPEN

I control the power-up / down of the speaker amplifier.

SPEN

0x0

0x1

Explanation

Speaker amplifier power down

Speaker amplifier power up

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COEFSEL

In BU26154, an A side, a B side prepare filter setting at the time of the reproduction, a volume setting register. The

register value of the A side, in the case of "1", I use a register level of the B side when this bit is "0".

COEFSEL

Explanation

0x0

0x1

It uses the register A side.

It uses the register B side.

AVREN

It controls power-up / down of the Rch analog volume.

AVREN

0x0

0x1

Explanation

Rch analog volume power down

Rch analog volume power up

SPMDSEL

It sets the speaker amplifier to D class or AB class. At the time of the change, set SPEN=0 before setting SPMDSEL.

SPMDSEL

0x0

0x1

Explanation

Set speaker amplifier to AB-class.

Set speaker amplifier to D-class.

Thermal Shutdown Control Register

MAPCON

0x00

INDEX

b07

(initial)

-

b06

b05

b04

b03

b02

b01

b00

R

0x2c

W

0x2d

-

TSDEN

1

TSDEN

It controls a thermal shut down function.

Setting

Explanation

0x0

0x1

disable

enable

Zero Cross Comparator Power Management Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x2e

0x2f

-

ZCEN

0

-

This register sets ON/OFF of the zero cross function of the digital volume.

ZCEN

This function is effective for EFFECT VOLUME and RDATT

Setting

Explanation

0

1

disable

enable

MICBIAS Voltage Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

0

b00

R

W

(Initial)

0x30

0x31

-

MICBCON

0

This register sets the output voltage reading of the microphone bias.

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MICBCON [1:0]

These bits are to set the MICBIAS. Set the MICBIAS voltage less than HVDD x 0.85.

Setting

0x0

0x1

0x2

The output voltage

REGOUT / 2 x 1.67V

REGOUT / 2 x 2.22V

REGOUT / 2 x 2.78V

REGOUT / 2 x 3.33V

0x3

Analog Volume Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

0

b03

1

b02

b01

1

b00

0

R

W

(Initial)

0x3a

0x3b

-

AVVOL

0

This register sets the Gain of the analog volume of Lch and Rch. The fader function of the AMP Volume Control Function

Enable register is also available.

AVOL[5:0]

0x3Fto0x1a

0x19

Gain[dB]

-

AVOL[5:0]

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

Gain[dB]

-2.0

+18.0

+17.0

+16.0

+15.0

+14.0

+13.0

+12.0

+11.0

+10.0

+8.0

-4.0

0x18

-6.0

0x17

-8.0

0x16

-12.0

-16.0

-20.0

-24.0

-28.0

MUTE

0x15

0x14

0x13

0x12

0x11

0x0f

0x0e

+7.0

0x0d

+6.0

0x0c

+4.0

0x0b

+2.0

0x0a

0.0

Playback Digital Attenuator Control Register

INDEX

MAPCON

0x0

b07

b06

b05

1

b04

1

b03

b02

1

b01

1

b00

1

R

W

(Initial)

0x3e

0x3f

PDATT

1

Playback Digital Attenuator Control Register B

INDEX

MAPCON

0x2

b07

b06

b05

1

b04

1

b03

b02

1

b01

1

b00

1

R

W

(Initial)

0x72

0x73

PDATTB

1

PDATT[7:0]/ PDATTB[7:0]/

This register sets the Gain of the digital volume

in the case of COEFSEL=0, the register level of PDATT is effective.

In the case of COEFSEL=1, the register level of PDATTB is effective.

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PDATT/

PDATTB

Gain

(dB)

PDATT

[7:0]

Gain

(dB)

PDATT

[7:0]

Gain

(dB)

PDATT

[7:0]

Gain

(dB)

This is

prohibited

from

0x00 - to

0x6E

0x93

-54.0

0xB8

-35.5

0xDD

-17.0

setting

MUTE

-71.5

-71.0

-70.5

-70.0

-69.5

-69.0

-68.5

-68.0

-67.5

-67.0

-66.5

-66.0

-65.5

-65.0

-64.5

-64.0

-63.5

-63.0

-62.5

-62.0

-61.5

-61.0

-60.5

-60.0

-59.5

-59.0

-58.5

-58.0

-57.5

-57.0

-56.5

-56.0

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

0x80

0x81

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x89

0x8A

0x8B

0x8C

0x8D

0x8E

0x8F

0x94

0x95

0x96

0x97

0x98

0x99

0x9A

0x9B

0x9C

0x9D

0x9E

0x9F

0xA0

0xA1

0xA2

0xA3

0xA4

0xA5

0xA6

0xA7

0xA8

0xA9

0xAA

0xAB

0xAC

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

0xB3

0xB4

-53.5

-53.0

-52.5

-52.0

-51.5

-51.0

-50.5

-50.0

-49.5

-49.0

-48.5

-48.0

-47.5

-47.0

-46.5

-46.0

-45.5

-45.0

-44.5

-44.0

-43.5

-43.0

-42.5

-42.0

-41.5

-41.0

-40.5

-40.0

-39.5

-39.0

-38.5

-38.0

-37.5

0xB9

0xBA

0xBB

0xBC

0xBD

0xBE

0xBF

0xC0

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC7

0xC8

0xC9

0xCA

0xCB

0xCC

0xCD

0xCE

0xCF

0xD0

0xD1

0xD2

0xD3

0xD4

0xD5

0xD6

0xD7

0xD8

0xD9

-35.0

-34.5

-34.0

-33.5

-33.0

-32.5

-32.0

-31.5

-31.0

-30.5

-30.0

-29.5

-29.0

-28.5

-28.0

-27.5

-27.0

-26.5

-26.0

-25.5

-25.0

-24.5

-24.0

-23.5

-23.0

-22.5

-22.0

-21.5

-21.0

-20.5

-20.0

-19.5

-19.0

0xDE

0xDF

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xE8

0xE9

0xEA

0xEB

0xEC

0xED

0xEE

0xEF

0xF0

0xF1

0xF2

0xF3

0xF4

0xF5

0xF6

0xF7

0xF8

0xF9

0xFA

0xFB

0xFC

0xFD

0xFE

-16.5

-16.0

-15.5

-15.0

-14.5

-14.0

-13.5

-13.0

-12.5

-12.0

-11.5

-11.0

-10.5

-10.0

-9.5

-9.0

-8.5

-8.0

-7.5

-7.0

-6.5

-6.0

-5.5

-5.0

-4.5

-4.0

-3.5

-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

0x90

-55.5

0xB5

-37.0

0xDA

-18.5

0xFF

(Prohibit

setting)

0x91

0x92

-55.0

-54.5

0xB6

0xB7

-36.5

-36.0

0xDB

0xDC

-18.0

-17.5

Play HPF2 Setting Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

0

b03

b02

0

b01

b00

R

W

(Initial)

HPF2CSEL

0

PLHPF2OD PLHPF2EN

0x46

0x47

-

PLHPF2CUT

0

Play HPF2 Setting Register B

This register is a setting register of HPF for the reproduction. In the case of COEFSEL=0, PLHPF2EN, PLHPF2OD,

PLHPF2CUT, the register level of HPF2CEL are effective. In the case of COEFSEL=1, PLHPF2ENB, PLHPF2ODB,

PLHPF2CUTB, the value of the HPF2CELB register become effective.

PLHPF2EN/ PLHPF2ENB

This bit is enables HPF for the reproduction.

PLHPF2EN/

Explanation

PLHPF2ENB

0

1

Disable

Enable

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PLHPF2OD/ PLHPF2ODB

This bit sets the degree of HPF for the reproduction.

PLHPF2OD/

Explanation

PLHPF2ODB

0

1

The second order

The first order

PLHPF2CUT/ PLHPF2CUTB

This bit sets the cut-off frequency of HPF for reproduction. In the case of "0", HPF2CEL becomes effective for setting this bit.

PLHPF2CUT/

Fs=8,16,32kHz

PLHPF2CUTB

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

80Hz

100Hz

130Hz

160Hz

200Hz

260Hz

320Hz

400Hz

HPF2CEL/ HPF2CELB

I make HPF at the time of the reproduction programmable, or I make it parametric, or this bit sets it.

HPF2CEL/

Explanation

HPF2CELB

0

1

PLHPF2CUT is effective.

PHPF2COEFL/H is effective.

Amplifier Volume Control Function Enable Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x48

0x49

-

AVMUTE AVFADE

0

This register controls the fading function of the analog volume.

AVFADE

It sets the fading function of the analog volume to ON/OFF.

AVFADE

Explanation

Fading function OFF

When a register set point of AVOL is just used for a real Volume

price and wants to do it and changes a value, setting of the

analog volume is updated immediately.

0

Fading function ON

When a register set point of AVOL was updated, a gain of the

analog volume changes by a +/-1 step towards a register set

point after the update in step time for AVFCON register setting.

1

AVMUTE

When this is set, mute becomes effective for the analog volume at the time of reproduction. It can control fading for the

mute shift by this bit by the analog volume forcibly by AVFADE.

AVMUTE

Explanation

0

As for the analog volume, a register set point of AVOL is effective.

At the time of re-start: The analog volume is set to MUTE.

It comes back to the setting Volume in AVOL by canceling it

because it writes it. This register level of AVOL cannot be

replaced by the setting of this bit.

1

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Amplifier Volume Fader Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

0

b01

b00

0

R

W

(Initial)

0x4a

0x4b

-

AVFCON

0

This register controls the amplifier volume fade function.

AVFCON[2:0]

These bits are to set the volume change step time of the amplifier volume fade function. The volume changes step by step

with this setting period. Step time is in proportion to sampling frequency (fs) as following table.

AVFCON[2:0]

fs conversion

time(fs=48kHz)

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

1/fs

4/fs

16/fs

20.8µs

83.3µs

333µs

1.33ms

5.33ms

21.3ms

85.3ms

341.ms

64/fs

256/fs

1024/fs

4096/fs

16384/fs

Play Programmable HPF2 CoefL Register

Play Programmable HPF2 CoefH Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

0

b02

b01

b00

R

W

(Initial)

0x4c

0x4d

PHPF2C0L

0

-

0

-

0

PHPF2C0H

0x0

0x4e

0x4f

0

Play Programmable HPF2 CoefL Register B

Play Programmable HPF2 CoefH Register B

INDEX

MAPCON

0x2

b07

b06

b05

b04

b03

b02

0

b01

b00

R

W

(Initial)

0x4c

0x4d

PHPF2C0LB

0

-

0

-

0

PHPF2C0HB

0x2

0x4e

0x4f

0

It is the register settings of the programmable high path filter cut-off frequency for the reproduction.

HPF2CSEL bit becomes effective when the register value is equal to "1".

If COEFSEL=0, then the register level of PHPF2C0L, PHPF2C0H is effective.

If COEFSEL=1, then the register level of PHPF2C0LB, PHPF2C0HB is effective.

PHPF2C0L [7:0]/ PHPF2C0LB [7:0]

PHPF2C0H [7:0]/ PHPF2C0HB [7:0]

This sets the cut-off frequency of the programmable high path filter for the reproduction.

Please refer for the setting method.

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DAC Clock Setting Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

0

b03

b02

b01

b00

R

W

(Initial)

0x58

0x59

-

OSRSEL

-

0

This register sets the DAC clock movement to be used in this LSI.

OSRSEL [1:0]

This register decides sampling frequency.

Setting

Explanation

0x0

0x1

0x2

8k,11.025k,12kHz

16k,22.05k,24kHz

32k,44.1k,48kHz

0x3

This is prohibited from setting

Mic Interface Control Register

INDEX

MAPCON

0x0

b07

b06

b05

0

b04

b03

b02

b01

b00

R

W

(Initial)

0x5a

0x5b

MINVOL

0

-

MINDIF

0

-

1

This register controls the microphone input interface.

MINDIF

It sets the MIC movement mode.

Setting

Explanation

0

1

Single-end mode

Differential mode

MINVOL

This bit sets the Analog MIC volume.

MINVOL

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

Gain

6dB

9dB

12dB

15dB

18dB

21dB

24dB

27dB

Sound Effect Mode Register

INDEX

MAPCON

0x0

b07

(Initial)

SEMODE[7]

0

b06

b05

b04

b03

b02

0

b01

b00

0

R

W

0x5c

0x5d

-

SEMODE[2:0]

0

Sound Effect Mode Register B

INDEX

MAPCON

0x2

b07

(Initial)

SEMODEB[7]

0

b06

b05

b04

b03

b02

0

b01

b00

0

R

W

0x5c

0x5d

-

SEMODEB[2:0]

0

If COEFSEL=0, then the register level of SEMODE is effective. If COEFSEL=1, then the value of the SEMODEB register

becomes effective.

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SEMODE [7]/SEMODEB [7]

You choose a course putting Filter Block, and please refer to the clause of "the signal flow" of "the function explanation" for

Filter Block.

SEMODE[7]/

Explanation

SEMODEB [7]

0

1

Use Filter Block on Recording path.

Use Filter Block on Playback path.

SEMODE [2:0]/ SEMODEB [2:0]

This sets distribution of EQ/Notch Filter.

SEMODE[2:0]/

Explanation

SEMODEB[2:0]

0x0

0x1

0x2

0x3

0x4

0x5

Notch5 band / EQ0 band

Notch4 band / EQ1 band

Notch3 band / EQ2 band

Notch2 band / EQ3 band

Notch1 band / EQ4 band

Notch0 band / EQ5 band

When "0x01" is set, Band0 to Band3 filters Notch, and Band4 becomes the EQ.

SAI Transmitter Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x60

0x61

PCMFO24

FMTO

0

MSBO

0

ISSCKO

0

AFOO

0

DLYO

0

WSLO

0

1

This register controls the SAI transmission format setting. The RECPLAY bit of the Record/Playback Running Control

register, please change this register in recording stop state (0x0), and please use it by setting again same as the SAI

reception side (SAI Receiver Control register).

WSLO

You appoint LRCLK polarity at the time of the transmission of this LSI, and please set this bit in "1" in (FMTO at the time of

"1") in a transfer mode by all means in the frame same period.

Setting

Explanation

Left channel transmission at SAI_LRCLK is “L” level; right

channel transmission at SAI_LRCLK is “H” level.

0

Left channel transmission at SAI_LRCLK is “H” level; right

channel transmission at SAI_LRCLK is “L” level.l

1

DLYO

This bit appoints 1 clock delay existence / nothing of transmission data.

Setting

Explanation

0

1

Serial data delay existence

Serial data delay nothing

AFOO

You appoint in front of filling / attacking the enemy from behind of transmission data, and, in the case of a slave mode, this

bit is ignored, and it is in previous final stage is fixed, and please set this bit in "0" in (FMTO at the time of "1") in a transfer

mode by all means in the frame same period.

Setting

Explanation

0

1

Left-justify

Right-justify

ISSCKO

This bit sets BCLK terminal to 32fs/64fs.

Setting

Explanation

0

1

32fs

64fs

MSBO

This bit sets the MSB first /LSB first data transmission.

Setting

Explanation

0

1

MSB first

LSB first

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FMTO

This bit sets the transmission mode.

Setting

Explanation

0

1

LRCLK transfer mode

Frame synchronization transfer mode

PCMFO24

This bit sets PCM format of the SAI transmission.

Setting

Explanation

0x2

0x3

16bit PCM

24bit PCM

Other than the

above

This is prohibited from setting

SAI Receiver Control Register

INDEX

MAPCON

0x0

b07

b06

1

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x62

0x63

PCMFI24

FMTI

0

MSBI

0

ISSCKI

0

AFOI

0

DLYI

0

WSLI

0

1

This register is a register controlling SAI reception format setting, and RECPLAY bit of the Record/Playback Running

Control register, please change this register in recording stop state (0x0), and please use it by setting again same as the

SAI transmission side (SAI Transmitter Control register).

WSLI

This bit selects LRCLK polarity of the LSI. This bit must be set to “1” when at Flame synchronous transfer mode (FMTI is “1”).

Setting

Explanation

Left channel is received when SAI_LRCLK is “L” level, right

channel is received at SAI_LRCLK is “H” level.

0

Left channel is received when SAI_LRCLK is “H” level, right

channel is received at SAI_LRCLK is “L” level.

1

DLYI

This bit specifies the existence for serial input data one clock delay of master device.

Setting

Explanation

0

1

Serial data delay existence

Serial data delay nothing

AFOI

This bit sets the receiving data to be Left-justify or Right-justify. This bit must be set to “0” when at Flame synchronous

transfer mode (FMTI is “1”).

Setting

Explanation

0

1

Left-justify

Right-justify

ISSCKI

This bit sets the sampling frequency of SAI_BCLK pin.

Setting

Explanation

0

1

32fs

64fs

MSBI

This bit sets the SAI receiving data to be MSB-first or LSB-first.

Setting

Explanation

0

1

MSB first

LSB first

FMTI

This bit sets the receiving mode

Setting

Explanation

0

1

LRCLK transfer mode

Frame synchronization transfer mode

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PCMFI24

This bit sets the SAI PCM receiving format.

Setting

Explanation

0x2

0x3

16bit PCM

24bit PCM

Other than the

above

This is prohibited from setting

SAI Mode select Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x64

0x65

-

BSWP

0

-

MST

0

This register is a register setting a movement mode of SAI, and RECPLAY bit of the Record/Playback Running Control

register, please change this register in recording stop state (0x0).

MST

It appoints whether this bit uses SAI with a master mode or a slave mode.

Setting

Explanation

0

1

Slave mode

Master mode

BSWP

As for this bit, it is done byte swap I2S data with PCM format by 16bitPCM without depending on the setting of the I2S

Receiver Control/I2S Transmitter Control register at the time of setting when I set byte swap having I2S or not on the same

side of transmission and reception data and there is byte swap and sets it.

Setting

Explanation

There is no byte swap

0

(16bit data line up :15bit-8bit,7bit-0bit)

(24bit data line up :23bit-16bit,15bit-8bit,7bit-0bit)

There is byte swap

1

(16bit data line up :7bit-0bit,15bit-8bit)

(24bit data line up :7bit-0bit,15bit-8bit 23bit-16bit)

DSP Filter Function Enable Register

INDEX

MAPCON

0x0

b07

(Initial)

HPF2OD

0

b06

b05

b04

b03

b02

b01

b00

R

W

0x66

0x67

EQ4EN

0

EQ3EN

0

EQ2EN

0

EQ1EN

0

EQ0EN

0

HPF2EN HPF1EN

0

1

DSP Filter Function Enable Register

INDEX

MAPCON

0x0

b07

(Initial)

HPF2OD

0

b06

b05

b04

b03

b02

b01

b00

R

W

0x66

0x67

EQ4EN

0

EQ3EN

0

EQ2EN

0

EQ1EN

0

EQ0EN

0

HPF2EN HPF1EN

0

1

DSP Filter Function Enable Register B

INDEX

MAPCON

0x2

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x66

0x67 HPF2ODB EQ4ENB EQ3ENB EQ2ENB EQ1ENB EQ0ENB HPF2ENB HPF1ENB

0

1

This register sets the filter function of the digital code processing ON/OFF.

If COEFSEL=0, then register level of HPF1/2EN, EQ0/1/2/3/4EN, HPF2OD is effective. If COEFSEL=1, then value of

HPF1/2ENB, EQ0/1/2/3/4ENB, HPF2ODB register becomes effective.

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HPF1EN/ HPF1ENB

This bit is to set ON or OFF of a first-order high pass filter for DC cut. Do not change this bit during operation of the

recording (0x13/0x14: RECPLAY=0x1, 0x3, or 0x7). If this bit is changed, the noise may be generated.

When this IC being operated the playing (RECPLAY=0x2), this bit operating don't have effective.

HPF1EN/

Explanation

HPF1ENB

0

1

Primary high-pass filter OFF for the DC cut

Primary high-pass filter ON for the DC cut

HPF2EN/ HPF2ENB

This bit is to set ON or OFF of a second-order high pass filter for noise cut. Do not change this bit during operation of the

recording (RECPLAY=0x1,0x3, or 0x7). If this bit is changed, the noise may be generated.

The bit of HPF2EN is effective only when 0xA6/0xA7:RLPFEN is enable.

HPF2EN/

Explanation

HPF2ENB

0

1

Second high-pass filter OFF for noise reduction

Second high-pass filter ON for noise reduction

EQ0EN/EQ0ENB

This bit is to set ON or OFF of equalizer band 0. In case of changing this bit during recording and playback operation

(RECPLAY=0x1, 0x2, 0x3, or 0x7), enables digital volume fade function (0x68/0x69: DVFADE=1) and then change the gain

to 0dB.

EQ0EN/

EQ0ENB

Explanation

0

1

Equalizer band 0 OFF

Equalizer band 0 ON

EQ1EN/EQ1ENB

This bit is to set ON or OFF of equalizer band 1. In case of changing this bit during recording and playback operation

(0x13/0x14: RECPLAY=0x1, 0x2, 0x3, or 0x7), enables digital volume fade function (0x68/0x69: DVFADE=1) and then

change the gain to 0dB.

EQ1EN/

EQ1ENB

Explanation

0

1

Equalizer band 1 OFF

Equalizer band 1 ON

EQ2EN/EQ2ENB

This bit is to set ON or OFF of equalizer band 2. In case of changing this bit during recording and playback operation

(0x13/0x14: RECPLAY=0x1, 0x2, 0x3, or 0x7), enables digital volume fade function (0x68/0x69: DVFADE=1) and then

change the gain to 0dB.

EQ2EN/

EQ2ENB

Explanation

0

1

Equalizer band 2 OFF

Equalizer band 2 ON

EQ3EN/EQ3ENB

This bit is to set ON or OFF of equalizer band 3. In case of changing this bit during recording and playback operation

(0x13/0x14: RECPLAY=0x1, 0x2, 0x3, or 0x7), enables digital volume fade function (0x68/0x69: DVFADE=1) and then

change the gain to 0dB.

EQ3EN/

Explanation

EQ3ENB

0

1

Equalizer band 3 OFF

Equalizer band 3 ON

EQ4EN/EQ4ENB

This bit is to set ON or OFF of equalizer band 4. In case of changing this bit during recording and playback operation

(0x13/0x14: RECPLAY=0x1, 0x2, 0x3, or 0x7), enables digital volume fade function (0x68/0x69: DVFADE=1) and then

change the gain to 0dB.

EQ4EN/

Explanation

EQ4ENB

0

1

Equalizer band 4 OFF

Equalizer band 4 ON

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HPF2OD/HPFODB

This bit is to set number of high pass filter order (HPF2EN bit) for noise cut. In recording or playback operation(0x13/0x14:

RECPLAY≠0）,do not change this bit. If this bit is changed, the noise may be generated.

HPF2OD/

Explanation

HPF2ODB

0

1

The second filter

Primary filter

Digital Volume Control Function Enable Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x68

0x69

-

DVMUTE DVFADE

-

RALCEN PALCEN

0

This register sets ON/OFF of digital, the Volume control function.

PALCEN

This bit is to set ON or OFF of the playing ALC.

It must not be wrote during recording and playback operation (0x13/0x14: RECPLAY=0x1, 0x3, or 0x7).

If this bit was set as the operation, this IC cannot guarantee correct operating.

PALCEN

Explanation

0

1

Reproduction ALC OFF

Reproduction ALCON

RALCEN

This bit is to set ON or OFF of the recording ALC.

It must not be wrote during recording and playback operation (0x13/0x14: RECPLAY=0x2).

If this bit was set as the operation, this IC cannot guarantee correct operating.

RALCEN

Explanation

0

1

Recording ALC OFF

Recording ALC ON

DVFADE

This bit is to set ON or OFF of the digital volume fade function.

The fade function is effective for recording/playback digital volume and equalizer gain.

DVFADE

Explanation

Fading Function OFF:

The register setting value of RDATT, PDATT and EQGAIN0 to 3

is used actual volume value as it is. Therefore the value is

effective immediate.

0

Fading Function ON:

The volume is changing to the register setting value of RDATT,

PDATT and EQGAIN0 to 3 with 1 step per DVFCON register step

time.

1

DVMUTE

This bit is to set MUTE of the digital volume. This mute function is effective for the recording digital volume at recording and

effective for playback digital volume at playback. The fade function by DVFADE is effective against the volume change by

this bit.

DVMUTE

Explanation

0

Register value of RDVOL and PDATT is effective.

Digital volume is set to MUTE.

Register value of RDVOL and PDATT cannot be changed by this

bit, the volume is resumed by releasing this bit (DVMUTE=0) to

the original setting value of RDVOL and PDVOL.

1

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Mixer & Volume Control Register

INDEX

MAPCON

0x0

b07

b06

b05

0

b04

0

b03

0

b02

0

b01

0

b00

0

R

W

(Initial)

0x6a

0x6b

DVFCON

RMCON

LMCON

0

This register controls L/R mixer processing at the time of the SAI reception and a fading function of the digital Volume.

LMCON[1:0]

This bit sets the input channel of SAI reception data of the DAC (Lch).

Setting

Explanation

0x0

I use L

0x1

I use R

0x2

0x3

I use (L+R)

I use (L+R)/2

RMCON[1:0]

This bit sets it about SAI reception data which channel you input into DAC (Rch).

Setting

Explanation

0x0

I use R

0x1

I use L

0x2

0x3

I use (L+R)

I use (L+R)/2

DVFCON[3:0]

These bits are to set the volume change step time of the digital volume fade function. The volume changes step by step

(0.5dB) with this setting period. Step time is in proportion to sampling frequency (fs) as following table.

Setting

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xC

0xD

0xE

fs conversion

Time(fs=48kHz)

1/fs

2/fs

4/fs

8/fs

16/fs

32/fs

64/fs

128/fs

256/fs

512/fs

1024/fs

2048/fs

4096/fs

8192/fs

16384/fs

20.8µs

41.7µs

83.3µs

167µs

333µs

667µs

1.33ms

2.67ms

5.33ms

10.7ms

21.3ms

42.7ms

85.3ms

171ms

341ms

Record Digital Attenuator Control Register

INDEX

MAPCON

0x0

b07

b06

b05

1

b04

1

b03

1

b02

1

b01

1

b00

1

R

W

(Initial)

0x6c

0x6d

RDVOL

1

This register sets digital Volume Gain of the recording course.

MUTE could be set from -71.5dB to 0.0dB by 0.5dB step.

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RDATT[7:0]

Setting

Gain(dB)

Setting

0x93

Gain(dB)

-54.0

Setting

0xB8

Gain(dB)

-35.5

Setting

0xDD

Gain(dB)

-17.0

This is

prohibited

from

0x00 -

0x6E

setting

MUTE

-71.5

-71.0

-70.5

-70.0

-69.5

-69.0

-68.5

-68.0

-67.5

-67.0

-66.5

-66.0

-65.5

-65.0

-64.5

-64.0

-63.5

-63.0

-62.5

-62.0

-61.5

-61.0

-60.5

-60.0

-59.5

-59.0

-58.5

-58.0

-57.5

-57.0

-56.5

-56.0

-55.5

-55.0

-54.5

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

0x80

0x81

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x89

0x8A

0x8B

0x8C

0x8D

0x8E

0x8F

0x90

0x91

0x92

0x94

0x95

0x96

0x97

0x98

0x99

0x9A

0x9B

0x9C

0x9D

0x9E

0x9F

0xA0

0xA1

0xA2

0xA3

0xA4

0xA5

0xA6

0xA7

0xA8

0xA9

0xAA

0xAB

0xAC

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

0xB3

0xB4

0xB5

0xB6

0xB7

-53.5

-53.0

-52.5

-52.0

-51.5

-51.0

-50.5

-50.0

-49.5

-49.0

-48.5

-48.0

-47.5

-47.0

-46.5

-46.0

-45.5

-45.0

-44.5

-44.0

-43.5

-43.0

-42.5

-42.0

-41.5

-41.0

-40.5

-40.0

-39.5

-39.0

-38.5

-38.0

-37.5

-37.0

-36.5

-36.0

0xB9

0xBA

0xBB

0xBC

0xBD

0xBE

0xBF

0xC0

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC7

0xC8

0xC9

0xCA

0xCB

0xCC

0xCD

0xCE

0xCF

0xD0

0xD1

0xD2

0xD3

0xD4

0xD5

0xD6

0xD7

0xD8

0xD9

0xDA

0xDB

0xDC

-35.0

-34.5

-34.0

-33.5

-33.0

-32.5

-32.0

-31.5

-31.0

-30.5

-30.0

-29.5

-29.0

-28.5

-28.0

-27.5

-27.0

-26.5

-26.0

-25.5

-25.0

-24.5

-24.0

-23.5

-23.0

-22.5

-22.0

-21.5

-21.0

-20.5

-20.0

-19.5

-19.0

-18.5

-18.0

-17.5

0xDE

0xDF

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xE8

0xE9

0xEA

0xEB

0xEC

0xED

0xEE

0xEF

0xF0

0xF1

0xF2

0xF3

0xF4

0xF5

0xF6

0xF7

0xF8

0xF9

0xFA

0xFB

0xFC

0xFD

0xFE

0xFF

-16.5

-16.0

-15.5

-15.0

-14.5

-14.0

-13.5

-13.0

-12.5

-12.0

-11.5

-11.0

-10.5

-10.0

-9.5

-9.0

-8.5

-8.0

-7.5

-7.0

-6.5

-6.0

-5.5

-5.0

-4.5

-4.0

-3.5

-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

Playback Effect Volume Control Register

INDEX

MAPCON

0x0

b07

b06

b05

1

b04

b03

1

b02

b01

b00

1

R

W

(Initial)

0x70

0x71

Effect VOL

1

Playback Effect Volume Control Register B

INDEX

MAPCON

0x2

b07

b06

b05

1

b04

1

b03

b02

1

b01

1

b00

1

R

W

(Initial)

0x70

0x71

Effect VOLB

1

This register sets the digital Volume Gain of the reproduction course. If COEFSEL=0, then register level of Effect Vol is

effective. If COEFSEL=1, then value of the Effect Vol B register becomes effective.

MUTE could be set from -71.5dB to 0.0dB by 0.5dB step.

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Effect Vol[7:0]/ Effect Vol B[7:0

Sets the Digital Volume Gain.

Effect Vol/

Gain(dB)

Setting

Gain(dB)

-54.0

Setting

0xB8

Gain(dB)

-35.5

Setting

0xDD

Gain(dB)

-17.0

Effect Vol B

This is

prohibited

from

0x00 - 0x6E

0x93

setting

MUTE

-71.5

-71.0

-70.5

-70.0

-69.5

-69.0

-68.5

-68.0

-67.5

-67.0

-66.5

-66.0

-65.5

-65.0

-64.5

-64.0

-63.5

-63.0

-62.5

-62.0

-61.5

-61.0

-60.5

-60.0

-59.5

-59.0

-58.5

-58.0

-57.5

-57.0

-56.5

-56.0

-55.5

-55.0

-54.5

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

0x80

0x81

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x89

0x8A

0x8B

0x8C

0x8D

0x8E

0x8F

0x90

0x91

0x92

0x94

0x95

0x96

0x97

0x98

0x99

0x9A

0x9B

0x9C

0x9D

0x9E

0x9F

0xA0

0xA1

0xA2

0xA3

0xA4

0xA5

0xA6

0xA7

0xA8

0xA9

0xAA

0xAB

0xAC

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

0xB3

0xB4

0xB5

0xB6

0xB7

-53.5

-53.0

-52.5

-52.0

-51.5

-51.0

-50.5

-50.0

-49.5

-49.0

-48.5

-48.0

-47.5

-47.0

-46.5

-46.0

-45.5

-45.0

-44.5

-44.0

-43.5

-43.0

-42.5

-42.0

-41.5

-41.0

-40.5

-40.0

-39.5

-39.0

-38.5

-38.0

-37.5

-37.0

-36.5

-36.0

0xB9

0xBA

0xBB

0xBC

0xBD

0xBE

0xBF

0xC0

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC7

0xC8

0xC9

0xCA

0xCB

0xCC

0xCD

0xCE

0xCF

0xD0

0xD1

0xD2

0xD3

0xD4

0xD5

0xD6

0xD7

0xD8

0xD9

0xDA

0xDB

0xDC

-35.0

-34.5

-34.0

-33.5

-33.0

-32.5

-32.0

-31.5

-31.0

-30.5

-30.0

-29.5

-29.0

-28.5

-28.0

-27.5

-27.0

-26.5

-26.0

-25.5

-25.0

-24.5

-24.0

-23.5

-23.0

-22.5

-22.0

-21.5

-21.0

-20.5

-20.0

-19.5

-19.0

-18.5

-18.0

-17.5

0xDE

0xDF

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xE8

0xE9

0xEA

0xEB

0xEC

0xED

0xEE

0xEF

0xF0

0xF1

0xF2

0xF3

0xF4

0xF5

0xF6

0xF7

0xF8

0xF9

0xFA

0xFB

0xFC

0xFD

0xFE

0xFF

-16.5

-16.0

-15.5

-15.0

-14.5

-14.0

-13.5

-13.0

-12.5

-12.0

-11.5

-11.0

-10.5

-10.0

-9.5

-9.0

-8.5

-8.0

-7.5

-7.0

-6.5

-6.0

-5.5

-5.0

-4.5

-4.0

-3.5

-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

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EQ Band0 Gain Setting Register

EQ Band1 Gain Setting Register

EQ Band2 Gain Setting Register

EQ Band3 Gain Setting Register

EQ Band4 Gain Setting Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

0

b02

b01

b00

R

W

(Initial)

0x74

0x76

0x78

0x7a

0x7c

0x75

EQGAIN0

1

0

1

EQGAIN1

0x0

0x77

0x79

0x7b

0x7d

0

EQGAIN2

EQGAIN3

EQGAIN4

0x0

EQ Band0 Gain Setting Register B

EQ Band1 Gain Setting Register B

EQ Band2 Gain Setting Register B

EQ Band3 Gain Setting Register B

EQ Band4 Gain Setting Register B

INDEX

MAPCON

0x2

b07

b06

b05

b04

0

b03

b02

b01

b00

R

W

(Initial)

0x74

0x76

0x78

0x7a

0x7c

0x75

EQGAIN0B

1

0

1

EQGAIN1B

0x2

0x77

0x79

0x7b

0x7d

0

EQGAIN2B

0x2

0

EQGAIN3B

0x2

0

EQGAIN4B

0x2

0

This register sets the gain of each band of the equalizer. If COEFSEL=0, then the register level of EQGAIN0 to 4 is effective.

If COEFSEL=1, then value of the EQGAIN0B to EQGAIN4B register becomes effective.

This register can set EQ gain from -71.5dB to 12.0dB(step by step 0.5dB). Also it can set MUTE.

EQ can work as a notch filter by MUTE setting.

EQGAIN/

EQGAINB

0 - to 4 [7:0]

Gain

(0dB)

EQGAIN/

EQGAINB

0 - to4[7:0]

Gain

(0dB)

EQGAIN/

EQGAINB

0 - to4[7:0]

Gain

(dB)

EQGAIN/

EQGAINB

0 - to4[7:0]

Gain

(dB)

0x00 - to 0x57

0x58

MUTE

-71.5

-71.0

-70.5

-70.0

-69.5

-69.0

-68.5

-68.0

-67.5

-67.0

-66.5

-66.0

-65.5

-65.0

-64.5

-64.0

-63.5

-63.0

-62.5

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x89

0x8A

0x8B

0x8C

0x8D

0x8E

0x8F

0x90

0x91

0x92

0x93

0x94

0x95

-50.5

-50.0

-49.5

-49.0

-48.5

-48.0

-47.5

-47.0

-46.5

-46.0

-45.5

-45.0

-44.5

-44.0

-43.5

-43.0

-42.5

-42.0

-41.5

-41.0

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

0xB3

0xB4

0xB5

0xB6

0xB7

0xB8

0xB9

0xBA

0xBB

0xBC

0xBD

0xBE

0xBF

0xC0

-29.0

-28.5

-28.0

-27.5

-27.0

-26.5

-26.0

-25.5

-25.0

-24.5

-24.0

-23.5

-23.0

-22.5

-22.0

-21.5

-21.0

-20.5

-20.0

-19.5

0xD8

0xD9

0xDA

0xDB

0xDC

0xDD

0xDE

0xDF

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xE8

0xE9

0xEA

0xEB

-7.5

-7.0

-6.5

-6.0

-5.5

-5.0

-4.5

-4.0

-3.5

-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0.5

1.0

1.5

2.0

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0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

0x80

0x81

-62.0

-61.5

-61.0

-60.5

-60.0

-59.5

-59.0

-58.5

-58.0

-57.5

-57.0

-56.5

-56.0

-55.5

-55.0

-54.5

-54.0

-53.5

-53.0

-52.5

-52.0

-51.5

-51.0

0x96

0x97

0x98

0x99

0x9A

0x9B

0x9C

0x9D

0x9E

0x9F

0xA0

0xA1

0xA2

0xA3

0xA4

0xA5

0xA6

0xA7

0xA8

0xA9

0xAA

0xAB

0xAC

-40.5

-40.0

-39.5

-39.0

-38.5

-38.0

-37.5

-37.0

-36.5

-36.0

-35.5

-35.0

-34.5

-34.0

-33.5

-33.0

-32.5

-32.0

-31.5

-31.0

-30.5

-30.0

-29.5

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC7

0xC8

0xC9

0xCA

0xCB

0xCC

0xCD

0xCE

0xCF

0xD0

0xD1

0xD2

0xD3

0xD4

0xD5

0xD6

0xD7

-19.0

-18.5

-18.0

-17.5

-17.0

-16.5

-16.0

-15.5

-15.0

-14.5

-14.0

-13.5

-13.0

-12.5

-12.0

-11.5

-11.0

-10.5

-10.0

-9.5

0xEC

0xED

0xEE

0xEF

0xF0

0xF1

0xF2

0xF3

0xF4

0xF5

0xF6

0xF7

0xF8

0xF9

0xFA

0xFB

0xFC

0xFD

0xFE

0xFF

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

10.5

11.0

11.5

12.0

-9.0

-8.5

-8.0

High Pass Filter2 Cut-off Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

0

b01

b00

0

R

W

(Initial)

0x7e

0x7f

-

HPF2CUT

0

This register is to set the cut-off frequency of the high-pass filter for the noise reduction during recording.

Don’t change the setting of this register under the filter processing concerned(HPF2EN="1" and RELPLAY=0x1,0x3 or 0x7).

HPF2CUT[2:0]

These set the cut-off frequency of the noise reduction high-pass filter during recording and the numerical value of below list

expresses 1.5dB damping and 3dB damping frequency in each second order filter(HPF2OD="1") and one order filter

(HPF2OD="0").

Cut-off Frequency(Hz)

HPF2CUT

[2:0]

fs=8kHz,

16kHz,

32kHz

fs=11.025kHz,

22.05kHz,

44.1kHz

fs=12kHz,

24kHz,

48kHz

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

80

110

138

179

221

276

358

441

551

120

150

195

240

300

390

480

600

100

130

160

200

260

320

400

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Programmable Equalizer Band0 Coefficient-a0 (L) Register

Programmable Equalizer Band0 Coefficient-a0 (H) Register

Programmable Equalizer Band0 Coefficient-a1 (L) Register

Programmable Equalizer Band0 Coefficient-a1 (H) Register

Programmable Equalizer Band1 Coefficient-a0 (L) Register

Programmable Equalizer Band1 Coefficient-a0 (H) Register

Programmable Equalizer Band1 Coefficient-a1 (L) Register

Programmable Equalizer Band1 Coefficient-a1 (H) Register

Programmable Equalizer Band2 Coefficient-a0 (L) Register

Programmable Equalizer Band2 Coefficient-a0 (H) Register

Programmable Equalizer Band2 Coefficient-a1 (L) Register

Programmable Equalizer Band2 Coefficient-a1 (H) Register

Programmable Equalizer Band3 Coefficient-a0 (L) Register

Programmable Equalizer Band3 Coefficient-a0 (H) Register

Programmable Equalizer Band3 Coefficient-a1 (L) Register

Programmable Equalizer Band3 Coefficient-a1 (H) Register

Programmable Equalizer Band4 Coefficient-a0 (L) Register

Programmable Equalizer Band4 Coefficient-a0 (H) Register

Programmable Equalizer Band4 Coefficient-a1 (L) Register

Programmable Equalizer Band4 Coefficient-a1 (H) Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

0

b02

b01

b00

R

W

(Initial)

0x80

0x82

0x84

0x86

0x88

0x8a

0x8c

0x8e

0x90

0x92

0x94

0x96

0x98

0x9a

0x9c

0x9e

0xa0

0xa2

0xa4

0xa6

0x81

EQ0A0L

0

EQ0A0H

EQ0A1L

EQ0A1H

EQ1A0L

EQ1A0H

EQ1A1L

EQ1A1H

EQ2A0L

EQ2A0H

EQ2A1L

EQ2A1H

EQ3A0L

EQ3A0H

EQ3A1L

EQ3A1H

EQ4A0L

EQ4A0H

EQ4A1L

EQ4A1H

0x83

0x85

0x87

0x89

0x8b

0x8d

0x8f

0

0x91

0x93

0x95

0x97

0x99

0x9b

0x9d

0x9f

0xa1

0xa3

0xa5

0xa7

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INDEX

MAPCON

0x2

b07

b06

b05

b04

b03

0

b02

b01

b00

R

W

(Initial)

0x7e

0x80

0x82

0x84

0x86

0x88

0x8a

0x8c

0x8e

0x90

0x92

0x94

0x96

0x98

0x9a

0x9c

0x9e

0xa0

0xa2

0xa4

0x7f

EQ0A0LB

0

EQ0A0HB

0x81

0x83

0x85

0x87

0x89

0x8b

0x8d

0x8f

0

EQ0A1LB

EQ0A1HB

EQ1A0LB

EQ1A0HB

EQ1A1LB

EQ1A1HB

EQ2A0LB

EQ2A0HB

EQ2A1LB

EQ2A1HB

EQ3A0LB

EQ3A0HB

EQ3A1LB

EQ3A1HB

EQ4A0LB

EQ4A0HB

EQ4A1LB

EQ4A1HB

0x91

0x93

0x95

0x97

0x99

0x9b

0x9d

0x9f

0xa1

0xa3

0xa5

These registers are to set the coefficients a0 and a1 of each five band programmable equalizer. One coefficients value is

specified by two bytes data. The centre frequency and band width of the filter can be set by changing these register value.

Please don’t change the register setting during corresponding filter operation

EQ0A0L to EQ4A1H are became effective at COEFSEL=0 and EQ0A0LB to EQ4A1HB are became effective at

COEFSEL=1.

The detailed setting value is described in the Filter function.

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Zero Detection Setting Register

INDEX

MAPCON

0x0

b07

b06

0

b05

0

b04

0

b03

b02

b01

b00

R

W

(Initial)

0xdc

0xdd

ZDTIME

-

ZDEN

0

This register controls zero detection for low power consumption mode. When zero detection is enable and "0" data are

inputted in succession, a part of internal clock and speaker amplifier goes to disable to operate under low power

consumption. Controlling a zero detection function for low power consumption mode movement, and enabling this function,

some internal clocks stop it, and a speaker amplifier is disabled. When data, not 0 data, is input, the disable block starts

operation again.

In addition, the zero detection is effective only speaker amplifier playing mode. In the other modes, please set ZDEN bit in

"0".

ZDEN

Enables/Disables the zero detection function.

ZDEN

Explanation

0x0

0x1

A zero detection function is disabled.

A zero detection function is enabled.

ZEROTIM

Sets "0" detection period. When "0" continues more than the following set points in succession with LCH/RCH, it becomes

low power consumption mode.

ZEROTIM

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0a

Explanation

256/fs

512/fs

1024/fs

2048/fs

4096/fs

8192/fs

16384/fs

32768/fs

65536/fs

131072/fs

262144/fs

This is prohibited

from setting

0x0b to 0x0f

MIC select Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0xe8

0xe9

-

MIN2EN

0

MIN1EN

1

This register sets microphone input.

MIN1EN

Using MIN1 terminal in analog MIC.

Setting

Explanation

0

1

Does not use MIN1 terminal.

Use MIN1 terminal.

MIN2EN

Using MIN2 terminal in analog MIC. Please set it in "0" when in the differential mode.

Setting

Explanation

Does not use MIN2 terminal.

Use MIN2 terminal.

0

1

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FPLL M setting Register

FPLL N Setting (L) Register

FPLL N Setting (H) Register

FPLL D Setting Register

FPLL F Setting (L) Register

FPLL F Setting (H) Register

FPLL F_D Setting (L) Register

FPLL F_D Setting (H) Register

FPLL V setting Register

INDEX

MAPCON

0x1

b07

b06

b05

b04

b03

b02

0

b01

b00

0

R

W

(Initial)

0x02

0x04

0x06

0x08

0x0a

0x0c

0x0e

0x10

0x12

0x03

-

FPLLM

0

FPLLNL

0x1

0x05

0x07

0x09

0x0b

0x0d

0x0f

0

-

0

-

0

-

0

-

0

-

0

-

0

FPLLNH

0

0x1

-

FPLLD

0

-

0x1

-

0

FPLLFL

FPLLFH

0x1

0

0x1

FPLLFDL

FPLLFDH

0x1

0

0x1

0x11

0x13

0

-

0

-

0

-

0

-

FPLLV

0x1

-

0

This register sets the output frequency of PLL.

Please use your prepared clock setting register level that is computed separately using clock setting calculation tool.

The register set point and the relations of the output frequency are streets of the lower expression.

PLL output frequency (Hz)=PLL input frequency / FPLLM X (FPLLN+FPLLD/16+FPLLF/FPLLF_D/16) *2 / FPLLV

Soft Clip Enable Register

Soft Clip Threshold H Register

Soft Clip Threshold M Register

Soft Clip Threshold L Register

Soft Clip Gain Register

INDEX

MAPCON

0x1

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x20

0x22

0x24

0x26

0x28

0x21

-

SCEN

0

-

SCTHRH

0

0x1

0x23

0x25

0x27

0x29

0

1

SCTHRM

0x1

0

SCTHRL

0x1

0

-

0

-

0

-

0

-

0

-

0

SCGAIN

0

0x1

-

This register controls the soft clip function.

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SCEN

Sets the soft clip enable.

Setting

Explanation

0

1

Disable

Enable

SCTHRH

SCTHRM

SCTHRL

This register sets the soft clip threshold level.

When PCM signal with more than of this bit is input, the LSI clips it according to a value of SCGAIN and works.

The value of threshold level is 23bit (SCTHRM [6:0], SCTHRM [7:0], and SCTHRL [7:0])

Please do not change the value of this bit during Soft Clip function movement.

SCGAIN

This sets the magnification during soft clip. In addition, please do not change the value of this bit during movement.

Setting

Explanation

0x0

Double

0x1

0x2

0x3

0x4

0x5

0x6

0x7

1 time (default)

I double 1/2

I double 1/4

I double 1/8

I double 1/16

I double 1/32

I double 1/64

Touch ADC Control Register

INDEX

MAPCON

b07

(Initial)

TCHEN

0

b06

b05

b04

b03

b02

b01

b00

R

W

1

0x60

0x61

TCHA2

1

TCHA1

1

-

TCHRSEL

0

TCHA0

TCHMODE

-

1

0

-

This register controls the touch panel interface, and a light, please do "1" in bit 3.

TCHEN

This enables and disables the touch panel interface. In the case of "0", this bit is cleared after (an automatic mode in the

case of enable), the lead of the AD conversion data of the touch panel interface TCHA2 bit by "0".

TCHEN

0x0

0x1

Explanation

A touch panel interface is disabled.

A touch panel interface is enabled.

TCHA2

It controls the convert mode of the touch panel interface, and, in the case of "1", this bit interrupts it after the lead of the AD

conversion data of the touch panel interface automatically and changes in a mode. The next conversion starts by an

automatic mode leading AD conversion result in the case of disable.

TCHA2

0x0

0x1

Explanation

An automatic mode is enabled.

An automatic mode is disabled.

TCHA1, TCHA0

This controls the convert mode of the touch panel interface.

TCHEN

TCHA2

TCHA1, TCHA0

Explanation

TCHEN=1

*

0x0

0x1

0x2

0x3

It becomes the X-axis measurement mode.

It becomes the Y-axis measurement mode.

It becomes the Z1 axis measurement mode.

It becomes the Z2 axis measurement mode.

It becomes the interrupt mode.

*

TCHEN=0

0x0

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TCHRSEL

Choose interrupt pull up resistance using for one of a touch panel interface.

TCHRSEL

Explanation

0x0

0x1

I interrupt it, and pulling up resistance becomes 50kΩ.

I interrupt it, and pulling up resistance becomes 90kΩ.

TCHMODE

Choose touch panel interface mode.

TCHMODE

Explanation

0x0

0x1

12Bit Mode

8Bit Mode

Touch ADC result1 Register

Touch ADC result2 Register

INDEX

MAPCON

0x1

b07

b06

b05

0

b04

b03

b02

b01

b00

R

W

(Initial)

0x62

0x63

ADCR1

0

-

0

-

0

-

0

-

ADCR2

0x1

0x64

0x65

0

-

This register is to get analog-to-digital conversion data of the touch panel interface ADC. In the 12bit mode, please read

register in order of ADCR1 ($62h), ADCR2 ($64h).

TOUTCHAD1

This register is to get analog-to-digital conversion data of the touch panel interface ADC. In the 8 bit mode, please read

only this register. In the 12 bit mode, this register is higher 8 bits of the 12bit ADC output data.

TOUTCHAD2

This register is to get analog-to-digital conversion data of the touch panel interface ADC. In the 8 bit mode, this register

value is "0". In the 12 bits mode, this register is lower 4 bits of the 12bit ADC output data.

Headphone Amplifier Input Control Register

INDEX

MAPCON

0x1

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x82

0x83

-

HPRIN2EN HPRIN1EN

-

HPLIN1EN

0

This register is to set the input path of the headphones amplifier. Please do not set HPRIN1EN bit and the HPRIN2EN bit

to "1" simultaneously. Please set only either bit to " 1 ".

HPLIN1EN

This bit is to set the input path of the Lch headphones amplifier.

HPLIN1EN

Explanation

0x0

0x1

Disconnect the output of Lch-DAC to Lch headphones amplifier.

Connect the output of Lch-DAC to Lch headphones amplifier.

HPRIN1EN

This bit is to set the input path of the Rch headphones amplifier.

HPRIN1EN

Explanation

0x0

0x1

Disconnect the output of Lch-DAC to Rch headphones amplifier.

Connect the output of Lch-DAC to Rch headphones amplifier.

HPRIN2EN

This bit is to set the input path of the Rch headphones amplifier.

HPRIN2EN

Explanation

0x0

0x1

Disconnect the output of Rch-DAC to Rch headphones amplifier.

Connect the output of Rch-DAC to Rch headphones amplifier.

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Speaker Amplifier Input Control Register

INDEX

MAPCON

0x1

b07

b06

b05

b04

b03

b02

b01

0

b00

0

R

W

(Initial)

0x84

0x85

-

SPIN2EN SPIN1EN

SPVOL

0

This register is to set the input path and the volume of the speaker amplifier.

SPVOL

This register is to set the volume level of the speaker amplifier.

SPVOL

Explanation

0x0

0dB

0x1

6dB

0x2

0x3

12dB

18dB

SPIN1EN

This bit is to set the input path of the speaker amplifier.

SPIN1EN

Explanation

0x0

0x1

Disconnect the output of the Lch volume to a speaker amplifier.

Connect the output of the Lch volume to a speaker amplifier.

SPIN2EN

This bit is to set the input path of the speaker amplifier.

SPIN2EN

Explanation

0x0

0x1

Disconnect the output of the Rch volume to a speaker amplifier.

Connect the output of the Rch volume to a speaker amplifier.

Play Programmable LPF Setting Register

INDEX

MAPCON

0x1

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0xa0

0xa1

-

PLPFOD PLPFEN

0

This register is to set “LPF” block for DAC-path (playback) in digital signal flow. This is to set Enable/Disable and filter order.

This function is effective for DAC-path (playback) at “PLPFEN=1” and “SEMODE [7] =1”.

PLPFEN

This bit is to set Enable/Disable of low pass filter for DAC-path.

PLPFEN

Explanation

LPF for DAC-path is Disable

LPF for DAC-path is Enable

0

1

PLPFOD

This bit is to set number of low pass filter order for DAC-path.

PLPFOD

Explanation

LPF for DAC-path is second-order

LPF for DAC-path is first-order

0

1

Play Programmable LPF Coef (L) Register

Play Programmable LPF Coef (H) Register

INDEX

MAPCON

0x1

b07

b06

b05

b04

b03

0

b02

b01

b00

R

W

(Initial)

0xa2

0xa3

PLPFC0L

0

PLPFC0H

0x1

0xa4

0xa5

0

This register is to set “LPF” block for DAC-path (playback) in digital signal flow. This is to set Enable/Disable and filter order.

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PLPFC0L [7:0] / PLPFCOH [7:0]

This bit is to set low pass filter cut off frequency for DAC-path.

This value has to change by sampling frequency.

Please use Filter Setting Calculation program for *PLPFC0L / PLPFC0H setting.

Rec Programmable LPF Setting Register

INDEX

MAPCON

0x1

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0xa6

0xa7

-

RLPFOD RLPFEN

0

This register is to set “LPF” block for ADC-path (record) in digital signal flow. This is to set Enable/Disable and filter order.

This function is exclusive to “HPF2” controlled by HPF2EN of DSP Filter Function Enable register.

This function is effective for ADC-path (record) at “RLPFEN=1” and “SEMODE [7] =1”.

RLPFEN

This bit is to set Enable/Disable of low pass filter for ADC-path.

RLPFEN

Explanation

0

1

LPF for DAC-path is Disable (HPF2 is available)

LPF for DAC-path is Enable (HPF2 is not available. HPF2EN-bit

is not valid)

RLPFOD

This bit is to set number of low pass filter order for ADC-path.

RLPFOD

Explanation

LPF for ADC-path is second-order

LPF for ADC-path is first-order

0

1

Rec Programmable LPF Coef (L) Register

Rec Programmable LPF Coef (H) Register

INDEX

MAPCON

0x1

b07

b06

b05

b04

b03

0

b02

b01

b00

R

W

(Initial)

0xa8

0xa9

RLPFC0L

0

RLPFC0H

0x1

0xaa

0xab

0

This register is to set “LPF” block for ADC-path (playback) in digital signal flow.

Audio Analog Control2 Register

MAPCON

0x02

INDEX

b07

(initial)

-

b06

b05

b04

b03

b02

b01

b00

R

W

0x04

0x05

-

1

-

HPLSEN

1

-

1

-

HPLSEN

This bit controls the level shifter for headphone amplifier.

Setting

Explanation

0x0

0x1

Disable the level shifter for headphone amplifier

Enable the level shifter for headphone amplifier

Audio Analog Control1 Register

MAPCON

0x02

INDEX

b07

(initial)

-

b06

b05

b04

b03

b02

b01

b00

R

W

0x12

0x13

-

AREFI1EN

1

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AREFI1EN

This bit controls the reference current of the analog circuit for the audio block.

Setting

Explanation

0x0

0x1

Disable the reference current of the analog circuit for the audio block.

Enable the reference current of the analog circuit for the audio block.

Register MAP Control Register

INDEX

MAPCON

0x2

b07

b06

b05

b04

b03

b02

b01

b00

0

R

W

(Initial)

0x1c

0x1d

-

MAPCON

0

MAPCON

Please refer to a register map about the target register to change front and back side of the register map, and to be

replaced by.

The register is to set register map. Please refer register map about the map of the changing object.

Setting

Explanation

0x0

It is accessible to register MAP0

0x1

0x2

0x3

It is accessible to register MAP1

It is accessible to register MAP2

Prohibit

PLL External Components Setting Register

INDEX

MAPCON

2

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x00

0x01

-

EXMODE

1

This register is to select use or not use the external filter for PLL.

EXMODE

This register is to select use or not use the external filter for PLL. When you use PLL with BCLK clock as a clock source ,

please set it to "1" by all means.

EXMODE

Explanation

0x00

0x01

not use a external filter.

use a external filter.

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Typical Performance Curves

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

0

-10

-20

-30

-40

-50

HVDD=TVDD=CPVDD

=SPVDD=3.3V, 25℃

LALCMXGAIN=6.0dB

MINVOL=9.0dB

MINVOL=18.0dB

MINVOL=27.0dB

-60

-70

-80

-90

LALCMXGAIN=-9.0dB

MINVOL=18.0dB

MINVOL=27.0dB

HVDD=TVDD=CPVDD

=SPVDD=3.3V, 25℃

HVDD1=IOVDD=SPLVDD

=SPRVDD=3.3V, 25℃

-80

-60

-40

-20

0

-80

-60

-40

-20

0

Input Level [dBV]

Figure 42. MIC Input Level [dBV] vs S/(N+D) [dBFS]

Analog Mic Input tot ADC out, PDATT=0

Figure 41. MIC Input Level [dBV] vs Output Level [dBFS]

Analog Mic Input tot ADC out, PDATT=0

0

-10

-20

-30

-10

-20

HVDD=TVDD=CPVDD

=SPVDD=3.3V, 25℃

-30

-40

-50

-60

-70

-80

-90

HVDD=TVDD=CPVDD

=SPVDD=3.3V, 25℃

-40

-50

-40

-30

-20

-10

0

-50

-40

-30

-20

-10

0

Input Level [dBFS]

Figure 43. DAC input Level [dBFS] vs HPAMP Output

Figure 44. DAC input Level [dBFS] vs HPAMP

Level [dB]

THD+N[dB]

0

HVDD=TVDD=CPVDD

=SPVDD=3.3V, 25℃

-10

-20

-30

-40

-50

-60

-70

SPVOL

=0dB

SPVOL=18dB

SPVOL=12dB

-20

SPVOL=6dB

SPVOL=12dB

-30

SPVOL=6dB

SPVOL=18dB

-40

HVDD=TVDD=CPVDD

=SPVDD=3.3V, 25℃

SPVOL=0dB

-50

-40

-30

-20

-10

0

-50

-40

-30

-20

-10

0

Input Level [dBFS]

Figure 45. DAC input Level [dBFS] vs SPAMP-D

Class Output Level [dB]

Figure 46. DAC input Level [dBFS] vs SPAMP-D

Class THD+N [dB]

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0

-10

-20

-30

-40

-50

-60

-70

0

HVDD=TVDD=CPVDD

=SPVDD=3.3V, 25℃

HVDD=TVDD=CPVDD

=SPVDD=3.3V, 25℃

-10

-20

-30

-40

-50

SPVOL=18dB

SPVOL=12dB

SPVOL=6dB

SPVOL=0dB

SPVOL=6dB

SPVOL=12dB

SPVOL=18dB

SPVOL=0dB

-50

-40

-30

-20

-10

0

-50

-40

-30

-20

-10

0

Input Level [dBFS]

Figure 47. DAC input Level [dBFS] vs SPAMP-AB

Class Output Level [dB]

Figure 48. DAC input Level [dBFS] vs SPAMP-AB

Class THD+N [dB]

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Power dissipation

4.00

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.00

0

20

40

60

80

100

120

140

ambient temperature : Ta(℃)

Figure 49.VQFN040V6060 Package

Measuring instrument: TH-156 (Kuwano Electrical)

Measuring status: PCB mounting(Rohm)

PCB size: 74.2mm × 74.2mm × 1.6mm (PCB with thermal via)

The quarity of the material: FR4

The part of package bottom exposure heat sink connected PCB by solder.

PCB (1): 1-layer board (Size of copper foil on bottom: 23.69mm2), θja = 125.0℃/W

PCB (2): 4-layer board (Size of copper foil on top and bottom: 23.69mm2, 2nd and 3rd layer

Size of copper foil on bottom: 5505mm2), θja = 33.2℃/W

PCB (3): 4-layer board (Size of copper foil on bottom: 5505mm2), θja = 27.4℃/W

Please consider power dissipation by an actual using status, and perform the thermal design which has a margin enough.

Although this product is exposing the frame on the bottom side of a package, heat dissipation processing is performed to

this portion, and we assume raising and using heat dissipation efficiency. Please use not only PCB-top pattern but also

PCB-bottom pattern, taking heat dissipation pattern as large as possible at it.

Although D-class speaker amplifier have very high efficiency compared with the conventional analog-speaker amplifier and

there is also little generation of heat, when continuous action is carried out by the maximum output power, actual power

dissipation may exceed Pd. Please consider the thermal design enough so that power dissipation of averaging output

power does not exceed Pd.

（Tjmax ： Maximum junction temperature=125℃, Ta ：Ambient temperature[℃], θja ：Package thermal registance[℃/W],

Poav：Averaging output power[W], η：Efficiency）

Package Power dissipation Pd （W） = （Tjmax - Ta）/ θja

Circuit Power dissipation Pdiss（W） = Poav * （1 / η- 1）

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I/O equivalence circuit(s)

Terminal

No.

Terminal

Name

Terminal

I/O

Terminal

Power

Equivalent Circuit

HPVDD

1

40

HPL

HPR

O

HPVDD

HPVSS

CPVDD

2

HPVDD

O

CPVDD

CPGND

CPN

4

HPVSS

O

CPVDD

HPVSS

CPGND

5

CPN

O

CPVDD

HPVSS

6

SPVDD

-

SPVDD

SPGND

SPVDD

7

8

SDOUT+

SPOUT-

O

SPVDD

SPGND

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Terminal

No.

Terminal

Name

Terminal

I/O

Terminal

Power

Equivalent Circuit

SPVDD

9

SPGND

-

REGOUT

10

VMID

O

REGOUT

HGND2

HVDD

11

MICBIAS CAP

O

HVDD

HGND2 HGND2

REGOUT

12

13

MIN1

MIN2

I

REGOUT

HGND1

REGOUT

HVDD

14

HGND2

-

REGOUT

HVDD

15

16

HGND1

-

N.C

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Terminal

No.

Terminal

Name

Terminal

I/O

Terminal

Power

Equivalent Circuit

17

18

HVDD

-

HVDD

HGND1

HVDD

REGOUT

-

HVDD

HGND1

REGOUT

19

PLLC

O

REGOUT

HGND1

HGND2

HVDD

20

RESETB

I

HVDD

HGND1

HVDD

21

30

TSTO

IRQB

O

HVDD

HGND1

HVDD

22

23

25

28

MCLKI

CSB/SCL

SCLK/SAD

SAI_SDIN

I

HVDD

HGND1

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Terminal

No.

Terminal

Name

Terminal

I/O

Terminal

Power

Equivalent Circuit

HVDD

24

26

27

SDATA/SDA

SAI_LRCLK

SAI_BCLK

IO

HVDD

HGND1

TVDD

31

32

33

34

YP

XP

XN

YN

O

TVDD

TGND

TVDD

35

TGND

-

36

TVDD

-

TVDD

TGND

HPVDD

37

HPCOM

-

HPVSS

38

CPVDD

-

CPVDD

CPGND

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Terminal

No.

Terminal

Name

Terminal

I/O

Terminal

Power

Equivalent Circuit

CPVDD

39

CPP

-

CPVDD

CPGND

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Operational Notes

1) Absolute Maximum Ratings

An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc.,

can break down devices, thus don’t exceed the absolute maximum ratings of supply voltage, temperature. If any

special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical

safety measures including the use of fuses, etc.

2) GND voltage

Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state.

3) Short circuit between terminals and erroneous mounting

In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting

can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or

between the terminal and the power supply or the GND terminal, the ICs can break down.

4) Operation in strong electromagnetic field

Be noted that using ICs in the strong electromagnetic field can malfunction them.

5) Thermal design

If use speaker amplifier function, please consider power dissipation by an actual using status, and perform the thermal

design which have a margin enough. If an input signal is made excessive in the state with insufficient heat dissipation,

desired output power may not only be securable, but the thermal shutdown may operate.

6) Thermal shutdown

This IC has the thermal shutdown circuit. If the thermal shutdown operates, speaker output terminal and line output

terminal will stop in the open state(high inpedance state).The thermal shutdown is only a function for suspending the

output operation of IC to the last at the time of the thermal run-away under the abnormal condition in which chip

temperature(Tjmax) exceeded 170 degrees. It is a circuit to protect IC, and the purpose is not offering protection and a

guarantee of the set.

7) Short protection of output terminals

This IC has the short protect function for output terminals. If the short protect function operates, output terminal will be

latched and stop in the open state(high inpedance state).After a stop, even if a short state is removed, it does not

return to normal operation automatically. Please once turn off a power supply or a shutdown signal to make it return,

and let turn on again and reboot.

8) Operating condition

Operating voltage and operating temperature are ranges which perform basic function. Electrical characteristics and

absolute maximum rating are not guaranteed in full voltage range or full temperature range.

9) Electrical characteristics specification

Each audio characteristic specification, such as limit output power, total harmonic distortion shows the standard

performance of the device, and depends for it on board layout / use parts / power supply part greatly.

Typical specification value is a value when a device and each parts are directly mounted in the board of Rohm's

standard.

10) Power supply

Large peak current rushes into a SPVDD power supply line at the time of ClassD speaker amplifier use.

The audio characteristic is affected by the value of a power supply decoupling capacitor, and layout.

The power supply decoupling capacitor should be layouted (1uF or more) with sufficiently low ESR (equivalent series

resistance) to most close of IC terminal.

Moreover, in the design of a board pattern, the wiring of a power supply / GND line should become low impedance. In

that case, even if digital power supply and analog power supply are same potential, please devide the digital power

pattern and the analog power pattern and reduce a surroundings lump of the digital noise to the analog power supply

by the common impedance of a wiring pattern.

Please take the same pattern design into consideration also about a GND line. Moreover, while inserting a capacitor

between power supply-GND terminals about all the power supply terminals of LSI, and please determine the value of

capacitor after sufficient confirmation that there is no problem in the characteristics of capacitors to be used (a capacity

omission happens at low temperature) in the case of electrolytic capacitors use.

11) External capacitor

In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a

degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc.

12) Status of this document

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The Japanese version of this document is formal specification. A customer may use this translation version only for a

reference to help reading the formal version.

If there are any differences in translation version of this document formal version takes priority.

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Ordering Information

B U 2 6 1 5 4 M U V -

E 2

Part Number

Package

MUV:VQFP040V6060

Packaging and forming specification

E2: Embossed tape and reel

Physical Dimension, Tape and Reel Information

Package Name

VQFN040V6060

Tape

Embossed carrier tape

2000pcs

Quantity

E2

Direction

of feed

The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand

(

)

Direction of feed

1pin

Reel

Order quantity needs to be multiple of the minimum quantity.

∗

Marking Diagrams

VQFN040V6060 (TOP VIEW)

Part Number Marking

BU26154

LOT Number

1PIN MARK

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Revision History

Date

Revision

Changes

001

002

Rev.001 First revision release

P1. Change the Height of Package

P4. Change the application circuit

23.Jun.2014

26.Oct.2015

P13. Change the VMIC reference voltage (SPVDD=> HVDD)

P38, P48,P49,P50,P51,P73 Register function explanation and register details explanation

-

Removed MCLKOE bit and ADCREN bit、

Added Analog Input Power Management, Speaker Amplifier Power Management registers

MAPCON setting

-

Changed ZCEN explanation(PDATT => EFFECT VOLUME)

Added the explanation of Playback Digital Attenuator Control Register /B “FFh setting”

Changed HPLSEN bit of Audio analog contol2 register

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Notice

Precaution on using ROHM Products

1. Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,

OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you

intend to use our Products in devices requiring extremely high reliability (such as medical equipment ^{(Note 1)}, transport

equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car

accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or

serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.

Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any

damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific

Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are designed and manufactured for use under standard conditions and not under any special or

extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any

special or extraordinary environments or conditions. If you intend to use our Products under any special or

extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of

product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of

flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning

residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PGA-E

Rev.002

Daattaasshheeeett

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

QR code printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PGA-E

Rev.002

Daattaasshheeeett

General Precaution

1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.

ROHM shall not be in an y way responsible or liable for failure, malfunction or accident arising from the use of a ny

ROHM’s Products against warning, caution or note contained in this document.

2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior

notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s

representative.

3. The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all

information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or

liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or

concerning such information.

Notice – WE

Rev.001


型号：	BU26154MUV
厂家：	ROHM
描述：	BU26154是内置Cap-Less耳机放大器、扬声器放大器、触摸屏接口的低功耗紧凑型CODEC，适用于数码相机和电子词典。搭载了稳压器，以便在噪声干扰下稳定sensitive的CODEC部的特性｡扬声器放大器可进行AB类动作与D类动作的切换。因此，存在FM无线电等干扰的影响时，可通过采用AB类动作来防止干扰。作为数字信号处理，搭载了用于特定频带降噪用途的高通滤波器、陷波滤波器和5频段均衡器及准谐波低音功能、噪声门等，实现了灵活的音质效果处理。电子放大器无线数码相机稳压器
文件：	总89页 (文件大小：1657K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BU26154MUV [ROHM]

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