BU7261SF [ROHM]

Operational Amplifier, 1 Func, 10000uV Offset-Max, CMOS, PDSO8, LEAD FREE, SOP-8;
BU7261SF
型号: BU7261SF
厂家: ROHM    ROHM
描述:

Operational Amplifier, 1 Func, 10000uV Offset-Max, CMOS, PDSO8, LEAD FREE, SOP-8

放大器 光电二极管
文件: 总17页 (文件大小:463K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
TECHNICAL NOTE  
General-purpose Operational Amplifier/Comparator  
Low Voltage  
CMOS Operational Amplifier  
BU7261G,BU7261SG, BU7241G,BU7241SG,  
BU7262F/FVM,BU7262S F/FVM, BU7242F/FVM,BU7242S F/FVM  
Description  
BU7261 G  
High speed  
Low pow er  
Single  
Dual  
CMOS op-amp BU7261/BU7241 family and  
BU7262/BU7242 family are input and output  
full swing op-amp. These ICs integrate one  
op-amp or two independent op-amps and phase  
compensation capacitor on a single chip.  
The features of these ICs are low operating supply  
Voltage +1.8V to +5.5V(single supply) and low  
supply current, extremely low input bias current.  
(BU7261SG:105  
)
BU7262 F/FVM  
(BU7262S F/FVM:105  
)
BU7241 G  
Single  
Dual  
(BU7261SG:105  
)
BU7242 F/FVM  
(BU7242S F/FVM:105  
)
Features  
1) Low operating supply voltage (1.8[V]~+5.5[V])  
2) 1.8 [V] to5.5[V](single supply)  
±0.9[V] to±2.75[V](split supply)  
8) Internal ESD protection  
Human body model (HBM) ±4000[V](Typ.)  
9) Wide temperature range  
40[] to85[℃]  
3) Input and Output full swing  
4) Internal phase compensation  
(BU7261G,BU7262 family, BU7241G,BU7242 family)  
40[] to105[]  
5) High slew rate(BU7261 family, BU7262 family)  
6) Low supply current(BU7241 family, BU7242 family)  
7) High large signal voltage gain  
(BU7261SG,BU7262S family, BU7241SG,BU7242S family)  
Pin Assignments  
VDD  
OUT2  
IN2-  
1
2
3
4
8
7
6
5
OUT1  
VDD  
OUT  
1
2
3
5
4
IN+  
CH1  
- +  
IN1-  
+
-
VSS  
IN-  
CH2  
+ -  
IN1+  
VSS  
IN2+  
SSOP5  
SOP8  
MSOP8  
BU7261G  
BU7261SG  
BU7241G  
BU7241SG  
BU7262F  
BU7262SF  
BU7242F  
BU7242SF  
BU7262FVM  
BU7262SFVM  
BU7242FVM  
BU7242SFVM  
2007. Octber  
Absolute maximum ratingTa=25[])  
Rating  
Parameter  
Symbol  
Uni  
BU7261GBU7262 F/FVM  
BU7241GBU7242 F/FVM  
BU7261SGBU7262S F/FVM  
BU7241SGBU7242S F/FVM  
Supply Voltage  
7  
VDDVSS  
(VSS0.3) to VDD0.3  
VDD-VSS  
Vid  
Vicm  
Topr  
Tstg  
V
V
V
Differential Input Voltage(*1)  
Input Common-mode voltage range  
Operating Temperature  
Storage Temperature  
40 to85  
40 to105  
55 to125  
125  
Maximum junction Temperature  
Tjmax  
Note: Absolute maximum rating item indicates the condition which must not be exceeded.  
Application of voltage in excess of absolute maximum rating or use out absoluted maximum rated temperature environment may cause deterioration of characteristics.  
(*1) The voltage difference between inverting input and non-inverting input is the differential input voltage.  
Then input terminal voltage is set to more then VEE.  
Electrical characteristics  
BU7261 series, BU7262series (Unless otherwise specified VDD=+3[V], VSS=0[V], Ta=25[℃])  
Guaranteed limit  
Temperature  
Range  
BU7261G  
BU7262 F/FVM  
Condition  
Parameter  
Symbol  
Unit  
BU7261SG  
BU7262S F/FVM  
Min.  
Min.  
-
-
-
Typ.  
1
-
1
Max.  
Typ.  
1
-
Max.  
9
10  
-
Input offset voltage (*2)(*4)  
25℃  
Full range  
25℃  
9
-
Vio  
mV  
VDD=1.8 to 5.5[V], VOUT=VDD/2  
10  
-
Input offset Current (*2)  
Input Bias Current (*2)  
Supply current (*4)  
Iio  
Ib  
-
-
1
pA  
pA  
25℃  
25℃  
Full range  
25℃  
25℃  
25℃  
25℃  
25℃  
25℃  
25℃  
25℃  
25℃  
25℃  
25℃  
25℃  
25℃  
-
-
-
1
250  
-
-
-
-
-
-
-
1
550  
-
-
-
-
550  
600  
-
1100  
1200  
-
RL=All Op-Amps  
AV=0[dB],VIN=1.5[V]  
IDD  
µA  
High level output voltage  
Low level output voltage  
Large single voltage gain  
Input common-mode voltage range  
Common-mode rejection ratio  
Power supply rejection ratio  
Output source current (*3)  
Output sink current (*3)  
Slew rate  
Gain bandwidth product  
Phase margin  
Total harmonic distortion  
Channel separation  
VOH  
VOL  
AV  
Vicm  
CMRR  
PSRR  
IOH  
IOL  
VDD-0.1  
VDD-0.1  
V
V
dB  
V
dB  
dB  
mA  
mA  
RL=10[k]  
RL=10[k]  
RL=10[k]  
VDD-VSS=3[V]  
-
70  
0
45  
60  
4
5
-
-
-
VSS+0.1  
-
70  
0
45  
60  
4
5
-
-
-
VSS+0.1  
95  
-
-
3
-
-
-
-
-
-
-
-
-
95  
-
-
3
-
-
-
-
-
-
-
-
-
60  
80  
10  
12  
1.1  
2
50°  
0.05  
-
60  
80  
10  
12  
1.1  
2
50°  
0.05  
100  
VDD-0.4[V]  
VSS+0.4[V]  
SR  
FT  
V/µs CL=25[pF]  
MHz CL=25[pF], AV=40[dB]  
θ
CL=25[pF], AV=40[dB]  
VOUT=1[Vp-p],f=1[kHz]  
Av=40[dB]  
THD  
CS  
-
-
-
-
%
dB  
(*2) Absolute value  
(*3) Under the high temperature environment, consider the power dissipation of IC when selecting the output current.  
When the terminal shot circuits are continuously output, the output current is reduced to climb to the temperature inside IC.  
(*4) Full rangeBU7261, BU7262Ta=-40[] to +85[] BU7261S, BU7262STa=-40[] to +105[]  
Electrical characteristics  
BU7241 series, BU7242 series (Unless otherwise specified VDD=+3[V], VSS=0[V], Ta=25[℃])  
Guaranteed limit  
Temperature  
Range  
BU7241G  
BU7242F/FVM  
Condition  
Parameter  
Symbol  
Unit  
BU7241SG  
BU7242S F/FVM  
Min.  
Min.  
Typ.  
Max.  
Typ.  
Max.  
Input offset voltage (*5)(*7)  
25℃  
Full range  
25℃  
25℃  
25℃  
Full range  
25℃  
25℃  
25℃  
25℃  
25℃  
25℃  
25℃  
25℃  
25℃  
25℃  
25℃  
25℃  
-
-
-
-
-
-
1
-
1
1
70  
-
-
-
95  
-
60  
80  
10  
12  
0.4  
0.9  
50°  
0.05  
-
9
10  
-
-
150  
250  
-
-
-
-
-
-
-
1
-
1
1
180  
-
-
-
95  
-
60  
80  
10  
12  
0.4  
0.9  
50°  
0.05  
100  
9
10  
-
-
360  
600  
-
Vio  
mV  
VDD=1.8 to 5.5[V], VOUT=VDD/2  
Input offset Current (*5)  
Input Bias Current (*5)  
Supply current (*7)  
Iio  
Ib  
pA  
pA  
RL=All Op-Amps  
AV=0[dB],VIN=1.5[V]  
IDD  
µA  
High level output voltage  
Low level output voltage  
Large single voltage gain  
Input common-mode voltage range  
Common-mode rejection ratio  
Power supply rejection ratio  
Output source current (*6)  
Output sink current (*6)  
Slew rate  
Gain bandwidth product  
Phase margin  
Total harmonic distortion  
Channel separation  
VOH  
VOL  
AV  
Vicm  
CMRR  
PSRR  
IOH  
IOL  
VDD-0.1  
VDD-0.1  
V
V
dB  
V
dB  
dB  
mA  
mA  
RL=10[k]  
RL=10[k]  
RL=10[k]  
VDD-VSS=3[V]  
-
70  
0
45  
60  
4
5
-
-
-
VSS+0.1  
-
70  
0
45  
60  
4
5
-
-
-
VSS+0.1  
-
3
-
-
-
-
-
-
-
-
-
-
3
-
-
-
-
-
-
-
-
-
VDD-0.4[V]  
VSS+0.4[V]  
SR  
FT  
V/µs CL=25[pF]  
MHz CL=25[pF], AV=40[dB]  
θ
CL=25[pF], AV=40[dB]  
VOUT=1[Vp-p],f=1[kHz]  
Av=40[dB]  
THD  
CS  
-
-
-
-
%
dB  
25℃  
(*5) Absolute value  
(*6) Under the high temperature environment, consider the power dissipation of IC when selecting the output current.  
When the terminal shot circuits are continuously output, the output current is reduced to climb to the temperature inside IC.  
(*7) Full rangeBU7241, BU7242Ta=-40[] to +85[] BU7241S, BU7242STa=-40[] to +105[]  
2/16  
Example of electrical characteristics  
BU7261 family  
BU7261 family  
BU7261 family  
BU7261 family  
800  
1000  
800  
600  
400  
200  
0
800  
600  
400  
200  
0
600  
BU7261G  
105℃  
25℃  
BU7261SG  
85℃  
400  
200  
0
-40℃  
105  
85  
0
50  
100  
150  
0
50  
100  
150  
1
2
3
4
5
6
AMBIENT TEMPERATURE [  
]
AMBIENT TEMPERATURE [  
]
SUPPLY VOLTAGE [V]  
Fig.1  
Fig.2  
Fig.3  
Derating curve  
Derating curve  
Supply Current – Supply Voltage  
BU7261 family  
BU7261 family  
BU7261 family  
8
6
4
2
0
6
4
2
0
1000  
800  
600  
400  
200  
0
5.5V  
105℃  
85℃  
25℃  
5.5V  
3.0V  
3.0V  
1.8V  
-40℃  
1.8V  
-60  
-30  
0
30  
60  
90  
120  
1
2
3
4
5
6
-60  
-30  
0
30  
60  
90  
120  
SUPPLY VOLTAGE [V]  
AMBIENT TEMPERATURE [  
]
AMBIENT TEMPERATURE [  
]
Fig.5  
Fig.6  
Fig.4  
Output Voltage High – Supply Voltage  
Output Voltage – Ambient Temperature  
Supply Current – Ambient Temperature  
(RL=10[k])  
(RL=10[k])  
BU7261 family  
BU7261 family  
BU7261 family  
20  
25  
50  
-40℃  
40  
30  
20  
10  
0
20  
25℃  
15  
10  
5
5.5V  
105℃  
15  
85℃  
3.0V  
10  
85℃  
1.8V  
105℃  
25℃  
5
-40℃  
0
-60  
0
0
0.5  
1
1.5  
2
2.5  
3
-30  
0
30  
60  
90  
120  
1
2
3
4
5
6
SUPPLY VOLTAGE [V]  
AMBIENT TEMPERATURE [  
]
OUTPUT VOLTAGE [V]  
Fig.7  
Fig.8  
Fig.9  
Output Voltage – Supply Voltage  
Output Voltage Low – Ambient Temperature  
Output Source Current – Output Voltage  
(RL=10[k])  
(RL=10[k])  
(VDD=3.0[V])  
BU7261 family  
BU7261 family  
BU7261 family  
80  
20  
15  
10  
5
40  
5.5V  
3.0V  
1.8V  
-40℃  
60  
30  
5.5V  
25℃  
40  
20  
85℃  
3.0V  
105℃  
20  
10  
1.8V  
0
0
-60  
0
-60  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
-30  
0
30  
60  
90  
120  
-30  
0
30  
60  
90  
120  
OUTPUT VOLTAGE [V]  
AMBIENT TEMPERATURE [  
]
AMBIENT TEMPERATURE [  
]
Fig.11  
Fig.12  
Fig.10  
Output Sink Current – Output Voltage  
Output Sink Current – Ambient Temperature  
Output Source Current – Ambient Temperature  
(VDD=3[V])  
(VOUT=VSS+0.4[V])  
(VOUT=VDD-0.4[V])  
(*) The above date is ability value of sample, it is not guaranteed. BU7261G:-40[] to85[] BU7261SG:-40[] to105[]  
3/16  
BU7261 family  
BU7261 family  
BU7261 family  
BU7261 family  
10.0  
10.0  
7.5  
15  
10  
5
7.5  
25℃  
5.0  
5.0  
5.5V  
-40℃  
105℃  
2.5  
2.5  
105℃  
25℃  
85℃  
0.0  
0
0.0  
1.8V  
85℃  
-40℃  
3.0V  
-2.5  
-5.0  
-7.5  
-10.0  
-2.5  
-5.0  
-7.5  
-10.0  
-5  
-10  
-15  
-1  
0
1
2
3
4
1
2
3
4
5
6
-60  
-30  
0
30  
60  
90  
120  
INPUT VOLTAGE [V]  
AMBIENT TEMPERATURE [  
]
SUPPLY VOLTAGE [V]  
Fig.13  
Fig.15  
Fig.14  
Input Offset Voltage – Input Voltage  
Input Offset Voltage – Supply Voltage  
Input Offset Voltage – Ambient Temperature  
(VDD=3[V])  
(Vicm=VDD, VOUT=1.5[V])  
(Vicm=VDD, VOUT=1.5[V])  
BU7261 family  
BU7261 family  
BU7261 family  
160  
160  
120  
100  
80  
60  
40  
20  
0
140  
120  
100  
80  
140  
1.8V  
105℃  
25℃  
40℃  
85℃  
120  
105℃  
5.5V  
3.0V  
85℃  
-40℃  
25℃  
100  
80  
60  
60  
1
2
3
4
5
6
1
2
3
4
5
6
-60  
-30  
0
30  
60  
90  
120  
SUPPLY VOLTAGE [V]  
SUPPLY VOLTAGE [V]  
AMBIENT TEMPERATURE [ ]  
Fig.16  
Fig.17  
Fig.18  
Large Signal Voltage Gain – Supply Voltage Large Signal Voltage Gain – Ambient Temperature Common Mode Rejection Ratio – Supply Voltage  
(VDD=3[V])  
BU7261 family  
BU7261 family  
BU7261 family  
120  
100  
80  
60  
40  
20  
0
120  
100  
80  
60  
40  
20  
0
5
4
3
2
1
0
5.5V  
5.5V  
3.0V  
1.8V  
3.0V  
1.8V  
-60  
-30  
0
30  
60  
90  
120  
-60  
-30  
0
30  
60  
90  
120  
-60  
-30  
0
30  
60  
90  
120  
AMBIENT TEMPERATURE [ ]  
AMBIENT TEMPERATURE [  
]
AMBIENT TEMPERATURE [  
]
Fig.19  
Fig.21  
Fig.20  
Common Mode Rejection Ratio  
Slew Rate L-H – Ambient Temperature  
Power Supply Rejection Ratio  
– Ambient Temperature  
– Ambient Temperature  
(VDD=3[V])  
BU7261 family  
BU7261 family  
100  
80  
60  
40  
20  
0
200  
150  
100  
50  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
Phase  
5.5V  
3.0V  
Gain  
1.8V  
0
1.E+00  
1.E+02  
1.E+04  
1.E+06  
1.E+08  
-60  
-30  
0
30  
60  
90  
120  
AMBIENT TEMPERATURE [  
]
FREQUENCY [Hz]  
Fig.23  
Fig.22  
Gain - Frequency  
Slew Rate H-L – Ambient Temperature  
(*) The above date is ability value of sample, it is not guaranteed. BU7261G:-40[] to85[] BU7261SG:-40[] to105[]  
4/16  
BU7262 family  
BU7262 family  
BU7262 family  
BU7262 family  
1000  
2000  
1600  
1200  
800  
400  
0
1000  
800  
600  
400  
200  
0
800  
105℃  
BU7262F  
BU7262SF  
BU7262FVM  
BU7262SFVM  
85℃  
25℃  
600  
400  
200  
0
-40℃  
85  
0
50  
100  
150  
105  
100  
0
50  
150  
1
2
3
4
5
6
AMBIENT TEMPERATURE [  
]
SUPPLY VOLTAGE [V]  
AMBIENT TEMPERATURE [  
]
Fig.1  
Fig.2  
Fig.3  
Derating curve  
Derating curve  
Supply Current – Supply Voltage  
BU7262 family  
BU7262 family  
BU7262 family  
1500  
1200  
900  
600  
300  
0
8
6
4
2
0
8
6
4
2
0
5.5V  
105℃  
25℃  
5.5V  
85℃  
3.0V  
3.0V  
1.8V  
-40℃  
1.8V  
-60  
-30  
0
30  
60  
90  
120  
-60  
-30  
0
30  
60  
90  
120  
1
2
3
4
5
6
SUPPLY VOLTAGE [V]  
AMBIENT TEMPERATURE [  
]
AMBIENT TEMPERATURE [  
]
Fig.5  
Fig.6  
Fig.4  
Output Voltage High – Supply Voltage  
Output Voltage High – Ambient Temperature  
Supply Current – Ambient Temperature  
(RL=10[k])  
(RL=10[k])  
BU7262 family  
BU7262 family  
BU7262 family  
50  
20  
25  
-40℃  
40  
20  
15  
25℃  
15  
10  
5
30  
5.5V  
105℃  
85℃  
1.8V  
20  
10  
105℃  
85℃  
3.0V  
10  
5
25℃  
-40℃  
0
-60  
0
0
-30  
0
30  
60  
90  
120  
0
0.5  
1
1.5  
2
2.5  
3
1
2
3
4
5
6
SUPPLY VOLTAGE [V]  
OUTPUT VOLTAGE [V]  
AMBIENT TEMPERATURE [  
]
Fig.8  
Fig.9  
Fig.7  
Output Voltage Low – Ambient Temperature  
Output Source Current – Output Voltage  
Output Voltage Low – Supply Voltage  
(RL=10[k])  
(VDD=3.0[V])  
(RL=10[k])  
BU7262 family  
BU7262 family  
BU7262 family  
20  
15  
10  
5
80  
40  
5.5V  
3.0V  
-40℃  
60  
40  
20  
0
30  
20  
10  
0
5.5V  
25℃  
3.0V  
1.8V  
1.8V  
85℃  
105℃  
0
-60  
-60  
-30  
0
30  
60  
90  
120  
-30  
0
30  
60  
90  
120  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
AMBIENT TEMPERATURE []  
OUTPUT VOLTAGE [V]  
AMBIENT TEMPERATURE[  
]
Fig.11  
Fig.12  
Fig.10  
Output Sink Current-Output Voltage  
Output Sink Current – Ambient Temperature  
Output Source Current – Ambient Temperature  
(VDD=3[V])  
(VOUT=VSS+0.4[V])  
(VOUT=VDD-0.4V)  
(*) The above date is ability value of sample, it is not guaranteed. BU7262 F/FVM:-40[] to85[] BU7262S F/FVM:-40[] to105[]  
5/16  
BU7262 family  
BU7262 family  
BU7262 family  
BU7262 family  
10.0  
7.5  
10.0  
7.5  
15  
10  
5
25℃  
5.0  
5.0  
5.5V  
3.0V  
-40℃  
25℃  
-40℃  
2.5  
2.5  
0.0  
0.0  
0
105℃  
85℃  
-2.5  
-5.0  
-7.5  
-10.0  
-2.5  
-5.0  
-7.5  
-10.0  
1.8V  
-5  
85℃  
105℃  
-10  
-15  
1
2
3
4
5
6
-60  
-30  
0
30  
60  
90  
120  
-1  
0
1
2
3
4
SUPPLY VOLTAGE[V]  
AMBIENT TEMPERATURE [  
]
INPUT VOLTAGE [V]  
Fig.14  
Fig.13  
Fig.15  
Input Offset Voltage – Supply voltage  
Input Offset Voltage – Ambient Temperature  
Input Offset Voltage – Input Voltage  
(Vicm=VDD,VOUT=1.5[V])  
(Vicm=VDD,VOUT=1.5[V])  
(VDD=3[V])  
BU7262 family  
BU7262 family  
BU7262 family  
160  
140  
120  
100  
80  
120  
100  
80  
60  
40  
20  
0
160  
25℃  
-40℃  
140  
105℃  
85℃  
1.8V  
120  
105℃  
85℃  
100  
25℃  
3.0V  
5.5V  
-40℃  
80  
60  
60  
1
2
3
4
5
6
1
2
3
4
5
6
-60  
-30  
0
30  
60  
90  
120  
SUPPLY VOLTAGE [V]  
SUPPLY VOLTAGE [V]  
AMBIENT TEMPERATURE []  
Fig.18  
Fig.17  
Fig.16  
Common Mode Rejection Ratio  
Large Signal Voltage Gain – Ambient Temperature  
Large Signal Voltage Gain  
– Supply Voltage(VDD=3[V])  
BU726 family  
BU7262 family  
BU7262 family  
5
4
3
2
1
0
120  
100  
80  
60  
40  
20  
0
120  
5.5V  
100  
80  
60  
40  
20  
0
5.5V  
3.0V  
1.8V  
3.0V  
1.8V  
-60  
-30  
0
30  
60  
90  
120  
-60  
-30  
0
30  
60  
90  
120  
-60  
-30  
0
30  
60  
90  
120  
AMBIENT TEMPERATURE [  
]
AMBIENT TEMPERATURE [  
]
AMBIENT TEMPERATURE [ ]  
Fig.19  
Fig.21  
Fig.20  
Common Mode Rejection ratio –  
Slew Rate L-H – Ambient Temperature  
Power Supply Rejection Ratio –  
Ambient temperature  
Ambient Temperature (VDD=3[V])  
BU7262 family  
BU7262 family  
100  
80  
60  
40  
20  
0
200  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
150  
100  
50  
5.5V  
Phase  
Gain  
3.0V  
1.8V  
0
1.E+00  
1.E+02  
1.E+04  
1.E+06  
1.E+08  
-60  
-30  
0
30  
60  
90  
120  
AMBIENT TEMPERATURE [  
]
FREQUENCY [Hz]  
Fig.23  
Fig.22  
Slew Rate H-L – Ambient Temperature  
Gain - Frequency  
(*) The above date is ability value of sample, it is not guaranteed. BU7262 F/FVM:-40[] to85[] BU7262S F/FVM:-40[] to105[]  
6/16  
BU7241 family  
BU7241 family  
BU7241 family  
BU7241 family  
800  
250  
200  
150  
100  
50  
800  
600  
400  
200  
0
600  
400  
200  
105℃  
85℃  
BU7241G  
BU7241SG  
25℃  
-40℃  
0
0
0
85  
105  
50  
100  
150  
0
50  
100  
150  
1
2
3
4
5
6
AMBIENT TEMPERATURE [  
]
AMBIENT TEMPERATURE [  
]
SUPPLY VOLTAGE [V]  
Fig.1  
Fig.3  
Fig.2  
Derating curve  
Supply Current – Supply Voltage  
Derating curve  
BU7241 family  
BU7241 family  
BU7241 family  
250  
200  
150  
100  
50  
8
6
4
2
0
8
6
4
2
0
5.5V  
5.5V  
1.8V  
105℃  
85℃  
3.0V  
3.0V  
1.8V  
25℃  
-40℃  
0
-60  
-30  
0
30  
60  
90  
120  
-60  
-30  
0
30  
60  
90  
120  
1
2
3
4
5
6
SUPPLY VOLTAGE [V]  
SUPPLY VOLTAGE [V]  
AMBIENT TEMPERATURE [  
]
Fig.5  
Fig.6  
Fig.4  
Output Voltage High – Supply Voltage  
Output Voltage High – Ambient Temperature  
Supply Current – Supply Voltage  
(RL=10[k])  
(RL=10[k])  
BU7241 family  
BU7241 family  
BU7241 family  
50  
60  
50  
40  
30  
20  
10  
0
60  
50  
40  
30  
20  
10  
0
40  
-40℃  
25℃  
5.5V  
30  
20  
10  
0
25℃  
3.0V  
85℃  
105℃  
-40℃  
105℃  
85℃  
1.8V  
-60  
-30  
0
30  
60  
90  
120  
1
2
3
4
5
6
0
0.5  
1
1.5  
2
2.5  
3
SUPPLY VOLTAGE [V]  
AMBIENT TEMPERATURE [  
]
OUTPUT VOLTAGE [V]  
Fig.9  
Fig.8  
Fig.7  
Output Source Current – Output Voltage  
Output Voltage Low – Ambient Temperature  
Output Voltage Low – Supply Voltage  
(VDD=3.0[V])  
(RL=10[k])  
(RL=10[k])  
BU7241 family  
BU7241 family  
BU7241 family  
20  
15  
10  
5
40  
80  
5.5V  
30  
20  
10  
0
60  
3.0V  
25℃  
85℃  
5.5V  
3.0V  
40  
20  
0
1.8V  
105℃  
-40℃  
1.8V  
0
-60  
-30  
0
30  
60  
90  
120  
-60  
-30  
0
30  
60  
90  
120  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
AMBIENT TEMPERATURE [  
]
OUTPUT VOLTAGE [V]  
AMBIENT TEMPERATURE [  
]
Fig.11  
Fig.12  
Fig.10  
Output Sink Current – Output Voltage  
Output Sink current – Ambient Temperature  
Output Source Current – Ambient Temperature  
(VDD=3[V])  
(VOUT=VSS+0.4[V])  
(VOUT=VDD-0.4[V])  
(*) The above date is ability value of sample, it is not guaranteed. BU7241G:-40[] to85[] BU7241SG:-40[] to105[]  
7/16  
BU7241 family  
BU7241 family  
BU7241 family  
BU7241 family  
10.0  
7.5  
15  
10  
5
10.0  
7.5  
5.0  
5.0  
-40℃  
5.5V  
25℃  
2.5  
2.5  
105℃  
25℃  
85℃  
0.0  
0
0.0  
105℃  
-40℃  
85℃  
-2.5  
-5.0  
-7.5  
-10.0  
-2.5  
-5.0  
-7.5  
-10.0  
3.0V  
1.8V  
-5  
-10  
-15  
1
2
3
4
5
6
-1  
0
1
2
3
4
-60  
-30  
0
30  
60  
90  
120  
INPUT VOLTAGE [V]  
SUPPLY VOLTAGE [V]  
AMBIENT TEMPERATURE [  
]
Fig.13  
Fig.15  
Fig.14  
Input Offset Voltage – Supply Voltage  
Input Offset Voltage – Input Voltage  
Input Offset Voltage – Ambient Temperature  
(Vicm=VDD, VOUT=1.5[V])  
(VDD=3[V])  
(Vicm=VDD, VOUT=1.5[V])  
BU7241 family  
BU7241 family  
BU7241 family  
160  
160  
140  
120  
100  
80  
120  
100  
80  
60  
40  
20  
0
105℃  
25℃  
140  
105℃  
85℃  
3.0V  
5.5V  
85℃  
120  
100  
80  
25℃  
-40℃  
-40℃  
1.8V  
60  
60  
1
2
3
4
5
6
-60  
-30  
0
30  
60  
90  
120  
1
2
3
4
5
6
SUPPLY VOLTAGE [V]  
AMBIENT TEMPERATURE [  
]
SUPPLY VOLTAGE [V]  
Fig.16  
Fig.17  
Fig.18  
Large Signal Voltage Gain  
– Supply Voltage  
Large Signal Voltage Gain  
– Ambient Temperature  
Common Mode Rejection Ratio  
– Supply Voltage (VDD=3[V])  
BU7241 family  
BU7241 family  
BU7241 family  
120  
100  
80  
60  
40  
20  
0
150  
120  
90  
60  
30  
0
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
5.5V  
5.5V  
3.0V  
1.8V  
3.0V  
1.8V  
-60  
-30  
0
30  
60  
90  
120  
-60  
-30  
0
30  
60  
90  
120  
-60  
-30  
0
30  
60  
90  
120  
AMBIENT TEMPERATURE [ ]  
AMBIENT TEMPERATURE [  
]
AMBIENT TEMPERATURE [ ]  
Fig.20  
Fig.21  
Fig.19  
Power Supply Rejection Ratio –  
Slew Rate L-H – Ambient Temperature  
Common Mode Rejection Ratio  
(VDD=3[V])  
Ambient Temperature  
BU7241 family  
BU7241 family  
2.0  
1.5  
1.0  
0.5  
0.0  
100  
80  
60  
40  
20  
0
200  
150  
100  
50  
Phase  
5.5V  
3.0V  
Gain  
1.8V  
0
-60  
-30  
0
30  
60  
90  
120  
1.E+00  
1.E+02  
1.E+04  
1.E+06  
1.E+08  
AMBIENT TEMPERATURE [  
]
FREQUENCY[Hz]  
Fig.22  
Fig.23  
Slew Rate H-L – Ambient Temperature  
Gain - Frequency  
(*) The above date is ability value of sample, it is not guaranteed. BU7241G:-40[] to85[] BU7241SG:-40[] to105[]  
8/16  
BU7242 family  
BU7242 family  
BU7242 family  
BU7242 family  
800  
600  
400  
200  
0
1000  
1000  
800  
600  
400  
200  
0
800  
BU7242SF  
BU7242F  
BU7242FVM  
BU7242SFVM  
105℃  
600  
400  
200  
0
85℃  
25℃  
-40℃  
105  
100  
85  
0
50  
100  
150  
0
50  
150  
1
2
3
4
5
6
SUPPLY VOLTAGE [V]  
AMBIENT TEMPERATURE [  
]
AMBIENT TEMPERATURE [ ]  
Fig.1  
Fig.2  
Fig.3  
Derating curve  
Derating curve  
Supply Current – Supply Voltage  
BU7242 family  
BU7242 family  
BU7242 family  
800  
600  
400  
200  
0
8
6
4
2
0
8
6
4
2
0
5.5V  
105℃  
85℃  
5.5V  
3.0V  
1.8V  
25℃  
3.0V  
-40℃  
1.8V  
-60  
-30  
0
30  
60  
90  
120  
1
2
3
4
5
6
-60  
-30  
0
30  
60  
90  
120  
SUPPLY VOLTAGE [V]  
AMBIENT TEMPERATURE [  
]
AMBIENT TEMPERATURE [  
]
Fig.6  
Fig.5  
Fig.4  
Output Voltage High – Ambient Temperature  
Output Voltage High – Supply Voltage  
Supply Current – Ambient Temperature  
(RL=10[k])  
(RL=10[k])  
BU7242 family  
BU7242 family  
BU7242 family  
50  
40  
30  
20  
10  
0
25  
20  
15  
10  
5
40  
-40℃  
25℃  
30  
105℃  
85℃  
20  
5.5V  
3.0V  
85℃  
105℃  
10  
0
25℃  
1.8V  
-40℃  
0
-60  
-30  
0
30  
60  
90  
120  
1
2
3
4
5
6
0
0.5  
1
1.5  
2
2.5  
3
SUPPLY VOLTAGE [V]  
AMBIENT TEMPERATURE [  
]
OUTPUT VOLTAGE [V]  
Fig.8  
Fig.7  
Fig.9  
Output Voltage Low – Ambient Temperature  
Output Voltage Low – Supply Voltage  
Output Source Current – Output Voltage  
(RL=10[k])  
(RL=10[k])  
(VDD=3.0[V])  
BU7242 family  
BU7242 family  
BU7242 family  
80  
20  
40  
5.5V  
3.0V  
1.8V  
60  
15  
10  
5
30  
20  
10  
0
85℃  
105℃  
25℃  
5.5V  
40  
20  
0
3.0V  
1.8V  
-40℃  
0
-60  
-30  
0
30  
60  
90  
120  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
-60  
-30  
0
30  
60  
90  
120  
AMBIENT TEMPERATURE []  
OUTPUT VOLTAGE [V]  
AMBIENT TEMPERATURE[  
]
Fig.11  
Fig.10  
Fig.12  
Output Sink Current – Ambient Temperature  
Output Sink Current – Output Voltage  
Output Source Current – Ambient Temperature  
(VOUT=VSS+0.4[V])  
(VDD=3[V])  
(VOUT=VDD-0.4[V])  
(*) The above date is ability value of sample, it is not guaranteed. BU7242F/FVM:-40[] to85[] BU7242SF/FVM:-40[] to105[]  
9/16  
BU7242 family  
BU7242 family  
BU7242 family  
BU7242 family  
10.0  
7.5  
15  
10  
5
10.0  
7.5  
5.5V  
3.0V  
5.0  
5.0  
-40℃  
25℃  
25℃  
-40℃  
85℃  
2.5  
2.5  
0
0.0  
0.0  
85℃  
105℃  
105℃  
-2.5  
-5.0  
-7.5  
-10.0  
-2.5  
-5.0  
-7.5  
-10.0  
-5  
1.8V  
-10  
-15  
-60  
-30  
0
30  
60  
90  
120  
-1  
0
1
2
3
4
1
2
3
4
5
6
INPUT VOLTAGE [V]  
AMBIENT TEMPERATURE [  
]
SUPPLY VOLTAGE[V]  
Fig.13  
Fig.15  
Fig.14  
Input Offset Voltage – Supply Voltage  
Input Offset Voltage – Input Voltage  
Input Offset Voltage – Ambient Temperature  
(Vicm=VDD, VOUT=1.5[V])  
(VDD=3[V])  
(Vicm=VDD, VOUT=1.5[V])  
BU7242 family  
BU7242 family  
BU7242 family  
160  
160  
120  
100  
80  
60  
40  
20  
0
105℃  
85℃  
140  
120  
100  
80  
140  
120  
100  
80  
105℃  
1.8V  
85℃  
25℃  
-40℃  
5.5V  
3.0V  
25℃  
-40℃  
60  
60  
1
2
3
4
5
6
-60  
-30  
0
30  
60  
90  
120  
1
2
3
4
5
6
SUPPLY VOLTAGE [V]  
AMBIENT TEMPERATURE []  
SUPPLY VOLTAGE [V]  
Fig.16  
Fig.17  
Fig.18  
Large Signal Voltage – Supply Voltage  
Large Signal Voltage – Ambient Temperature  
Common Mode Rejection Ratio – Supply Voltage  
(VDD=3[V])  
BU7242 family  
BU7242 family  
BU7242 family  
120  
100  
120  
3.0  
5.5V  
3.0V  
100  
80  
60  
40  
20  
0
2.5  
2.0  
80  
60  
40  
20  
0
5.5V  
1.5  
1.8V  
1.0  
3.0V  
0.5  
0.0  
1.8V  
-60  
-30  
0
30  
60  
90  
120  
-60  
-30  
0
30  
60  
90  
120  
-60  
-30  
0
30  
60  
90  
120  
AMBIENT TEMPERATURE [  
]
AMBIENT TEMPERATURE []  
AMBIENT TEMPERATURE [  
]
Fig.19  
Fig.21  
Fig.20  
Common Mode Rejection Ratio –  
Slew Rate L-H – Ambient Temperature  
Power Supply Rejection Ratio –  
Ambient Temperature  
Ambient Temperature(VDD=3[V])  
BU7242 family  
BU7242 family  
2.0  
1.5  
1.0  
0.5  
0.0  
100  
80  
60  
40  
20  
0
200  
150  
100  
50  
Phase  
5.5V  
Gain  
3.0V  
1.8V  
0
-60  
-30  
0
30  
60  
90  
120  
1.E+00  
1.E+02  
1.E+04  
1.E+06  
1.E+08  
AMBIENT TEMPERATURE [  
]
FREQUENCY [Hz]  
Fig.23  
Fig.22  
Gain - Frequency  
Slew Rate H-L – Ambient Temperature  
(*) The above date is ability value of sample, it is not guaranteed. BU7242F/FVM:-40[] to85[] BU7242SF/FVM:-40[] to105[]  
10/16  
Schematic diagram  
Fig.1 simplified schematic  
Test circuit1 NULL method  
VDD,VSS,EK,Vicm Unit : [V]  
Parameter  
Calculation  
VF  
S1  
ON  
ON  
S2  
ON  
ON  
S3  
VDD VSS  
EK  
-1.5  
-0.5  
-2.5  
Vicm  
3
Input offset voltage  
VF1  
VF2  
VF3  
VF4  
VF5  
VF6  
VF7  
OFF  
ON  
3
0
1
2
Large signal voltage gain  
3
0
1.5  
0
3
Common-mode rejection ratio  
(Input common-mode voltage range)  
ON  
ON  
ON  
ON  
OFF  
OFF  
3
0
0
-1.5  
-0.9  
3
4
1.8  
5.5  
Power supply rejecyion ratio  
0
Calculation-  
1. Input offset Voltage (Vio)  
2. Large signal voltage gain (Av)  
3. Common-mode rejection ratio (CMRR)  
4. Power supply rejection ratio (PSRR)  
0.1[µF]  
Rf =50[k]  
0.01[µF]  
500[k]  
VDD  
SW1  
EK  
15[V]  
Vo  
Ri=1[M]  
0.015[µF]  
RS 50[]  
500[k]  
0.015[µF]  
DUT  
NULL  
SW3  
RS 50[]  
Ri=1[M]  
1000[pF]  
VF  
RL  
VRL  
Vicm  
SW2  
50[k]  
-15[V]  
VSS  
Fig.2 Test Circuit 1 (one channel only)  
11/16  
Test circuit2 switch condition  
Unit: [V]  
SW SW SW SW SW SW SW SW SW SW SW SW  
10 11 12  
SW No.  
1
2
3
4
5
6
7
8
9
Supply current  
OFF OFF ON OFF ON OFF OFF OFF OFF OFF OFF OFF  
OFF ON OFF OFF ON OFF OFF ON OFF OFF ON OFF  
OFF ON OFF OFF ON OFF OFF OFF OFF ON OFF OFF  
OFF OFF ON OFF OFF OFF ON OFF ON OFF OFF ON  
ON OFF OFF ON ON OFF OFF OFF ON OFF OFF ON  
maximum output voltage RL=10 [k]  
output current  
Slew rate  
maximum frequency  
Vin[V]  
SW3  
3
SW4  
R2 100[k]  
VDD=3[V]  
0
SW1  
SW2  
t
Input waveform  
Vout[V]  
SW8  
SW9  
SW10  
SW11  
SW12  
SW5  
SW6  
SW7  
R1  
1[k]  
SR=ΔV/Δt  
3
GND  
ΔV  
RL  
CL  
VIN-  
VIN+  
Vo  
0
t
Δ
t
Output waveform  
Fig3. Test circuit2 (one channel only)  
Fig4. Slew rate input output wave  
Test circuit3 Channel separation  
R2=100[k]  
R2=100[k]  
VDD  
VDD  
R1=1[k]  
R1=1[k]  
VOUT1  
=1[Vrms]  
V
V
VOUT2  
R1//R2  
R1//R2  
VIN  
VSS  
VSS  
100×VOUT1  
VOUT2  
CS=20Log  
Fig5. Test circuit3  
12/16  
Description of electrical characteristics  
Described here are the terms of electric characteristics used in this technical note. Items and symbols used are also shown.  
Note that item name and symbol and their meaning may differ from those on another manufacture’s document or general document.  
1. Absolute maximum ratings  
Absolute maximum rating item indicates the condition which must not be exceeded. Application of voltage in excess of absolute  
Maximum rating or use out of absolute maximum rated temperature environment may cause deterioration of dharacteristics.  
1.1 Power supply voltage VDD/VSS)  
Indicates the maximum voltage that can be applied between the positive power supply terminal and negative power supply terminal  
without deterioration or destruction of characteristics of internal circuit.  
1.2  
Differential input voltage Vid)  
Indicates the maximum voltage that can be applied between non-inverting terminal and inverting terminal without deterioration and  
destruction of characteristics of IC.  
1.3  
1.4  
Input common-mode voltage range Vicm)  
Indicates the maximum voltage that can be applied to non-inverting terminal and inverting terminal without deterioration or destruction of  
characteristics. Input common-mode voltage range of the maximum ratings not assure normal operation of IC. When normal  
Operation of IC is desired, the input common-mode voltage of characteristics item must be followed.  
Power dissipation Pd)  
Indicates the power that can be consumed by specified mounted board at the ambient temperature 25(normal temperature). As for  
package product, Pd is determined by the temperature that can be permitted by IC chip in the packagemaximum junction temperature)  
and thermal resistance of the package  
2. Electrical characteristics item  
2.1  
Input offset voltage Vio)  
Indicates the voltage difference between non-inverting terminal and inverting terminal. It can be translated into the input voltage  
difference required for setting the output voltage at 0 [V]  
2.2  
2.3  
Input offset current Iio)  
Indicates the difference of input bias current between non-inverting terminal and inverting terminal.  
Input bias current Ib)  
Indicates the current that flows into or out of the input terminal. It is defined by the average of input bias current at non-inverting terminal  
and input bias current at inverting terminal.  
2.4  
2.5  
Circuit current ICC)  
Indicates the IC current that flows under specified conditions and no-load steady status.  
High level output voltage / Low level output voltageVOH/VOL)  
Indicates the voltage range that can be output by the IC under specified load condition. It is typically divided into high-level output voltage  
and low-level output voltage. High-level output voltage indicates the upper limit of output voltage. Low-level output voltage indicates the  
lower limit.  
2.6  
Large signal voltage gain AV)  
Indicates the amplifying rate (gain) of output voltage against the voltage difference between non-inverting terminal and inverting terminal.  
It is normally the amplifying rate (gain) with reference to DC voltage.  
Av = (Output voltage fluctuation) / (Input offset fluctuation)  
2.7  
Input common-mode voltage range Vicm)  
Indicates the input voltage range where IC operates normally.  
2.8 Common-mode rejection ratio CMRR)  
Indicates the ratio of fluctuation of input offset voltage when in-phase input voltage is changed. It is normally the fluctuation of DC.  
CMRR =(Change of Input common-mode voltage/Input offset fluctuation)  
2.9 Power supply rejection ratio PSRR)  
Indicates the ratio of fluctuation of input offset voltage when supply voltage is changed. It is normally the fluctuation of DC.  
PSRR=(Change of power supply voltage/Input offset fluctuation)  
2.10 Channel separationCS)  
Indicates the fluctuation of input offset voltage or that of output voltage with reference to the change of output voltage of driven channel.  
2.11 Slew rate SR)  
Indicates the time fluctuation ratio of voltage output when step input signal is applied  
2.12 Unity gain frequency ft)  
Indicates a frequency where the voltage gain of Op-Amp is 1.  
2.13 Total harmonic distortion + Noise THDN)  
Indicates the fluctuation of input offset voltage or that of output voltage with reference to the change of output voltage  
of driven channel  
2.14 Input referred noise voltage Vn)  
Indicates a noise voltage generated inside the operational amplifier equivalent by ideal voltage source connected  
in series with input terminal  
13/16  
Derating curve  
Power dissipation (total loss) indicates the power that can be consumed by IC at Ta=25(normal temperature).IC is heated  
when it consumed power, and the temperature of IC ship becomes higher than ambient temperature. The temperature that can  
be accepted by IC chip depends on circuit configuration, manufacturing process, and consumable power is limited. Power  
dissipation is determined by the temperature allowed in IC chip (maximum junction temperature) and thermal resistance of  
package (heat dissipation capability). The maximum junction temperature is typically equal to the maximum value in the  
storage package (heat dissipation capability). The maximum junction temperature is typically equal to the maximum value in  
the storage temperature range. Heat generated by consumed power of IC radiates from the mold resin or lead frame of the  
package. The parameter which indicates this heat dissipation capability (hardness of heat release) is called thermal resistance,  
represented by the symbol θj-a[/W]. The temperature of IC inside the package can be estimated by this thermal resistance.  
Fig.6 (a) shows the model of thermal resistance of the package. Thermal resistance θja, ambient temperature Ta, junction  
temperature Tj, and power dissipation Pd can be calculated by the equation below :  
θja (TjTa) / Pd  
[/W]  
・・・・・ (Ⅰ)  
Derating curve in Fig.6 (b) indicates power that can be consumed by IC with reference to ambient temperature. Power that can  
be consumed by IC begins to attenuate at certain ambient temperature. This gradient iis determined by thermal resistance θja.  
Thermal resistance θja depends on chip size, power consumption, package, ambient temperature, package condition, wind  
velocity, etc even when the same of package is used. Thermal reduction curve indicates a reference value measured at a  
specified condition. Fig7(c)-(f) show a derating curve for an example of BU7261series, BU7262series, BU7241,BU7242series.  
Power dissipation of LSI [W]  
Pd(max)  
θja = ( Tj Ta ) / Pd  
[
/W]  
P2  
θja2 < θja1  
Ambient temperature Ta [  
]
θja2  
P1  
Tj(max)  
θja1  
50  
Ambient temperature Ta [  
Chip surface temperature Tj [  
]
0
25  
75  
100  
125  
150  
Power dissipation P [W]  
]
BU7261/BU7241  
Tj(max)  
(b) Derating curve  
(a) Thermal resistance  
Fig.6 Thermal resistance and derating  
800  
600  
400  
200  
0
1000  
800  
BU7262F(*9)  
BU7242F(*9)  
620[mw]  
480[mw]  
BU7261G(*8)  
540[mw]  
600  
400  
200  
0
BU7241G(*8)  
BU7262FVM(*10)  
BU7242FVM(*10)  
85  
0
50  
100  
150  
0
50  
100  
150  
85  
AMBIENT TEMPERATURE [  
]
AMBIENT TEMPERATURE [  
]
(d) BU7262F/FVM BU7242F/FVM  
(c) BU7261G BU7241G  
1000  
800  
600  
400  
200  
0
800  
600  
400  
200  
0
BU7262SF(*9)  
BU7242SF(*9)  
620[mw]  
480[mw]  
BU7261SG(*8)  
BU7241SG(*8)  
540[mw]  
BU7262SFVM(*10)  
BU7242SFVM(*10)  
105  
100  
105  
0
50  
150  
0
50  
100  
150  
AMBIENT TEMPERATURE [  
(f) BU7262S F/FVM BU7242S F/FVM  
]
AMBIENT TEMPERATURE [  
(e) BU7261SG BU7241SG  
]
*8) (*9) (*10)  
Unit  
[mW/]  
5.4  
6.2  
4.8  
When using the unit above Ta=25[], subtract the value above per degree[]. Permissible dissipation is the value  
when FR4 glass epoxy board 70[mm]×70[mm]×1.6[mm] (cooper foil area below 3[]) is mounted.  
Fig.7 Derating Curve  
14/16  
Cautions on use  
1) Absolute maximum ratings  
Absolute maximum ratings are the values which indicate the limits,  
within which the given voltage range can be safely charged to the terminal.  
However, it does not guarantee the circuit operation.  
2) Applied voltage to the input terminal  
For normal circuit operation of voltage comparator, please input voltage for its  
input terminal within input common mode voltage VDD+0.3[V].  
Then, regardless of power supply voltage,VSS-0.3[V] can be applied to input  
terminals without deterioration or destruction of its characteristics.  
3) Operating power supply (split power supply/single power supply)  
The voltage comparator operates if a given level of voltage is applied between VDD and  
VSS. Therefore, the operational amplifier can be operated under single power supply  
or split power supply.  
4) Power dissipation (pd)  
If the IC is used under excessive power dissipation. An increase in the chip temperature will cause  
deterioration of the radical characteristics of IC.  
For example, reduction of current capability. Take consideration of the effective power dissipation and  
thermal design with a sufficient margin. Pd is reference to the provided power dissipation curve.  
5) Short circuits between pins and incorrect mounting  
Short circuits between pins and incorrect mounting when mounting the IC on a printed circuits board,  
take notice of the direction and positioning of the IC.  
If IC is mounted erroneously, It may be damaged. Also, when a foreign object is inserted between  
output, between output and VDD terminal or VSS terminal which causes short circuit, the IC may be damaged.  
6) Using under strong electromagnetic field  
Be careful when using the IC under strong electromagnetic field because it may malfunction.  
7) Usage of IC  
When stress is applied to the IC through warp of the printed circuit board,  
The characteristics may fluctuate due to the piezo effect.  
Be careful of the warp of the printed circuit board.  
8) Testing IC on the set board  
When testing IC on the set board, in cases where the capacitor is connected to the low impedance,  
make sure to discharge per fabrication because there is a possibility that IC may be damaged by stress.  
When removing IC from the set board, it is essential to cut supply voltage.  
As a countermeasure against the static electricity, observe proper grounding during fabrication process  
and take due care when carrying and storage it.  
9) The IC destruction caused by capacitive load  
The transistors in circuits may be damaged when VDD terminal and VSS terminal is shorted with the charged  
output terminal capacitor.When IC is used as a operational amplifier or as an application circuit,  
where oscillation is not activated by an output capacitor,the output capacitor must be kept below  
0.1[μF] in order to prevent the damage mentioned above.  
10) Decupling capacitor  
Insert the deculing capacitance between VDD and VSS, for stable operation of operational amplifier.  
11) Latch up  
Be careful of input vltage that exceed the VDD and VSS. When CMOS device have sometimes occur  
latch up operation. And protect the IC from abnormaly noise  
15/16  
Dimensions  
SSOP5  
SOP8  
MSOP8  
Model number construction  
Specify the product by the model number  
when placing an order.  
-
Make sure of the combinations of items.  
Start with the leftmost space without leaving  
any empty space between characters.  
B U 7 2 6 2 S F  
E 2  
E2 Embossed tape on reel with pin 1 near far when pulled out  
TR Embossed tape on reel with pin 1 near far when pulled out  
ROHM product name  
Package type  
G : SSOP5  
F : SOP8  
FVM : MSOP8  
BU7261 BU7261S  
BU7241 BU7241S  
BU7262 BU7262S  
BU7242 BU7242S  
Packing specification reference  
Packing  
specification name  
Package  
Quantity  
Embossed carrier tape  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SSOP5  
SOP8  
TR  
E2  
TR  
3000  
2500  
3000  
1Pin  
Direction of feed  
Reel  
Direction of feed  
1Pin  
Reel  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MSOP8  
Direction of feed  
1Pin  
Reel  
Appendix  
Notes  
No technical content pages of this document may be reproduced in any form or transmitted by any  
means without prior permission of ROHM CO.,LTD.  
The contents described herein are subject to change without notice. The specifications for the  
product described in this document are for reference only. Upon actual use, therefore, please request  
that specifications to be separately delivered.  
Application circuit diagrams and circuit constants contained herein are shown as examples of standard  
use and operation. Please pay careful attention to the peripheral conditions when designing circuits  
and deciding upon circuit constants in the set.  
Any data, including, but not limited to application circuit diagrams information, described herein  
are intended only as illustrations of such devices and not as the specifications for such devices. ROHM  
CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any  
third party's intellectual property rights or other proprietary rights, and further, assumes no liability of  
whatsoever nature in the event of any such infringement, or arising from or connected with or related  
to the use of such devices.  
Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or  
otherwise dispose of the same, no express or implied right or license to practice or commercially  
exploit any intellectual property rights or other proprietary rights owned or controlled by  
ROHM CO., LTD. is granted to any such buyer.  
Products listed in this document are no antiradiation design.  
The products listed in this document are designed to be used with ordinary electronic equipment or devices  
(such as audio visual equipment, office-automation equipment, communications devices, electrical  
appliances and electronic toys).  
Should you intend to use these products with equipment or devices which require an extremely high level  
of reliability and the malfunction of which would directly endanger human life (such as medical  
instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers  
and other safety devices), please be sure to consult with our sales representative in advance.  
It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance  
of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow  
for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in  
order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM  
cannot be held responsible for any damages arising from the use of the products under conditions out of the  
range of the specifications or due to non-compliance with the NOTES specified in this catalog.  
Thank you for your accessing to ROHM product informations.  
More detail product informations and catalogs are available, please contact your nearest sales office.  
THE AMERICAS / EUPOPE / ASIA / JAPAN  
ROHM Customer Support System  
Contact us : webmaster@ rohm.co.jp  
www.rohm.com  
TEL : +81-75-311-2121  
FAX : +81-75-315-0172  
Copyright © 2007 ROHM CO.,LTD.  
21, Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan  
Appendix1-Rev2.0  

相关型号:

BU7261SF-E2

Operational Amplifier, 1 Func, 10000uV Offset-Max, CMOS, PDSO8, LEAD FREE, SOP-8
ROHM

BU7261SFVM

Operational Amplifier, 1 Func, 10000uV Offset-Max, CMOS, PDSO8, LEAD FREE, MSOP-8
ROHM

BU7261SFVM-TR

Operational Amplifier, 1 Func, 10000uV Offset-Max, CMOS, PDSO8, LEAD FREE, MSOP-8
ROHM

BU7261SG

Low Voltage Operation CMOS Operational Amplifiers
ROHM

BU7261SG-TR

Operational Amplifier, 1 Func, 10000uV Offset-Max, CMOS, PDSO5, SSOP-5
ROHM

BU7262F

Low Voltage Operation CMOS Operational Amplifiers
ROHM

BU7262F-E2

Input/Output Full Swing Input/Output Full Swing
ROHM

BU7262FVM

Low Voltage Operation CMOS Operational Amplifiers
ROHM

BU7262FVM-TR

Operational Amplifier, 2 Func, 10000uV Offset-Max, CMOS, PDSO8, MSOP-8
ROHM

BU7262G

Operational Amplifier, 2 Func, 10000uV Offset-Max, CMOS, PDSO5, LEAD FREE, SSOP-5
ROHM

BU7262G-TR

Operational Amplifier, 2 Func, 10000uV Offset-Max, CMOS, PDSO5, LEAD FREE, SSOP-5
ROHM

BU7262NUX

Full Swing Low Voltage Operation CMOS Operational Amplifiers
ROHM