BU91R64CH-M_技术文档

Datasheet

Low Duty LCD Segment Driver

For Automotive COG Application

BU91R64CH-M Max 320 Segments (80SEG x 4COM)

General Description

Key Specifications

BU91R64CH-M is a 1/4, 1/3, 1/2 Duty or Static COG type

LCD driver that can be used for automotive applications

and can drive up to 320 LCD Segments.

 Supply Voltage Range:

+2.7 V to +6.0 V

 LCD Drive Power Supply Range: +2.7 V to +6.0 V

 Operating Temperature Range: -40 °C to +105 °C

This driver can be cascaded up-to maximum of 4 drivers

for larger LCD panel application.

It supports VA LCD displays, which has better optical

performance with higher LCD voltage driving and higher

frame frequency driving.

 Max Segments:

 Display Duty:

 Bias:

320 Segments

1/4, 1/3, 1/2, Static Selectable

1/2, 1/3 Selectable

 Interface: 2-wire / 3-wire Serial Interface Selectable

This driver includes read function for display data and

command registers, wherein it is possible to detect

malfunction due to noise.

Special Characteristics

 ESD(HBM) ^{(Note 2)}

:

±2,000 V(Typ)

±100 mA(Typ)

 Latch-up Current ^{(Note 2)}

:

It can also support other error detections such as

interface checksum detection, glass breaking detection,

logic error detection and SEG / COM toggle detection.

A defective mounting of COG can easily be controlled by

using terminals to measure ITO resistance.

It can support operating temperature of up to +105 °C

and compliant for AEC-Q100, as required for Automotive

Application.

(Note 2) There is data when LSI was put on a temporary package.

Applications

 Instrument Clusters

 Climate Controls

 Car Audios / Radios

 Meters

 White Goods

 Healthcare Products

 Battery Operated Applications

etc.

Features

 AEC-Q100 Compliant ^{(Note 1)}

 1/4, 1/3, 1/2 Duty or Static Drive Selectable

1/4 Duty Drive:

1/3 Duty Drive:

1/2 Duty Drive:

Static Drive:

Max 320 Segments

Max 240 Segments

Max 160 Segments

Max 80 Segments

Package

Au Bump Chip

 Integrated Buffer AMP for LCD Driving

 Integrated Oscillator Circuit and

Software

Programmable Frame Frequency from 66 Hz to

488 Hz

 Support External Clock Input

 Integrated EVR Function to Adjust LCD Contrast

 Integrated Power On Reset Circuit

 No External Components

 Low Power Consumption Design

 Support Display Inhibit Control

 Configurable COM Driving Order

 Support Max 4 Drivers Cascade Connection

(BU91R64 / R65 / R66CH-M Available)

 Support Register and Display Data Read-back

Function

 Support LCD Contact Resistance Measurement

 Support Error Detection and Status Read Function

Glass Breaking Detection

Interface Checksum

Logic Error Detection

SEG / COM Toggle Detection

(Note 1) Quality Information:

There is data when LSI was put on a temporary package.

Please use it as reference data.

〇Product structure : Silicon monolithic integrated circuit 〇This product has no designed protection against radioactive rays

.

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Contents

General Description ................................................................................................................................................................1

Features.................................................................................................................................................................................1

Key Specifications...................................................................................................................................................................1

Special Characteristics............................................................................................................................................................1

Applications............................................................................................................................................................................1

Package.................................................................................................................................................................................1

Contents.................................................................................................................................................................................2

Typical Application Circuit........................................................................................................................................................6

Block Diagram ........................................................................................................................................................................6

Terminal Description................................................................................................................................................................7

Recommended ITO Layout......................................................................................................................................................8

Terminal Resistance ..........................................................................................................................................................10

PAD Arrangement ................................................................................................................................................................. 11

Dimension ............................................................................................................................................................................12

PAD Coordinates ..................................................................................................................................................................13

Absolute Maximum Ratings (VSS = 0V).................................................................................................................................15

Recommended Operating Conditions ....................................................................................................................................15

Electrical Characteristics .......................................................................................................................................................16

DC Characteristics.............................................................................................................................................................16

Oscillation Characteristics..................................................................................................................................................17

2-wire Serial Interface Characteristics ................................................................................................................................18

3-wire Serial Interface Characteristics ................................................................................................................................19

I/O Equivalence Circuit..........................................................................................................................................................20

MCU Interface ......................................................................................................................................................................21

START and STOP Condition (2-wire)..................................................................................................................................21

Acknowledge (ACK) (2-wire)..............................................................................................................................................21

Command / Display Data Transfer Method (2-wire).............................................................................................................22

Display Data Transfer Method (2-wire) ...............................................................................................................................23

Display Data Read-back Method (2-wire) ...........................................................................................................................24

Command Registers Read-back Method (2-wire)................................................................................................................25

Command / Display Data Transfer Method (3-SPI)..............................................................................................................26

Command Transfer Method (3-SPI)....................................................................................................................................26

Display Data Transfer Method (3-SPI) ................................................................................................................................27

Display Data Read-back Method (3-SPI) ............................................................................................................................28

Command Registers Read-back Method (3-SPI) ................................................................................................................28

OSC (Oscillator)....................................................................................................................................................................29

SYNC CTRL (Multi-chip Structure).........................................................................................................................................30

LCD Driver Voltage Generator / LCD Bias Selector ................................................................................................................33

POR and Reset Initialize Condition........................................................................................................................................33

Blink Control (Blink Timing Generator) ...................................................................................................................................33

Error Detection......................................................................................................................................................................34

Glass Breaking Detection...................................................................................................................................................35

Checksum Detection..........................................................................................................................................................37

Logic Error Detection.........................................................................................................................................................38

SEG / COM Toggle Detection.............................................................................................................................................39

Contact Resistance Check.................................................................................................................................................39

Command / Function List.......................................................................................................................................................40

Detailed Command Description .............................................................................................................................................40

1. Mode Set 1 (MODESET1)..............................................................................................................................................40

2. Address Set (ADSET) ....................................................................................................................................................41

3. Sub Address Set (SADSET)...........................................................................................................................................41

4. Frame Rate Set (FRSET)...............................................................................................................................................42

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5. Blink Control1 (BLKCTL1)..............................................................................................................................................43

6. Blink Control2 (BLKCTL2)..............................................................................................................................................43

7. Command Extension (CMDXTN)....................................................................................................................................44

8. Software Reset (SWRST) ..............................................................................................................................................44

9. Mode Set 2 (MODESET2)..............................................................................................................................................45

10. Mode Set 3 (MODESET3)............................................................................................................................................45

11. Contrast Setting (CNTSET) ..........................................................................................................................................46

12. Read Control (RDCTL).................................................................................................................................................47

13. Checksum (CHKSUM) .................................................................................................................................................47

14. COM Set (COMSET)....................................................................................................................................................48

LCD Driving Waveform..........................................................................................................................................................49

1/3 Bias, 1/4 Duty Drive.....................................................................................................................................................49

1/2 Bias, 1/4 Duty Drive.....................................................................................................................................................50

1/3 Bias, 1/3 Duty Drive.....................................................................................................................................................51

1/2 Bias, 1/3 Duty Drive.....................................................................................................................................................52

1/3 Bias, 1/2 Duty Drive.....................................................................................................................................................53

1/2 Bias, 1/2 Duty Drive.....................................................................................................................................................54

Static Drive........................................................................................................................................................................55

Example of Display Data.......................................................................................................................................................56

Initialize Sequence................................................................................................................................................................57

Start Sequence.....................................................................................................................................................................58

Start Sequence Example1 .................................................................................................................................................58

Start Sequence Example2 .................................................................................................................................................59

Cautions in Power On / Off....................................................................................................................................................60

Display Off Operation in External Clock Mode........................................................................................................................61

In Multi-chip Structure in Internal Clock Mode.....................................................................................................................61

Note on The Multiple Device Connection to 2-wire Serial Interface..........................................................................................62

Note in Case that the SDA is stuck at LOW............................................................................................................................62

Operational Notes.................................................................................................................................................................63

1.

2.

3.

4.

5.

6.

7.

8.

Reverse Connection of Power Supply ......................................................................................................................63

Power Supply Lines.................................................................................................................................................63

Ground Voltage.......................................................................................................................................................63

Ground Wiring Pattern.............................................................................................................................................63

Recommended Operating Conditions.......................................................................................................................63

Inrush Current.........................................................................................................................................................63

Testing on Application Boards..................................................................................................................................63

Inter-pin Short and Mounting Errors .........................................................................................................................63

Unused Input Pins...................................................................................................................................................63

Regarding the Input Pin of the IC.............................................................................................................................63

Ceramic Capacitor...................................................................................................................................................63

Disturbance Light ....................................................................................................................................................64

9.

10.

11.

12.

Ordering Information.............................................................................................................................................................65

Minimum Order Quantity (MOQ)............................................................................................................................................65

Marking Diagram...................................................................................................................................................................65

Packing Quantity...................................................................................................................................................................66

Pellet Drawing ......................................................................................................................................................................66

Package Condition................................................................................................................................................................67

Physical Dimension Tray Information.....................................................................................................................................68

Revision History....................................................................................................................................................................69

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Figure 1. PAD / Bump Information...................................................................................................................................12

Figure 2. Operating Current vs Power Supply Voltage .....................................................................................................16

Figure 3. Frame Frequency vs Temperature....................................................................................................................17

Figure 4. Interface Timing of 2-wire Serial Interface.........................................................................................................18

Figure 5. Interface Timing of 3-wire Serial Interface.........................................................................................................19

Figure 6. 2-wire Command / Data Transfer Format..........................................................................................................21

Figure 7. Acknowledge Timing........................................................................................................................................21

Figure 8. Wrong Slave Address Case..............................................................................................................................21

Figure 9. 2-wire Interface Protocol ..................................................................................................................................22

Figure 10. Case of Exiting Data Transfer State in 2-wire..................................................................................................22

Figure 11. Display Data Transfer in 2-wire.......................................................................................................................23

Figure 12. DDRAM Address Map in Write Mode..............................................................................................................23

Figure 13. Display Data Read-back in 2-wire...................................................................................................................24

Figure 14. Bit-Assignment in Display Data Read-back in 2-wire .......................................................................................24

Figure 15. DDRAM Address Map in Read Mode..............................................................................................................24

Figure 16. Command Registers Read-back Method in 2-wire...........................................................................................25

Figure 17. Command / Data Transfer in 3-SPI Command / Data Transfer in 3-SPI............................................................26

Figure 18. Escape from Data Transfer Condition in 3-SPI ................................................................................................26

Figure 19. Case of Less Than 8-bit Data Transfer in 3-SPI...............................................................................................26

Figure 20. Display Data Transfer and Bit Assignment in 3-SPI .........................................................................................27

Figure 21. Case of Less Than 4-bit Write Data Transfer in 3-SPI......................................................................................27

Figure 22. Display Data Read-back in 3-SPI....................................................................................................................28

Figure 23. Bit Assignment in Display Data Read-back in 3-SPI ........................................................................................28

Figure 24. Command Registers Read-back in 3-SPI........................................................................................................28

Figure 25. Internal Clock Mode.......................................................................................................................................29

Figure 26. External Clock Mode......................................................................................................................................29

Figure 27. Synchronization of Multi-chip Cascaded Connection .......................................................................................31

Figure 28. Example of Cascaded Connection..................................................................................................................32

Figure 29. Example Different Duty Drive Panel Configuration...........................................................................................32

Figure 30. Bank Blink Mode Function (Blink Frequency as 32 Frame Case) .....................................................................33

Figure 31. DDRAM Address Map of Blink Area (Bank Blink Mode) ...................................................................................33

Figure 32. Detection Block and Data Path.......................................................................................................................34

Figure 33. Glass Breaking Detection...............................................................................................................................35

Figure 34. Sequence of Glass Breaking Detection...........................................................................................................36

Figure 35. Sequence of Checksum Detection..................................................................................................................37

Figure 36. Example of Checksum Calculation .................................................................................................................37

Figure 37. Sequence of Logic Error Detection .................................................................................................................38

Figure 38. Sequence of SEG / COM Toggle Detection.....................................................................................................39

Figure 39. DUMMY PADs for the Contact Resistance Measurement ................................................................................39

Figure 40. COM Scan Direction Image............................................................................................................................48

Figure 41. Example COM Line Pattern............................................................................................................................56

Figure 42. Example SEG Line Pattern.............................................................................................................................56

Figure 43. Example Display Pattern................................................................................................................................56

Figure 44. Recommended Power On / Off Sequence.......................................................................................................60

Figure 45. Power On / Off Waveform...............................................................................................................................60

Figure 46. Dummy Clock / STOP / START Condition .......................................................................................................60

Figure 47. CSB Timing ...................................................................................................................................................60

Figure 48. External Clock Stop Timing ............................................................................................................................61

Figure 49. DISPOFF Sequence in Multi-chip Structure ....................................................................................................61

Figure 50. Example of BUS Connection ..........................................................................................................................62

Figure 51. SDA Output Cell Structure..............................................................................................................................62

Figure 52. Recovery Sequence from SDA Stuck..............................................................................................................62

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Table 1. Dimension (Completion Size).............................................................................................................................12

Table 2. Bump Specs and Dimensions............................................................................................................................12

Table 3. Command Registers Map for Read-back............................................................................................................25

Table 4. Detection Functions...........................................................................................................................................34

Table 5. Frame Frequency (Internal Clock Mode) ............................................................................................................42

Table 6. Frame Frequency (External Clock Mode) ...........................................................................................................42

Table 7. V0 Voltage Setting.............................................................................................................................................46

Table 8. DDRAM Data Example......................................................................................................................................56

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Typical Application Circuit

2-wire Serial Interface

VLCD

3-wire Serial Interface

VLCD

BU91R64CH-M

GLSCHKI

BU91R64CH-M

VDD

VLCD

GLSCHKI

VDD

COMA0

:

COMA3

COMA0

:

COMA3

:

VDD

SEG0

:

SEG39

SEG0

:

SEG39

MCU

COMB0

:

COMB3

CSB

SCK

SDO

SDI

CSB

SCK

SDI

COMB0

:

COMB3

Segment LCD

Display Area

80 x 4 dots

Segment LCD

Display Area

80 x 4 dots

SCL

SDA

SCL

SDAI

SDAO

SDO

SEG40

:

SEG79

SEG40

:

SEG79

CLOCK

INHB

OSCIO

INHB

ERR

INHB

ERROUT COMC0

COMC0

:

ERR

ERROUT

:

COMC3

VSS

GLSCHKO

Insert capacitance (C ≥ 0.1μF) between VDD / VLCD and VSS

Block Diagram

...

VLCD

LCD Voltage

Generator

Detect comparator

COM Driver

Detect comparator

SEG Driver

V0

LCD

Bias

COM CTRL

SEG CTRL

Selector

Toggle Error Detector

DDRAM(Latch)

BIAS

DUTY0

Timing Controller

DUTY1

INHB

BLINK

CTRL

DDRAMCTL

SYNCB

OSCIO

SYNC

CTRL

EXTCLK

DFF

Interface

Error

OSC

Serial Interface

MS1

MS2

detector

Register

Block

GLSCHKI

GLSCHKO

VDD

GLSCHK

detector

Error CTRL

If_top

POR

TR

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Terminal Description

Terminal Name

Handling

when unused

I/O

Function

VDD

VLCD

VSS

I

Power supply for logic

-

Power supply for LCD driving circuit

Ground

Single- / Multi-chip setting

2-wire Interface

Slave Address[7:1]

3-wire Interface

Function

Master

MS1

MS2

I

VDD / VSS

MS2

MS1

Function

Master

Slave1

Slave2

Slave3

VSS

VDD

VSS

VDD

VSS

VDD

0111110 / 0111000

0111111 / 0111001

0111110 / 0111000

0111111 / 0111001

Slave1

Slave2

Slave3

Clock mode setting

VDD: External Clock Mode, VSS: Internal Clock Mode

Clock input / output setting

External Clock Mode: input of external clock

Internal Clock Mode: output of internal clock

Synchronous signal input / output for multi-chip mode

Master: Synchronous signal output

Slave: master SYNCB signal input

EXTCLK

OSCIO

I

VDD / VSS

OPEN

I/O

SYNCB

IFSEL

I/O

I

OPEN

MCU Interface select

VDD: 3-wire Serial Interface

VDD / VSS

VSS: 2-wire Serial Interface

SDAI

SDAO

SCL

I

O

I

Serial data input for 2-wire Serial Interface

Serial data output for 2-wire Serial Interface

VSS

OPEN

VSS

Serial clock for 2-wire Serial Interface

Chip select for 3-wire Serial Interface

Serial clock for 3-wire Serial Interface

Serial data input for 3-wire Serial Interface

Serial data output for 3-wire Serial Interface

CSB

SCK

SDI

I

VSS

I

VSS

SDO

O

OPEN

Inhibit display status in spite of Display On by command setting

VDD: Keep display status by command setting

VSS: Inhibit display status. All SEG and COM terminals output VSS level.

INHB

I

VDD

Duty Drive select

DUTY0

VDD / VSS

DUTY1

DUTY0

VSS

Duty Drive

1/4 Duty Drive

VSS

VDD

VSS

1/3 Duty Drive

DUTY1

I

VDD / VSS

VDD

1/2 Duty Drive

VDD

Static Drive (also set to 1/1 Bias)

LCD Bias select

VDD: 1/2 Bias, VSS: 1/3 Bias (Static Drive: don’t care)

Output for glass breaking detection

Connect to GLSCHKI for glass breaking detection.

Input for glass breaking detection

Connect to GLSCHKO for glass breaking detection.

Output data of error detection

VDD: Abnormal status, VSS: Normal status

BIAS

I

VDD / VSS

OPEN

GLSCHKO

GLSCHKI

ERROUT

O

I

VSS

O

OPEN

DUMMY0 to

DUMMY3

DUMMY

-

I

Can be used for the contact resistance measurement.

OPEN

VSS

Open

POR enable setting ^{(Note 1)}

TR

VDD: POR disable, VSS: POR enable

Test input (ROHM use only)

Must be connected to VSS.

T0,T1,T2

I

VSS

SEG0 to SEG79

O

Segment output for LCD driving

Common output for LCD driving

OPEN

COMA0 to COMA3

COMB0 to COMB3

COMC0 to COMC3

(Note 1) This function is guaranteed by design, not tested in production process. Software Reset is necessary to initialize IC in case of TR = VDD.

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Recommended ITO Layout

Function

POR

Setting

USE

TR = VSS

YES

Error Detection

(Glass Breaking Detection,

Contact Resistance Check)

NO

1/4 Duty Drive

(DUTY0, DUTY1) = (VSS, VSS)

Multi-chip Mode

Duty Drive

1/3 Bias

BIAS = VSS

2-wire Serial Interface

IFSEL = VSS

Bias Setting

I/F

Internal Clock Mode

EXTCLK = VSS

Master

(MS1, MS2) = (VSS, VSS)

NO

Clock Mode

Master/Slave

Inhibit Function

INHB = VDD

LCD module terminals

Test pads on the glass (If necessary)

ITO layout image

From GLSCHKO→

DUMMY

SEG1

DUMMY3

1

158

150

SEG2

SEG0

SEG3

COMA3

SEG4

COMA2

SEG5

COMA1

SEG6

COMA0

SEG7

GLSCHKI

SEG8

SEG9

VSS

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

COMB0

COMB1

COMB2

COMB3

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

SEG62

SEG63

SEG64

SEG65

SEG66

SEG67

SEG68

SEG69

SEG70

SEG71

SEG72

SEG73

SEG74

SEG75

SEG76

SEG77

DUMMY0

10

SDAO

SDAI

SDA

SCL

SDAI

140

SCL

CSB

20

30

SCK

SDI

SDO

130

120

ERROUT

OSCIO

SYNCB

ERROUT

INHB

EXTCLK

T0

VDD

T0

T1

T2

40

50

T2

TR

DUTY0

DUTY1

BIAS

MS1

MS2

IFSEL

110

100

VSS

VDD

VSS

60

VSS

VLCD

90

80

DUMMY1

DUMMY

GLSCHKO

70

76

COMC3

COMC2

COMC1

COMC0

SEG79

SEG78

DUMMY

VLCD

DUMMY2

To GLSCHKI→

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Recommended ITO Layout – continued

Function

Setting

Not USE

TR = VDD

POR

Error Detection

Multi-chip Mode

NO

YES

Static Drive

(DUTY0, DUTY1) = (VDD, VDD)

Static Drive

BIAS = VSS

3-wire Serial Interface

IFSEL = VDD

Duty Drive

Bias Setting

I/F

Internal Clock Mode

EXTCLK = VSS

Slave1

(MS1, MS2) = (VDD, VSS)

YES

Clock Mode

Master/Slave

Inhibit Function

INHB = MCU control

LCD module terminals

ITO layout image

DUMMY3

DUMMY

SEG1

1

SEG2

SEG0

158

150

SEG3

COMA3

COMA2

COMA1

COMA0

SEG4

SEG5

SEG6

SEG7

GLSCHKI

SEG8

SEG9

VSS

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

COMB0

COMB1

COMB2

COMB3

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

SEG62

SEG63

SEG64

SEG65

SEG66

SEG67

SEG68

SEG69

SEG70

SEG71

SEG72

SEG73

SEG74

SEG75

SEG76

SEG77

DUMMY0

10

SDAO

SDAI

CSB

SDAI

SCL

CSB

140

CSB

SCK

20

30

SCK

SDI

SDO

ERROUT

OSCIO

SYNCB

130

120

SDO

OSCIO

SYNCB

INHB

EXTCLK

T0

INHB

T0

T1

T2

40

50

T2

VDD

TR

DUTY0

DUTY1

BIAS

MS1

MS2

IFSEL

110

100

VSS

VDD

VSS

60

VSS

VLCD

90

80

DUMMY1

DUMMY

GLSCHKO

COMC3

COMC2

COMC1

COMC0

SEG79

SEG78

DUMMY

VLCD

70

76

DUMMY2

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Recommended ITO Layout – continued

Terminal Resistance

PAD No.

Terminal Name

Maximum Resistance

12, 13

14, 15

16, 17

18, 19

20, 21

22, 23

24, 25

26, 27

28, 29

30, 31

32, 33

56 to 58

59 to 62

63 to 65

SDAO

SDAI

SCL

1,500 Ω

400 Ω

CSB

SCK

SDI

SDO

ERROUT

OSCIO

SYNCB

INHB

VDD

VSS

400 Ω

VLCD

400 Ω

Refer to Glass Breaking Detection for GLSCHKI and GLSCHKO terminal resistance

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PAD Arrangement

Alignment Mark2

PAD No.160

Alignment Mark 1

81 μm

PAD No.1

81 μm

Mark Center Coordinates

(X,Y) = (226.00, -2135.00)

Y

X

(0, 0)

Alignment Mark 2

27 μm

PAD No.76

PAD No.77

Alignment Mark1

(Bump side up)

Mark Center Coordinates

(X,Y) = (226.00, 2135.00)

The origin of X/Y coordinates is the center

of the chip with bump side up.

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Dimension

Table 1. Dimension (Completion Size)

Topic

Mark

Specification Limit

785 ± 40 μm

Chip Size X

Chip Size Y

Chip Size : X Direction

Chip Size : Y Direction

Chip Thickness

4,435 ± 40 μm

300 ± 20 μm

Chip Thickness

A (PAD1 to PAD160)

B (PAD1 to PAD160)

C (PAD1 to PAD160)

Bump Size : X Direction

Bump Size : Y Direction

Average of Bump Height

75.0 ± 3.0 μm

36.0 ± 3.0 μm

15.0 ± 3.0 μm

PAD

Table 2. Bump Specs and Dimensions

Topic

Specification Limit

Straight Bump

Bump Structure

Bump Co-planarity on Chip

3.0 μm or less

Bump Hardness (Microvicker’s Meter)

50 HV ± 20 HV

Bump Strength

7.35 mg/μm²or more

Passivation Opening

Y

Y’

Aluminum

Au Bump

A

Y-Y’ Cross Section

B

Bump Height

Au Bump

Aluminum

Passivation

UBM (TiW/Au)

C

Figure 1. PAD / Bump Information

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PAD Coordinates

Unit: μm

PAD

No

1

2

3

4

5

6

7

Terminal

Name

DUMMY

SEG1

SEG0

COMA3

COMA2

COMA1

COMA0

GLSCHKI

VSS

DUMMY0

SDAO

SDAI

SCL

CSB

SCK

SDI

SDO

Bump Center

Bump Size

PAD

No

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

Terminal

Name

Bump Center

Bump Size

X

Y

X

Y

X

Y

X

Y

-320.50

2116.50

2065.50

2014.50

1963.50

1912.50

1861.50

1810.50

1759.50

1659.50

1608.50

1557.50

1298.80

1247.80

1196.80

1145.80

1094.80

1043.80

992.80

941.80

890.80

839.80

788.80

737.80

685.05

630.05

575.05

520.05

465.05

410.05

355.05

300.05

228.85

177.85

126.85

75.85

75

36

VSS

VLCD

-320.50

320.50

-1290.55

-1341.55

-1392.55

-1443.55

-1494.55

-1557.50

-1608.50

-1659.50

-1710.50

-1810.50

-1861.50

-1912.50

-1963.50

-2014.50

-2065.50

-2116.50

-2128.60

-2077.60

-2014.50

-1963.50

-1912.50

-1861.50

-1810.50

-1759.50

-1708.50

-1657.50

-1606.50

-1555.50

-1504.50

-1453.50

-1402.50

-1351.50

-1300.50

-1249.50

-1198.50

-1147.50

-1096.50

-1045.50

-994.50

-943.50

-892.50

-841.50

-790.50

-739.50

-688.50

-637.50

-586.50

-535.50

-484.50

-433.50

-382.50

-331.50

-280.50

-229.50

-178.50

-127.50

-76.50

75

36

VLCD

DUMMY1

DUMMY

GLSCHKO

COMC3

COMC2

COMC1

COMC0

SEG79

SEG78

DUMMY

DUMMY2

SEG77

SEG76

SEG75

SEG74

SEG73

SEG72

SEG71

SEG70

SEG69

SEG68

SEG67

SEG66

SEG65

SEG64

SEG63

SEG62

SEG61

SEG60

SEG59

SEG58

SEG57

SEG56

SEG55

SEG54

SEG53

SEG52

SEG51

SEG50

SEG49

SEG48

SEG47

SEG46

SEG45

SEG44

SEG43

SEG42

SEG41

SEG40

COMB3

COMB2

COMB1

COMB0

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

SDO

ERROUT

OSCIO

SYNCB

INHB

92

93

94

95

96

97

98

99

INHB

EXTCLK

T0

T1

T2

TR

24.85

-26.15

-77.15

-128.15

-179.15

-230.15

-281.15

-332.15

-383.15

-434.15

-485.15

-536.15

-587.15

-638.15

-689.15

-740.15

-791.15

-842.15

-893.15

-944.15

-1035.55

-1086.55

-1137.55

-1188.55

-1239.55

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

TR

DUTY0

DUTY1

BIAS

MS1

MS2

IFSEL

VDD

-25.50

25.50

76.50

VSS

Refer to PAD Arrangement for the definition of X/Y coordinates.

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PAD Coordinates – continued

Unit μm

Bump Size

Bump Center

PAD

No

Terminal

Name

X

Y

X

Y

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

SEG39

SEG38

SEG37

SEG36

SEG35

SEG34

SEG33

SEG32

SEG31

SEG30

SEG29

SEG28

SEG27

SEG26

SEG25

SEG24

SEG23

SEG22

SEG21

SEG20

SEG19

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

320.50

127.50

178.50

229.50

280.50

331.50

382.50

433.50

484.50

535.50

586.50

637.50

688.50

739.50

790.50

841.50

892.50

943.50

75

36

994.50

1045.50

1096.50

1147.50

1198.50

1249.50

1300.50

1351.50

1402.50

1453.50

1504.50

1555.50

1606.50

1657.50

1708.50

1759.50

1810.50

1861.50

1912.50

1963.50

2014.50

2077.60

2128.60

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

DUMMY3

Refer to PAD Arrangement for the definition of X/Y coordinates.

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Absolute Maximum Ratings (VSS = 0V)

Ratings

Parameter

Symbol

Unit

Remarks

Power Supply

Min

-0.5

-5

Typ

-

Max

+7.0

+5

Maximum Voltage1

Supply Current1

VDD

I_VDD

V

mA

V

For VDD

-

Maximum Voltage2

Supply Current2

LCD Drive Voltage

VLCD

I_VLCD

V_IN

-0.5

-5

+7.0

+5

For VLCD

mA

V

Input Voltage Range

Output Voltage Range

-0.5

+7.0

-

V_OUT

V_ESD

I_LU

-0.5

-

+7.0

-

V

Human Body Model (HBM)

±2,000

-

(Note 1), (Note 2)

Latch-up Current^{(Note 1), (Note 3)}

Maximum Junction Temperature

Storage Temperature Range

-

±100

-

mA

°C

Tjmax

-55

-

+125

Tstg

-55

-

+125

(Note 1) Not 100 % tested. There is data when LSI was put on a temporary package. Use as a reference data.

(Note 2) Testing standards: JESD22-A114E

(Note 3) Testing standards: JESD78

Caution : Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is

operated over the absolute maximum ratings.

Recommended Operating Conditions

Ratings

Parameter

Symbol

Unit

Remarks

Min

-40

Typ

-

Max

Operational Temperature

Power Supply Voltage 1

Power Supply Voltage 2

Topr

VDD

+105

°C

V

-

2.7

-

6.0

Power Supply

VLCD

V

LCD Drive Voltage

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Electrical Characteristics

DC Characteristics

(Unless otherwise specified, Ta = -40 °C to +105 °C, VDD / VLCD = 2.7 V to 6.0 V, VSS = 0 V)

Limits

Parameter

Symbol

Unit

Condition

Min

Typ

Max

“H” Level Input Voltage1

“L” Level Input Voltage1

“H” Level Input Voltage2

“L” Level Input Voltage2

“H” Level Input Current

“L” Level Input Current

“H” Level Output Voltage1

“L” Level Output Voltage1

“L” Level Output Voltage2

V_IH1

V_IL1

0.7VDD

-

VDD

V

SCL, SDAI

VSS

-

0.3VDD

V_IH2

V_IL2

0.8VDD

VDD

V

CSB, SCK, SDI, INHB, OSCIO^(Note)

0

-

0.2VDD

V

SCL, SDAI, CSB, SCK, SDI, INHB,

OSCIO, TR, MS1, MS2, EXTCLK,

IFSEL, DUTY0, DUTY1, BIAS,

GLSCHKI

I_IH

-

1

-

µA

V

I_IL

-1

-

V_OH1

V_OL1

V_OL2

R_ON1

R_ON2

I_VDD1

I_VLCD1

VDD-0.9

-

VDD

0.9

0.4

-

SDO, ERROUT (I_LOAD= -1 mA)

SDO, ERROUT (I_LOAD= +1 mA)

SDAO (I_LOAD= +3 mA)

VSS

-

V

VSS

-

V

SEG

COM

-

3

-

kΩ

µA

LCD Driver

On Resistance

I_LOAD= ±10 µA

-

5.0

Display Off (DISPOFF),

Oscillation stop

Standby Current

Operating Current

-

VDD = 5.0 V, VLCD = 5.0 V,

Ta = +25 °C,

1/4 Duty Drive, 1/3 Bias

Frame Inversion

FR = 155.3 Hz setting

(External Clock = 3.42 kHz)

All outputs are open

I_VDD2

-

0.5

6.5

20.0

30.0

µA

I_VLCD2

(Note) For External Clock Mode and slave mode.

[Reference Data]

10.0

9.0

8.0

Ta = +25 ˚C,

1/4 Duty Drive, 1/3 Bias

Frame Inversion

FR = 155.3 Hz setting

(External Clock = 3.42 kHz)

All outputs are open

I_VLCD2

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0.0

I_VDD2

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Power Supply Voltage 1 / Power Supply Voltage 2 [V]

Figure 2. Operating Current vs Power Supply Voltage

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Electrical Characteristics – continued

Oscillation Characteristics

(Unless otherwise specified, Ta = -40 °C to +105 °C, VDD / VLCD = 2.7 V to 6.0 V, VSS = 0 V)

Limits

Parameter

Symbol

Unit

Condition

Min

Typ

Max

MODESET3 P0 = “0”, FRSET(P2 to

P0) = “110” (155.3 Hz setting)

VDD = 2.7 V to 6.0 V,

108.7

155.3

201.9

Frame Frequency 1

f_CLK1

Hz

Ta = -40 °C to +105 °C

MODESET3 P0 = “0”, FRSET(P2 to

139.8

155.3

170.8

Frame Frequency 2

f_CLK2

Hz P0) = “110” (155.3 Hz setting)

VDD = 5.0 V, Ta = -40 °C to +105 °C

µs

-

0.3

External Clock Rise Time

External Clock Fall Time

External Clock Frequency

External Clock Duty

tr_CLK

tf_CLK

f_CLK3

t_DTY

800

30

33

-

12,000

70

Hz

%

External Clock Mode

50

-

Frame Frequency Range

in External Clock Mode

500

f_FRAME

Hz

Keep Frame Frequency range from 33 Hz to 500 Hz in case of External Clock Mode, also keep external clock frequency

range from 800 Hz to 12,000 Hz.

The calculation formula is shown in 4. Frame Rate Set (FRSET).

[Reference Data]

210

200

190

VDD = 6.0 V

180

VDD = 5.0 V

MODESET3 P0 = “0”,

FRSET(P2 to P0) = “110”

(155.3 Hz setting)

170

160

150

140

130

120

110

100

90

VDD = 3.3 V

VDD = 2.7 V

80

-40 -20

0

20 40 60 80 100

Temperature [˚C]

Figure 3. Frame Frequency vs Temperature

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Electrical Characteristics – continued

2-wire Serial Interface Characteristics

(Unless otherwise specified, Ta = -40 °C to +105 °C, VDD = 2.7 V to 6.0 V, VSS = 0 V)

Limits

Typ

Parameter

Input Rise Time

Symbol

Unit

Condition

Min

-

Max

0.3

µs

-

tr

tf

-

0.3

Input Fall Time

2.5

-

SCL Cycle Time

t_CYC

0.6

1.3

0.1

1.3

0.6

“H” Level SCL Pulse Width

“L” Level SCL Pulse Width

SDA Setup Time

t_SHW

t_SLW

t_SDS

SDA Hold Time

t_SDH

t_BUF

Bus Free Time

START Condition Hold Time

START Condition Setup Time

STOP Condition Setup Time

t_HD;STA

t_SU;STA

t_SU;STO

STOP START

SDAI

SCL

t_BUF

t_SLW

tf

t_CYC

t_HD;STA

tr

t_SDH

t_SHW

t_SDS

SDAI

t_SU;STA

t_SU;STO

Figure 4. Interface Timing of 2-wire Serial Interface

Since SDAO is an open-drain output, Read access time depends on ITO resistance R_ITO, Pull-up resistance R_PUand load

capacitance C_L.

R_ITO

:

ITO resistance on the LCD glass. (Any component is not necessary to be attached.)

Pull-up resistance on PCB. 1 kΩ ≤ R_PU≤ 10 kΩ is recommended.

R_PU

:

C_L:

A parasitic capacitance to VSS in an application circuit. (Any component is not necessary to be attached.)

R_PUshould be determined with consideration of V_ILin MCU side.

Power Supply for I/O Level

R_PU

BU91R64CH-M

SDAO

MCU

C_L

R_ITO

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Electrical Characteristics – continued

3-wire Serial Interface Characteristics

(Unless otherwise specified, Ta = -40 °C to +105 °C, VDD = 2.7 V to 6.0 V, VSS = 0 V)

Limits

Typ

Parameter

Symbol

Unit

Condition

Min

-

Max

ns

µs

ns

-

80

Input Rise Time

tr

-

80

Input Fall Time

tf

400

120

200

120

1.6

120

-

SCK Cycle Time

t_SCYC

t_SHWW

t_SHWR

t_SLWW

t_SLWR

t_SDS

t_SDH

t_CSS

t_CSH

t_CHW

t_DC

-

Write Access

Read Access

Write Access

Read Access

“H” Level SCK Pulse Width (Write)

“H” Level SCK Pulse Width (Read)

“L” Level SCK Pulse Width (Write)

“L” Level SCK Pulse Width (Read)

SDI Setup Time

-

SDI Hold Time

CSB Setup Time

-

CSB Hold Time

-

“H” CSB Pulse Width

SDO Output Delay Time

SDO Rise Time

µs R_ITO= 1.0 kΩ, C_L= 10 pF

1.5

µs

-

t_DR

R_ITO= 1.0 kΩ, C_L= 10 pF

CSB

t_CHW

tr

t_SCYC

t_CSH

t_CSS

t_SLWW

SCK

t_SHWW

t_SDH

t_SDS

tf

SDI

CSB

t_SLWR

SCK

SDO

t_SHWR

t_DC

t_DR

Figure 5. Interface Timing of 3-wire Serial Interface

“t_DC” and “t_DR” depend on ITO resistance R_ITOand load capacitance C_L.

R_ITO

:

ITO resistance on the LCD glass. (Any component is not necessary to be attached.)

C_L:

A parasitic capacitance to VSS in an application circuit. (Any component is not necessary to be attached.)

BU91R64CH-M

SDO

MCU

C_L

R_ITO

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I/O Equivalence Circuit

VLCD

VDD

VSS

TR, T0, T1, T2

DUMMY0

BIAS, MS1, MS2

EXTCLK

SDAI, SCL

DUMMY1

SDI, SCK, CSB

IFSEL, INHB

DUTY0, DUTY1

DUMMY2

VSS

DUMMY3

VDD

OSCIO

SYNCB

SDAO

VSS

VDD

VLCD

SDO

ERROUT

GLSCHKO

VSS

VLCD

SEG0 to SEG79

COMA0 to COMA3

COMB0 to COMB3

COMC0 to COMC3

GLSCHKI

VSS

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MCU Interface

BU91R64CH-M supports two MCU Interfaces. In IFSEL = VSS, 2-wire Serial Interface (hereinafter referred to as “2-wire”) is

available. And in IFSEL = VDD, 3-wire Serial Interface (hereinafter referred to as “3-SPI”) is available.

START and STOP Condition (2-wire)

In IFSEL = VSS, BU91R64CH-M is controlled by 2-wire signals (SDAI, SCL).

It is necessary to generate “START Condition” and “STOP Condition” when sending command or Display Data.

SDAI

SCL

S

P

START Condition

STOP Condition

Figure 6. 2-wire Command / Data Transfer Format

Acknowledge (ACK) (2-wire)

Data format is comprised of 8-bit data to SDAI. And an acknowledge bit is returned from SDAO terminal after the 8-bit data is

sent. SDAO is also used in Display Data read-back and Command Registers read-back. The serial data input line (SDAI)

and the serial data output line (SDAO) are separated in PAD assignment, but both terminals can be connected together to

facilitate a single line SDA.

After the transfer of 8-bit data (Slave Address, Control Byte, Command, Display Data), release the SDA line at the falling

edge of the eighth clock. The SDA line is then pulled low until the falling edge of the ninth clock SCL. (Output cannot be

pulled high because of open-drain NMOS output structure). If the acknowledge function is not required, keep SDA line at low

level from the eighth falling edge to the ninth falling edge of SCL.

Not acknowledged bit (NACK) will be returned in following cases.

(1) Incorrect Slave Address

(2) Different Sub Address (in receiving Display Data, CNTSET and COMSET commands)

SDAI

HiZ

HiZ or L

SDAO

SDA

(Connected signal of SDAI and SDAO)

SCL

S

1to7

8

9

1to7

8

9

1to7

8

9

P

Slave Address

ACK /

Control Byte

ACK /

Command / Display Data ACK /

START Condition

STOP Condition

Figure 7. Acknowledge Timing

When Slave Address cannot be recognized correctly in the first data transfer, NACK will be generated and next transfer will

be invalid. Even in the invalid status, BU91R64CH-M will return to valid status by receiving “START Condition” again.

Consider MCU Interface Characteristics such as Input rise time and Setup / Hold time when transferring command and data.

Refer to 2-wire Serial Interface Characteristics.

Slave Address

Data

Slave Address

Data

0 1 1 1 1 1

0 1 1 1 0 0

MS1 RW

S

0 1 0 0 0 0 0 0 NA

NA

NA P S

A

A ... P

01

0

Invalid Transfer

Valid Transfer

S: START Condition, P: STOP Condition, A: ACK, NA: NACK

Figure 8. Wrong Slave Address Case

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MCU Interface - continued

Command / Display Data Transfer Method (2-wire)

Issue Slave Address after generating “START Condition”. The first byte after Slave Address must be Control Byte. The

Control Byte consists of 8bits: CO, RS, and 6 undefined bits. The first bit is CO: continuous data bytes / single data byte

selector and the second bit is RS: Command / Display Data selector and the others are undefined bits.

CO

0

Function

Continuous data bytes available after the Control Byte.

Only single data byte available after the Control Byte.

After the data byte, Control Byte can be accepted again.

1

RS

0

Function

Command is received after the Control Byte.

1

Display Data is received after the Control Byte.

Continuous Display Data is available regardless of CO value.

The following procedure shows how to transfer Command and Display Data.

(1) Generate “START Condition”.

(2) Issue Slave Address. ^{(Note 1)}

(3) Transfer Control Byte.

(4) Transfer Command and Display Data.

(5) Generate “STOP Condition”.

(Note 1) Slave Address is specified by MS1 setting. (2-wire mode only)

MS1

0

1

Slave Address [7:1]

0111110 / 0111000

0111111 / 0111001

Slave Address

Control Byte

Command / Display Data

0

1

0

1

0

MS1

CO RS

S

RW

A

*

A

A P

START Condition

Read / Write ACK

STOPCondition

<Write: Two DisplayData bytes>

Slave Address

Control Byte (CO:0, RS:1)

0

1

0

1

0

MS1

S

0

A

0

1

*

A DisplayData

A Command

A DisplayData

A P

START Condition

Write Mode ACK

STOPCondition

<Write: Two command bytes>

Slave Address

Control Byte (CO:1, RS:0)

Control Byte (CO:0, RS:0)

0

1

0

1

0

MS1

S

0

A

1

0

*

A

0

*

A Command

A P

START Condition

Write Mode ACK

STOPCondition

<Write: One command byte and two DisplayData bytes>

Slave Address Control Byte (CO:1, RS:0)

Control Byte (CO:0, RS:1)

0

1

0

1

0

MS1

S

0

A

1

0

*

A

0

1

*

A DisplayData

A P

START Condition

Write Mode ACK

STOPCondition

Figure 9. 2-wire Interface Protocol

BU91R64CH-M cannot accept Control Byte / Command once it enters into continuous data transfer state. “STOP Condition”

and “START Condition” are necessary in order to accept Command again. If “START Condition” or “STOP Condition” is

received during Command / Display Data transfer, the byte in transferring will be cancelled.

Then if Slave Address is received after the “START Condition”, BU91R64CH-M enters into Control Byte transfer state.

Slave Address

Control Byte

Command

Slave Address

Control Byte

DisplayData

0 1 1 1 1 1

0 1 1 1 0 0

0 1 1 1 1 1

0 1 1 1 0 0

MS1 RW

0/1

CO

0

RS

1

MS1 RW

CO RS

S

A

*

* *

A

P S

A

*

A

A ... P

0

0/1

0

1

Canceled

Valid Transfer

S: START Condition, P: STOP Condition, A: ACK, NA: NACK

Figure 10. Case of Exiting Data Transfer State in 2-wire

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BU91R64CH-M

MCU Interface - continued

Display Data Transfer Method (2-wire)

For Display Data write, set R/W bit in Slave Address byte to “0” (Write Mode) and Bit6 in Control Byte to “1”. BU91R64CH-M

has a Display Data RAM (DDRAM) of 80 x 4 = 320-bit. SADSET and ADSET commands specify the address where the first

Display Data Byte is written. The address is automatically incremented in every 4-bit data and the Display Data is written to

DDRAM at the same timing. Smaller Display Data than 4-bit will be cancelled in the transfer.

Burst write into DDRAM is available by transferring data continuously. The address is returned to 00h by the auto-increment

function after writing Display Data to the last address. BU91R64CH-M escapes from the burst mode by STOP Condition.

Ex. in 1/4 Duty Drive, the address is returned to 00h (for SEG0) after writing data into address = 4Fh (for SEG79). In case of

Static Drive Mode, maximum address is 13h (for SEG76 to SEG79).

The relationships between input Display Data, DDRAM address map and SEG output are as follows.

Slave Address

Command

SADSET

Cotrol Byte

0000 0000

Command

ADSET

0111 11 MS1 R/W

S

A

P

0/1

0

0111 00

Write Mode

CO:0, RS:0

Slave Address

Cotrol Byte

DisplayData

0111 11 MS1 R/W

S

A

0100 0000

a

b

c

d

e

f

g

h

A

i

j

k

l m n o p A ... P

0/1

0

0111 00

Write Mode

S: START Condition, P: STOP Condition, A: ACK, NA: NACK

CO:0, RS:1

DisplayData

Figure 11. Display Data Transfer in 2-wire

1/4 Duty

ADSET

D7,D3

D6,D2

D5,D1

D4,D0

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh

40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh

…

a

b

c

d

e

f

g

h

i

j

k

l

m

n

o

COM0

COM1

COM2

COM3

p

1/3 Duty

ADSET

D7,D3

D6,D2

D5,D1

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh

40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh

…

a

b

c

-

e

f

g

-

i

j

k

-

m

n

o

-

COM0

COM1

COM2

-

1/2 Duty

ADSET

D7,D3

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh

40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh

…

a

b

-

e

f

-

i

j

-

m

n

-

COM0

COM1

Area for

bank blink

D6,D2

-

Static drive

ADSET

D7 to D0

00h

01h

02h

03h

…

10h

11h

12h

13h

a

-

b

-

c

-

d

-

e

-

f

g

-

h

-

i

j

k

-

l

m

-

n

-

o

-

p

-

COM0

-

Area for

bank blink

-

Figure 12. DDRAM Address Map in Write Mode

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BU91R64CH-M

MCU Interface - continued

Display Data Read-back Method (2-wire)

For Read Mode, set R/W bit in Slave Address byte to “1”. In advance, Read_data bit in RDCTL must be set to “1” for reading

Display Data. The Display Data values can be read during Read Mode. The sequence of the Display Data read-back is

shown below.

Slave Address

Command

CMDXTN

Contol Byte

0000 0000

Command

SADSET

Command

ADSET

Command

RDCTL

0111 11

0111 00

MS1 R/W

0/1

S

A

A P

0

Read_en = “1”

Write Mode

CO:0, RS:0

Read_data = “1”

Slave Address

DisplayData

0111 11 MS1 R/W

0111 00

a b c d e f g h

S

A

...

Display Data NA

From MCU

P

0/1

1

S: START Condition, P: STOP Condition, A: ACK, NA: NACK

Read Mode

From MCU

Figure 13. Display Data Read-back in 2-wire

During Read Mode, the Display Data can be read from the DDRAM through the SDAO line. The data will output

synchronized with falling edge of SCL input.

SADSET and ADSET must be set first during Write Mode in advance. If DDRAM address is not specified before Display Data

read, the current DDRAM address is used as the first read address. Address will be incremented automatically by +2

addresses after 8-bit data output. The Address will be set to 00h automatically after maximum address.

MCU must reply ACK to BU91R64CH-M after each 8-bit data output to keep Read Mode. If MCU replies no ACK response

(NACK), BU91R64CH-M will escape Read Mode and SDAO output status will be released.

S

P

A

HiZ

A

HiZ

NA

SDAI

SDAO

SCL

Slave Address (Read)

HiZ

Display Data

a

b

c

d

e

f

g

h

HiZ

i

j

k

l

m

n

o

p

HiZ

S: START Condition, P: STOP Condition, A: ACK, NA: NACK

Figure 14. Bit-Assignment in Display Data Read-back in 2-wire

1/4 Duty

ADSET

D7,D3

D6,D2

D5,D1

D4,D0

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh

40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh

…

a

b

c

d

e

f

g

h

i

j

k

l

m

n

o

COM0

COM1

COM2

COM3

p

1/3 Duty

ADSET

D7,D3

D6,D2

D5,D1

D4,D0

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh

40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh

…

a

b

c

*

e

f

g

*

i

j

k

*

m

n

o

*

COM0

COM1

COM2

*

1/2 Duty

ADSET

D7,D3

D6,D2

D5,D1

D4,D0

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh

40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh

…

a

b

c

d

e

f

g

h

i

j

k

l

m

n

o

COM0

COM1

Area for

p

bank blink

Static drive

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh

40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh

…

ADSET

D7,D3

D6,D2

D5,D1

D4,D0

a

*

e

*

i

m

*

COM0

*

k

*

c

*

g

*

o

*

Area for

bank blink

Figure 15. DDRAM Address Map in Read Mode

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BU91R64CH-M

MCU Interface - continued

Command Registers Read-back Method (2-wire)

For Read Mode, set R/W bit in Slave Address byte to “1”. In advance, Read_data bit in RDCTL must be set to “0” for reading

Command Registers. The Command Registers can be read during Read Mode. The sequence of the Command Registers

read-back is shown below and is similar to the Display Data read sequence.

Control Byte

Command

Slave Address

Command

0111 11

0111 00

MS1 R/W

0000 0000

CMDXTN

S

A

S

A

SADSET

A

RDCTL

A P

0/1

0

Read_en = “1”

Read_data = “0”

CO:0, RS:0

Write Mode

Slave Address

0111 11

0111 00

Read Data

1st Byte

Read Data

2nd Byte

Read Data

A

Read Data

1st Byte

MS1 R/W

0/1

NA

P

A

...

1

S: START Condition,

P: STOP Condition,

A: ACK, NA: NACK

6th Byte

Read Mode

From MCU

From MCU From MCU

From MCU

Figure 16. Command Registers Read-back Method in 2-wire

After the sixth byte data, the first byte data will be outputted again. Command Registers read-back mode can be released at

NACK condition (Same as Read Display Data).

Table 3. Command Registers Map for Read-back

Byte

Bit

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

Read Data

Enable for Glass Breaking Detection

Enable for Interface Checksum Detection

Enable for Logic Error Detection

Enable for SEG / COM Toggle Detection

Status of Glass Breaking Detection

Status of Interface Checksum Detection

Status of Logic Error Detection

Status of SEG / COM Toggle Detection

Display On

Remark

MODESET2 P3

MODESET2 P2

MODESET2 P1

MODESET2 P0

1: Abnormal, 0: Normal

MODESET1 P3

BLKCTL1 P2

MODESET3 P1

MODESET3 P2

MODESET3 P0

FRSET P2

FRSET P1

FRSET P0

BLKCTL1 P1

BLKCTL1 P0

BLKCTL2 P1

COMSET P3

CNTSET P3

CNTSET P2

CNTSET P1

CNTSET P0

CHKSUM P3

CHKSUM P2

CHKSUM P1

CHKSUM P0

-

1st Byte

Blink Mode

2x frequency in frame Inversion

Inversion Mode

2nd Byte

3rd Byte

4th Byte

5th Byte

6th Byte

Higher Frequency Mode

Frame Rate Bit2

Frame Rate Bit1

Frame Rate Bit0

Blink Freq. Bit1

Blink Freq. Bit0

Blink Area Select

EVR Bit4

EVR Bit3

EVR Bit2

EVR Bit1

EVR Bit0

IFCHKSUM Bit3

IFCHKSUM Bit2

IFCHKSUM Bit1

IFCHKSUM Bit0

0

COMSET Bit2

COMSET P2

COMSET P1

COMSET P0

-

COMSET Bit1

COMSET Bit0

0

-

Sub Address Set Bit1

Sub Address Set Bit0

0

SADSET P1

SADSET P0

-

0

-

0

-

0

-

0

-

Address Set Bit6

Address Set Bit5

Address Set Bit4

Address Set Bit3

Address Set Bit2

Address Set Bit1

Address Set Bit0

ADSET P6

ADSET P5

ADSET P4

ADSET P3

ADSET P2

ADSET P1

ADSET P0

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BU91R64CH-M

MCU Interface - continued

Command / Display Data Transfer Method (3-SPI)

In IFSEL = VDD, BU91R64CH-M is controlled by 3-wire signals (CSB, SCK, and SDI). First, Interface counter is initialized

with CSB = high, then CSB = low enables SDI and SCK input.

D7 to D0 follows continuously after CSB =low. Internal data is latched at the rising edge of SCK. Command is converted to

8-bit parallel data at the rising edge of the eighth SCK. Display Data is stored at the fourth and the eighth falling edge of SCK.

The protocol of 3-SPI transfer is as follows.

Command

Command / DisplayData

CSB

SCK

SDI

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5

Figure 17. Command / Data Transfer in 3-SPI Command / Data Transfer in 3-SPI

Command Transfer Method (3-SPI)

After CSB changes from high to low, the first byte is always a command input. To escape Display Data transfer condition or

to send command again, CSB should be set from low to high then set to low.

CSB

SDI

Command SADSET

ADSET

DisplayData DisplayData

Write canceled

Command

1st byte: Command input

1st byte:

Command input

Figure 18. Escape from Data Transfer Condition in 3-SPI

Command transfer is done by 8-bit unit, so if CSB is set from low to high with less than 8-bit data transfer, command will be

cancelled. It will be able to transfer command when CSB = low again.

Command

CSB

SCK

SDI

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

MODESET1 command transfer

Vaild command

Command cancelled (less than 8-bit)

Invaild command

MODESET1 command transfer

Vaild command

Status

Figure 19. Case of Less Than 8-bit Data Transfer in 3-SPI

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BU91R64CH-M

MCU Interface - continued

Display Data Transfer Method (3-SPI)

In 3-SPI, BU91R64CH-M enters to Display Data write state after receiving ADSET command. BU91R64CH-M has a Display

Data RAM (DDRAM) of 80 x 4 = 320-bit. SADSET and ADSET commands specify the address where the first Display Data

Byte is written. The address is automatically incremented in every 4-bit data and the Display Data is written to DDRAM at the

same timing. Smaller Display Data than 4-bit will be cancelled in the transfer.

Burst write into DDRAM is available by transferring data continuously. The address is returned to 00h by the auto-increment

function after writing Display Data to the last address. BU91R64CH-M escapes from the burst mode by setting CSB to high.

Ex. in 1/4 Duty Drive mode, the address is returned to 00h (for SEG0) after writing Display Data into address = 4Fh (for

SEG79). In case of Static Drive Mode, maximum address is 13h (for SEG76 to SEG79).

The DDRAM address map is same as the one in 2-wire Serial Interface (Refer to Figure 12. DDRAM Address Map in Write

Mode).

Command

SADSET

Command

ADSET

P1 P0

P6 P5 P4 P3 P2 P1 P0

...

1

0

a

b

c

d

e

f

g

h

i

j

k

l m n o p

DisplayData

Figure 20. Display Data Transfer and Bit Assignment in 3-SPI

Escape from RAM Write Mode by CSB="H"

CSB

SCK

SDI

D3

ADSET (00h)

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D2

D1

D0

Display Data to

Address 00h

Display Data to

Address 01h

Display Data to

Address 02h

This data is ignored

Figure 21. Case of Less Than 4-bit Write Data Transfer in 3-SPI

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BU91R64CH-M

MCU Interface - continued

Display Data Read-back Method (3-SPI)

Set Read_en = “1” and Read_data = “1” in RDCTL register to enter to Display Data Read Mode. The Display Data values

can be read during this mode. The sequence of the Display Data Read-back is shown below.

CSB

Display Data Display Data

Display Data

SDI

SADSET

ADSET

CMDXTN

RDCTL

...

Read_en = "1"

Read_data = "1" Displayread data from SDO

Figure 22. Display Data Read-back in 3-SPI

During Display Data Read Mode, the Display Data can be read from the DDRAM through the SDO line. The data will output

synchronized with falling edge of SCK input.

SADSET and ADSET must be set first during Write Mode in advance. If DDRAM address is not specified before Display Data

read, the current DDRAM address is used as the first read address. Address will be incremented automatically by +2

addresses after 8-bit data output. The Address will be set to 00h automatically after maximum address. Display Data Read

Mode will be released by setting CSB to high (SDO output also be stopped).

The DDRAM address map is same as the one in 2-wire Serial Interface (Refer to Figure 15. DDRAM Address Map in Read

Mode).

CSB

SCK

SDI

RDCTL (Read_en = "1")

D7 D6 D5 D4 D3 D2 D1 D0

SDO

Figure 23. Bit Assignment in Display Data Read-back in 3-SPI

Command Registers Read-back Method (3-SPI)

Set Read_en = “1” and Read_data = “0” in RDCTL register to enter Command Registers Read Mode. The Command

Registers values can be read during this mode. The sequence of the Command Registers read-back is shown below.

CSB

Read Data

1st Byte

Read Data

2nd Byte

Read Data

6th Byte

Read Data

1st Byte

SADSET

CMDXTN

RDCTL

...

SDI

Read_en = "1"

Read_data = "0"

Register read data fromSDO

Figure 24. Command Registers Read-back in 3-SPI

After reading the 6th byte data, the first byte data will be output again. Command Registers Read Mode will be released after

CSB change from low to high. (SDO stops).

The Command Registers Map is same as the one in 2-wire. Refer to Table 3. Command Registers Map for Read-back.

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BU91R64CH-M

OSC (Oscillator)

In master chip (MS1 = VSS and MS2 = VSS), the clock mode can be selected by EXTCLK. The clock signals for logic and

analog circuit can be generated in internal oscillator if EXTCLK = VSS or can be provided from external clock input if

EXTCLK = VDD.

Clock Mode

Internal Clock Mode

External Clock Mode

EXTCLK

VSS

OSCIO

To Output Internal Generated Clock Signal

To Input External Clock

VDD

In cascaded connection, slave chip (MS1 = VDD or MS2 = VDD) is always in External Clock Mode regardless of EXTCLK.

In case of External Clock Mode, a clock signal should be always supplied to BU91R64CH-M. Removing the clock may freeze

the LCD in a DC state which is not suitable for the LCD.

EXTCLK

BU91R64CH-M

Master chip

OSCIO Open

(MS1 = VSS, MS2 = VSS)

Figure 25. Internal Clock Mode

VDD

EXTCLK

OSCIO

VSS

BU91R64CH-M

Master chip

(MS1 = VSS, MS2 = VSS)

< Clock

Figure 26. External Clock Mode

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BU91R64CH-M

SYNC CTRL (Multi-chip Structure)

BU91R64CH-M supports large display application by connecting up to four IC in cascade. BU91R64CH-M can be combined

with BU91R65CH-M and BU91R66CH-M.

The relationship of MS1 / MS2 setting, OSCIO, SYNCB and SADSET are shown below. To synchronize each IC, connect the

synchronizing signal (SYNCB) and the synchronous clock (OSCIO) from the Master to Slave ICs.

In case of 2-wire Serial Interface

OSCIO

Slave

Address

[7:1]

SYNCB

SADSET

(P1,P0)

EXTCLK = VDD ^{(Note 1)}EXTCLK = VSS ^{(Note 2)}

MS2 MS1 Mode

I/O

Connected to

I/O

Connected to

I/O

Connected to

Slave1 to

Slave3

(OSCIO)

Slave1 to

Slave3

(SYNCB)

0111 110 /

0111 000

VSS

VSS Master

IN

MCU

OUT

(0,*)

0111 111 /

0111 001

Master

(OSCIO)

Master

(SYNCB)

VSS

VDD

VDD Slave1

VSS Slave2

IN

MCU

IN

(0,*)

(1,*)

0111 110 /

0111 000

Master

(OSCIO)

Master

(SYNCB)

0111 111 /

0111 001

Master

(OSCIO)

Master

(SYNCB)

VDD VDD Slave3

(*: don’t care)

(Note 1) Frame rate is fixed (24 clock / frame) regardless of FRSET and MODESET3.

(Note 2) Frame rate depends on FRSET and MODESET3. All of Master and Slave1 to Slave3 must be same setting in the registers.

In case of 3-wire Serial Interface

OSCIO

SYNCB

SADSET

(P1,P0)

EXTCLK = VDD ^{(Note 1)}EXTCLK = VSS ^{(Note 2)}

MS2 MS1

Mode

Master

I/O

Connected to

I/O

Connected to

I/O

Connected to

Slave1 to

Slave3

Slave1 to

Slave3

VSS

IN

MCU

OUT

(0, 0)

(OSCIO)

(SYNCB)

Master

(OSCIO)

Master

(SYNCB)

VSS

VDD

VSS

Slave1

Slave2

Slave3

IN

MCU

IN

(0, 1)

(1, 0)

(1, 1)

Master

(OSCIO)

Master

(SYNCB)

Master

(OSCIO)

Master

(SYNCB)

VDD VDD

(Note 1) Frame rate is fixed (24 clock / frame) regardless of FRSET and MODESET3.

(Note 2) Frame rate depends on FRSET and MODESET3. All of Master and Slave1 to Slave3 must be same setting in the registers.

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BU91R64CH-M

SYNC CTRL (Multi-chip Structure) - continued

The relationship between COM and SYNCB timing is as follows.

1Frame

COM

SYNCB

(a-1) 1/4 Duty Drive and Frame Inversion

(a-2) 1/4 Duty Drive and Line Inversion

1Frame

COM

SYNCB

(b-1) 1/3 Duty Drive and Frame Inversion

(b-2) 1/3 Duty Drive and Line Inversion

1Frame

COM

SYNCB

(c-1) 1/2 Duty Drive and Frame Inversion (1/2bias)

(c-2) 1/2 Duty Drive and Line Inversion (1/2bias)

1Frame

COM

SYNCB

(d-1) Static Drive and Frame Inversion

(d-2) Static Drive and Line Inversion

OSCIO

SYNCB

COM

Typ 10µs

In Blink Mode,

SYNCB "L" pulse width will be twice longer

to synchronize normal and blink display .

(e) Driver timing waveform

Figure 27. Synchronization of Multi-chip Cascaded Connection

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BU91R64CH-M

SYNC CTRL (Multi-chip Structure) - continued

The example of cascaded connection

<2-wire serial, Internal Clock Mode, Detection enable>

Display Area

…

COM

SEG

COM

SEG

COM

SEG

BU91R64CH-M

Master(MS2 = VSS, MS1 = VSS)

EXTCLK = VSS

Slave1(MS2 = VSS, MS1= VDD)

EXTCLK = VSS

Slave2(MS2 = VDD, MS1 = VSS)

EXTCLK = VSS

VDD

MCU

<3-wire serial, External Clock Mode, Detection disable>

Display Area

…

COM

SEG

COM

SEG

COM

SEG

BU91R64CH-M

Master(MS2 = VSS, MS1 = VSS)

EXTCLK = VDD

Slave1(MS2 = VSS, MS1 = VDD)

EXTCLK = VDD

Slave2(MS2 = VDD, MS1 = VSS)

EXTCLK = VDD

MCU

Figure 28. Example of Cascaded Connection

1/4 Duty LCD Panel

Static LCD Panel

1/4 Duty LCD Panel

Static LCD Panel

80SEG x 4COM

(320dots), 5 V

160SEG x 1COM

(160dots), 5 V

80SEG x 4COM

(320dots), 5 V

160SEG x 1COM

(160dots), 5 V

BU91R64CH-M

BU91R65CH-M

Master, 1/4 Duty Drive

Master, Static Drive

Slave1, Static Drive

(MS2, MS1) = (VSS,VSS)

(MS2, MS1) = (VSS,VDD)

(DUTY1,DUTY0) = (VSS, VSS)

(DUTY1,DUTY0) = (VDD, VDD)

MCU

- Same LCD frame frequency

- One FPC

- Different LCD frame frequency

- Few Pin count

Figure 29. Example Different Duty Drive Panel Configuration

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BU91R64CH-M

LCD Driver Voltage Generator / LCD Bias Selector

BU91R64CH-M generates LCD driving voltage with on-chip Buffer AMP. 1/3 or 1/2 Bias Drive can be selected by external

terminal (BIAS) setting. Line / frame inversion can be set by MODESET3 command. Refer to LCD Driving Waveform.

POR and Reset Initialize Condition

BU91R64CH-M has POR (Power On Reset) circuit. Keep Power On / Off specification and sequence described in Cautions

in Power On / Off. Initial condition after executing Software Reset and POR is as follows.

- Display is off.

- DDRAM address is initialized (DDRAM Data is not initialized).

- Each Command Registers are reset initialize condition. Refer to Detailed Command Description.

Blink Control (Blink Timing Generator)

Blink function is asserted by Blink Control1 command (BLKCTL1). In All Segments Blink Mode, all dots blink is available. In

Bank Blink Mode, individual dot blink is available only in 1/2 Duty and Static Drive mode. Refer to 5. Blink Control1

(BLKCTL1). The Displayed RAM mapping is switched at blink frequency as following images.

(1) All Segments Blink Mode

DisplayData

1

0

1

SEG A SEG B SEG C SEG D

SEG output

ON OFF OFF ON

OFF

ON

OFF

ON

SEG A SEG B SEG C SEG D

x16 Frame

SEG A SEG B SEG C SEG D

x16 Frame

SEG A SEG B SEG C SEG D

Blink frequency: 32 Frame

(2) Bank Blink Mode (Available in 1/2 Duty and Static Drive mode)

DisplayData

1

0

1

SEG A SEG B SEG C SEG D

Blink Data

1

0

SEG A SEG B SEG C SEG D

SEG output

ON OFF OFF ON

ON

OFF

ON

OFF

ON

SEG A SEG B SEG C SEG D

x16 Frame

SEG A SEG B SEG C SEG D

x16 Frame

SEG A SEG B SEG C SEG D

Blink frequency: 32 Frame

Figure 30. Bank Blink Mode Function (Blink Frequency as 32 Frame Case)

Blink data can be written in Blink Control 2 command (BLKCTL2) P1 = “1”. The command sequence and the relationship

between data input and DDRAM Address Map are as follows.

Slave Address

Command

BLKCTL2

1111101*

Cotrol Byte

0000 0000

Command

SADSET

Command

ADSET

0111 11 MS1 R/W

S

A

S

A

P

0/1

0

0111 00

P1:1 Blink area in RAMwrite

Write Mode

CO:0, RS:0

Slave Address

Cotrol Byte

0100 0000

DisplayData

0111 11 MS1 R/W

A

a

b

c

d

e

f

g

h

i

j

k

l m n o p A ... P

0/1

0

0111 00

Write Mode

CO:0, RS:1

DisplayData

S: START Condition, P: STOP Condition, A: ACK, NA: NACK

1/2 Duty

ADSET

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh

40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh

…

-

a

b

-

e

f

-

i

-

m

n

-

…

-

COM0

COM1

Blink data for COM0

Blink data for COM1

D7,D3

D6,D2

j

Static drive

ADSET

00h

01h

02h

03h

…

10h

11h

12h

13h

-

i

-

l

-

COM0

D7 to D0

a

b

c

d

e

f

g

h

j

k

m

n

o

p

Blink data for COM0

Figure 31. DDRAM Address Map of Blink Area (Bank Blink Mode)

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Error Detection

BU91R64CH-M has the following Error Detection functions. When one of functions in a following table detects abnormal

status, ERROUT terminal output high level. Then the item with abnormal status can be identified by reading Command

Registers.

MCU can detect all events which cause abnormal display by these functions. MCU can take action such as Stopping the

display or displaying information about abnormal state when LCD module encountered problem.

Table 4. Detection Functions

Detection Function

Item

Detected Error

Detection Timing

Availability

LCD Glass Breaking

During DISPON

By DISPON Command

By CHKSUM Command

Always in DISPON

Glass Breaking Detection

Checksum Detection

I/F Communication Error

Logic DFF Malfunction

SEG / COM Output Level Error

COG Bonding Status

Always

During DISPON

(No Power Applied)

Logic Error Detection

SEG / COM Toggle Detection

Contact Resistance Check

Always in DISPON

(In LCD Module Assembly)

Block diagram and data path of Detection block are shown below.

...

VLCD

LCD Voltage

Generator

Detect Comparator

SEG Driver

V0

SEG/COMtTooggggleledDeteetcetciotinon

COM Driver

LCD

Bias

Selector

COM CTRL

SEG CTRL

Toggle Error Detector

DDRAM(Latch)

DDRAMCTL

BIAS

Timing Controller

DUTY0

DUTY1

INHB

BLINK

CTRL

Logic error Detection

Checksum Detection

SYNCB

OSCIO

SYNC

CTRL

EXTCLK

DFF

Error

detector

OSC

Interface

detector

Serial Interface

If_top

MS1

MS2

Glass Breaking Detection

Register

Block

GLSCHKI

GLSCHKO

VDD

GLSCHK

detector

Error CTRL

Contact Resistance Check

POR

TR

Glass Breaking Detection

Checksum Detection

Error

CTRL

ERROOUT

Logic Error Detection

SEG / COMToggle Detection

if_top

SDAO (2-wire)

SDO (3-wire)

Each detection status can

be read by read command

register

LCD Module

ERROUT

MCU

LCD Driver

LCD Display

MCU I/F

SEG / COM Toggle Detection

Glass Breaking Detection

Checksum Detection

Logic Error Detection

Figure 32. Detection Block and Data Path

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Error Detection - continued

Glass Breaking Detection

BU91R64CH-M can detect LCD glass breaking status.

In Single-chip Use Case,

Crack

Wire on the LCD glass

GLSCHKO

ERROUT

(to MCU)

GLSCHKI

ERROUT

(to MCU)

High level outputs during abnormal status

such as glass breaking

Low level outputs during normal status

[ Case of LCD Panel No Breaking ]

[ Case of LCD Panel Breaking ]

In Multi-chip Cascaded Use Case,

Master

Slave1

Slave2

Slave3

Master Master

GLSCHKI GLSCHKO

Slave1 Slave1

GLSCHKI GLSCHKO

Slave2 Slave2

GLSCHKI GLSCHKO

Slave3 Slave3

GLSCHKI GLSCHKO

Master

ERROUT

Slave1

ERROUT

Slave2

ERROUT

Slave3

ERROUT

Figure 33. Glass Breaking Detection

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BU91R64CH-M

Glass Breaking Detection – continued

Glass breaking detection will be judged after 4 frames from MODESET1 command (DISPON). High level will be judged at

the end of the second frame after MODESET1 command (DISPON) and low level will be judged at the end of the fourth

frame after the command. See following sequence.

Command

Frame

DISPON

4th

DISPON

1st

2nd

3rd

1st

2nd

H

3rd

4th

1st

2nd

3rd

4th

GLSCHKO

GLSCHKI

H

L

H

L

L: If glass broken

NG

Detection result

OK

Judged as NG

OK

Judged as OK

(Command Register Read-back: D3 bit in 1st Byte)Judged as OK

ERROUT

Abnormal status

Figure 34. Sequence of Glass Breaking Detection

Thus, the detection period depends on the Frame Frequency setting. It is necessary to consider ITO wiring resistance and

capacitance to keep the following calculation:

2 × 휏 < 2 × 퐹푟푎푚푒 퐷푢푡푦

[s]

(A)

where:

휏 is the CR time constant. 휏 = 퐶 × 푅. 퐶: ITO capacitance, 푅: ITO resistance.

When Frame rate = 200 Hz, Wire length around LCD glass = 500 counts, ITO sheet count = 60 Ω and ITO capacitance =

100 pF

퐼푇푂 푟푒푔푖푠푡푎푛푐푒 = 60[훺] × 500 [푐표푢푛푡] = 30,000

[Ω]

[

]

[

]

2 × 휏 = 2 × 퐶 × 푅 = 2 × 100 푝퐹 × 30 푘훺 = 6

[µs]

ꢀ

2 × 퐹푟푎푚푒 퐷푢푡푦 = 2 × _ꢁꢂꢂ= 10

[ms]

In this case, (A) is satisfied. So glass check function will work correctly.

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Error Detection - continued

Checksum Detection

This function detects the error due to command or Display Data alteration by electric noise during transfer from MCU.

Checksum detection will be judged after every CHKSUM command. See following sequence.

Slave Address+Control Byte

Command (2-wire)

S

Command

CHKSUM

P

S

Command Command CHKSUM

P

Calculate checksumfor input data and

compare internal checksumvalue and CHKSUMcommand value

Detection result

H: incorrect

L: correct

(Command Register Read-back: D2 bit in 1st Byte)

ERROUT

Abnormal status

Slave Address+Control Byte

Command (2-wire)

S

SADSET ADSET Display Data Display Data Display Data

P

S

CHKSUM

P

Calculate checksumfor input data and

compare internal checksumvalue and CHKSUMcommand value

Detection result

H: incorrect

L: correct

(Command Register Read-back: D2 bit in 1st Byte)

ERROUT

Abnormal status

S: START Condition, P: STOP Condition, A: ACK, NA: NACK

: valid data for internal checksum calculation

Figure 35. Sequence of Checksum Detection

Checksum calculation example:

(1) Display Data Write Case

2-wire Serial I/F

Slave

Address

7C

Slave

Address

7C

SADSET

ADSET

DisplayData

CHKSUM

XXXX

S

A

Control Byte

00

A

P

S

A

Control Byte

01

A

P

S

A

A P

SCL / SDAI / SDAO

Address

7C

E

0

2

A

3

D

Write

Master

Write

3-wire Serial I/F

CSB

SADSET

ADSET

DisplayData

CHKSUM

D XXXX

SCK /SDI

E

0

2

A

3

Master

(2) Command Registers Read Case (Read values are not used for checksum calculation.)

2-wire Serial I/F

Slave

Command

Register

Command

Register

Command

Register

Slave

Address

CMDXTN

RDCTL

CHKSUM

YYYY

S

Address /

Control Byte

7C 00

A

S

A

NA

P

S

Address /

Control Byte

7C 00

A

A P

SCL / SDAI / SDAO

F

D

C

2

7D

0

1

2

3

4

5

D

Register Read Read mode

3-wire Serial I/F

CSB

CMDXTN

RDCTL

CHKSUM

YYYY

SCK / SDI

SDO

F

D

C

2

D

Command

Register

Command

Register

Command

Register

0

1

2

3

4

5

S: START Condition, P: STOP Condition, A: ACK, NA: NACK

: valid data for internal checksum calculation

Calculation (1) RAMWrite Case

Calculation (2) Read Case

Hex Dec

SADSET upper 4-bit

SADSET lower 4-bit

ADSET upper 4-bit

ADSET lower 4-bit

DisplayData upper 4-bit

DisplayData lower 4-bit

CHKSUMupper 4-bit

Sum

E

0

2

A

3

14

0

2

10

3

CMDXTN upper 4-bit

CMDXTN lower 4-bit

RDCTL upper 4-bit

RDCTL lower 4-bit

CHKSUMupper 4-bit

Sum

F

D

C

2

D

37

15

13

12

2

13

55

D

2A

13

42

-> “YYYY” = “7h”

-> “XXXX” = “Ah”

Figure 36. Example of Checksum Calculation

In 2-wire, the checksum calculation value will be same in ICs which use same Slave Address and different sub address.

In 3-wire, all IC’s checksum values will be same.

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Error Detection - continued

Logic Error Detection

This function detects occurrence of registers (DFF) errors due to electric noise. DFFs for detection are placed around logic

area. Judgement is always proceeding in DISPON status. Logic error detection will be judged after every 2 frames from

DISPON command. See following sequence.

Command

Frame

DISPON

1st

Set

2nd

1st

2nd

1st

2nd

1st

2nd

1st

2nd

1st

2nd

Re-set

DFF for

101010101

100010101

Not match!

101010101

010101010

detection

Match!

DFF for

101010101

010101010

Expected DFF data inversed

expectation

Detection result

(Command Register Read-back:

D1 bit in 1st Byte)

OK

Judged OK

NG

Judged NG

OK

Judged OK

OK

Judged OK

Keeping Error status

even if judged OK

Error Status cleared

ERROUT

Abnormal Status

Figure 37. Sequence of Logic Error Detection

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Error Detection - continued

SEG / COM Toggle Detection

This function is to detect whether SEG / COM output toggle (AC inversion) in DDRAM data bit = “1”.

Detectable status are considered as following conditions,

(1) SEG / COM waveform stuck at VSS level (SEG can detect in DDRAM data bit = “1” case only).

(a) LCD broken.

(b) ITO wiring connected to VSS line.

(c) SEG / COM output broken such as short with VSS level.

(2) SEG / COM waveform stuck at V0 level (SEG can detect in DDRAM data bit = “1” case only).

(a) LCD broken.

(b) ITO wiring connected to VLCD line.

(c) SEG / COM output broken such as short with VLCD / V0 level.

Command

Frame

...

DISPON

...

COM

...

(Stuck at

VSS Case)

...

Abnormal Waveform

Normal Operation

...

Abnormal Waveform

COM

(Stuck at

V0 Case)

...

Normal Operation

...

Detection Result

...

(Command Resister Read-back: D0 bit in 1st Byte)

Judge as NG

Result is cleared

Judge as OK

ERROUT

...

Abnormal Status

Need Maximum

84 frames in 1/4 Duty

MaxFrame

Need Maximum

84 frames in 1/4 Duty

1/4Duty

1/3Duty

1/2Duty

Static

84

63

42

21

Figure 38. Sequence of SEG / COM Toggle Detection

Contact Resistance Check

COG contact resistance can be inspected by measuring resistance in DUMMY0, DUMMY1, DUMMY2 and DUMMY3

terminals. Abnormal COG bonding status can be detected if the values are outliers.

BU91R64CH-M

(BUMP side down)

Wired in driver IC

The resistance ≤ 5 Ω^(Note)

(Note) Not 100 % tested

Figure 39. DUMMY PADs for the Contact Resistance Measurement

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BU91R64CH-M

Command / Function List

Description List of Command / Function

Identify Sub

Address by

SADSET

Available in

CMDXTN

Mode

No.

Command

Function

Normal Command

1

2

3

4

5

6

7

Mode Set 1(MODESET1)

Address Set (ADSET)

Display On / Off

-

No

-

DDRAM Address Setting

IC Selecting

Sub Address Set (SADSET)

Frame Rate Set (FRSET)

Blink Control1 (BLKCTL1)

Blink Control2 (BLKCTL2)

Frame Frequency

Blink Mode / Blink Frequency Setting

Blink Area Setting

Command Extension (CMDXTN) Access enable for extended commands

Extension Command

8

Software Reset (SWRST)

Mode Set 2(MODESET2)

Mode Set 3(MODESET3)

Contrast Setting (CNTSET)

Read Control (RDCTL)

Checksum(CHKSUM)

Software Reset

-

Yes

9

Error Detection Control

-

10

11

12

13

14

Line / Frame Inversion, Frame Frequency

Contrast adjustment

-

Yes

-

Read Control

Checksum Trigger and Expected Value

COM driving order select, Contrast adjustment

-

COM Set (COMSET)

Yes

Detailed Command Description

1. Mode Set 1 (MODESET1)

MSB

LSB

D7

1

D6

1

D5

0

D4

0

D3

P3

D2

*

D1

*

D0

*

(*: don’t care)

Set Display On and Off

P3

Setup

Reset Initialize Condition

0

1

Display Off (DISPOFF)

Display On (DISPON)

○

-

Display Off: Regardless of DDRAM data, all Segment and Common output will be stopped (VSS level).

Display On: Segment and Common output will be active and will start to read the Display Data from DDRAM.

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Detailed Command Description – continued

2. Address Set (ADSET)

MSB

D7

0

LSB

D0

P0

D6

P6

D5

P5

D4

P4

D3

P3

D2

P2

D1

P1

Set address. (P6 to P0 = “0000000” in reset initialize condition)

Don’t set out of range address, otherwise address will be set to “0000000”.

In 3-SPI case, next transferred data will be recognized as Display Data.

The range of address (7-bit) is shown as bellow.

1/4, 1/3 and 1/2 Duty Drive mode: 00h to 4Fh

Static Drive Mode:

00h to 13h

3. Sub Address Set (SADSET)

MSB

D7

1

LSB

D0

P0

D6

1

D5

1

D4

0

D3

0

D2

0

D1

P1

Set sub address to define one of BU91R6xCH sub address.

The following command can be set independently after SADSET command.

- Display Data write

- Display Data read

- Command Registers read

- Contrast Setting (CNTSET)

- COM set (COMSET)

In 2-wire Serial Interface mode

P1

0

P0

*

Available IC

Reset Initialize Condition

Master or Slave1 ^{(Note 1)}(MS2 = VSS)

Slave2 or Slave3 ^{(Note 1)}(MS2 = VDD)

○

1

*

-

(Note 1): Bit1 of Slave Address selects one of “Master / Slave1” or one of “Slave2 / Slave3”.

(*: don’t care)

In 3-wire Serial Interface mode

P1

0

P0

0

Available IC

Reset Initialize Condition

Master (MS2 = VSS, MS1 = VSS)

Slave1 (MS2 = VSS, MS1 = VDD)

Slave2 (MS2 = VDD, MS1 = VSS)

Slave3 (MS2 = VDD, MS1 = VDD)

○

-

0

1

0

-

1

-

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Detailed Command Description – continued

4. Frame Rate Set (FRSET)

MSB

D7

1

LSB

D0

P0

D6

1

D5

1

D4

0

D3

1

D2

P2

D1

P1

Set Frame Frequency

In Internal Clock Mode, Frame Frequency is calculated as shown in the following table.

Table 5. Frame Frequency (Internal Clock Mode)

MODESET3

FRSET

P1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Frame Freqency [Hz] (Number of Clock Pulses)

Line Inversion Frame Inversion

Reset Initilaze Condition

P1

0

1

P0

0

1

0

1

P2

0

1

0

1

0

1

0

1

P0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

65.7 (624)

74.3 (552)

85.4 (480)

-

ᴑ

-

122.0 (336)

131.4 (312)

142.4 (288)

155.3 (264)

170.8 (240)

189.8 (216)

213.5 (192)

244.0 (168)

284.7 (144)

427.1 ( 96)

569.4 ( 72) (Prohibited)

854.2 ( 48) (Prohibited)

1708.3 ( 24) (Prohibited)

65.7 (624)

74.3 (552)

85.4 (480)

131.4 (312)

148.6 (276)

170.8 (240)

122.0 (336)

244.0 (168)

131.4 (312)

262.8 (156)

142.4 (288)

284.7 (144)

155.3 (264)

310.6 (132)

170.8 (240)

341.7 (120)

189.8 (216)

379.6 (108)

213.5 (192)

427.1 ( 96)

244.0 (168)

488.1 ( 84)

284.7 (144)

427.1 ( 96)

569.4 ( 72) (Prohibited)

854.2 ( 48) (Prohibited)

1708.3 ( 24) (Prohibited)

569.4 ( 72) (Prohibited)

854.2 ( 48) (Prohibited)

1138.9 ( 36) (Prohibited)

1708.3 ( 24) (Prohibited)

3416.7 ( 12) (Prohibited)

1

In External Clock Mode, Frame Frequency is calculated as shown in following table,

Table 6. Frame Frequency (External Clock Mode)

Frame Freqency [Hz]

MODESET3

FRSET

Reset Initilaze Condition

P1

0

P0

*

P2

*

P1

*

P0

*

Line Inversion

Frame Inversion

External Clock / 24

ᴑ

1

*

External Clock / 24

External Clock / 12

-

(*: don’t care)

(Example 1)

EXTCLK = VDD

External Clock: 1,800 Hz

MODESET3 P1: 0

Frame Frequency = External Clock / 24 = 1,800 / 24 = 75 Hz @Line / Frame Inversion

(Example 2)

EXTCLK = VDD

External Clock: 3,500 Hz

MODESET3 P1: 1

Frame Frequency = External Clock / 24 = 3,500 / 24 = 145.8 Hz @Line Inversion

Frame Frequency = External Clock / 12 = 3,500 / 12 = 291.7 Hz @Frame Inversion

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Detailed Command Description – continued

5. Blink Control1 (BLKCTL1)

MSB

D7

1

LSB

D0

P0

D6

1

D5

1

D4

1

D3

0

D2

P2

D1

P1

Set Blink Mode

P2

Blink Mode

Reset Initialize Condition

0

1

All Segments Blink Mode

Bank Blink Mode

○

-

Bank Blink Mode is available in 1/2 Duty Drive and Static Drive.

Set Blink Frequency

P1

0

P0

0

Blink Frequency

Reset Initialize Condition

Off

○

-

0

1

32 Frames

64 Frames

128 Frames

1

0

-

1

-

About Frame Frequency calculation, refer to 4. Frame Rate Set (FRSET).

About Bank Blink Mode, refer to Blink Control (Blink Timing Generator).

6. Blink Control2 (BLKCTL2)

MSB

D7

1

LSB

D0

*

D6

1

D5

1

D4

1

D3

1

D2

0

D1

P1

(*: don’t care)

Set Blink Area in 1/2 Duty Drive and Static Drive in Bank Blink Mode

P1

0

DDRAM Write Area

Normal Display Area

Blink Area

Reset Initialize Condition

○

1

-

This register is available only in 1/2 Duty Drive and Static Drive.

About data writing to blink area, refer to Blink Control (Blink Timing Generator).

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Detailed Command Description – continued

7. Command Extension (CMDXTN)

MSB

D7

1

LSB

D0

P0

D6

1

D5

1

D4

1

D3

1

D2

1

D1

0

Set CMDXTN Mode Effective

P0

Mode

Reset Initialize Condition

Ineffective CMDXTN Mode

(Normal Mode)

0

1

○

CMDXTN Mode

(Extension Mode)

-

The following extension commands are accessible only in CMDXTN mode,

1. SWRST

2. MODESET2

3. MODESET3

4. CNTSET

5. RDCTL

6. CHKSUM

7. COMSET

To access normal command such as DISPON etc., set P0 = “0” (ineffective CMDXTN mode).

Refer to Command / Function List.

8. Software Reset (SWRST)

MSB

D7

1

LSB

D0

P0

D6

0

D5

0

D4

0

D3

*

D2

*

D1

*

(*: don’t care)

This register can be accessed in CMDXTN mode only.

Set software reset effective

P0

0

Operation

No Operation

Software Reset Execute

Reset Initialize Condition

○

1

-

When “Software Reset” is executed, BU91R64CH-M will be reset to initial condition.

Refer to POR and Reset Initialize Condition.

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Detailed Command Description – continued

9. Mode Set 2 (MODESET2)

MSB

D7

1

LSB

D0

P0

D6

0

D5

0

D4

1

D3

P3

D2

P2

D1

P1

This register can be accessed in CMDXTN mode only.

Set Glass breaking detection to enable

P3

0

Setup

Reset Initialize Condition

Disable

Enable

○

1

-

Set Checksum detection to enable

P2

0

Setup

Reset Initialize Condition

Disable

Enable

○

1

-

Set Logic error detection to enable

P1

0

Setup

Reset Initialize Condition

Disable

Enable

○

1

-

Set SEG / COM toggle detection to enable

P0

0

Setup

Reset Initialize Condition

Disable

Enable

○

1

-

ERROUT output function will be effective when any bit of P3 to P0 is set to enable, refer to Detailed Command

Description.

10. Mode Set 3 (MODESET3)

MSB

D7

1

LSB

D0

P0

D6

0

D5

1

D4

0

D3

0

D2

P2

D1

P1

This register can be accessed in CMDXTN mode only.

Set LCD Driving Mode

P2

0

Driving Mode

Line Inversion Mode

Frame Inversion Mode

Reset Initialize Condition

○

1

-

Power consumption is reduced in the following order: Line inversion > Frame inversion

Typically, when driving large capacitance LCD, Line inversion will increase the influence of crosstalk.

Regarding driving waveform, refer to LCD Driving Waveform.

Set x2 Frame frequency in Frame inversion mode

P1

0

Mode

Reset Initialize Condition

Normal Frequency Mode

x2 Frequency in Frame Inversion

○

1

-

This command is only effective in Frame inversion mode.

In detail, refer to 4. Frame Rate Set (FRSET).

Set Frame Frequency Mode

P0

0

Frame Frequency Mode

Normal Frequency Mode

High Frequency Mode

Reset Initialize Condition

○

1

-

In detail, refer to 4. Frame Rate Set (FRSET).

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Detailed Command Description – continued

11. Contrast Setting (CNTSET)

MSB

D7

1

LSB

D0

P0

D6

0

D5

1

D4

1

D3

P3

D2

P2

D1

P1

This register can be accessed in CMDXTN mode only.

This command can set sub address individually by SADSET command.

Set EVR for Contrast adjustment.

BU91R64CH-M is able to control V0 voltage level (the maximum level voltage of LCD driving) by a 32-step electrical volume

register (EVR).

Table 7. V0 Voltage Setting

Unit: V

COMSET

CNTSET

VLCD [V]

4.0

Reset Initialize

Condition

Formula

P3

0

1

P3 P2 P1 P0

6.0

5.5

5.0

3.5

3.0

2.5

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.000 * VLCD

0.967 * VLCD

0.937 * VLCD

0.909 * VLCD

0.882 * VLCD

0.857 * VLCD

0.833 * VLCD

0.810 * VLCD

0.789 * VLCD

0.769 * VLCD

0.750 * VLCD

0.731 * VLCD

0.714 * VLCD

0.697 * VLCD

0.681 * VLCD

0.666 * VLCD

0.652 * VLCD

0.638 * VLCD

0.625 * VLCD

0.612 * VLCD

0.600 * VLCD

0.588 * VLCD

0.576 * VLCD

0.566 * VLCD

0.555 * VLCD

0.545 * VLCD

0.535 * VLCD

0.526 * VLCD

0.517 * VLCD

0.508 * VLCD

0.500 * VLCD

0.491 * VLCD

6.000 5.500 5.000 4.000 3.500 3.000 2.500

5.802 5.323 4.839 3.871 3.387 2.903 2.419

5.622 5.156 4.688 3.750 3.281 2.813 2.344

5.454 5.000 4.545 3.636 3.182 2.727 2.273

5.292 4.853 4.412 3.529 3.088 2.647 2.206

5.142 4.714 4.286 3.429 3.000 2.571 2.143

4.998 4.583 4.167 3.333 2.917 2.500 2.083

4.860 4.459 4.054 3.243 2.838 2.432 2.027

4.734 4.342 3.947 3.158 2.763 2.368 1.974

4.614 4.231 3.846 3.077 2.692 2.308 1.923

4.500 4.125 3.750 3.000 2.625 2.250 1.875

4.386 4.024 3.659 2.927 2.561 2.195 1.829

4.284 3.929 3.571 2.857 2.500 2.143 1.786

4.182 3.837 3.488 2.791 2.442 2.093 1.744

4.086 3.750 3.409 2.727 2.386 2.045 1.705

3.996 3.667 3.333 2.667 2.333 2.000 1.667

3.912 3.587 3.261 2.609 2.283 1.957 1.630

3.828 3.511 3.191 2.553 2.234 1.915 1.596

3.750 3.438 3.125 2.500 2.188 1.875 1.563

3.672 3.367 3.061 2.449 2.143 1.837 1.531

3.600 3.300 3.000 2.400 2.100 1.800 1.500

3.528 3.235 2.941 2.353 2.059 1.765 1.471

3.456 3.173 2.885 2.308 2.019 1.731 1.442

3.396 3.113 2.830 2.264 1.981 1.698 1.415

3.330 3.056 2.778 2.222 1.944 1.667 1.389

3.270 3.000 2.727 2.182 1.909 1.636 1.364

3.210 2.946 2.679 2.143 1.875 1.607 1.339

3.156 2.895 2.632 2.105 1.842 1.579 1.316

3.102 2.845 2.586 2.069 1.810 1.552 1.293

3.048 2.797 2.542 2.034 1.780 1.525 1.271

3.000 2.750 2.500 2.000 1.750 1.500 1.250

2.946 2.705 2.459 1.967 1.721 1.475 1.230

O

-

Prohibited Setting

Avoid setting EVR of “V0 < 2.5V” and “V0 > VLCD – 0.6V” condition. BU91R64CH-M output voltage will be unstable in such

conditions.

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Detailed Command Description – continued

12. Read Control (RDCTL)

MSB

D7

1

LSB

D0

P0

D6

1

D5

0

D4

0

D3

*

D2

*

D1

P1

(*: don’t care)

This register can be accessed in CMDXTN mode only.

Set Read enable (This bit is available in 3SPI mode only. In 2-wire, this bit is undefined.)

P1

0

Read_en

Reset Initialize Condition

Read disable (Write Mode)

Read enable (Read Mode)

○

1

-

Set Read data

P0

Read_mode

Command Registers Read

DDRAM Data Read

Reset Initialize Condition

0

1

○

-

13. Checksum (CHKSUM)

MSB

LSB

D7

1

D6

1

D5

0

D4

1

D3

P3

D2

P2

D1

P1

D0

P0

This register can be accessed in CMDXTN mode only.

P3 to P0: The sum of all Command Registers value for interface checksum function. Set this value after calculating the sum

of each Command Registers value. In detail, refer to Checksum Detection.

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Detailed Command Description – continued

14. COM Set (COMSET)

MSB

D7

1

LSB

D0

P0

D6

1

D5

1

D4

0

D3

P3

D2

P2

D1

P1

This register can be accessed in CMDXTN mode only.

This command can set sub address individually by SADSET command.

P3: Set MSB of CNTSET

Refer to Contrast Setting command (CNTSET).

P2 to P0: Set COM scanning order of COMA, COMB and COMC individually.

P2: Set COMC Scanning Order

P1: Set COMB Scanning Order

P0: Set COMA Scanning Order

P2

(COMC)

P1

(COMB)

P0

(COMA)

Duty

Drive

Reset Initialize

Condition

Toggle Order of COM*0 to COM*3

1/4 Duty

1/3 Duty

1/2 Duty

Static

COM*0→COM*1→COM*2→COM*3

COM*0→COM*1→COM*2 ^{(Note 1)}

COM*0→COM*1 ^{(Note 2)}

0

1

0

1

0

1

○

COM*0 ^{(Note 3)}

1/4 Duty

1/3 Duty

1/2 Duty

Static

COM*3→COM*2→COM*1→COM*0

COM*3→COM*2→COM*1 ^{(Note 1)}

COM*1→COM*0 ^{(Note 2)}

-

COM*0 ^{(Note 3)}

(*: A for P0, or B for P1, or C for P3)

(Note 1) COMA3 = COMA0

(Note 2) COMA2 = COMA0, COMA3 = COMA1

(Note 3) COMA1 / 2 / 3 = COMA0

SmallerITOresistance byshorterwire

LargerITO resistance due to longerwire routing

4

1

5

2

6

3

4

1

5

2

6

3

Scan Direction

Swap Scan Direction

Figure 40. COM Scan Direction Image

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LCD Driving Waveform

1/3 Bias, 1/4 Duty Drive

Frame Inversion

Line Inversion

SEGn SEGn+1 SEGn+2 SEGn+3

COMA0

COMA1

COMA2

COMA3

State A

State B

COMA0

State A

State B

COMA1

COMA2

COMA3

1frame

V0

COMA0

COMA1

COMA2

COMA3

COMA0

COMA1

COMA2

COMA3

VSS

V0

VSS

V0

VSS

V0

VSS

V0

VSS

V0

VSS

V0

VSS

V0

VSS

V0

SEGn

VSS

V0

VSS

V0

SEGn+1

SEGn+2

SEGn+3

SEGn+1

SEGn+2

SEGn+3

VSS

V0

VSS

V0

VSS

V0

VSS

V0

VSS

+V0

VSS

+V0

State A

(COMA0

-SEGn)

-V0

+V0

State B

(COMA1

-SEGn)

-V0

COMSET P2 = “0”, Normally white type LCD case

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LCD Driving Waveform - continued

1/2 Bias, 1/4 Duty Drive

Frame Inversion

Line Inversion

SEGn SEGn+1 SEGn+2 SEGn+3

COMA0

COMA1

COMA2

COMA3

State A

State B

COMA0

COMA1

COMA2

COMA3

stateA

stateB

1frame

V0

COMA0

COMA1

COMA0

VSS

V0

VSS

V0

COMA1

VSS

V0

VSS

V0

COMA2

COMA3

SEGn

COMA2

VSS

V0

VSS

V0

COMA3

VSS

V0

VSS

V0

SEGn

VSS

V0

VSS

V0

SEGn+1

SEGn+2

SEGn+3

SEGn+1

VSS

V0

VSS

V0

SEGn+2

VSS

V0

VSS

V0

SEGn+3

VSS

+V0

VSS

+V0

State A

(COMA0

-SEGn)

(COMA0

-SEGn)

-V0

+V0

State B

(COMA1

-SEGn)

(COMA1

-SEGn)

-V0

COMSET P2 = “0”, Normally white type LCD case

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LCD Driving Waveform - continued

1/3 Bias, 1/3 Duty Drive

Frame Inversion

Line Inversion

SEGn SEGn+1 SEGn+2 SEGn+3

COMA0

COMA1

COMA2

COMA3

State A

State B

COMA0

State A

State B

COMA1

COMA2

COMA3

Same waveform as COMA0

1frame

V0

COMA0

COMA1

COMA2

COMA3

COMA0

COMA1

COMA2

COMA3

VSS

V0

VSS

V0

VSS

V0

VSS

V0

VSS

V0

VSS

V0

VSS

V0

VSS

V0

SEGn

VSS

V0

VSS

V0

SEGn+1

SEGn+2

SEGn+3

SEGn+1

SEGn+2

SEGn+3

VSS

V0

VSS

V0

VSS

V0

VSS

V0

VSS

+V0

VSS

+V0

State A

(COMA0

-SEGn)

-V0

+V0

State B

(COMA1

-SEGn)

-V0

COMSET P2 = “0”, Normally white type LCD case

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LCD Driving Waveform - continued

1/2 Bias, 1/3 Duty Drive

Frame Inversion

Line Inversion

SEGn SEGn+1 SEGn+2 SEGn+3

COMA0

COMA1

COMA2

COMA3

State A

State B

COMA0

COMA1

COMA2

COMA3

stateA

stateB

Same waveform as COMA0

1frame

V0

COMA0

COMA1

COMA0

VSS

V0

VSS

V0

COMA1

VSS

V0

VSS

V0

COMA2

COMA3

SEGn

COMA2

VSS

V0

VSS

V0

COMA3

VSS

V0

VSS

V0

SEGn

VSS

V0

VSS

V0

SEGn+1

SEGn+2

SEGn+3

SEGn+1

VSS

V0

VSS

V0

SEGn+2

VSS

V0

VSS

V0

SEGn+3

VSS

+V0

VSS

+V0

State A

(COMA0

-SEGn)

(COMA0

-SEGn)

-V0

+V0

State B

(COMA1

-SEGn)

(COMA1

-SEGn)

-V0

COMSET P2 = “0”, Normally white type LCD case

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LCD Driving Waveform - continued

1/3 Bias, 1/2 Duty Drive

Frame Inversion

Line Inversion

SEGn SEGn+1SEGn+2SEGn+3

COMA0

COMA1

COMA2

COMA3

State A

COMA0

COMA1

COMA2

COMA3

State A

State B

Same waveform as COMA0

Same waveform as COMA1

Same waveform as COMA0

Same waveform as COMA1

1frame

V0

COMA0

COMA1

COMA2

COMA3

COMA0

VSS

V0

VSS

V0

COMA1

VSS

V0

VSS

V0

COMA2

VSS

V0

VSS

V0

COMA3

VSS

V0

VSS

V0

SEGn

VSS

V0

VSS

V0

SEGn+1

SEGn+2

SEGn+3

SEGn+1

VSS

V0

VSS

V0

SEGn+2

VSS

V0

VSS

V0

SEGn+3

VSS

+V0

VSS

+V0

State A

(COMA0

State A

(COMA0

-SEGn)

-V0

+V0

-V0

+V0

State B

(COMA1

State B

(COMA1

-SEGn)

-V0

COMSET P2 = “0”, Normally white type LCD case

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LCD Driving Waveform - continued

1/2 Bias, 1/2 Duty Drive

Frame Inversion

Line Inversion

SEGn SEGn+1 SEGn+2 SEGn+3

COMA0

COMA1

COMA2

COMA3

State A

COMA0

COMA1

COMA2

COMA3

stateA

State B

stateB

Same waveform as COMA0

Same waveform as COMA1

1frame

V0

COMA0

COMA1

COMA0

VSS

V0

VSS

V0

COMA1

VSS

V0

VSS

V0

COMA2

COMA3

SEGn

COMA2

VSS

V0

VSS

V0

COMA3

VSS

V0

VSS

V0

SEGn

VSS

V0

VSS

V0

SEGn+1

SEGn+2

SEGn+3

SEGn+1

VSS

V0

VSS

V0

SEGn+2

VSS

V0

VSS

V0

SEGn+3

VSS

+V0

VSS

+V0

State A

(COMA0

-SEGn)

(COMA0

-SEGn)

-V0

+V0

State B

(COMA1

-SEGn)

(COMA1

-SEGn)

-V0

COMSET P2 = “0”, Normally white type LCD case

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LCD Driving Waveform - continued

Static Drive

Frame Inversion

Line Inversion

SEGn SEGn+1 SEGn+2 SEGn+3

COMA0

stateA stateB

COMA0

stateA stateB

COMA1 to COMA3

Same waveform as COMA0

COMA1 to COMA3

Same waveform as COMA0

1frame

V0

COMA0 to

COMA3

COMA0 to

COMA3

VSS

V0

VSS

V0

SEGn

VSS

V0

VSS

V0

SEGn+1

SEGn+2

SEGn+3

SEGn+1

SEGn+2

SEGn+3

VSS

V0

VSS

V0

VSS

V0

VSS

V0

VSS

+V0

VSS

+V0

State A

(COMA0

-SEGn)

-V0

+V0

State B

(COMA0

-SEGn+1)

-V0

Normally white type LCD case

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Example of Display Data

In case of LCD layout pattern shown in Figure 41. Example COM Line Pattern and Figure 42. Example SEG Line Pattern

and DDRAM data shown in Table 8. DDRAM Data Example, display pattern will be shown as in Figure 43. Example Display

Pattern.

COMA0

COMA1

COMA2

COMA3

Figure 41. Example COM Line Pattern

SEG1 SEG3

SEG2

SEG5 SEG7

SEG4 SEG6 SEG8

SEG9

SEG10

Figure 42. Example SEG Line Pattern

Table 8. DDRAM Data Example

COMA0

COMA1

COMA2

COMA3

Address

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah

0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h

(The COMscan order: COMSET P0 = “0”)

Figure 43. Example Display Pattern

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Initialize Sequence

Follow the Power On sequence below to set IC to initial reset condition.

Power On

↓

START Condition

↓

9 clock pulses in SCL with SDA = High level

↓

STOP Condition

↓

START Condition

↓

9 clock pulses in SCL with SDA = High level

↓

STOP Condition

↓

START Condition

↓

Issue Slave Address

↓

Issue Control Byte

↓

Issue CMDXTN (Enter to Extension Mode)

↓

Issue SWRST (Execute Software Reset).

After Power On and before sending initialize sequence, each register value, DDRAM address and DDRAM data are random

if POR is disabled by TR = VDD or Power On sequence cannot keep the conditions in Figure 45. Power On / Off

Waveform.

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Start Sequence

Start Sequence Example1

No.

Input

D7 D6 D5 D4 D3 D2 D1 D0

Descriptions

1

2

3

Power On

Wait 100µs

START

-

VDD = 0 V→3.3 V (t_R= 1 ms), VLCD = 0 V→5.0 V

Initialize BU91R64CH-M

START Condition

4

5

Dummy Byte

STOP

1

-

1

-

1

-

1

-

1

-

1

-

1

-

1

-

9 clock pulses in SCL with SDA = High level

STOP Condition

6

START

-

START Condition

7

8

Dummy Byte

STOP

1

-

1

-

1

-

1

-

1

-

1

-

1

-

1

-

9 clock pulses in SCL with SDA = High level

STOP Condition

9

START

-

START Condition

10

11

12

13

14

15

Slave Address

Control Byte

CMDXTN

SWRST

0

1

-

1

0

1

0

-

1

0

1

0

-

1

0

1

0

-

1

0

1

0

-

1

0

1

0

-

0

-

0

1

-

Issue Slave Address

Issue Control Byte

Enter to Extension Mode

Software Reset

STOP Condition

START Condition

STOP

START

-

16 Slave Address

0

1

0

-

1

0

1

0

1

0

-

1

0

1

0

1

0

1

0

-

1

0

1

0

1

0

1

0

1

0

-

1

0

1

0

1

0

1

0

-

1

0

1

0

1

0

-

0

1

0

-

0

1

0

-

Issue Slave Address

Issue Control Byte

Display Off

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

Control Byte

MODESET1

CMDXTN

MODESET2

MODESET3

CNTSET

Enter to Extension Mode

All detections: disabled

Line Inversion, Normal Frequency Mode

V0 = 1.000 x VLCD level

Read setting (disabled)

COM Set

Enter to Normal Mode

Frame frequency = 155.3 Hz

Blink off

Data write access to Normal Display Area

Sub Address Set

Address Set

STOP Condition

START Condition

RDCTL

COMSET

CMDXTN

FRSET

BLKCTL1

BLKCTL2

SADSET

ADSET

STOP

START

Slave Address

Control Byte

Display Data

:

-

0

*

:

1

*

:

1

0

*

:

1

0

*

:

1

0

*

:

1

0

*

:

0

*

:

0

*

:

Issue Slave Address

Issue Control Byte

Address 00h to 01h

Address 02h to 03h

:

35

Display Data

STOP

*

-

0

1

-

*

-

1

0

1

-

*

-

1

0

-

*

-

1

0

-

*

-

1

0

1

-

*

-

1

0

-

*

-

0

-

*

-

0

-

Address 4Eh to 4Fh

STOP Condition

START Condition

Issue Slave Address

Issue Control Byte

Display On

36

37

38

39

40

41

START

Slave Address

Control Byte

MODESET1

STOP

STOP Condition

(*: don’t care)

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Start Sequence – continued

Start Sequence Example2

Initialize

Initialize Sequence

DISPON Sequence

DISPON

Display Data Write

DISPOFF

Display Data Write Sequence

DISPOFF Sequence

BU91R64CH-M is initialized with “Initialize Sequence”, starts to display with “DISPON Sequence”, updates Display Data with

“Display Data Write Sequence” and stops the display with “DISPOFF Sequence”.

Execute “DISPON Sequence” when MCU starts display again.

Initialize Sequence

Input

DISPON Sequence

Input

Data

Description

D7 D6 D5 D4 D3 D2 D1 D0

VDD on

START

VLCD on

Wait for 100µs

START

Dummy Byte

STOP

START

Dummy Byte

STOP

Slave Address

Control Byte

CMDXTN

MODESET2

MODESET3

CNTSET

RDCTL

COMSET

CMDXTN

FRSET

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Enter to Extension Mode

All detections: disabled

Inversion / FR setting

Contrast Set

Read setting

COM Set

Enter to Normal Mode

Frame Frequency

Blink setting

Data write setting

Display On

1

Keep high in ACK bit

START

Slave Address

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Control Byte

CMDXTN

SWRST

BLKCTL1

BLKCTL2

MODESET1

STOP

Enter to Extension Mode

Software Reset

STOP

START

Slave Address

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Display Data Write Sequence

Input

Data

Control Byte

MODESET1

CMDXTN

MODESET2

MODESET3

CNTSET

RDCTL

COMSET

CMDXTN

FRSET

Description

Display Off

D7 D6 D5 D4 D3 D2 D1 D0

Enter to Extension Mode

All detections: disabled

Inversion / FR setting

Contrast Set

Read setting

COM Set

Enter to Normal Mode

Frame Frequency

Blink setting

Data write setting

Sub Address Set

Address Set

START

Slave Address

0

1

0

1

0

1

0

1

0

1

0

Control Byte

MODESET1

CMDXTN

MODESET2

MODESET3

CNTSET

RDCTL

COMSET

CMDXTN

FRSET

BLKCTL1

BLKCTL2

SADSET

ADSET

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Display On

Enter to Extension Mode

All detections: disabled

Inversion / FR setting

Contrast Set

Read setting

COM Set

Enter to Normal Mode

Frame Frequency

Blink setting

Data write setting

Sub Address Set

Address Set

BLKCTL1

BLKCTL2

SADSET

ADSET

STOP

START

Slave Address

0

*

1

*

1

0

*

1

0

*

1

0

*

1

0

*

0

*

0

*

Control Byte

Display Data

:

STOP

START

Slave Address

STOP

0

*

1

*

1

0

*

1

0

*

1

0

*

1

0

*

0

*

0

*

Control Byte

Display Data

:

STOP

DISPOFF Sequence

Input

Data

D7 D6 D5 D4 D3 D2 D1 D0

Description

START

Slave Address

Control Byte

MODESET1

STOP

0

1

0

1

0

1

0

1

0

1

0

Display Off

(*: don’t care)

Abnormal operation may occur in BU91R64CH-M due to the effect of noise or other external factor. To avoid this

phenomenon, it is highly recommended to input command according to sequence described above during initialization,

Display On / Off and refresh of Display Data.

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Cautions in Power On / Off

Please keep Power On / Off sequence as below waveform. To prevent incorrect display, malfunction and abnormal current,

VDD must be turned on before VLCD in power up sequence. VDD must be turned off after VLCD in power down sequence.

Please satisfies t1 > 0 ns, t2 > 0 ns.

To refrain from data transmission is strongly recommended while power supply is rising up or falling down to prevent from the

occurrence of disturbances on transmission and reception.

t1

t2

VLCD

VDD

10 %

VDD Min

Figure 44. Recommended Power On / Off Sequence

BU91R64CH-M has “POR” (Power On Reset) circuit and Software Reset function. Keep the following recommended Power

On conditions in order to power up properly.

Set power up conditions to meet the recommended t_R, t_F, t_OFF, and V_BOTspecification below in order to ensure POR

operation. Set terminal TR = VSS to enable POR circuit.

t_F

t_R

VDD

Recommended condition of t_R, t_F,t_OFF, V_BOT(Ta = 25 °C)

(Note)

t_OFF

t_R

1 ms

to 500 ms to 500 ms

t_F

t_OFF

V_BOT

1 ms

Less than

0.1 V

VSS

Min 20 ms

(Note) This function is guaranteed by design, not tested in production process.

Figure 45. Power On / Off Waveform

If it is difficult to keep above conditions, execute the following sequence as quickly as possible after Power On. Setting TR =

VDD disables the POR circuit, in such case, execute the following sequence. Note that however it cannot accept command

while supply is unstable or below the minimum supply range. Note also that software reset is not a complete alternative to

POR function.

2-wire Serial Interface

3-wire Serial Interface

1. Generate two dummy bytes with START and STOP 1. Set CSB to High level.

Conditions SDAI must be “1” as data.

VDD

SDAI

SCL

CSB

SCK

SDI

Dummy Byte

(9 SCL pulses)

Dummy Byte

(9 SCL pulses)

Figure 47. CSB Timing

START

Condition

STOP START

Condition Condition

STOP

Condition

Figure 46. Dummy Clock / STOP / START Condition

2. Set CSB to low level, then execute Software Reset as

follows:

2. Execute Software Reset as follows

Send START Condition

Send CMDXTN command (FDh)

Send SWRST command (81h)

Send Slave Address (7Ch, 7Eh, 70h or 72h)

Send Control Byte (00h)

Send CMDXTN command (FDh)

Send SWRST command (81h)

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Display Off Operation in External Clock Mode

Clock stop timing in Display Off

After receiving MODESET1 Display Off (DISPOFF), BU91R64CH-M enters to DISPOFF sequence synchronized with frame

then Segment and Common terminals output VSS level.

Therefore, in External Clock Mode, it is necessary to input the external clock (minimum 26 clock pulses) based on each

Frame Frequency setting after sending MODESET1 DISPOFF command.

Command

OSCIO

MODESET1 DISPOFF

To Input External Clock at Least 26

clock pulses or more

Frame

SEG

VSS

COMA0

COMA1

COMA2

COMA3

Display On

Display Off

The last display

frame after receiving

MODESET1

Figure 48. External Clock Stop Timing

In case of External Clock Mode, a clock signal shall be always supplied to BU91R64CH-M. Removing the clock may freeze

the LCD in a DC state which is not suitable for the LCD.

In Multi-chip Structure in Internal Clock Mode

In multi-chip structure and in internal clock mode, clock signal for Slave 1 to Slave 3 display are provided by Master IC. So if

Master IC receives Display Off before Slave ICs, the clock from Master IC will stop and Slave ICs hold the SEG and COM

level not VSS level, then causes abnormal display. To prevent this issue, DISPOFF must be sent to Slave ICs earlier than to

Master IC.

DISPOFF in Slave 1 to Slave 3 must be set earlier than Master IC to

prevent incorrect display in the panels driven by Slave 1 to Slave 3 ICs.

MODESET1 DISPOFF

for Slave1 to Slave3

MODESET1 DISPOFF

for Master

Command

Frame

Master

SEG

VSS

COMA0

OSCIO

Display On in Master IC

Display Off

Slave1 to Slave3

SEG

VSS

COMA0

Display On in Slave 1 to Slave3 IC

Display Off

Figure 49. DISPOFF Sequence in Multi-chip Structure

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Note on The Multiple Device Connection to 2-wire Serial Interface.

Do not access the other device without power supply (VDD) to the BU91R64CH-M.

MCU

BU91R64CH-M

Other Device

Figure 50. Example of BUS Connection

To control the slope of the falling edge, a capacitor is connected between gate and drain of a NMOS transistor as shown in

the following figure. The gate is in a high-impedance state when the power supply (VDD) is not supplied.

In this condition, the gate voltage is pulled up by the current flow through the capacitance as a result of the SDAO signal's

transition from low to high.

The NMOS transistor turns on and draws some current (Ids) from the SDAO if the gate voltage (Vg) is higher than the

threshold voltage (Vth).

An external resistor (R) is connected between the power line and SDAO line to keep the SDA line as logic high.But the line

cannot be kept as logic high if the voltage drop (R*Ids) is large.

Apply power supply (VDD) to BU91R64CH-M when the multiple devices are on the same bus.

VDD

Z = 1/jωC

SDAO

Vg

Internal Circuit

Figure 51. SDA Output Cell Structure

Note in Case that the SDA is stuck at LOW

Normally, BU91R64CH-M SDA status is controlled by MCU, so it set SDA to VSS level only in ACK timing and in output “0”

case during Read Mode.

If the data line (SDAO) is stuck at LOW by BU91R64CH-M unexpectedly, MCU should send two dummy bytes with START

and STOP Conditions as show in Figure 52. Recovery Sequence from SDA Stuck. BU91R64CH-M will release SDAO

stuck within this sequence.

SDAO will be released with in this sequence

SDAO

SDAI

SCL

Dummy Byte

(9 SCL pulses)

START

Condition

STOP START

Condition Condition

STOP

Condition

Figure 52. Recovery Sequence from SDA Stuck

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Operational Notes

1. Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power

supply pins.

2. Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the

digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog

block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and

aging on the capacitance value when using electrolytic capacitors.

3. Ground Voltage

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.

4. Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations

on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5. Recommended Operating Conditions

The function and operation of the IC are guaranteed within the range specified by the recommended operating

conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical

characteristics.

6. Inrush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow

instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power

supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and

routing of connections.

7. Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may

subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply

should always be turned off completely before connecting or removing it from the test setup during the inspection

process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during

transport and storage.

8. Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and

unintentional solder bridge deposited in between pins during assembly to name a few.

9. Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and

extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small

charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and

cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the

power supply or ground line.

10. Regarding the Input Pin of the IC

In the construction of this IC, P-N junctions are inevitably formed creating parasitic diodes or transistors. The operation

of these parasitic elements can result in mutual interference among circuits, operational faults, or physical damage.

Therefore, conditions which cause these parasitic elements to operate, such as applying a voltage to an input pin

lower than the ground voltage should be avoided. Furthermore, do not apply a voltage to the input pins when no power

supply voltage is applied to the IC. Even if the power supply voltage is applied, make sure that the input pins have

voltages within the values specified in the electrical characteristics of this IC.

11. Ceramic Capacitor

When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with

temperature and the decrease in nominal capacitance due to DC bias and others.

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Operational Notes – continued

12. Disturbance Light

In a device where a portion of silicon is exposed to light such as in a WL-CSP and chip products, IC characteristics

may be affected due to photoelectric effect. For this reason, it is recommended to come up with countermeasures that

will prevent the chip from being exposed to light.

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Ordering Information

B U 9 1 R 6 4 C H

-

M 3 B W

Part Number

Product Rank

M: for Automotive

Minimum Order Quantity (MOQ)

Orderable Part Number

BU91R64CH-M3BW

Minimum Order Quantity

900 pcs

Marking Diagram

Product control number

Y

X

(Bump side down)

Refer to PAD Arrangement for the definition of X/Y coordinates.

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Packing Quantity

Packing QTY.

(Standard QTY)

Tray:

Block:

Vacuum Pack:

90 pcs / tray

450 pcs / block (1 block = 5 trays)

450 pcs / vacuum pack (1 vacuum pack = 1 blocks)

Inner Box

Outer Box

900 pcs / inner box (1 inner box = 2 vacuum packs)

1,800 pcs / outer box (1 outer box = 2 inner boxes)

Pellet Drawing

PAD No.160

PAD No.1

Y

Input Side

Output Side

Y

X

PAD No.77

PAD No.76

(Bump side up)

Refer to PAD Arrangement for the definition of X/Y coordinates.

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Package Condition

Products should be aligned to the same direction with Bump side up.

“Chamfering” side is aligned with X/Y direction of the chip as shown in the following drawing.

C

RH21010466R-040A

Y

X

Refer to PAD Arrangement for the definition of X/Y coordinates.

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Physical Dimension Tray Information

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Revision History

Data

Revision

001

Changes

18.May. 2018

New Release

Updating Minimum Order Quantity and Packing Quantity

Minor modifications by formality check

Updating Minimum Order Quantity and Packing Quantity

Minor modifications by formality check

13.Sep. 2019

08.Jan. 2020

002

003

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Notice

Precaution on using ROHM Products

(Note 1)

1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment

,

aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,

bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales

representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any

ROHM’s Products for Specific Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.

Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the

use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our

Products under any special or extraordinary environments or conditions (as exemplified below), your independent

verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.

However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble

cleaning agents for cleaning residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PAA-E

Rev.004

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl₂, H₂S, NH₃, SO₂, and NO₂

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PAA-E

Rev.004


型号：	BU91R64CH-M
厂家：	ROHM
描述：	本产品支持高液晶电压驱动及高帧频率驱动，也可驱动高显示精度的VA液晶。而且，具备显示数据及指令寄存器读取功能，可检测出因噪声导致的误动作。除此之外，还支持MCU通信校验和、玻璃破碎、逻辑电路状态、SEG/COM端子拨动动作的异常检测。使用ITO电阻测量端子，更方便进行COG贴装不良的管理。还支持+105℃动作，符合车载应用要求的AEC-Q 100标准。通信驱动
文件：	总72页 (文件大小：2015K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BU91R64CH-M [ROHM]

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