BU97501KV-E2 [ROHM]
Liquid Crystal Driver,;
| 型号： | BU97501KV-E2 |
| 厂家： | 
ROHM |
| 描述： | Liquid Crystal Driver, 驱动 接口集成电路 |
| 文件： | 总33页 (文件大小：1146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
Multifunction LCD Segment Driver
BU97501KV
MAX 204 segments (51SEG×4COM)
Features
Key Specifications
Key input function for up to 30 keys (A key scan is
performed only when a key is pressed.)
Either 1/4 or 1/3 duty can be selected
1/4 duty drive：Up to 204 segments
1/3 duty drive：Up to 156 segments
Integrated RAM for display data (DDRAM)
Segment/GPO (Max 4port) output mode selectable
Support standby mode
■
■
■
■
■
■
■
Supply Voltage Range:
2.7V to 6.0V
4.5V to 6.0V
-40°C to +85°C
LCD drive power supply Range:
Operating Temperature Range:
Max Segments:
Display Duty:
Bias:
204 Segments
1/3, 1/4 selectable
1/2, 1/3 selectable
Interface:
3wire serial interface
Package
Integrated Power-on Reset circuit
Integrated Oscillator circuit
No external component
VQFP64
W(Typ.)×D(Typ.)×H(Max.)
Low power consumption design
Applications
Telephone
FAX
Portable equipment (POS, ECR, PDA etc.)
DSC
DVC
Car audio
Home electrical appliance
Meter equipment
VQFP64
12.00mm x 12.00mm x 1.60mm
Typical Application Circuit
Key Matrix
(P1)
(General purpose ports)
(P2)
(For use control of backlight)
KI1/S48
(P4)
KS1/S42
|
|
KI5/S52
KS6/S47
VDD
COM1
COM2
COM3
+5V
P1/S1
P2/S2
(Note1)
+5.5V
VLCD
P4/S4
S5
(Note1)
LCD Panel
(Up to 204
Segments)
OSC
RESB
From
Controller
CSB
SCL
SD
S40
COM4/S41
To Controller
DO
(Note1) Insert capacitors between VDD/VLCD and VSS C≥0.1uF.
Figure 1. Typical Application Circuit
○Product structure：Silicon monolithic integrated circuit ○This product is not designed for protection against radioactive rays.
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Block Diagram / Pin Configuration / Pin Description
LCD VOLTAGE
GENERATOR
VLCD
SEGMENT DRIVER & LATCH
49
32
KS5/
S
4
6
S32
COMMON
DRIVER
+
-
KS6/S47
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
KI1/S48
+
-
SHIFT REGISTER
KI2/S49
KI3/S50
KI4/S51
KI5/S52
CLOCK
GENERATOR
OSC
CONTROL
REGISTER
OSC
DO
RESB
DO
CSB
SCL
SD
3-SPI
INTERFACE
KEY BUFFER
SD
SCL
CSB
VDD
VLCD
VDD
VSS
64
17
P.O.R
KEY SCAN
Figure 2. Block Diagram
Figure 3. Pin Configuration (TOP VIEW)
Terminal
No.
Handling When
Terminal
I/O
Functions
Unused
VDD
VSS
VSS
-
CSB
SCL
SD
59
60
61
63
I
I
I
-
Chip select : “L” active
Serial data transfer clock
Input serial data
VDD
Power Supply for the logic
External Clock Input:
Fix to low or open when the internal clock mode setting.
Output data
OSC
DO
56
58
I/O
O
OPEN/VSS
OPEN
Reset Input:
RESB=“L” : Display is disabled.
RESB=“H” : Display is controllable.
RESB
57
I
VDD
However, serial data can not be transferred when RESB is “L”.
VSS
VLCD
64
62
-
-
-
-
Power supply pin. Must be connected to ground.
Power Supply for the LCD driver
COMMON output for LCD driver
COM1~COM3
41 to 43
O
OPEN
COMMON / SEGMENT output for LCD driver.
COM4/S41
44
O
OPEN
Assigned as SEGMENT output in 1/3Duty mode.
SEGMENT output for LCD driving / General Purpose Output
S1/P1～S4/P4 pins can also be used as General Purpose
Outputs when set up by the control data.
S1/P1~S4/P4
S5~S40
1 to 4
O
O
OPEN
OPEN
5 to 40
SEGMENT output for LCD driver
Key scan outputs
Although normal key scan timing lines require diodes to be
inserted in the timing lines to prevent shorts, since these
outputs are unbalanced CMOS transistor outputs, these
outputs will not be damaged by shorting when these outputs
are used to form a key matrix.
KS1/S42~KS6/S47 45 to 50
O
OPEN
The KS1/S42 to KS6/S47 pins can be used as segment
outputs when specified by the control data.
Key scan inputs
These pins have built-in pull-down resistors.
The KI1/S48 to KI5/S52 pins can be used as segment outputs
when specified by the control data.
KI1/S48~KI5/S52
51 to 55
I/O
OPEN
Table 1. Pin Description
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Absolute Maximum Ratings (Ta=25°C, VSS=0.0V)
Parameters
Symbol
Ratings
Unit
Remarks
Power Supply voltage 1
Power Supply voltage 2
Power Dissipation
VDD
VLCD
Pd
-0.5 to +7.0
-0.5 to +7.0
1.00(Note2)
V
V
Power supply
LCD drive voltage
W
V
Input voltage range
VIN
-0.5 to VDD+0.5
Operating temperature
range
Topr
Tstg
-40 to +85
°C
°C
Storage temperature range
-55 to +125
(Note2) When operated higher than Ta=25°C, subtract 10mW per degree. (Using ROHM standard board)
(Board size: 70mm×70mm×1.6mm material: FR4 board copper foil: land pattern only)
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated
over the absolute maximum ratings.
Recommended Operating Conditions
Ratings
Parameters
Symbol
Unit
Remarks
MIN
2.7
TYP
MAX
6.0
Power Supply voltage 1
Power Supply voltage 2
VDD
-
-
V
V
Power supply
LCD driver voltage
VLCD
4.5
6.0
(Note3) The power supply condition shall be met VLCD ≥ VDD.
Electrical Characteristics
(Unless otherwise specified, Ta=-40°C to +85°C, VDD=2.7 to 6.0V, VLCD=4.5 to 6.0V, VSS=0.0V)
Limits
Parameters
“H” Input Voltage
“L” Input Voltage
“H” Input Current
“L” Input Current
Input Floating Voltage
Pull-down Resistance
Symbol
Unit
Conditions
MIN
0.7VDD
VSS
-
-5.0
TYP
-
-
-
-
-
MAX
VIH
VIL
IIH
IIL
VIF
RPD
VDD
0.3VDD
5.0
V
V
µA
µA
V
SD, SCL, CSB, RESB, OSC
SD, SCL, CSB, RESB, OSC
SD, SCL, CSB, RESB, OSC, VI=5.5V
SD, SCL, CSB, RESB, OSC, VI=0.0V
KI1 to KI5
-
-
50
0.05VDD
250
100
kΩ
KI1 to KI5, VLCD=5.0V
Output Off Leakage Current IOFFH
-
-
6.0
µA
DO, Vo=5.5V
VOH1 VLCD-1.0
VOH2 VLCD-1.0
VOH3 VLCD-1.0
VOH4 VLCD-1.0
-
-
-
-
-
-
-
-
-
-
-
-
P1 to P4, Io=-1mA
S1 to S52, Io=-20µA
COM1 to COM4, Io=-100µA
KS1 to KS6, Io=-500µA
P1 to P4, Io=1mA
S1 to S52, Io=20µA
COM1 to COM4, Io=100µA
KS1 to KS6, Io=25µA
DO, Io=1mA
S1 to S52
1/2 Bias, Io=±20µA
COM1 to COM4
1/2 Bias, Io=±100µA
S1 to S52
1/3 Bias, Io=±20µA
S1 to S52
1/3 Bias, Io=±20µA
COM1 to COM4
1/3Bias, Io=±100µA
COM1 to COM4
1/3 Bias, Io=±100µA
Input Pin ALL ”L”
Display off, Disable oscillator
“H” Level Output Voltage
“L” Level Output Voltage
V
-
VOL1
VOL2
VOL3
VOL4
VOL5
-
-
-
-
-
1.0
1.0
1.0
1.0
0.5
V
V
1/2VLCD
-1.0
1/2VLCD
-1.0
2/3VLCD
-1.0
1/3VLCD
-1.0
2/3VLCD
-1.0
1/3VLCD
-1.0
1/2VLCD
+1.0
1/2VLCD
+1.0
2/3VLCD
+1.0
1/3VLCD
+1.0
2/3VLCD
+1.0
1/3VLCD
+1.0
VMID1
VMID2
VMID3
VMID4
VMID5
VMID6
IstVDD
IstVLCD
IVDD1
IVLCD1
IVLCD2
-
-
-
LCD Bias Voltage
-
-
-
-
-
-
-
-
1
1
2
40
65
5
5
Input Pin ALL ”L”
Display off, Disable oscillator
VDD=VLCD=5.0V, Output unloaded
fFR=80Hz
VDD=VLCD=5.0V,Output unloaded
1/2 Bias, fFR=80Hz
VDD=VLCD=5.0V, Output unloaded
1/3 Bias, fFR=80Hz
Current Consumption
10
95
140
µA
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Electrical Characteristics – continued
Oscillation Characteristics (Ta=-40°C to +85°C, VDD=2.7 to 6.0V, VLCD=4.5V to 6.0V, VSS=0.0V)
Limits
Parameters
Symbol
Unit
Conditions
MIN
56
TYP
80
MAX
104
92
Frame Frequency1
Frame Frequency2
fFR1
fFR2
Hz
Hz
VLCD=4.5V to 6.0V, fFR = 80Hz setting
VLCD=5.0V, fFR = 80Hz setting
68
80
External clock mode
(DRV CTRL1 setting : P2P1=11)
External Clock Frequency
fFR3
kHz
30
-
600
Frame frequency is decided external frequency and dividing ratio of DRV CTRL1 setting.
【Reference Data】
100
VDD = 4.0V Setting
90
VLCD = 6.0V
VLCD = 5.0V
80
VLCD = 4.5V
70
60
-40 -20
0
20
40 60
80
Temperature[ ]
℃
Figure 4. Typical temperature characteristics
MPU interface Characteristics (Ta=-40 to +85°C, VDD=2.7V to 6.0V, VLCD=4.5 to 6.0V, VSS=0.0V)
Limits
Parameters
Symbol
Unit
Conditions
MIN
-
TYP
MAX
Input Rise Time
tr
-
-
-
-
-
-
-
-
-
-
-
-
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
Input Fall Time
tf
-
80
SCL Cycle Time
“H” SCL Pulse Width
“L” SCL Pulse Width
SD Setup Time
tSCYC
tSHW
tSLW
tSDS
tSDH
tCSS
tCSH
tCHW
tDC
400
100
100
20
20
50
50
50
-
-
-
-
-
SD Hold Time
-
-
CSB Setup Time
CSB Hold Time
-
“H” CSB Pulse Width
DO Output Delay Time
DO Rise Time
-
1.5
1.5
DO RPU=4.7kΩ, CL=10pF (Note4)
DO RPU=4.7kΩ, CL=10pF (Note4)
tDR
-
(Note4) Since DO can be an open-drain output; these values depend on the resistance of the pull-up resistor RPU and the load capacitance CL.
tCHW
CSB
tCSS
tCSH
tr
tSCYC
tf
tSLW
SCL
tSHW
tSDS
tSDH
SD
DO
tDR
tDC
Figure 5. 3-wire Serial Interface Timing
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I/O equivalent circuit
３
Figure 6. I/O equivalent circuit
Function descriptions
Command and Data Transfer Method
3-SPI (3-wire Serial Interface)
This device is controlled by a 3-wire signal (CSB, SCL, and SD).
First, Interface counter is initialized with CSB=“H"
Setting CSB=”L” enables SD and SCL inputs.
First, Interface counter is initialized with CSB=“H", and then CSB=”L” makes SD and SCL input enable.
The protocol of 3-SPI transfer is shown as follows.
Each command starts with D7 bit as MSB data, followed by D6 to D0 (this is while CSB =”L”).
(Internal data is latched at the rising edge of SCL, then the data is converted to an 8-bit parallel data at the falling edge of
the 8th CLK.)
When you rise CSB = “H”, in case command less than 8bit, command and data are canceled.
(1) Write Mode
Figure 7. 3-SPI Data Transfer Format
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(2) Read Mode (KEY RD command only)
The following occurs when Key Read by KEY RD command.
If KEY RD command is recognized at the rising edge of 8th CLK, it enters Read mode after the falling edge of 8th CLK
and then key data is output through DO.
Setting CSB=”H” can exit Read mode after or during Serial Data Transfer.
Figure 8. Serial Data Output Format
Command Transfer Method
After CSB=”H”→”L”, the 1st byte shall be a command.
Please refer to “Command Table”.
When set command except Data write(DATAWR), the next byte will be (continuously) a command.
When set DATAWR command, the following bytes will be display data bytes.
Command
Command
Command
Command
(DATAWR)
Display Data
…
Once it becomes display data transfer mode, it will not be able to send command.
If you send command again, please rise CSB=”H”.
Display Data Transfer Method
This LSI has Display Data RAM (DDRAM) of 51×4=204bit.
The relationship between data input and display data, DDRAM data and address are as follows.
Command
00001010
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11 D12 D13
…
→ Display Data
Display data will be stored in DDRAM. The address to be written is specified by Address set (ADSET) command and the
address is automatically incremented in every 4bit data if 1/4 Duty mode or in every 3 bit if 1/3 Duty mode respectively.
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1/3 Duty Mode
DDRAM Address/Segment Outputs
...
...
00h
D1
D2
D3
S1
01h
D4
D5
D6
S2
02h
D7
D8
D9
S3
27h
D118
D119
D120
S40
28h
D121
D122
D123
S41
29h
D124
D125
D126
S42
31h
32h
33h
0
1
2
D148 D151
D149 D152
D150 D153
D154 COM1
D155 COM2
D156 COM3
S52
BIT
S50
S51
Transferred data is written to the DDRAM by every 3bits. The write operation is cancelled if it changes CSB=”L”→”H”
before 3bits data transfer.
1/4 Duty Mode
DDRAM Address/ Segment Outputs
...
...
00h
D1
D2
D3
D4
S1
01h
D5
D6
D7
D8
S2
02h
D9
27h
D157
D158
D159
D160
S40
28h
D161
D162
D163
D164
S42
29h
D165
D166
D167
D168
S43
30h
31h
32h
0
1
2
3
D193 D197
D194 D198
D195 D199
D196 D200
D201 COM1
D202 COM2
D203 COM3
D204 COM4
S52
D10
D11
D12
S3
BIT
S50
S51
Transferred Data is written to the DDRAM by every 4bits. The write operation is cancelled if it changes CSB=”L”→”H”
before 4bits data transfer.
Relationship between Display Data and Segment Output Pins
1/3 Duty Mode
output
terminal
output
terminal
COM1
COM2
COM3
Address
COM1
COM2
COM3
address
S1/P1
S2/P2
S3/P3
S4/P4
S5
D1
D2
D3
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
S27
S28
D79
D82
D80
D83
D81
D84
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
D4
D5
D6
D7
D8
D9
S29
D85
D86
D87
D10
D13
D16
D19
D22
D25
D28
D31
D34
D37
D40
D43
D46
D49
D52
D55
D58
D61
D64
D67
D70
D73
D76
D11
D14
D17
D20
D23
D26
D29
D32
D35
D38
D41
D44
D47
D50
D53
D56
D59
D62
D65
D68
D71
D74
D77
D12
D15
D18
D21
D24
D27
D30
D33
D36
D39
D42
D45
D48
D51
D54
D57
D60
D63
D66
D69
D72
D75
D78
S30
D88
D89
D90
S31
D91
D92
D93
S6
S32
D94
D95
D96
S7
S33
D97
D98
D99
S8
S34
D100
D103
D106
D109
D112
D115
D118
D121
D124
D127
D130
D133
D136
D139
D142
D145
D148
D151
D154
D101
D104
D107
D110
D113
D116
D119
D122
D125
D128
D131
D134
D137
D140
D143
D146
D149
D152
D155
D102
D105
D108
D111
D114
D117
D120
D123
D126
D129
D132
D135
D138
D141
D144
D147
D150
D153
D156
S9
S35
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S36
S37
S38
S39
S40
COM4/S41
KS1/S42
KS2/S43
KS3/S44
KS4/S45
KS5/S46
KS6/S47
KI1/S48
KI2/S49
KI3/S50
KI4/S51
KI5/S52
(Note5) In case of S1/P1~S4/P4, COM4/S41, KS1/S42~KS6/S47 and KI1/S48~KI5/S52 are selected for segment output.
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For example, S11 output case
Bits in a DDRAM
Segment Output Pin (S11)
D31
0
D32
0
D33
0
Off-state of the LCD elements corresponding to COM1, 2 and 3
On-state of the LCD element corresponding to COM3
On-state of the LCD element corresponding to COM2
On-state of the LCD elements corresponding to COM2 and 3
On-state of the LCD element corresponding to COM1
On-state of the LCD elements corresponding to COM1 and 3
On-state of the LCD elements corresponding to COM1 and 2
On-state of the LCD elements corresponding to COM1, 2 and 3
0
0
1
1
0
0
1
1
1
0
0
0
1
1
0
1
1
1
0
1
1
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1/4 duty
output
terminal
output
terminal
COM1 COM2 COM3 COM4 Address
COM1 COM2 COM3 COM4 address
S1/P1
S2/P2
S3/P3
S4/P4
S5
D1
D2
D3
D4
D8
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
S27
S28
D105 D106 D107 D108
D109 D110 D111 D112
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
D5
D6
D7
D9
D10
D14
D18
D22
D26
D30
D34
D38
D42
D46
D50
D54
D58
D62
D66
D70
D74
D78
D82
D86
D90
D94
D98
D11
D15
D19
D23
D27
D31
D35
D39
D43
D47
D51
D55
D59
D63
D67
D71
D75
D79
D83
D87
D91
D95
D99
D12
D16
D20
D24
D28
D32
D36
D40
D44
D48
D52
D56
D60
D64
D68
D72
D76
D80
D84
D88
D92
D96
D100
S29
D113 D114 D115 D116
D117 D118 D119 D120
D121 D122 D123 D124
D125 D126 D127 D128
D129 D130 D131 D132
D133 D134 D135 D136
D137 D138 D139 D140
D141 D142 D143 D144
D145 D146 D147 D148
D149 D150 D151 D152
D153 D154 D155 D156
D157 D158 D159 D160
D161 D162 D163 D164
D165 D166 D167 D168
D169 D170 D171 D172
D173 D174 D175 D176
D177 D178 D179 D180
D181 D182 D183 D184
D185 D186 D187 D188
D189 D190 D191 D192
D193 D194 D195 D196
D197 D198 D199 D200
D201 D202 D203 D204
D13
D17
D21
D25
D29
D33
D37
D41
D45
D49
D53
D57
D61
D65
D69
D73
D77
D81
D85
D89
D93
D97
S30
S31
S6
S32
S7
S33
S8
S34
S9
S35
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S36
S37
S38
S39
S40
KS1/S42
KS2/S43
KS3/S44
KS4/S45
KS5/S46
KS6/S47
KI1/S48
KI2/S49
KI3/S50
KI4/S51
KI5/S52
D101 D102 D103 D104
(Note6) In case of S1/P1~S4/P4, KS1/S42~KS6/S47 and KI1/S48~KI5/S52 are selected for segment output.
For example, S11 output case
Bits in the DDRAM
Segment Output Pin (S11)
D41
0
D42
0
D43
0
D44
0
Off-state of the LCD elements corresponding to COM1,2 ,3 and4
On-state of the LCD element corresponding to COM4
0
0
0
1
0
0
1
0
On-state of the LCD element corresponding to COM3
0
0
1
1
On-state of the LCD elements corresponding to COM3 and 4
On-state of the LCD element corresponding to COM2
0
1
0
0
0
1
0
1
On-state of the LCD elements corresponding to COM2 and 4
On-state of the LCD elements corresponding to COM2 and 3
On-state of the LCD elements corresponding to COM2,3 and 4
On-state of the LCD element corresponding to COM1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
On-state of the LCD elements corresponding to COM1 and 4
On-state of the LCD elements corresponding to COM1 and 3
On-state of the LCD elements corresponding to COM1, 3 and 4
On-state of the LCD elements corresponding to COM1 and 2
On-state of the LCD elements corresponding to COM1,2 and 4
On-state of the LCD elements corresponding to COM1,2 and 3
On-state of the LCD elements corresponding to COM1,2 3 and 4
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
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Serial Data Output
Figure 9. Serial Data Output
KD1 to KD30: Key Data
SA: Sleep Acknowledge Data
Key Data Read Command (KEY RD): 1000_0101
(Note7) If a key data operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data(SA) will be invalid.
Output Data
KD1 to KD30: Key Data
When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and one of
those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship
between those pins and the key data bits.
KI1
KI2
KI3
KI4
KI5
KS1
KS2
KS3
KS4
KS5
KS6
KD1
KD2
KD3
KD4
KD5
KD6
KD7
KD8
KD9
KD10
KD15
KD20
KD25
KD30
KD11
KD16
KD21
KD26
KD12
KD17
KD22
KD27
KD13
KD18
KD23
KD28
KD14
KD19
KD24
KD29
SA: Sleep Acknowledge Data
This output data is used to set the state when the key is pressed. In this case, DO will go to the low level. If serial data is
input during this period and the mode is set (normal mode or sleep mode), the IC will be set to that mode. SA is set to 0
in the sleep mode and to 1 in the normal mode.
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Key Scan Operation
Key Scan Timing
The key scan period is 288T(s). To reliably determine the on/off state of the keys, the BU97501KV scans the keys twice
and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low level on
DO) 615T(s) after starting a key scan. If the key data does not agree and a key is pressed at that point, it scans the keys
again. Thus, BU97501KV cannot detect a key press shorter than 615T(s).
*
*
*
*
*
1
1
KS1
KS2
KS3
KS4
KS5
KS6
2
2
3
3
4
4
5
5
6
6
576 T[S]
1
fosc
T=
Figure 10. Key Scan Timing
Normal Mode
KS1/S42 - KS6/S47 pins are set high.
When a key is pressed, a key scan is started and the keys are scanned until all keys are released. Multiple key presses
are recognized by determining whether multiple key data bits are set.
If a key is pressed for longer than 615 T(s) (Where T=1/fosc (When External clock input, fosc is a quarter of external
clock)), the BU97501KV outputs a key data read request (a low level on DO) to the controller. The controller
acknowledges this request and reads the key data. However, if CSB is ”L” during a serial data transfer, DO will be set
high.
After the controller reads the key data, the key data read request is cleared (DO is set high) and BU97501KV performs
another key scan. Also note that DO can be controlled to be an open-drain output or a CMOS output. If set to be an
open-drain output, a pull-up resistor (between 1 and 10KΩ) is required.
Figure 11. Key scan operation in normal mode
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Sleep Mode
KS1/S42 - KS6/S47 pins are set high or low by SLP CTRL P3,P2 data. (Refer to the SLP CTRL description).
If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the OSC pin
is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses are recognized
by determining whether multiple key data bits are set.
If a key is pressed for longer than 615T(s)(Where T=1/fosc (When External clock input, fosc is a quarter of external
clock)) the BU97501KV outputs a key data read request (a low level on DO) to the controller. The controller
acknowledges this request and reads the key data. However, if CSB is ”L” during a serial data transfer, DO will be set
high.
After the controller reads the key data, the key data read request is cleared (DO is set high) and the BU97501KV
performs another key scan. However, this does not clear sleep mode. Also note that DO can be controlled to be an
open-drain output or a CMOS output. During open-drain output selection, DO is an open-drain output so a pull-up
resistor (between 1 KΩ and 10KΩ) is required.
Sleep mode key scan example
Example: when SLP CTRL P3= [0], P2= [1] (sleep with only KS6 high)
(Note8) These diodes are required to reliably recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the
above example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to
KS5 lines are pressed at the same time.
Figure 12. Key scan operation in sleep mode
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Multiple Key Presses
Although the BU97501KV is capable of key scanning without inserting diodes for dual key presses, triple key presses on
the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than
these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be
inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should
check the key data for three or more 1 bit and ignore such data.
OSCILLATOR
Several kinds of clock for logic and analog circuits are generated from internal oscillation circuit or external clock.
The OSC pins are open if the internal oscillator is used.
(Note9) To use external clock mode, please set in DRV CTRL1 command.
Clock Input
OSC
VSS
OSC
OPEN
BU97501KV
BU97501KV
Figure 13. Internal clock mode
Figure 14. External clock mode
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LCD Driver Bias/Duty Circuit
This LSI generates LCD driving voltage with on-chip Buffer AMP.
And it can drive LCD at low power consumption.
* 1/3 or 1/2Bias and line or frame inversion mode can be selected by DRV CTRL2.
* 1/4 or 1/3Duty can be selected by DRV CTRL1 command.
Refer to “LCD waveform” about each LCD waveform.
LCD waveform
1/4duty, 1/3bias
Line inversion
Frame inversion
Figure 15. LCD waveform in line inversion
Figure 16. LCD waveform in frame inversion
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1/4duty, 1/2bias
Line inversion
Frame inversion
Figure 17. LCD waveform in line inversion
Figure 18. LCD waveform in frame inversion
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1/3duty, 1/3bias
Line inversion
Frame inversion
Figure 19. LCD waveform in line inversion
Figure 20. LCD waveform in frame inversion
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1/3duty, 1/2bias
Line inversion
Frame inversion
Figure 21. LCD waveform in line inversion
Figure 22. LCD waveform in frame inversion
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Command Table
BIN
Command.
Descriptions
D7 D6 D5 D4 D3 D2 D1 D0
SLP CTRL
SEG CTRL
DRV CTRL1
DRV CTRL2
DRV CTRL3
KEY RD
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
0
0
1
0
0
1
0
1
1
1
1
0
1
0
0
1
1
P3 P2
*
*
*
Sleep Control
P3 P2 P1
P3 P2 P1
Segment Control
0
0
Drive Control1 （Duty Set, OSC Control）
Drive Control2 （Bias Set, Inversion Mode）
0
P2 P1
P3 P2
*
0
P0 Drive Control3 （Keyscan Output Set, DO Set）
0
0
1
1
0
0
1
1
*
Key Data Read
SWRST
0
Software Reset
DISCTRL
ADSET
P1
Display Control （Display On/Off）
P5 P4 P3 P2 P1 P0 Address Set
DATA WR
0
0
1
0
1
0
Data Write
(* : Don’t care)
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Detailed command description
Sleep Control (SLP CTRL)
MSB
LSB
D0
D7
1
D6
0
D5
0
D4
1
D3
P3
D2
P2
D1
*
*
(* : Don’t care)
P3, P2: Normal mode/Sleep mode switching control data
These control data bits select Key Scan Output Pins KS1 to KS6 States of during Key Scan Standby.
Control
bits
Output Pin States During Key Scan
Standby
KS1 KS2 KS3 KS4 KS5 KS6
Reset
Conditions
Segment
outputs/Common
Outputs
Internal
OSC
Mode
P3
P2
0
0
0
1
1
Normal
Sleep
Sleep
Sleep
enabled
disabled
Operating
H
L
H
L
L
H
L
L
H
L
L
H
L
H
H
H
H
H
H
1
○
0
Low(VSS)
L
1
H
H
H
H
（Note10）When DRV CTRL3（P3, P2）=（1, 1）, KS1 to KS6 outputs are selected as Segment outputs.
Segment Control (SEG CTRL)
MSB
D7
LSB
D0
D6
0
D5
1
D4
1
D3
P3
D2
P2
D1
P1
1
*
(* : Don’t care)
P3 to P1 : Segment Output / General purpose output switching control data
These control bits select the function of the S1/P1 to S4/P4 output pins.
(Segment Output Pins or General Purpose Output Pins).
Reset
Control bits
Status of the pins
conditions
P3
0
P2
0
P1
0
S1/P1 S2/P2 S3/P3 S4/P4
S1
P1
P1
P1
P1
S2
S2
P2
P2
P2
S3
S3
S3
P3
P3
S4
S4
S4
S4
P4
○
0
0
1
0
1
0
0
1
1
1
0
0
(Note11) Sn(n=1 to 4)
Pn(n=1 to 4)
:
:
assigned as a Segment Output pin
assigned as a General Purpose Output pin
Relationship of bit assignment between general purpose output pin and bit in DDRAM
Corresponding bit in DDRAM
Output Pin
1/3 Duty
1/4 Duty
S1/P1
S2/P2
S3/P3
S4/P4
D1
D4
D1
D5
D7
D9
D10
D13
In case of 1/4 Duty mode and S4/P4 is configured as a general purpose output pins.
S4/P4 is set to HIGH (VLCD level) if D13 is set to “1” in DDRAM.
S4/P4 is cleared to LOW (VSS level) if D13 is set to “0” in DDRAM.
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Drive Control1 (DRV CTRL1)
MSB
D7
LSB
D0
D6
1
D5
0
D4
0
D3
P3
D2
P2
D1
P1
1
0
P3: 1/3 duty drive or 1/4 duty drive switching control data
This control data bit selects either 1/3 duty drive or 1/4 duty drive.
Reset
conditions
Status of (COM4/
S41)
P3
Duty mode
0
1
1/4
1/3
COM4
S41
○
(Note12) COM4: COMMON output
S41: SEGMENT output
P2,P1 : Frame frequency switching control data
These control data bits select Frame frequency setting.
Reset
Setting
P2
P1
conditions
80Hz
100Hz
120Hz
0
0
1
0
1
0
○
External Clock
input
1
1
Relationships between Frame frequency (fFR) and Divide number
Divide number
fFR [Hz]
P2
P1
1/3 Duty
1/4 Duty
512
1/3 Duty
1/4 Duty
0
0
1
1
0
1
0
1
510
408
80
100
120
-
80
100
120
-
408
342
344
2040
2048
Formula to calculate Frame frequency from frequency and Divide number:
“Frame frequency = frequency / Divide number”
Ex) In case, 1/4 Duty mode,(P2,P1) = (0,0)
fFR = 40.96[KHz] / 512 = 80[Hz]
(Note13) Built-in Oscillator circuit frequency = 40.96 KHz (typ).
Drive Control2 (DRV CTRL2)
MSB
D7
LSB
D0
D6
1
D5
0
D4
1
D3
0
D2
P2
D1
P1
1
0
P2: 1/3 bias drive or 1/2 bias drive switching control data
This control data bit selects either 1/3 bias drive or 1/2 bias drive.
Reset
P2
Bias mode
conditions
0
1
1/2
1/3
○
P1: Line Inversion or Frame Inversion switching control data
This control data bit selects either line inversion drive or frame inversion drive.
Inversion
mode
Reset
conditions
P1
0
1
Line
○
Frame
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Drive Control3 (DRV CTRL3)
MSB
D7
LSB
D0
D6
0
D5
1
D4
0
D3
P3
D2
P2
D1
*
1
P0
(* : Don’t care)
P3 to P2: Key Scan output port/Segment output port switching control data
These control data bits select Key Scan outputs or Segment outputs.
Control
Output Pin State
Bits
Maximum
Number of
Input keys
Reset
Conditions
KS1/
S42
KS2/
S43
KS3/
S44
KS4/
S45
KS5/
S46
KS5
KS6/
S47
KS6
P3
0
P2
0
KS1
KS2
KS3
KS4
30
0
1
1
1
0
1
S42
S42
S42
KS2
S43
S43
KS3
KS3
S44
KS4
KS4
S45
KS5
KS5
S46
KS6
KS6
S47
25
20
0
○
When (P3,P2)=(1,1), Keyscan doesn't function. Key scan pins are all segment outputs.
Thus, maximum segment display number and RAM last address change based on this value.
Control
Bits
Maximum Segment
Display Number
Status of Pins
Last Address
KS1/
S42
KS1
S42
S42
S42
KS2/
S43
KS2
KS2
S43
S43
KS3/
S44
KS3
KS3
KS3
S44
KS4/
S45
KS4
KS4
KS4
S45
KS5/
S46
KS5
KS5
KS5
S46
KS6/
S47
KS6
KS6
KS6
S47
P3
P2
1/3 Duty 1/4 Duty 1/3 Duty 1/4 Duty
0
0
1
1
0
1
0
1
123
126
129
156
160
164
168
204
28h
29h
2Ah
33h
27h
28h
29h
32h
P0: Output setting for DO
This control data bit selects either open drain output or CMOS output.
Reset
Conditions
P0
Setting
0
1
open drain output
CMOS output
○
Pull up resistor (1kꢀ - 10kꢀ) is required when selecting Open Drain Output setting for DO.
Be careful the Pull up voltage not to be higher than VDD voltage.
Key Data Read (KEY RD)
MSB
D7
LSB
D0
D6
0
D5
0
D4
0
D3
0
D2
1
D1
0
1
1
Display Control (DISCTRL)
MSB
LSB
D0
*
D7
1
D6
1
D5
1
D4
1
D3
1
D2
0
D1
P1
(* : Don’t care)
P1: Segment on/off control data
This control data bit controls the on/off state of the segments.
Reset
conditions
Display status
P1
1
ON
0
OFF
○
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Software Reset (SWRST)
MSB
D7
LSB
D0
D6
1
D5
1
D4
1
D3
0
D2
0
D1
0
1
1
This is the Software Reset command.
After sending this command, each register, DDRAM data and DDRAM address are initialized.
Address Set (ADSET)
MSB
D7
LSB
D0
D6
1
D5
P5
D4
P4
D3
P3
D2
P2
D1
P1
0
P0
Address which could be set starts from 00(Hex) until RAM last address.
Setting of values other than the above is not allowed. (Otherwise, address is set to 0.)
Refer to “Display Data Transfer Method” for RAM last address.
Data Write (DATAWR)
MSB
D7
LSB
D0
D6
0
D5
0
D4
0
D3
1
D2
0
D1
1
0
0
Data transfer can be started by this command.
Set the CSB pin to High to terminate the data transfer.
Refer to “Command and Data Transfer Method”.
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Initialize sequence
Recommended sequence after Power-On to set this device to initial condition.
Software reset sequence
Hardware reset sequence
Power on
Power on
↓
↓
CSB ‘H’ …Initialized I/F
RESB ‘L’
↓
↓
CSB ‘L’ …Start transferring I/F Data
RESB ‘H’
↓
↓
SWRST (execute Software Reset)
CSB ‘H’ …Initialized I/F
↓
↓
DISCTRL (Display off)
CSB ‘L’ …Start transferring I/F Data
↓
↓
Set each Command
SWRST (execute Software Reset)
↓
↓
DATA WR
DISCTRL (Display off)
↓
↓
CSB ‘H’
Set each Command
↓
↓
CSB ‘L’
DATA WR
↓
↓
SLP CTRL
CSB ‘H’
↓
↓
DISCTRL (Display on)
CSB ‘L’
↓
↓
Start display
SLP CTRL
↓
DISCTRL (Display on)
↓
Start display
(Note14) Each register value, DDRAM address and DDRAM data are random condition after power on till initialize sequence is executed.
(Note15) Each register value, DDRAM address are reset by a hardware reset operation.
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Cautions in Power-On Sequence
Power-On Reset (POR) Circuit
This LSI has “P.O.R” (Power-On Reset) circuit and Software Reset function.
When the power is ON, IC internal circuit and reset pass through unstable low-voltage region.
Internal IC is not totally reset because VDD rises and this may result to malfunction.
Thus, POR circuit and function of software reset are installed in order to prevent this.
Please follow the following recommended Power-On sequences to allow the reset action to complete.
Set the power up conditions to meet the recommended tR, tF, tOFF, and Vbot spec below in order to ensure
P.O.R operation.
tR
tF
tR, tF, tOFF, Vbot recommended conditions
VDD
tR
tF
tOFF
Vbot
Less than
5ms
Less than
5ms
More than
150ms
Less than
0.1V
tOFF
Vbot
Figure 23. Power ON/OFF waveform
If it is difficult to meet above conditions, execute the following sequence after Power-On.
(1)
(2)
Set CSB to High
Clear CSB to Low and then issue a SWRST command.
VDD
CSB
Min 1ms
Min 50ns
SWRST
Command
Figure 24. SWRST Command Sequence
Power Up Sequence and Power Down Sequence
To prevent incorrect display, malfunction and abnormal current,
VDD must be turned on before VLCD In power up sequence.
VDD must be turned off after VLCD In power down sequence.
Please satisfies VLCD≥VDD, t1>0ns, t2>0ns
t2
t1
VLCD
10%
10%
VDD min
VDD min
VDD
Figure 25. Power On/Off Sequence
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DISPLAY DDRAM DATA EXAMPLE
If LCD layout pattern is shown as in Figure 26 and 27 and DDRAM data is shown as in Table2, display
pattern will be shown as in Figure 28.
com1
com2
com3
com4
Figure 26. Example COM Line pattern
S6
S5
S1
S8
S3
S4
S2
Figure 27. Example of SEG Line pattern
Figure 28. Example of display pattern
S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
8
S
9
S
S
S
S
S
S
S
S
S
S
S
10 11 12 13 14 15 16 17 18 19 20
COM1
COM2
COM3
D0
D1
D2
D3
1
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
1
0
1
0
1
0
0
0
1
1
0
1
0
0
1
0
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
COM4
Address
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h
Table 2. DDRAM Data map
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Operational Notes
1.
2.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply terminals.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
4.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Thermal Consideration
Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in
deterioration of the properties of the chip. The absolute maximum rating of the Pd stated in this specification is when
the IC is mounted on a 70mm x 70mm x 1.6mm glass epoxy board. In case of exceeding this absolute maximum
rating, increase the board size and copper area to prevent exceeding the Pd rating.
6.
7.
Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately
obtained. The electrical characteristics are guaranteed under the conditions of each parameter.
Rush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush
current may flow instantaneously due to the internal powering sequence and delays, especially if the IC
has more than one power supply. Therefore, give special consideration to power coupling capacitance,
power wiring, width of ground wiring, and routing of connections.
8.
9.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
10. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)
and unintentional solder bridge deposited in between pins during assembly to name a few.
11. Unused Input Terminals
Input terminals of an IC are often connected to the gate of a MOS transistor (CMOS?). The gate has extremely high
impedance and extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it.
The small charge acquired in this way is enough to produce a significant effect on the conduction through the
transistor and cause unexpected operation of the IC. So unless otherwise specified, unused input terminals should be
connected to the power supply or ground line.
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12. Regarding the Input Pin of the IC
In the construction of this IC, P-N junctions are inevitably formed creating parasitic diodes or transistors. The
operation of these parasitic elements can result in mutual interference among circuits, operational faults, or physical
damage. Therefore, conditions which cause these parasitic elements to operate, such as applying a voltage to an
input pin lower than the ground voltage should be avoided. Furthermore, do not apply a voltage to the input terminals
when no power supply voltage is applied to the IC. Even if the power supply voltage is applied, make sure that the
input terminals have voltages within the values specified in the electrical characteristics of this IC.
13. Ceramic Capacitor
When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
14. Area of Safe Operation (ASO)
Operate the IC such that the output voltage, output current, and power dissipation are all within the Area of Safe
Operation (ASO).
15. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls below
the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
16. Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
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Ordering Information
B
U
9
7
5
0
1
K
V
-
E 2
Package
Part Number
Packaging and forming specification
E2: Embossed tape and reel
(VQFP64)
KV : VQFP64
Marking Diagram(s)
VQFP64 (TOP VIEW)
Part Number Marking
LOT Number
B U 9 7 5 0 1 K V
1PIN MARK
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Physical Dimension, Tape and Reel Information
Package Name
VQFP64
1 PIN MARK
（UNIT：mm）
PKG：VQFP64
Drawing: EX252-5001-1
<Tape and Reel information>
Tape
Embossed carrier tape (with dry pack)
Quantity
1000pcs
E2
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
(
)
Direction of feed
1pin
Reel
Order quantity needs to be multiple of the minimum quantity.
∗
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Version / Revision History
Version
001
002
date
07. Aug. 2013 1st ver
07. Nov. 2013 Page.4 Add Electrical Characteristics of External Clock Frequency
description
Page.2 Modify Pin Description OSC, DO, RESB, VSS and S1/P1～S4/P4 Functions
Page.3 Modify Absolute Maximum Ratings Power Dissipation
Page.3 Modify Electrical Characteristics precondition
Page.3 Modify Electrical Characteristics LCD Bias Voltage VMID1 Conditions
Page.4 Modify Electrical Characteristics External Clock Frequency Symbol
Page.4 Add Typical temperature characteristics VDD condition
Page.4 Modify MPU Interface Characteristics tCHW Parameter name
Page.4 Modify Figure 5 Title
Page.5 Modify I/O equivalent circuit
Page.5-6 Modify Command and Data Transfer Method description
Page.6 Modify Command Transfer Method description
Page.6 Modify Display Data Transfer Method description
Page.10 Modify Serial Data Output description
Page.10 Modify Output Data description
Page.11-12 Modify Key Scan Operation description
Page.14-17 Modify LCD Driver Bias/Duty Circuit figure
Page.18 Modify Table name
Page.19 Minor translation change Sleep Control command description to have more
conformity between Japanese and English version
003
31. Jan. 2014
Page.19 Minor translation change Segment Control command description to have
more conformity between Japanese and English version
Page.20 Minor translation change Drive Control1 command description to have more
conformity between Japanese and English version
Page.20 Minor translation change Drive Control2 command description to have more
conformity between Japanese and English version
Page.21 Add Drive Control3 command description
Page.21 Minor translation change Drive Control3 command description to have more
conformity between Japanese and English version
Page.22 Minor translation change Software command description to have more
conformity between Japanese and English version
Page.22 Delete Address Set command description
Page.22 Minor translation change Address command description to have more
conformity between Japanese and English version
Page.22 Modify Data Write command description
Page.23 Add Initialize sequence Note14, Note15
Page.29 Add Physical Dimension, Tape and Reel Information description
Page.11 Add fosc explanation when External clock input
Page.12 Add fosc explanation when External clock input
Page.24 Add the condition when power up and power down
004
005
11.Apr.2014
20. Jan. 2015 Page.24 Add the condition when power up and power down
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Notice
Precaution on using ROHM Products
1. Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PGA-E
Rev.002
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Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PGA-E
Rev.002
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General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall not be in an y way responsible or liable for failure, malfunction or accident arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3. The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
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