ML5243_技术文档

FEDL5243_001-04

1. December, 2020

ML5243-001

5-Series Cell Li-ion Rechargeable Battery Protection IC

■ General Description

The ML5243 is a protection IC for the 5-cell Li-ion rechargeable battery pack. It detects individual cell

overvoltage/undervoltage and the pack overcurrent/over-temperature, and its output signal indicates

charge/discharge enable. And it has open-wire detection function of battery connection wire.

■ Features

• 3 to 5 cell high-precision overvoltage and undervoltage detection function

Voltage detecting function for individual cells

Overvoltage detection threshold

2^ndovervoltage detection threshold

Undervoltage detection threshold

4.225 V, Detection accuracy: ±25 mV (0 to 60°C)

4.325V,

2.0 V,

Detection accuracy: ±35 mV (0 to 60°C)

Detection accuracy: ±50 mV (0 to 60°C)

• Overcurrent detection function

Discharge overcurrent detection threshold

Charge overcurrent detection threshold

Short circuit detection threshold

70 mV,

-30 mV,

Detection accuracy: ±15 mV (0 to 60°C)

300 mV, Detection accuracy: ±20 mV (0 to 60°C)

• Temperature detection function

: With external NTC (10 k, B=3435) and 4.7 k resistor

Discharge inhibition temperature: detection 70 °C or higher, release 65 °C or lower

Charge inhibition temperature : detection -5 °C or lower/50°C or higher, release 0 °C or higher/45°C

or lower

• Detection delay timer built-in

Overvoltage/undervoltage detection delay time : 2sec

2^ndovervoltage detection delay time

Open-wire detection delay time

: 8sec

: 3.6sec

TEST MODE reduces each detection delay time as 0.1sec by controlling the TEST pin input.

• Three type of charge/discharge enable signal output/

Selected from CMOS / Nch open drain / Pch open drain (high voltage tolerant output)

• Detection voltages and detection delay times are modified by product code.

• Low current consumption (-40 to 85°C)

Normal operation state : 4.5 µA (typ.), 10 µA (max)

Power-down state

: 0.1 µA (typ.), 1.0 µA (max)

• Supply voltage

: +5 V to +25 V

• Operating temperature

• Package

: -40°C to +85°C

: 20-pin TSSOP

Note) This product is not intended for automotive use and for any equipment, device, or system that requires a

specific quality or high level of reliability (e.g., medical equipment, transportation equipment, aerospace

machinery, nuclear-reactor controller, fuel-controller, various safety devices). If you are not sure whether

your application corresponds to such special purposes, please contact your local ROHM sales

representative in advance.

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■ Block Diagram

VDD

Voltage

Regulator

VREG

VNTC

V5

V4

Clock

Generator

Thermistor

Driver

Cell Voltage

Detector

Temperature

Detector

TSNS

V3

TEST

V2

V1

CS1

CS0

Reference

Voltage

Generator

Control Logic

&

Delay Timer

PF

CHG

DCHG

GND

Current

Detector

Charger/Load

Detector

VRSNS

ISENSE

■ Pin Configuration (top view)

1

2

3

4

5

6

20

19

18

17

VDD

V5

VREG

CS1

V4

CS0

V3

VNTC

V2

16 TSNS

15 TEST

V1

GND 7

ISENSE 8

N.C. 9

14

13

12

11

GND

PF

VRSNS

CHG

DCHG

10

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■ Pin Description

Pin No. Pin name I/O

Description

Power supply input pin.

Connect an external CR filter for noise rejection.

1

VDD

—

Battery cell 5 high voltage input pin.

2

3

4

5

6

7

V5

V4

I

Battery cell 5 low voltage input and Battery cell 4 high voltage input pin.

Battery cell 4 low voltage input and Battery cell 3 high voltage input pin.

Battery cell 3 low voltage input and Battery cell 2 high voltage input pin.

Battery cell 2 low voltage input and Battery cell 1 high voltage input pin.

Ground pin.

V3

V2

V1

GND

Current sense resistor input pin. Connect a resistor of the resistance value corresponding

to the detecting current between this pin and the GND pin. Should be tied to GND if not

used.

8

9

ISENSE

N.C.

I

No connected. Connect to GND or Leave it electrically unconnected.

Discharge enable pin.

Output type is selected from CMOS / NMOS open drain / PMOS open drain. And its

asserted level is selected from “L” level/”H” level.

10

DCHG

O

Charge enable pin.

Output type is selected from CMOS / NMOS open drain / PMOS open drain. And its

asserted level is selected from “L” level/”H” level.

11

12

CHG

O

Load/charger connection detecting input pin. Load or charger presence is decided by this

input level.

VRSNS

IO

2^ndovervoltage alarm output. Output type is selected from CMOS / NMOS open drain /

PMOS open drain. And its asserted level is selected from “L” level/”H” level.

13

14

PF

O

Ground pin.

GND

—

Detection delay time reduced test input pin.

Every detection delay time is reduced by setting the voltage of this pin as VREG pin level.

Internal 10k pull-down resistor is connected.

15

TEST

I

Input pin for high/low temperature charge/discharge inhibition detection. Connect a

thermistor between this pin and GND. Should be tied to the VNTC pin through 10k

resistor if not used.

Thermistor power supply. Should be connected to TSNS through a 4.7 k resistor.

If not used, this 4.7 k resistor should be connected.

16

17

TSNS

VNTC

I

O

Pins to specify battery cell number. Either the VREG or the GND level should be applied.

CS1

CS0

Number of connected

Battery cells

5 cell

18,19 CS0,CS1 IO

GND

VREG

4 cell

VREG

GND / VREG

3 cell

Built-in 3.3 V regulator output pin. Should be tied to GND through a 1 F or larger

capacitor. Do not use this pin as power supply for an external circuit.

20

VREG

O

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■ Absolute Maximum Ratings

GND=0V, Ta=25°C

Item

Symbol

V_DD

Condition

Applied to VDD pin

Rating

Unit

Supply voltage

-0.3 to +50

V

V_IN1

Applied to V1 to V5 pins

Applied to VRSNS pin

-0.3 to V_DD+0.3

V

V_IN2

V_DD-50 to V_DD+0.3

Input voltage

Applied to CS0, CS1, ISENSE,

TSNS pins

V_IN3

V_IN5

-0.3 to V_REG+0.3

-0.3 to +4.8

V

Applied to TEST pin

Applied to DCHG, CHG, PF pins,

if output type is CMOS.

Applied to PF pin if output type is

PMOS open drain

V_OUT1

-0.3 to V_DD+0.3

V

Applied to DCHG, CHG, PF pins,

if output type is NMOS open drain.

V_OUT2

-0.3 to +50

Output voltage

Applied to DCHG, CHG pins, if

output type is PMOS open drain.

V_OUT3

V_DD-50 to V_DD+0.3

V

V_OUT4

V_OUT5

Applied to VREG pin

Applied to VNTC pin.

-0.3 to +4.8

V

-0.3 to V_REG+0.3

Power

dissipation

P_D

I_OS

—

1.0

10

W

mA

°C

Short-circuit

output current

Applied to DCHG, CHG, PF,

VNTC pins

Storage

temperature

T_STG

—

-55 to +150

■ Recommended Operating Conditions

(GND= 0 V)

Item

Symbol

V_DD

Condition

Applied to VDD pin

—

Range

5 to 25

Unit

V

Supply voltage

Operational temperature

T_OP

-40 to +85

°C

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■ Electrical Characteristics

⚫

DC Characteristics

V_DD=5 V to 25 V, GND=0 V, Ta=-40 to +85°C

Item

Symbol

V_IH

Condition

—

Min.

Typ.

—

Max.

V_REG

V_REG×0.2

2

Unit

V

Digital "H" input voltage (Note 1)

Digital "L" input voltage (Note 1)

Digital "H" input current (Note 2)

Digital "L" input current (Note 1)

Digital "H" input current (Note 3)

V_REG×0.8

V_IL

—

0

—

V

I_IH

V_IH= V_REG

V_IL= GND

V_IH= 3V

—

µA

I_IL

–2

150

—

I_IHT

300

600

normal operation

mode,

I_INVC1

–0.5

0.1

0.5

µA

Cell monitoring pin V5 to V1

Input current

I_INVC2

V_OL

power-down mode

I_OL= 100 µA

I_OH=-100 µA

–0.5

0

0.0

—

0.5

0.2

V_DD

µA

V

"L" output voltage (Note 4)

"H" output voltage (Note 4)

Pch open-drain

output leakage current (Note 4)

Nch open-drain

V_OH

V_DD-0.2

—

V

I_LKP

V_O=0 V to V_DD

Vo = 0 V to V_DD

2

—

2

µA

I_LKN

V_REG

V_NTC

2

—

2

µA

V

output leakage current (Note 4)

VREG pin output voltage

With no load

With 14.7 kΩ resistor

connection

3.0

2.2

3.3

2.4

3.7

2.6

VNTC pin output voltage

V

Charge overcurrent

detected,

VRSNS pin pull-up resistor

R_VRU

0.2

0.5

1.5



Power-down mode

Discharge overcurrent

detected,

VRSNS pin pull-down resistor

R_VRD

1

3

10

2



Short circuit detected

VRSNS pin input leakage

current

I_LKVR

I_INTS

I_INIS

Normal mode

-2

—

µA

TSNS pin input current

ISENSE pin input current

V_NSTS=0 V to V_REG

–1

—

1

µA

V_ISENSE= -0.1 V to 1 V

Note 1: Applied to CS0, CS1, and TEST pins.

Note 2: Applied to CS0, CS1 pins.

Note 3: Applied to TEST pin.

Note 4: Applied to DCHG, CHG, PF pins.

⚫

Supply Current Characteristics

V_DD= 5 to 25 V, GND=0 V, Ta=-40 to +85°C

Item

Symbol

I_DD

Condition

No output load

(Note1)

Min.

Typ.

Max.

Unit

Current consumption in

normal operation mode

Current consumption

in power-down mode

—

4.5

10

µA

I_DDS

No output load

0.1

1.0

µA

(Note1) 4.7k resistor is connected between VNTC and TSNS pins, and 10k resistor is connected between

TSNS and GND pins.

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⚫

Code 001: Detection/Release Threshold Characteristics (Ta = 0 to 60 °C)

V_DD=18 V, GND=0 V, Ta=0 to 60°C

Item

Symbol

V_OV

Condition

Min.

Typ.

Max.

Unit

Overvoltage detection

threshold

—

4.200

4.225

4.250

V

Overvoltage release

threshold

2^ndOvervoltage detection

threshold

2^ndOvervoltage release

threshold

V_OVR

V_SOV

V_SOVR

V_UV

—

3.975

4.290

4.225

1.95

2.95

0.5

4.025

4.325

4.275

2.00

3.00

0.6

4.075

4.360

4.325

2.05

3.05

0.7

V

Undervoltage detection

threshold

V

Undervoltage release

threshold

V_UVR

V_OW

V

Open-wire detection/release

threshold

V

Discharge overcurrent

detection threshold

Charge overcurrent

detection threshold

Short circuit

V_OCU

V_OCO

V_SHRT

—

55

70

85

mV

-45

-30

-15

280

300

320

detection threshold

High temperature charge

inhibition detection TSNS pin

threshold

V_CHD

V_CHR

V_DHD

V_DHR

V_CCD

V_CCR

—

1.07

1.15

0.72

0.80

2.08

1.99

1.12

1.22

0.77

0.85

2.13

2.06

1.17

1.29

0.82

0.90

2.18

2.13

V

High temperature charge

inhibition Release

TSNS pin threshold

High temperature discharge

inhibition detection

TSNS pin threshold

High temperature discharge

inhibition release

TSNS pin threshold

Low temperature charge

inhibition detection

TSNS pin threshold

Low temperature charge

inhibition release

TSNS pin threshold

Charger connection detection

VRSNS pin threshold

Power-up from

power-down mode

Charge overcurrent

detection

V_DD

0.35

ｘ

V_DDｘ

0.65

V_PC

V_PLU

V_PLD

V_DDｘ0.5

V

0

0.2

0.4

Charger removal detection

VRSNS pin threshold

V_DD

0.65

ｘ

V_DD

ｘ

V_DDｘ

0.85

Power-down mode

0.75

Discharge overcurrent

detection, short circuit

detection

Load removal detection

VRSNS pin threshold

V_RL

1.0

1.2

1.4

V

VREG drop detection

threshold

V_UREG

V_RREG

—

2.1

2.3

2.4

2.6

2.7

2.9

V

VREG drop release

threshold

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⚫

Code001: Detection Delay and Monitor Cycle Characteristics (Ta = 0 to 60 °C)

V_DD=18 V, GND=0 V, Ta=0 to 60°C

Item

Symbol

t_DET

Condition

Min.

300

Typ.

400

—

Max.

500

Unit

ms

Cell voltage monitor cycle

Overvoltage detection delay

2^ndOvervoltage detection

delay

—

t_OV

5×t_DET

6×t_DET

ms

t_SOV

t_UV

—

20×t_DET

5×t_DET

9×t_DET

—

21×t_DET

6×t_DET

ms

Undervoltage detection delay

Open-wire detection/release

delay

t_OW

10×t_DET

Discharge overcurrent

detection delay

t_OCU

—

250

50

500

100

750

150

ms

Charge overcurrent detection

delay

t_OCO

t_SHRT

t_PT

Short circuit detection delay

Temperature monitor cycle

Temperature measurement

time

—

0.2

0.5

1.0

ms

300

400

500

t_TM

—

1.9

3.9

5.5

ms

Temperature

detection/release delay

t_TDR

1×t_PT

—

2×t_PT

Discharge

overcurrent state,

short circuit state

Charge overcurrent

state

Load removal detection delay

t_ORL

50

100

150

ms

Charger removal detection

delay

t_OCHG

t_DETT

t_OVT

50

75

0

100

—

150

ms

Cell voltage monitor cycle

for test mode

TEST pin = “H”,

Ta=25°C

125

Overvoltage detection delay

for test mode

2^ndOvervoltage detection

delay for test mode

Undervoltage detection delay

for test mode

TEST pin = “H”,

Ta=25°C

1×t_DETT

125

T TEST pin = “H”,

Ta=25°C

t_SOVT

t_UVT

t_OWT

t_PTT

0

—

TEST pin = “H”,

Ta=25°C

0

—

Open-wire detection/release

delay for test mode

Temperature monitor cycle

for test mode

TEST pin = “H”,

Ta=25°C

0

—

TEST pin = “H”,

Ta=25°C

75

100

Temperature

detection/release delay

for test mode

TEST pin = “H”,

t_TDRT

0

—

1×t_PTT

ms

Ta=25°C

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■ Timing Diagrams

⚫ Overvoltage Detection and Recovery

Voltage difference

between adjacent cell

monitor pins (Vn+1-Vn)

V_OV

V_OVR

t_DETt_DETt_DETt_DETt_DETt_DETt_DETt_DETt_DETt_DETt_DETt_DETt_DET

①

③

④

⑥

②

⑤

t_OV

V_DD

CHG

State

0V

Measuring

Detection delay time

Overvoltage state

Overvoltage is not

detected

(Note) CHG pin is CMOS output mode and ”H” active.

⚫

2^ndOvervoltage Detection and Recovery

V_SOV

Voltage difference

V_SOVR

between adjacent cell

monitor pins (Vn+1-Vn)

t_DETt_DETt_DETt_DET

t_DET

t_DETt_DETt_DET

19

20

21

1

2

3

t_SOV

V_DD

PF

0V

2^ndovervoltage is not

detected

Measuring Detection

delay time

2^ndovervoltage

state

State

2^ndovervoltage is not

detected

(Note) PF pin is CMOS output mode and ”H” active.

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⚫

Undervoltage Detection and Recovery

Voltage difference

between adjacent cell

monitor pins (Vn+1-Vn)

V_UVR

V_UV

t_DETt_DETt_DETt_DETt_DETt_DETt_DET

t_DETt_DETt_DETt_DETt_DET

t_DET

①

②

③

④

⑥

⑤

t_UV

V_DD

DCHG

0V

VRSNS

0V

Measuring

Detection delay

Undervoltage

state

State

Undervoltage state

Is not detected

Undervoltage is not

detected

(Note) DCHG pin is CMOS output mode and ”H” active

⚫

Power-down after Undervoltage detection and Power-up

Voltage difference

between adjacent cell

monitor pins (Vn+1-Vn)

V_UVR

V_UV

t_DETt_DETt_DET

t_DETt_DET

③

④

⑤

⑥

t_UV

V_DD

DCHG

CHG

0V

V_DD

0V

V_DD

V_PLD

V_PC

VRSNS

VREG

0V

V_REG

0V

Power-down state

Measuring

Detection delay

Undervoltage

state

State

Undervoltage is not

detected

(Note) DCHG and CHG pins are CMOS output mode and ”H” active

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⚫

Open-wire detection and recovery

Voltage difference

V_OW

between adjacent cell

monitor pins (Vn+1-Vn)

t_DETt_DET

t_DET

t_DETt_DETt_DET

⑨

①

⑩

⑨

⑩

①

t_OW

CHG

0V

DCHG

0V

VRSNS

State

Measuring

detection delay

Open-wire

detection state

Measuring

Release delay

(Note) DCHG and CHG pin are CMOS output mode and ”H” active.

The status is assumed to be undervoltge state.

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⚫

Discharge Over-current Detection and Recovery from it with Load Removal

V_OCU

0V

ISENSE

t_OCU

V_DD

DCHG

0V

V_DD

CHG

V_RL

VRSNS

0V

Measuring detection

delay time

t_ORL

No-Load

Load Connected

No-Load

State

Discharge Overcurrent

state

Normal State

(Note) DCHG and CHG pins are CMOS output mode and ”H” active

⚫

Charge Over-current Detection and Recovery from it with Charger Removal

0V

V_OCO

ISENSE

t_OCO

V_DD

DCHG

CHG

V_DD

0V

V_RLU

0V

VRSNS

State

Measuring detection

delay time

t_OCHG

No-Load

Charger connected

Charge Overcurrent state

Normal State

(Note) DCHG and CHG pins are CMOS output mode and ”H” active

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⚫

Short Circuit detection and Recovery from it with Load Removal

V_SHRT

0V

ISENSE

t_SHRT

V_DD

DCHG

0V

V_DD

CHG

V_RL

VRSNS

0V

Measuring detection

delay time

t_ORL

No-Load

Load is Removed

No-Load

Normal State

State

Short current

state

Normal State

(Note) DCHG and CHG pins are CMOS output mode and ”H” active

⚫

High temperature Charge inhinition detection and Recovery

V_NTC

VNTC

Hi-Z

t_PT

V_CHR

V_CHD

0V

TSNS

t_TM

t_TDR

V_DD

CHG

0V

V_DD

DCHG

Temperature

over 45℃ and

under 50℃

Temperature

under 50℃

Temperature

under 45℃

Temperature

Over 50℃

State

Normal State

High Temperature

Charge Inhibition state

(Note) DCHG and CHG pins are CMOS output mode and ”H” active

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⚫

Low Temperature Charge Inhibition Detection and Recovery

V_NTC

VNTC

Hi-Z

t_PT

V_CCD

V_CCR

TSNS

0V

t_TM

t_TDR

V_DD

CHG

0V

V_DD

DCHG

Temperature

Over -5℃ and

Under 0℃

Temperature

Under -5℃

Temperature

Over 0℃

Temperature

Over -5℃

State

Normal State

Low temperature charge

inhibition state

Normal State

(Note) DCHG and CHG pins are CMOS output mode and ”H” active

⚫

High Temperature Discharge Inhibition and Recovery

V_NTC

VNTC

Hi-Z

t_PT

V_DHR

V_DHD

TSNS

0V

t_TM

t_TDR

V_DD

DCHG

0V

CHG

State

0V

Temperature

Over 65℃ and

Under 70℃

Temperature

Under 70℃

Temperature

Under 65℃

Temperature

Over 70℃

High Temperature

Charge inhibition State

High Temperature

Discharge inhibition State

High Temperature

Charge inhibition State

(Note) DCHG and CHG pins are CMOS output mode and ”H” active

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■ Functional Description

States of ML5243

⚫

The ML5243 has the following twelve states which depend on individual cell voltages and the input

levels of the ISENSE and TSNS pins.

1. Initial state

2. Normal state

3. Overvoltage state

4. 2^ndOvervoltage state

5. Undervoltage state (including power-down mode)

6. Open-wire state

7. Discharge overcurrent state

8. Charge overcurrent state

9. Short circuit state

10. High temperature charge inhibition state

11. Low temperature charge inhibition state

12. High temperature discharge inhibition state

Each state is described below.

1. Initial State

The initial state refers to the period while the battery cells are being connected to the ML5243 and

connection of all the battery cells specified by the CS0 and CS1 pins is completed, before transitioning

to the normal state.

In the initial state, when the VREG pin voltage is below the VREG drop detection threshold V_UREG

the DCHG pin output is discharge inhibited state and the CHG pin output is charge permitted state.

When the VREG pin level reaches or exceeds the VREG drop release threshold V_RREG, individual

,

cell voltage monitoring takes place. If all the battery cells specified by the CS0 and CS1 pins reach or

exceed the undervoltage release threshold V_UVR, the system transitions to the normal state. Overvoltage,

overcurrent and temperature detection is also performed in parallel.

2. Normal State

The normal state refers to the period where all the battery cell voltages do not reach or exceed the

overvoltage/undervoltage detection threshold, the ISENSE pin voltage is below the overcurrent

detection threshold, and the TSNS pin voltage is below the high temperature detection threshold or

above the low temperature detection threshold. In the normal state, both the DCHG and CHG pin

outputs are set as both charge and discharge is permitted.

Individual cell voltages are monitored every 0.4 second for performing overvoltage/undervoltage

detection, while the pack temperature is also monitored using an external thermistor every 0.4 second.

The ISENSE pin voltage is always monitored to detect overcurrent in parallel.

3. Overvoltage State

When any one or more battery cell voltages reach or exceed the overvoltage detection threshold V_OV

for longer than the overvoltage detection delay time t_OV,the system enters the overvoltage state. If the

ML5243 detects that voltage of all cell is below the overvoltage detection threshold V_OVfor consecutive

two times, detection delay time counting is cleared.

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In the overvoltage state, the CHG pin output is set to charge disabled, while the DCHG pin output

maintains the value in the previous state.

Battery cell voltages decrease gradually by self-discharge or by a connected light load. When all of

them reach or decrease below the overvoltage detection release threshold V_OVR, the system recovers

from the overvoltage state.

4. 2^ndovervoltage state

When more than one battery cell voltage reaches or exceeds the 2^ndovervoltage detection threshold

V_SOV, and when it past longer than the 2^ndovervoltage detection delay time t_SOVsince the ML5243 has

detected it, the system enters the 2^ndovervoltage state. If the ML5243 detects that voltage of all cell is

below the 2^ndovervoltage detection threshold V_SOVfor consecutive two times, detection delay time

counting is cleared.

In the 2^ndovervoltage state, the PF pin output is set to 2^ndovercharge detected state, while the DCHG

pin output maintains the value in the previous state.

Battery cell voltages decrease gradually by self-discharge or a connected light load. When all of them

reach or decrease below the 2^ndovervoltage detection release threshold V_SOVR, the system recovers from

the 2^ndovervoltage state.

5. Undervoltage State

When more than one battery cell voltage reaches or decreases below the undervoltage detection

threshold V_UV, and when it past longer than the undervoltage detection delay time t_UVsince the ML5243

has detected it, the system enters the undervoltage state. If the ML5243 detects that voltage of all cell is

above the undervoltage detection threshold V_UVfor consecutive two times, detection delay time

counting is cleared.

In the undervoltage state, the DCHG pin output is set to discharge disabled, while the CHG pin

output maintains the value in the previous state.

In the undervoltage state, a 500 k pull-up resistor is connected between the VRSNS pin and VDD.

When the VRSNS pin voltage increases and reaches or exceeds the charger removal detection VRSNS

threshold V_PLD, the system enters power-down mode to reduce current consumption.

In the undervoltage state, if the 2^ndovervoltage is already detected, the ML5243 status doesn’t be

changed to power-down and VRSNS pin pull-up resistor is not connected.

If the VRSNS pin voltage reaches or decreases below the charger detection voltage V_PC, the system

wakes up all the circuits to resume monitoring individual battery cell voltages.

If the system was in the overvoltage, undervoltage, high temperature or any overcurrent state before

entering power-down mode, these error flags are cleared during power-down. After wake-up, if these

errors are detected again for longer than the specified detection delay time, the system reenters the

corresponding error state.

Battery cell voltages increase gradually while charging, and if all cell voltages reach or exceed the

undervoltage detection release threshold V_UVR, the system recovers from the undervoltage state.

6. Open-wire state

When more than one battery cell voltage reaches or decreases below the open-wire detection threshold

Vo_V, and when it past longer than the open-wire detection delay time to_Vsince the ML5243 has

detected it, the system enters the open-wire state. If the ML5243 detects that voltage of all cell exceeds

the open-wire detection threshold V_OWfor once, the detection delay time counting is cleared.

In the open-wire state, CHG pin output is set to charge disabled. Because open-wire detection

threshold V_OWis lower than undervoltage detection threshold V_UV, and undervoltage detection delay

time t_UVis shorter than open-wire detection delay time t_OW, in the open-wire state the status is also in the

undervoltage state, and DCHG pin output is set to discharge disabled.

When every cell voltage reaches or exceeds the open-wire detection threshold V_OW, and when it past

longer than the open-wire detection delay time t_OWsince the ML5243 has detected it, the system

15/28

FEDL5243_001-04

ML5243

recovers from the open-wire state and CHG pin output is set to charge enabled. If the ML5243 detects

that voltage of more than one cell voltage reaches or decrease below the open-wire detection threshold

V_OWfor once, the release delay time counting is cleared.

7. Discharge Overcurrent State

When the load is connected and ISENSE pin voltage reaches or exceeds the discharge overcurrent

detection threshold V_OCUfor longer than the discharge overcurrent detection delay time t_OCU, the system

enters the discharge overcurrent state, regardless of the individual battery cell voltages. In the discharge

overcurrent state, the DCHG pin output is set to discharge inhibiting state.

In the discharge overcurrent state, the VRSNS pin is pulled-down to GND with a 3 M resistor and

a backflow prevention diode.

The system recovers from the discharge overcurrent state when the VRSNS pin level reaches or

decrease below the load removal detection threshold V_RLfor longer than the load removal detection

delay time t_ORL

.

8. Charge Overcurrent State

When the charger is connected and ISENSE pin voltage reaches or exceeds the charge overcurrent

detection threshold V_OCOfor longer than the charge overcurrent detection delay time t_OCO, the system

enters the charge overcurrent state, regardless of the individual battery cell voltages. In the charge

overcurrent state the CHG pin output is set to charge inhibiting state, while the DCHG pin output

maintains the value in the previous state.

In the charge overcurrent state, a 500 k pull-up resistor is connected between the VRSNS pin and

VDD pin. The system recovers from the charge overcurrent state when the VRSNS pin voltage reaches

or exceeds the charger removal detection threshold V_PLUfor longer than the charger removal detection

delay time t_OCHG

.

9. Short Circuit State

When the pack is overloaded and the ISENSE pin voltage reaches or exceeds the short circuit

detection threshold V_SHRTfor longer than the short circuit detection delay time t_SHRT,the system enters

the short circuit state, regardless of the battery cell voltages.

In the short circuit state, a 3 M pull-down resistor is connected between the VRSNS pin and the

GND pin through a backflow prevention diode.

The system recovers from the short circuit state when the VRSNS pin level reaches or decreases

below the load removal detection threshold V_RLfor longer than the load removal detection delay time

t_ORL

.

10. High Temperature Charge inhibition State

Pack temperature is monitored using an external thermistor every 0.4 seconds regardless of the

battery cell voltages and current measuring. When the TSNS pin voltage reaches or decrease below the

high temperature charge inhibition detection threshold V_CHDfor longer than the temperature

detection/release delay time t_TDRthe system enters the high temperature charge inhibition state. In this

state, the CHG pin output is in the charge inhibition state.

If the TSNS pin voltage reaches or exceeds the high temperature charge inhibition release TSNS pin

threshold V_CHRfor longer than the temperature detection/release delay time t_TDR,the system recovers

from the high temperature charge inhibition state and the CHG pin output is in the charge enable state.

16/28

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ML5243

11. Low Temperature Charge Inhibition State

Pack temperature is monitored using an external thermistor every 0.4 seconds regardless of the

battery cell voltages and current measuring. When the TSNS pin voltage reaches or exceeds the low

temperature charge inhibition detection threshold V_CCDfor longer than the temperature detection/release

delay time t_TDRthe system enters the low temperature charge inhibition state. In this state, the CHG pin

output is in the charge inhibition state.

If the TSNS pin voltage reaches or decrease below the low temperature charge inhibition release

TSTN pin threshold V_CCRfor longer than the temperature detection/release delay time t_TDR,the system

recovers from the low temperature charge inhibition state and the CHG pin output is in the charge

enable state.

12. High Temperature Discharge Inhibition State

Pack temperature is monitored using an external thermistor every 0.4 seconds regardless of the

battery cell voltages and current measuring. When the TSNS pin voltage reaches or decrease below the

high temperature discharge inhibition detection threshold V_DHDfor longer than the temperature

detection/release delay time t_TDRthe system enters the high temperature discharge inhibition state. In

this state, the DCHG pin output is in the discharge inhibition state.

If the TSNS pin voltage reaches or exceeds the high temperature discharge inhibition release TSNS

pin threshold V_DHRfor longer than the temperature detection/release delay time t_TDR,the system

recovers from the high temperature discharge inhibition state and the DCHG pin output is in the

discharge enable state.

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ML5243

⚫

Selecting the Number of Battery Cells

Cell count is selectable from predefined 3 values using the CS0 and CS1 pins.

Its configuration is given in the table below.

CS1

CS0

Battery cell number

Unused Vn pins

GND

VREG

GND

VREG

GND

5 cell

4 cell

None

V1

V1, V2

3 cell

VREG

⚫

Code001: output pin status of each state

The table below shows the output pin status of each state.

CHG

“H”

“Hi-Z”

“H”

“Hi-Z”

DCHG

“L”

“H”

“L”

PF

VRSNS

“Hi-Z”

VREG

3.3V

0V

Initial state

Normal state

“L”

“H”

“L”

Overvoltage state

2nd Overvoltage state

Undervoltage state

Power down state

Open-wire state

Discharge overcurrent

state

500kpull-up

“L”

3.3V

“Hi-Z”

“L”

3.3V

3Mpull-down

Charge overcurrent

state

“Hi-Z”

“H”

“L”

“H”

“L”

3.3V

500kpull-up

3Mpull-down

“Hi-Z”

Short circuit state

High temperature

charge inhibit state

High temperature

discharge inhibit state

Low temperature

charge inhibit state

“H”

“L”

“H”

“L”

“Hi-Z”

3.3V

“Hi-Z”

⚫

Power-on/Power-off Sequence

Battery cells can be connected in any order, but it is recommend that the GND and VDD pins are

connected first, and then connection continues from lower to higher voltage cells. There are no

restrictions on the power supply voltage rise time at power-on, and power-off sequence or power supply

voltage fall time at power-off.

After power-on, the system usually transitions to the normal state. However, it may transition to the

undervoltage state due to chattering at power-on or other reasons. If it has transitioned to the

undervoltage state and moved to power-down mode, apply the charger connection detection threshold

V_PCor lower level to the VRSNS pin to power it up again.

In the battery connection, if it takes long time to set all the battery cells, the ML5243 might detect

overvoltage/2^ndovervoltage/undervoltage.

⚫

Handling VDD Pin and V1 to V5 Pins

Since the VDD pin is the power supply input, put a noise elimination RC filter in front of the VDD

input for stabilization. If the drive current requirement on the CHG, DCHG and PF pins is large, the

resistor value of this noise filter should be adjusted so that the voltage drop across the resistor is smaller

than 1 V.

The V1 to V5 pins are the monitor pins for individual cell voltages. Put a noise elimination RC filter

in front of each battery cell to prevent false detection. On a system with less than 5 battery cells, unused

Vn pins should be tied to GND.

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FEDL5243_001-04

ML5243

⚫

Handling VREG Pin

The VREG pin is the power source of the built-in regulator which supplies power to the internal

modules. Connect a 1 µF or larger capacitor between this pin and GND for stabilization. Do not use it as

a power supply for external circuits since the supply current of the built-in regulator is limited.

Unused Pin Treatment

The following table shows how to handle unused pins.

Unused pins

Vn

Recommended treatment

Connected to GND

VNTC

TSNS

VRSNS

ISENSE

CHG

Tied to the TSNS pin with a 4.7k resistor

Tied to the GND with a 10k resistor

Tied to the GND

Open

DCHG

PF

Open

⚫

Reducing each detection delay time

By setting the TEST pin as VREG level, cell voltage monitoring cycle and temperature monitoring

cycle is reduced to 100ms(typ) and each detection delay time is reduced down to 1 monitoring cycle

minimum.

19/28

FEDL5243_001-04

ML5243

⚫

Setting the CHG, DCHG and PF pin output level

CHG pin output level is shown.

CHG pin output level (“H” active output)

CMOS

“H” level

“L” level

“H” level

“L” level

N-ch open drain

“Hi-Z” level

“L” level

“Hi-Z” level

“L” level

P-ch open drain

“H” level

Initial state

Normal state

“H” level

Overvoltage state

2^ndOvervoltage state

Undervoltage state

Power down state

Open-wire state

Discharge overcurrent

state

“Hi-Z” level

“H” level

“Hi-Z” level

“L” level

“H” level

“Hi-Z” level

“H” or “Hi-Z” level

Charge overcurrent

state

“L” level

“H” level

“L” level

“Hi-Z” level

“L” level

“H” level

“H” or “Hi-Z” level

“H” level

Short circuit state

High temperature

charge inhibit state

High temperature

discharge inhibit state

low temperature

charge inhibit state

“L” level

“H” level

CHG pin output level (“L” active output)

CMOS

N-ch open drain

“L” level

P-ch open drain

Initial state

Normal state

“L” level

“H” level

“L” level

“H” level

“Hi-Z” level

“H” level

“Hi-Z” level

“H” level

“L” level

Overvoltage state

2^ndOvervoltage state

Undervoltage state

Power down state

Open-wire state

Discharge overcurrent

state

“Hi-Z” level

“L” level

“Hi-Z” level

“H” level

“L” level

“Hi-Z” level

Charge overcurrent

state

“H” level

“L” level

“H” level

“Hi-Z” level

“L” level

“H” level

“Hi-Z” level

“H” level

Short circuit state

High temperature

charge inhibit state

High temperature

discharge inhibit state

Low temperature

charge inhibit state

“Hi-Z” level

“H” level

“Hi-Z” level

“H” level

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FEDL5243_001-04

ML5243

DCHG pin output level is shown.

DCHG pin output level (“H” active output)

CMOS

“L” level

N-ch open drain

“L” level

“Hi-Z” level

“L” level

P-ch open drain

“Hi-Z” level

“H” level

“Hi-Z” level

Initial state

Normal state

“H” level

“L” level

Overvoltage state

2^ndOvervoltage state

Undervoltage state

Power down state

Open-wire state

Discharge overcurrent

state

“L” level

“Hi-Z” level

Charge overcurrent

state

“H” level

“L” level

“H” level

“Hi-Z” level

“L” level

“H” level

“Hi-Z” level

“H” level

Short circuit state

High temperature

charge inhibit state

High temperature

discharge inhibit state

Low temperature

charge inhibit state

“Hi-Z” level

“L” level

“H” level

“L” level

“Hi-Z” level

“H” level

“Hi-Z” level

DCHG pin output level (“L” active output)

CMOS

N-ch open drain

“Hi-Z” level

“L” level

“Hi-Z” level

P-ch open drain

Initial state

Normal state

“H” level

“L” level

“H” level

“Hi-Z” level

“H” level

Overvoltage state

2^ndOvervoltage state

Undervoltage state

Power down state

Open-wire state

Discharge overcurrent

state

“H” level

“Hi-Z” level

“H” level

Charge overcurrent

state

“L” level

“H” level

“L” level

“Hi-Z” level

“L” level

“Hi-Z” level

“H” level

Short circuit state

High temperature

charge inhibit state

High temperature

discharge inhibit state

Low temperature

charge inhibit state

“Hi-Z” level

“H” level

“L” level

“Hi-Z” level

“L” level

“H” level

“Hi-Z” level

PF pin output level is shown.

PF pin output level (“H” active output)

CMOS

“H” level

“L” level

N-ch open drain

“Hi-Z” level

“L” level

P-ch open drain

“H” level

“Hi-Z” level

2^ndOvervoltage state

other state

PF pin output level (“L” active output)

CMOS

“L” level

“H” level

N-ch open drain

“L” level

“Hi-Z” level

P-ch open drain

“Hi-Z” level

“H” level

2^ndOvervoltage state

other state

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FEDL5243_001-04

ML5243

⚫

Redefinition of Detection/Release Threshold Range and Step (product code)

The detection/release thresholds can be redefined as shown in the following table.

Since some combinations are unavailable, contact us for details.

Detecting voltage

Overvoltage detection

threshold

Symbol

V_OV

Threshold range

3.65 V to 4.35 V

Threshold step

25 mV

Overvoltage release

threshold

V_OVR

V_SOV

V_SOVR

V_UV

3.5 V to 4.25 V

3.85 V to 4.45 V

3.7 V to 4.35 V

1.5 V to 3.0 V

25 mV

100 mV

10 mV

50 mV

100 mV

10 mV

2^ndOvervoltage detection

threshold

2^ndOvervoltage release

threshold

Undervoltage detection

threshold

Undervoltage release

threshold

Charge overcurrent

detection threshold

Discharge overcurrent

detection threshold

Short circuit detection

threshold

High temperature Discharge

inhibition detection threshold

High temperature Charge

inhibition detection threshold

Low temperature Charge

inhibition detection threshold

V_UVN

V_OCO

V_OCU

V_SHRT

V_DHD

V_CHD

V_CCD

2.3 V to 3.5 V

-30 mV to -100 mV

50 mV to 300 mV

100 mV to 500 mV

0.6 V to 1.2 V

0.7 V to 1.3 V

2.0 V to 2.2 V

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FEDL5243_001-04

ML5243

⚫

Redefinition of Detection Delay Time of Overvoltage/2^ndovervoltage/undervoltage

detection

The detection delay times can be redefined as shown in the following table.

Settable time(cycles for detection)

Unit

Detection delay time

Overvoltage/undervoltage

detection delay time

2^ndovervoltage detection delay

time

Open-wire detection/release delay

time

9 to

10

40 to

41

9 to

10

11 to

12

13 to

14

1 to 2 3 to 4 5 to 6 7 to 8

cycle

10 to

11

20 to

21

30 to

31

5 to 6

cycle

—

11 to

12

13 to

14

1 to 2 3 to 4 5 to 6 7 to 8

Settable time (detection cycle=400ms)

0.4 to 1.2 to 2.0 to 2.8 to 3.6 to 4.4 to 5.2 to

Unit

sec

Detection delay time

Overvoltage/undervoltage

detection delay time

2^ndovervoltage detection delay

time

0.8

1.6

2.4

3.2

12 to

12.4

4.0

16 to

16.4

4.8

—

5.6

—

2.0 to 4.0 to 8.0 to

2.4

sec

4.4

8.4

Open-wire detection/release delay 0.4 to 1.2 to

time 0.8 1.6

20.0

to 2.4

2.8 to 3.6 to 4.4 to 5.2 to

3.2

4.0

4.8

5.6

Temperature detection delay time and release delay time are not resettable.

⚫

Redefinition of Overcurrent detection delay time

The detection delay times can be redefined as shown in the following table.

symbol

t_OCU

Settable time(ms)

Detection delay time

Discharge overcurrent detection

delay time

Charge overcurrent detection

delay time

Short circuit detection delay

time

25

50

100

0.3

200

0.4

300

0.5

400

—

500

—

t_OCO

t_SHRT

0.1

0.2

23/28

FEDL5243_001-04

ML5243

■ Application Circuit Example 1 (5-cell system)

Pack(+)

R_VDD

1

2

3

4

20

19

18

17

16

VDD

V5

VREG

CS1

C_REG

R_CELL

C_VDD

C_CELL

V4

CS0

V3

VNTC

TSNS

R_T

5 V2

R_NTC

6

V1

TEST 15

GND 14

PF 13

7 GND

ISENSE

8

C_IS

R_IS

9 N.C.

VRSNS

12

11

DCHG

10

CHG

R_VR

R_G

Pack(-)

R_GS

R_S

■Recommended Values for External Components

Recommended

value

Recommended

value

Component

C_IS

R_T

R_NTC

R_G

R_GS

R_VR

0.01 µF

4.7 kΩ

10 kΩ, B3435

10 kΩ

R_VDD

C_VDD

R_CEL

C_CEL

C_REG

R_S

1.5kΩ

2.2 µF

1 kΩ to 10 kΩ

0.1 µF or more

1 µF

1 MΩ

1 kΩ

1 mΩ

R_IS

1 kΩ

(Note) This circuit example and the recommended values of external components are not always

warranted. Evaluation on customer’s application is required and select circuit and parts

depend on customer’s application.

24/28

FEDL5243_001-04

ML5243

■ Application Circuit Example 2 (4-cell system, overcurrent is not implemented)

Pack(+)

R_VDD

1

2

3

4

20

19

18

17

16

VDD

V5

VREG

CS1

R_CELL

C_REG

C_VDD

C_CELL

V4

CS0

V3

VNTC

TSNS

R_T

R_NTC

5 V2

6

V1

TEST 15

GND 14

PF 13

Power-Up Control input

7 GND

ISENSE

8

9 N.C.

VRSNS

12

11

Charge control

output

DCHG

10

CHG

Discharge control

output

Pack(-)

■Recommended Values for External Components

Recommended

value

Recommended

value

Component

R_T

R_NTC

4.7 kΩ

10 kΩ, B3435

R_VDD

C_VDD

R_CEL

C_CEL

C_REG

1.5kΩ

2.2 µF

1 kΩ to 10 kΩ

0.1 µF or larger

1 µF

(Note) This circuit example and the recommended values of external components are not always

warranted. Evaluation on customer’s application is required and select circuit and parts

depend on customer’s application.

25/28

FEDL5243_001-04

ML5243

■ Package Dimensions

Caution regarding surface mount type packages

Surface mount type packages are susceptible to heat applied in solder reflow and moisture absorbed during

storage. Please contact your local ROHM sales representative for recommended mounting conditions (reflow

sequence, temperature and cycles) and storage environment.

26/28

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ML5243

■ Revision History

Page

Before

revision revision

Document No.

Issue date

Revision description

After

FEDL5243_001-01

FEDL5243_001-02

8, March. 2019

19, June. 2019

-

First edition.

15

25

15

25

overvoltage is corrected to undervoltage

R_T=1kΩ is corrected to 4.7kΩ

CHG pin status in Open-wire state, mistype is

corrected, “L” to “Hi-Z”.

FEDL5243_001-03

2, August. 2019

18

23

18

23

Open-wire detection/release delay time, mistype

is corrected “2 to 4 ” to “3 to 4 cycles”.

Changed Company name

FEDL5243_001-04

1, Dec. 2020

-

28

Changed “Notes”

27/28

FEDL5243_001-04

ML5243

Notes

1) The information contained herein is subject to change without notice.

2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals,

application notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating

conditions, etc.) are within the ranges specified. LAPIS Technology disclaims any and all liability for any

malfunctions, failure or accident arising out of or in connection with the use of LAPIS Technology Products

outside of such usage conditions specified ranges, or without observing precautions. Even if it is used within

such usage conditions specified ranges, semiconductors can break down and malfunction due to various factors.

Therefore, in order to prevent personal injury, fire or the other damage from break down or malfunction of

LAPIS Technology Products, please take safety at your own risk measures such as complying with the derating

characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe

procedures. You are responsible for evaluating the safety of the final products or systems manufactured by you.

3) Descriptions of circuits, software and other related information in this document are provided only to illustrate

the standard operation of semiconductor products and application examples. You are fully responsible for the

incorporation or any other use of the circuits, software, and information in the design of your product or system.

And the peripheral conditions must be taken into account when designing circuits for mass production. LAPIS

Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising

from the use of these circuits, software, and other related information.

4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of

LAPIS Technology or any third party with respect to LAPIS Technology Products or the information contained

in this document (including but not limited to, the Product data, drawings, charts, programs, algorithms, and

application examples、etc.). Therefore LAPIS Technology shall have no responsibility whatsoever for any

dispute, concerning such rights owned by third parties, arising out of the use of such technical information.

5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer

systems, gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our

Products in applications requiring a high degree of reliability (as exemplified below), please be sure to contact a

LAPIS Technology representative and must obtain written agreement: transportation equipment (cars, ships,

trains, etc.), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical

systems, servers, solar cells, and power transmission systems, etc. LAPIS Technology disclaims any and all

liability for any losses and damages incurred by you or third parties arising by using the Product for purposes

not intended by us. Do not use our Products in applications requiring extremely high reliability, such as

aerospace equipment, nuclear power control systems, and submarine repeaters, etc.

6) The Products specified in this document are not designed to be radiation tolerant.

7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this

document. However, LAPIS Technology does not warrant that such information is error-free and LAPIS

Technology shall have no responsibility for any damages arising from any inaccuracy or misprint of such

information.

8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the

RoHS Directive. LAPIS Technology shall have no responsibility for any damages or losses resulting

non-compliance with any applicable laws or regulations.

9) When providing our Products and technologies contained in this document to other countries, you must abide

by the procedures and provisions stipulated in all applicable export laws and regulations, including without

limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act..

10) Please contact a ROHM sales office if you have any questions regarding the information contained in this

document or LAPIS Technology's Products.

11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS

Technology.

(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.

2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan

https://www.lapis-tech.com/en/

28/28


型号：	ML5243
厂家：	ROHM
描述：	支持3～5节电池、具有电池电压、电流、温度和断线检测功能的电池监控保护LSI电池电压检测过电流检测温度检测断线检测充放电许可信号输出短路电流检测省时测试模式电池监控测试
文件：	总28页 (文件大小：1666K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ML5243 [ROHM]

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