ML62Q1335_技术文档

FEDL62Q1300-05

Issue Date: May 19, 2022

ML62Q1300 Group

16-bit micro controller

GENERAL DESCRIPTION

ML62Q1300 Group is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU nX-U16/100 and

integrated with program memory(Flash memory), data memory(RAM), data Flash and rich peripheral functions such as the

multiplier/divider, CRC generator, DMA controller, Clock generator, Timer, General Purpose Ports, UART, Synchronous serial

port, I²C bus interface unit (Master, Slave), Buzzer, Voltage Level Supervisor(VLS), Successive approximation type A/D

converter, D/A converter , Analog comparator, Safety function(IEC60730/60335 Class B) and so on.

The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by pipeline architecture parallel

processing.

The built-in on-chip debug function enables debugging and programming the software. Also, ISP(In-System Programming)

function supports the Flash programming in production line.

The ML62Q1300 Group has six packages (16pin - 32pin) and five kinds of memory sizes(16Kbyte - 64Kbyte).

Table 1 ML62Q1300 Group Product List

16pin

32pin

20pin

TSSOP20

SSOP20

Data memory

(RAM)

24pin

Program

memory

Data Flash

2Kbyte

SSOP16

WQFN16

TQFP32

WQFN32

WQFN24

64Kbyte

48Kbyte

32Kbyte

24Kbyte

16Kbyte

－

ML62Q1347

ML62Q1367

4Kbyte

2Kbyte

－

ML62Q1346

ML62Q1366

－

ML62Q1345

ML62Q1365

ML62Q1325

ML62Q1324

ML62Q1323

ML62Q1335

ML62Q1334

ML62Q1333

－

Please see the page 63 “Notes for product usage” and the page 64 “Notes” in this document on use with this ML62Q1300

group.

FEATURES

• CPU

− 16-bit RISC CPU: nX-U16/100(A35 core)

− Instruction system: 16-bit length instructions

‒ Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,

bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on

‒ Built-in On-chip debug function

‒ Built-in ISP (In-System Programming) function

‒ Minimum instruction execution time

Approximately 30.5 μs (at 32.768 kHz system clock)

Approximately 62.5ns/41.6ns (at 16 MHz/24MHz system clock)

• Coprocessor for multiplication and division

− Multiplication

: 16bit × 16bit (operation time : 4 cycles)

: 32bit ÷ 16bit (operation time : 8 cycles)

: 32bit ÷ 32bit (operation time : 16 cycles)

− Division

− Multiply-accumulate (non-saturating): 16bit × 16bit + 32bit (operation time : 4 cycles)

− Multiply-accumulate (saturating): 16bit × 16bit + 32bit (operation time : 4 cycles)

− Signed or Unsigned is selectable

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• Operating voltage and temperature

‒ Operating voltage: V_DD= 1.6 to 5.5 V (V_DDshould be 1.8V or over at Power-on)

‒ Operating temperature: -40 °C to +105 °C

• Internal memory

‒ Program memory area

Rewrite count: 100 cycles

Write unit: 32bit(4byte)

Erase unit: 16Kbyte/1Kbyte

Erase/Write temperature: 0 °C to +40 °C

‒ Data Flash memory area

Rewrite count 10,000 cycles

Write unit: 8bit(1byte)

Erase unit: all area/128byte

Erase/Write temperature: -40 °C to +85 °C

Back Ground Operation (CPU can work while erasing and rewriting)

This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.

SuperFlash® is a registered trademark of Silicon Storage Technology, Inc.

‒ Data RAM area

Rewrite unit: 8bit/16bit(1byte/2byte)

Parity check function is available (interrupt / reset are generatable at Parity error)

• Clock

‒ Low-speed clock (LSCLK)

Internal low-speed RC oscillation: Approximately 32.768 kHz

‒ High-speed clock (HSCLK)

PLL oscillation: 2 selectable oscillation frequency (24MHz and 16MHz) by code option

‒ Watch Dog Timer (WDT): built-in independent clock for WDT (RC1K: Approximately 1kHz )

• Reset

‒ Reset by reset input pin

‒ Reset by Power-On Reset

‒ Reset by WDT overflow

‒ Reset by WDT invalid clear

‒ Reset by RAM parity error

‒ Reset by unused ROM area access (instruction access)

‒ Reset by voltage level supervisor (VLS)

‒ Software reset by BRK instruction (reset CPU only)

‒ Reset the peripherals individually

‒ Collective reset to the all control pins and peripheral circuits

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• Power management

‒ HALT mode: CPU stops executing instruction, peripheral circuits continue working

‒ HALT-H mode: CPU stops executing instruction, high-speed clock oscillation stops and peripheral circuits continue

working with low-speed clock

‒ STOP mode: CPU and peripheral circuits stops executing instruction, both high-speed oscillation and low-speed

oscillation stop.

‒ STOP-D mode: CPU and peripheral circuits stops executing instruction, both high-speed oscillation and low-speed

oscillation stop. The internal logic voltage (V_DDL) goes down to reduce the current consumption (RAM data is retained).

‒ Clock gear: High-speed system clock frequency can be changed (1/1, 1/2, 1/4, 1/8, 1/16 or 1/32 of HSCLK)

‒ Block Control Function: Powers down the unused function blocks (reset the block or stop supplying the clock)

• Interrupt controller

− External interrupt ports : max. 8

− Non-maskable interrupt source: 1 (Internal sources: WDT)

− Maskable interrupt sources: max.32

− Four step interrupt levels

• Watchdog timer(WDT)

‒ Selectable Operating clock : select RC1K or LSCLK by code option

‒ Overflow period: 8selectable (7.8ms, 15.6ms, 31.3ms, 62.5ms, 125ms, 500ms, 2s and 8s)

‒ Selectable window function (enable or disable): configurable clear enable period (50% or 75% of overflow period)

‒ Selectable WDT operation : select Enable or Disable by code option

‒ Readable WDT counter : WDT counter monitor function

• DMA (Direct Memory Access) controller

− Channel: 2channel

− Transfer unit: 8bit/16bit

− Transfer count: 1 to 1024

− Transfer cycle: 2 cycle transfer

− Transfer address: Fixed addressing mode, inclement addressing mode, and decrement addressing mode

− Transfer target: Special Function Register (SFR)/RAM  SFR/RAM (Transfer from/to Flash is not supported)

− Transfer request: External pins, Serial communication unit, Successive approximation type A/D converter, 16bit timer,

and Functional timer

•

Low-speed Time base counter

− Generate 8 frequency (128Hz to1Hz) internal pulse signals by dividing the Low-speed clock (LSCLK)

− Selectable 3 interrupts from eight frequency internal pulse signals

− 1Hz or 2Hz output from general purpose port

• Functional timer

− Channel: 4 channel

− Built-in timer, capture, and PWM function by 16 bit counter

− Built-in Repeat mode, One shot mode is available

− Two types of PWM output with the same period and different duties, and complementary PWM output with the dead time

− Monitor input signal duty and the period by capture function

− Generate periodical interrupts, duty interrupts, and interrupts coincided with set value

− Counter Start, Stop, Counter clear triggered by an external inputs or Timer

− Generate Emergency stop and emergency stop interrupt triggered by an external input

− Same start/stop among different channels of the functional timer

− Selectable counter clock(external clock or divided by 1 to 128 of LSCLK or HSCLK) for each channels

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• 16-bit General timers

− Channel: Max. 6channel

‒ 8 bits timer mode and 16-bit timer mode

− Same start/stop among different channels of 16bit (8bit) timer

‒ Timer output (toggled by overflow)

− Selectable counter clock (external clock or divided by 1 to 128 of LSCLK or HSCLK) for each channels

• Serial communication unit

− Synchronous Serial Port (SSIO) mode or UART mode is selectable

− Channel: 2channel

< Synchronous Serial Port >

‒ Selectable from Master and Slave

‒ Selectable from LSB first or MSB first

‒ Selectable 8-bit length or 16-bit length

< UART mode>

‒ Full-duplex communication mode and half-duplex communication mode

‒ 5 to 8 bit length, parity or no parity, odd parity or even parity, 1 stop bit or 2 stop bits

‒ Selectable from Positive logic or Negative logic

‒ Selectable from LSB first or MSB first

‒ Configurable wide range communication speed

32.768kHz operation clock : 1bit/s to 4,800 bit/s

24MHz operation clock : 600bit/s to 3M bit/s

16MHz operation clock : 300bit/s to 2M bit/s

‒ Built-in baud rate generator

• I²C bus unit (Master / Slave)

‒ Selectable from Master mode or Slave mode

‒ Channel: 1 channel

< Master function >

‒ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)

‒ Handshake (Clock synchronization)

‒ 7bit address format (10bit address format is supported)

< Slave function >

‒ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)

‒ Clock stretch function

‒ 7bit address format

• I²C bus Master

‒ Channel: 1channel

‒ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)

‒ Handshake (Clock synchronization)

‒ 7bit address format (10bit address format is supported)

• General-purpose ports (GPIO)

‒ I/O port: Max. 28 (Including one pin for on-chip debug and pins for other shared functions)

‒ External interrupt port: 8

‒ LED driver port : Max. 27

‒ Carrier frequency output function (used for IR communication)

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• Successive approximation type A/D converter (SA-ADC)

‒ Channel: Max.8channel

‒ Resolution: 10bit

‒ Conversion time: Min. 2.25μs /channel (When the conversion clock speed is 8MHz)

‒ Reference voltages are selectable

(V_DDpin / Internal reference voltage (V_REFI= Approximately 1.55V) / External reference voltage (V_REFpin))

‒ Selected channel repeat conversion

‒ Dedicated result register for each channel

‒ Interrupt determining by upper limit or lower limit threshold of conversion result

•

Voltage level supervisor (VLS)

‒ Accuracy: ±4%

‒ Threshold voltage: 12 selectable (from 1.85V to 4.00V)

‒ Functional Voltage level detection reset (VLS reset)

‒ Functional Voltage level detection interrupt (VLS0 interrupt)

Analog comparator

‒ Channel: 1channel

‒ Selectable interrupt from the comparator output (rising edge or falling edge)

‒ Selectable from sampling or without sampling

‒ Comparable with external 2 inputs

‒ Comparable with external input and internal reference voltage (0.8V)

•

D/A converter

‒ Channel: Max 1channel

‒ Resolution: 8bit

‒ Output impedance: 6k ohm(Typ.)

‒ R-2R ladder type

Buzzer

‒ 4 buzzer mode (Continuous sound, Single sound, Intermittent sound 1 and Intermittent sound 2)

‒ 8 frequencies (4.096kHz to 293Hz)

‒ 15 step duty (1/16 to 15/16)

‒ Selectable from positive logic buzzer output or negative logic buzzer output

•

CRC(Cyclic Redundancy Check) generator

‒ Generation equation: X¹⁶+X¹²+X⁵+1

‒ Selectable from LSB first or MSB first

‒ Built-in Automatic program memory CRC calculation mode in HALT mode

Safety Function(IEC60730/60335 Class B)

‒ RAM/SFR guard

‒ Automatic program memory CRC calculation

‒ RAM parity error detection

‒ ROM unused area access reset (instruction access)

‒ Clock mutual monitoring

‒ WDT counter monitoring

‒ SA-ADC test

‒ UART test

‒ Synchronous serial I/O test

‒ I²C bus test

‒ GPIO test

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• Shipping package

−

16-pin plastic SSOP

ML62Q1323/1324/1325 - xxxMB (Blank part: ML62Q1323/1324/1325-NNNMB)

16-pin plastic WQFN

ML62Q1323/1324/1325 - xxxGD (Blank part: ML62Q1323/1324/1325-NNNGD)

20-pin plastic TSSOP

ML62Q1323/1324/1325 - xxxGD (Blank part: ML62Q1323/1324/1325-NNNMB)

20-pin plastic SSOP

ML62Q1333/1334/1335 - xxxTD (Blank part: ML62Q1333/1334/1335-NNNTD)

24-pin plastic WQFN

ML62Q1345/1346/1347 - xxxGD (Blank part: ML62Q1345/1346/1347-NNNGD)

32-pin plastic TQFP

ML62Q1365/1366/1367 - xxxTB (Blank part: ML62Q1365/1366/1367-NNNTB)

32-pin plastic WQFN

ML62Q1365/1366/1367 - xxxGD (Blank part: ML62Q1365/1366/1367-NNNGD)

xxx: ROM code number

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ML62Q1300 Group how to read the part number

ML 62 Q 13 6 7 – xxx TB

Package Type

GD

MB

TB

:WQFN

:SSOP

:TQFP

:TSSOP

TD

ROM Code Number

NNN :Blank

xxx

:Custom Code Number

Program Memory Size

3

4

5

6

7

:16Kbyte

:24Kbyte

:32Kbyte

:48Kbyte

:64Kbyte

Pin Count

2

3

4

6

:16pin

:20pin

:24pin

:32pin

Group Name

13

:1300 Group

Program Memory Type

Q

:Flash Memory

CPU Type

62

:16bit CPU nX-U16/100

LAPIS Technology Logic Product

Figure 1 ML62Q1300 Group Part Number

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ML62Q1300 Group Main Function List

Table 2 ML62Q1300 Group Main Function List

Interrupt

Timer

Serial

Analog

Part number

ML62Q1323

ML62Q1324

ML62Q1325

ML62Q1333

ML62Q1334

ML62Q1335

ML62Q1345

ML62Q1346

ML62Q1347

ML62Q1365

ML62Q1366

ML62Q1367

16

20

24

32

12

16

20

28

11

15

19

27

6

8

23

4

0

1

3

1

8

4

2

1

2

25

6

*¹: One 16-bit timer is configurable as two 8-bit timers.

*²: Synchronous Communication unit includes UART and Synchronous Serial Port. UART mode and Synchronous

Serial Port can not be used at the same time in the same channel.

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BLOCK DIAGRAM

CPU（nX-U16/100）

ECSR1～3

DSR/CSR

PC

EPSW1～3

ELR1～3

LR

Multiplier/Divider

(Coprocessor)

GREG

0 ～15

PSW

EA

Timing

Controller

ALU

SP

Program

Memory

（FLASH）

BUS

Controller

Instruction

Decoder

Instruction

Register

On-Chip

ICE

V_DD

V_SS

INT

SU0~1_SCLK*

SU0~1_SIN*

RAM

SU0~1_SOUT0*

Serial

Communication

V_DDL

V_REFO

SU0~1_RXD0*

SU0~1_TXD0*

SU0~1_RXD1*

SU0~1_TXD1*

Unit *¹

Power

Circuit

Data FLASH

RESET_N

TEST0*²

SYSTEM

FLASH

INT

Controller

I²C Bus

Unit

I2CU0_SDA*

I2CU0_SCL*

INT

Clock

Generation

Circuit

OUTLSCLK*

OUTHSCLK*

Interrupt

INT

I²C Bus

Master

I2CM0_SDA*

I2CM0_SCL*

Low-speed

RC

Oscillation

INT

WDT

VLS

TMH0~5OUT*

16-Bit

Timer

High-speed

PLL

Oscillation

INT

EXTRIG0～7

FTM0~3P*

FTM0~3N*

RC

Oscillation

(for WDT)

Functional

Timer

DMA

Controller

CRC

Generator

INT

Low Speed

Time Base

Counter

V_DD

V_SS

V_REF

TBCOUT1*

SA-ADC

AIN0 to AIN5/7*

BZ0P*

BZ0N*

Buzzer

CMP0P*

CMP0M*

Analog

Comparator

Safety

Function

INT

PX0~PX7

（X= 0~3)

GPIO

(External Interrupt)

D/A

Converter *³

DACOUT0*

Reset

EXI0~7

Function

* : Indicates the shared function of general ports.

*1 : Shared UART and Synchronous Serial Port.

*2 : Not available as the input port when connecting to the on-chip debug emulator.

*3 : ML62Q133x and ML62Q132x does not have the peripheral circuits.

Figure 2 ML62Q1300 Group Block Diagram

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PIN CONFIGURATION

Pin Layout of ML62Q1323/1324/1325 16pin SSOP Package

P27/EXI7/EXTRG7

V_DD

V_SS

1

2

3

4

5

6

7

16

15

14

13

12

11

10

P26/EXI6/EXTRG6

P23/EXI5/EXTRG5/V_REF

V_DDL

RESET_N

P22

(TOP VIEW)

SSOP16

P21/EXI4/EXTRG4

P00/TEST0

P02/EXI0/EXTRG0

P03/EXI1/EXTRG1

P20

P17/EXI3/EXTRG3

P13

8

9

P04/EXI2/EXTRG2

Figure 3 Pin Layout of 16pin SSOP Package

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Pin Layout of ML62Q1323/1324/1325 16pin WQFN Package

12

11

10

9

8

7

6

5

P13

13

14

P23/EXI5/EXTRG5/V_REF

P26/EXI6/EXTRG6

P04/EXI2/EXTRG2

P03/EXI1/EXTRG1

P02/EXI0/EXTRG0

(TOP VIEW)

WQFN16

15

16

P27/EXI7/EXTRG7

V_DD

1

2

3

4

Figure 4 Pin Layout of 16pin WQFN Package

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Pin Layout of ML62Q1333/1334/1335 20pin TSSOP/SSOP Package

RESET_N

P00/TEST0

1

2

3

4

5

6

7

8

9

20 V_DDL

19 V_SS

18 V_DD

17 P33

P02/EXI0/EXTRG0

P03/EXI1/EXTRG1

P04/EXI2/EXTRG2

P05

P27/EXI7/EXTRG7

16

15

14

13

(TOP VIEW)

TSSOP20

SSOP20

P26/EXI6/EXTRG6

P13

P25

P24

P17/EXI3/EXTRG3

P20

12 P23/EXI5/EXTRG5/V_REF

P22

11

P21/EXI4/EXTRG4 10

Figure 5 Pin Layout of 20pin TSSOP/SSOP Package

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Pin Layout of ML62Q1345/1346/1347 24pin WQFN Package

18

17

16

15

14

13

19

20

21

22

23

24

P13

P24

12

P25

P26/EXI6/EXTRG6

P27/EXI7/EXTRG7

P32

11 P12

10 P05

(TOP VIEW)

WQFN24

P04/EXI2/EXTRG2

9

8

7

P03/EXI1/EXTRG1

P02/EXI0/EXTRG0

P33

1

2

3

4

5

6

Figure 6 Pin Layout of 24pin WQFN Package

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Pin Layout of ML62Q1365/1366/1367 32pin TQFP Package

24

23

22

21

20

19

18

17

25

26

27

28

P24

P25

16 P13

P12

P11

P10

15

14

13

P26/EXI6/EXTRG6

P27/EXI7/EXTRG7

(TOP VIEW)

TQFP32

P30

P31

P32

P33

29

30

31

12 P07

11

P06

10

P05

32

9

P04/EXI2/EXTRG2

1

2

3

4

5

6

7

8

Figure 7 Pin Layout of 32pin TQFP Package

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Pin Layout of ML62Q1365/1366/1367 32pin WQFN Package

24

23

22

21

20

19

18

17

16

15

P13

P12

P24 25

P25 26

P26/EXI6/EXTRG6 27

14 P11

13

P27/EXI7/EXTRG7

P30

28

29

P10

(TOP VIEW)

WQFN32

12 P07

11 P06

30

31

32

P31

P32

P33

P05

P04/EXI2/EXTRG2

10

9

8

1

2

3

4

5

6

7

Figure 8 Pin Layout of 32pin WQFN Package

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PIN LIST

Table 3 Pin List

Pin No.

2^nd

function

3^rd

function

4^th

function

5^th

function

Timers

6^th

function

Others

7^th

function function

Others ADC

8^th

name

(Primary

function)

Primary

function

Others

Communic Communi Communic

ations

（

）

cations

ations

1

16

18

1

V_DD

-

2

3

4

5

-

1

2

3

4

-

19

20

1

2

3

4

5

6

2

3

4

5

6

V_SS

V_DDL

-

RESET_N

P00

2

TEST0

DACOUT0

-

P01

EXI0

EXTRG0

SU0_RXD0

SU0_SIN

6

7

8

5

6

7

3

4

5

7

8

9

7

8

9

P02

P03

P04

-

FTM0P

FTM0N

OUTLSCLK CMP0M

OUTHSCLK CMP0P

-

EXI1

EXTRG1

SU0_TXD0

SU0_SOUT

SU0_TXD1 I2CU0_SDA

EXI2

EXTRG2

SU0_SCLK

-

I2CU0_SCL TMH0OUT

-

6

-

10

-

10

11

12

13

P05

P06

P07

P10

-

I2CM0_SDA

-

SU0_RXD1

SU0_TXD1

SU0_RXD0 I2CM0_SCL

-

14

15

P11

P12

-

SU0_SCLK

-

SU0_RXD0

SU0_SIN

11

-

TMH4OUT

SU0_TXD0

SU0_SOUT

9

8

7

12

16

P13

-

SU0_TXD1

TMH1OUT

-

TMH3OUT

-

13

17

18

19

P14

P15

P16

-

I2CU0_SDA

I2CU0_SCL TMH5OUT

SU1_SCLK

EXI3

EXTRG3

10

11

12

9

8

9

14

15

16

20

21

22

P17

P20

P21

SU0_RXD1

SU0_RXD0

-

FTM1P

FTM1N

FTM2P

-

BZ0P

BZ0N

-

AIN0

AIN1

AIN2

10

11

SU0_TXD1

-

TBCOUT1

OUTLSCLK

EXI4

EXTRG4

SU1_RXD0

SU1_SIN

10

SU1_TXD0

SU1_SOUT

13

14

12

13

11

12

17

18

23

24

P22

P23

-

SU1_TXD1 I2CM0_SDA

FTM2N

OUTHSCLK

-

AIN3

V_REFO

EXI5

EXTRG5

V_REF

SU1_SCLK

-

I2CM0_SCL

TMH2OUT

SU1_RXD0

SU1_SIN

SU1_TXD0

SU1_SOUT

-

13

14

15

16

19

20

21

22

25

26

27

28

P24

P25

P26

P27

-

AIN4

AIN5

AIN6

AIN7

-

SU1_TXD1

-

EXI6

EXTRG6

EXI7

EXTRG7

15

16

14

15

SU1_RXD1

SU1_TXD1

SU1_RXD0 I2CU0_SDA

FTM3P

FTM3N

-

BZ0P

BZ0N

-

I2CU0_SCL

TBCOUT1

-

23

29

30

31

P30

P31

P32

-

SU1_RXD1

SU1_RXD0

-

17

24

32

P33

-

SU1_TXD1

-

TMH3OUT

-

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PIN DESCRIPTION

Table 4 Pin Description (1/4)

Function

Power

Signal name Pin name

I/O

－

Description

Negative power supply pin (-)

Positive power supply pin (+). Connect a capacitor C_V

between this pin and V_SS.

Logic

－

V_SS

－

V_DD

－

Power supply pin for internal logic (internal regulator’s

output). Connect a capacitor C_L(1μF) between this pin and

V_SS.

－

V_DDL

－

Input for testing, is used as on-chip debug interface and ISP

function.

Test

TEST0

V_REFO

P00

P23

I/O

－

P00 is initialized as pull-up input mode by the system reset.

－

Reference voltage output

Reset input.

Applying “L” level shifts the MCU in system reset mode.

Applying “H” level shifts the CPU in program running mode.

Used for on-chip debug interface and ISP function.

RESET_N RESET_N

I

Negative

System

No pull-up resistor is installed.

P02

OUTLSCLK

P21

P03

OUTHSCLK

P22

O

Low-speed clock output.

－

High-speed clock output.

General purpose I/O port

- High-impedance

- Input with Pull-UP (initial value)

- Input without Pull-UP

- CMOS output

P00

I/O

Positive

- N-channel open drain output

Not available to use as I/O pin when using for on-chip debug

interface or ISP function.

General port

(GPIO)

P01 – P07 P01 – P07

P10 – P17 P10 – P17

General purpose I/O

- High-impedance (initial value)

- Input with Pull-UP

- Input without Pull-UP

- CMOS output

- N-channel open drain output

I/O

Positive

P20 – P27 P20 – P27

P30 – P33 P30 – P33

17/63

FEDL62Q1300-05

Table 4 Pin Description (2/4)

I/O

Function

Signal name Pin name

Description

Logic

P03

P13

SU0_TXD0

O

Serial communication unit0 UART0 data output

Positive

P02

P07

P12

P17

P03

P10

Serial communication unit0 Full-duplex data input

Serial communication unit0 UART0 data input

SU0_RXD0

I

Positive

Serial communication unit0 Full-duplex data output

Serial communication unit0 UART1 data output

SU0_TXD1

O

P13

P20

P07

P17

P22

P25

SU0_RXD1

I

Serial communication unit0 UART1 data input

Serial communication unit1 UART0 data output

Positive

UART

SU1_TXD0

O

P21

P24

P26

P32

P22

P25

Serial communication unit1 Full-duplex data input

Serial communication unit1 UART0 data input

SU1_RXD0

I

Positive

Serial communication unit1 Full-duplex data output

Serial communication unit1 UART1 data output

SU1_TXD1

O

P27

P33

P26

P32

P02

SU1_RXD1

I

Serial communication unit1 UART1 data input

Positive

Serial communication unit0 Synchronous serial data

input

SU0_SIN

P12

P04

SU0_SCLK

Serial communication unit0 Synchronous serial clock

I/O

O

Positive

P11

P03

SU0_SOUT

P13

Serial communication unit0 Synchronous serial data

output

Synchronous

Serial Port

P21

Serial communication unit1 Synchronous serial data

input

SU1_SIN

P24

I

P16

SU1_SCLK

Serial communication unit1 Synchronous serial clock

I/O

O

P23

P22

SU1_SOUT

P25

Serial communication unit1 Synchronous serial data

output

I²C Unit0 (Master and Salve) Data I/O

N-channel open drain

Connect a pull-up resistor externally

P03

I2CU0_SDA

I2CU0_SCL

P15

P26

P04

P16

P27

P06

I/O

Positive

I²C Unit0 (Master and Salve) Clock I/O

N-channel open drain output

Connect a pull-up resistor externally

I²C Master0 Data I/O pin

I²C Bus

I2CM0_SDA

I2CM0_SCL

I/O

N-channel open drain output

Connect a pull-up resistor externally

I²C Master0 Clock I/O

N-channel open drain output

Connect a pull-up resistor externally

Positive

P22

P07

P23

18/63

FEDL62Q1300-05

Logic

Table 4 Pin Description (3/4)

Function

Signal name Pin name

I/O

Description

FTM0P

FTM0N

FTM1P

FTM1N

FTM2P

FTM2N

FTM3P

FTM3N

EXTRG0

EXTRG1

EXTRG2

EXTRG3

EXTRG4

EXTRG5

EXTRG6

EXTRG7

TMH0OUT

TMH1OUT

TMH2OUT

P02

P03

P17

P20

P21

P22

P26

P27

P02

P03

P04

P17

P21

P23

P26

P27

P04

P13

P23

P13

P33

P12

P16

P02

P03

O

I

O

Functional Timer0 P output

Functional Timer0 N output

Functional Timer1 P output

Functional Timer1 N output

Functional Timer2 P output

Functional Timer2 N output

Functional Timer3 P output

Functional Timer3 N output

Functional Timer event trigger input

16bit General Timer 0 output

16bit General Timer 1 output

16bit General Timer 2 output

Positive

Negative

Positive

Negative

Positive

Negative

Positive

Negative

—

Functional Timer

(FTM)

—

Positive

16bit General

Timer

TMH3OUT

O

16bit General Timer 3 output

TMH4OUT

TMH5OUT

EXTRG0

O

I

16bit General Timer 4 output

16bit General Timer 5 output

16bit General Timer trigger input

Positive

—

EXTRG1

I

—

Low-Speed

Time Base

Counter (LTBC)

P20

TBCOUT1

O

Low-speed Time Base Counter output

Positive

P27

P17

P26

P20

P27

BZ0P

BZ0N

O

Buzzer output (positive phase)

Buzzer output (negative phase)

Positive

Buzzer

Negative

19/63

FEDL62Q1300-05

Logic

Table 4 Pin Description (4/4)

Function

Signal name Pin name

I/O

Description

EXI0

EXI1

EXI2

EXI3

EXI4

EXI5

EXI6

EXI7

V_REF

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

P02

P03

P04

P17

P21

P23

P26

P27

P23

P17

P20

P21

P22

P24

P25

P26

P27

P03

P02

P01

I

－

External interrupt 0 input

External interrupt 1 input

External interrupt 2 input

External interrupt 3 input

External interrupt 4 input

External interrupt 5 input

External interrupt 6 input

External interrupt 7 input

SA-ADC external reference voltage input

SA-ADC channel 0 input

SA-ADC channel 1 input

SA-ADC channel 2 input

SA-ADC channel 3 input

SA-ADC channel 4 input

SA-ADC channel 5 input

SA-ADC channel 6 input

SA-ADC channel 7 input

Comparator input 0 (noninverting input)

Comparator input 0 (inverting input)

D/A converter0 output

—

External Interrupt

I

Successive

approximation

type A/D

converter

CMP0P

CMP0M

DACOUT0

I

O

Analog

comparator

D/A converter

20/63

FEDL62Q1300-05

TERMINATION OF UNUSED PINS

Table 5 Termination of unused pins

pin termination

RESET_N

P00/TEST0

P01 to P07

P10 to P17

P20 to P27

P30 to P33

Connect to V_DD

Connect to V_DDwith initial state (pulled-up input mode)

Open with initial state(Hi-impedance)

Note:



Terminate unused input pins according to the table 5 in order to avoid unexpected through-current

in the pins.

21/63

FEDL62Q1300-05

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(V_SS= 0V)

Parameter

Power supply voltage 1

Power supply voltage 2

Input voltage

Symbol

Condition

Ta = +25°C

Rating

Unit

V

V_DD

V_DDL

V_IN

-0.3 to +6.5

-0.3 to +2.0

-0.3 to V_DD+0.3*¹

V

V_OUT

-0.3 to V_DD+0.3*¹

Output voltage

1pin

Total

1pin

-40*²

-150*²

+40

“H” level output current

“L” level output current

I_OUTH

I_OUTL

Ta = +25°C

mA

Ta = +25°C

Total

+150

1

Power dissipation

Storage temperature

*¹6.5V or lower

PD

W

T_STG

―

-55 to +150

°C

*²The current flowing out the LSI through the pin is described in the negative number.

The applicable maximum current is the absolute value.

For example, -1mA means the maximum current 1mA flows out the LSI through the pin.

[Note]

Stresses above the absolute maximum ratings listed in the above table may cause permanent damage to the device.

These are stress ratings only and functional operation of the device at these conditions is not implied.

Recommended Operating Conditions

(V_SS= 0V)

Parameter

Symbol

Ta

Condition

Range

Unit

°C

V

Operating temperature (Ambient)

―

-40 to +105

-40 to +115

Operating temperature (Chip-Junction)

Tj

Operating voltage

V_DD

―

1.6 to 5.5

30k to 4M

30k to 25M

1.0 ±30%

V_DD= 1.6 to 5.5V

V_DD= 1.8 to 5.5V

―

Operating frequency (CPU)

V_DDLpin external capacitance

f_OP

C_L

Hz

μF

22/63

FEDL62Q1300-05

Thermal characteristics

The maximum chip-junction temperature, T_jmax, may be calculated using the following equation.

푇

푗 푚ꢀꢁ

= 푇

+ 푃_{퐷 푚ꢀꢁ}× 휃

ꢀ 푚ꢀꢁ 푗ꢀ

푇

ꢀ 푚ꢀꢁ

: maximum ambient temperature

푃_{퐷 푚ꢀꢁ}: LSI maximum power dissipation

: Package junction to ambient thermal resistance

휃

푗ꢀ

Design a Mounting board by considering heat radiation such as power dissipation and ambient temperature to satisfy the

recommended conditions.

The following table shows the each package’s thermal resistance for thermal design reference estimated by simulation based

on the PCB (printed circuit board) conditions define as a below.

Value

Parameter

Symbol

Package type

Unit

L1

L2

SSOP16

WQFN16

TSSOP20

SSOP20

WQFN24

WQFN32

TQFP32

90.5

80.8

79.6

79.3

59.0

50.6

67.6

84.3

74.7

74.0

73.8

51.0

43.5

61.8

Thermal

θ_ja

^oC/W

resistance

PCB conditions:

PCB name

L1

L2

Unit

mm

layer

―

PCB size （L / W / T）

Number of layer

Wiring density

114.3 / 76.2 / 1.6

1

114.3 / 76.2 / 1.6

2

60% (top layer)

60%(top and bottom layer)

Wind condition

No wind (0m/s)

―

WQFN package’s thermal resistance is simulated on the condition that the exposed pad is soldered on the PCB.

23/63

FEDL62Q1300-05

Current Consumption 1

Product： ML62Q1323, ML62Q1324, ML62Q1325, ML62Q1333, ML62Q1334, ML62Q1335

(V_DD=1.6 to 5.5V, V_SS=0V, Ta=-40 to +105^oC, unless otherwise specified)

Measuri

Parameter

Symbol

IDD0

Condition

Min.

Typ. *³

0.60

Max.

Unit

ng

circuit

Ta = -40 to

+85 ^oC

―

17

36

20

42

CPU is in STOP-D state.

Low-speed RC1K/RC32K and

PLL oscillation are stopped.

Supply current 0

µA

Ta = -40 to

+105 ^oC

Ta = -40 to

+85 ^oC

CPU is in STOP state.

Low-speed RC1K/RC32K and

PLL oscillation are stopped.

Supply current 1

Supply current 2

IDD1

IDD2

µA

0.75

3.6

17

Ta = -40 to

+105 ^oC

Ta = -40 to

+85 ^oC

Low-speed RC32K Oscillating.

CPU is in HALT state (LTBC

and WDT are operating^*1). PLL

oscillation is stopped.

―

27

44

Ta = -40 to

+105 ^oC

1

CPU: Running with 32kHz RC

oscillation clock*¹*²

PLL oscillation is stopped.

Ta = -40 to

+105 ^oC

Supply current 3

Supply current 4

Supply current 5

IDD3

IDD4

IDD5

―

66

3.8

5.3

CPU: Running with 16MHz PLL

oscillating clock*¹*²

PLL 16MHz is oscillating.

V_DD=1.8~5.5V

Ta = -40 to

+105 ^oC

3.1

4.4

mA

CPU: Running with 24MHz PLL

oscillating clock*¹*²

Ta = -40 to

+105 ^oC

PLL 24MHz is oscillating.

V_DD=1.8~5.5V

1

2

*

LTBC and WDT is operating, Significant bits of BLKCON0-3 and BRECON0-3 registers are all “1”

CPU running in wait mode

*³On the condition of V_DD=3.0V, Ta=+25 ^oC

24/63

FEDL62Q1300-05

Current Consumption 2

Product： ML62Q1345, ML62Q1346, ML62Q1347, ML62Q1365, ML62Q1366, ML62Q1367

(V_DD=1.6 to 5.5V, V_SS=0V, Ta=-40 to +105^oC, unless otherwise specified)

Measuri

Parameter

Symbol

IDD0

Condition

Min.

Typ. *³

0.80

Max.

Unit

ng

circuit

Ta = -40 to

+85 ^oC

―

18

40

21

45

CPU is in STOP-D state.

Low-speed RC1K/RC32K and

PLL oscillation are stopped.

Supply current 0

µA

Ta = -40 to

+105 ^oC

Ta = -40 to

+85 ^oC

CPU is in STOP state.

Low-speed RC1K/RC32K and

PLL oscillation are stopped.

Supply current 1

Supply current 2

IDD1

IDD2

µA

0.95

4.3

20

Ta = -40 to

+105 ^oC

Ta = -40 to

+85 ^oC

―

33

50

Low-speed RC32K Oscillating.

CPU is in HALT state¹.

PLL oscillation is stopped.

Ta = -40 to

+105 ^oC

1

CPU: Running with 32kHz RC

oscillation clock*¹*²

PLL oscillation is stopped.

Ta = -40 to

+105 ^oC

Supply current 3

Supply current 4

Supply current 5

IDD3

IDD4

IDD5

―

70

4.8

7.0

CPU: Running with 16MHz PLL

oscillating clock*¹*²

PLL 16MHz is oscillating.

V_DD=1.8~5.5V

Ta = -40 to

+105 ^oC

4.3

6.4

mA

CPU: Running with 24MHz PLL

oscillating clock*¹*²

Ta = -40 to

+105 ^oC

PLL 24MHz is oscillating.

V_DD=1.8~5.5V

1

2

*

LTBC and WDT is operating, Significant bits of BCKCON0-3 and BRECON0-3 registers are all “1”

CPU running in wait mode

*³On the condition of V_DD=3.0V, Ta=+25^oC

25/63

FEDL62Q1300-05

On-chip Oscillator

(V_DD=1.6 to 5.5V, V_SS=0V, Ta=−40 to +105^οC, unless otherwise specified)

Measur

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

ing

circuit

Ta= +25°C

Typ.

-1.0%

Typ.

-2.5%

Typ.

-3.0%

Typ.

-3.5%

Typ.

-1.0%

Typ.

-1.5%

Typ.

-2.5%

Typ.

-3.0%

Typ.

+1.0%

Typ.

+2.5%

Typ.

+3.0%

Typ.

-3.5%

Typ.

+1.0%

Typ.

+1.5%

Typ.

+2.5%

Typ.

+3.0%

Typ.

32.768

16/24

V_DD= 1.8 to 5.5V

Ta= -40 to +85°C

V_DD= 1.8 to 5.5V

Ta= -40 to +105°C

V_DD= 1.8 to 5.5V

Low-speed RC oscillator

frequency accuracy 1

f_RCL1

Without software adjustment

kHz

V_DD= 1.6 to 1.8V

Ta= -40 to +85°C

V_DD= 1.8 to 5.5V

Ta= -40 to +105°C

V_DD= 1.8 to 5.5V

Ta= -40 to +85°C

V_DD= 1.8 to 5.5V

Ta= -40 to +105°C

V_DD= 1.8 to 5.5V

Low-speed RC oscillator

frequency accuracy 2

With software adjustment

f_RCL2

f_PLL1

f_PLL2

1

PLL oscillation frequency

accuracy 1

Without software adjustment

16/24

V_DD= 1.6 to 1.8V

16/24

MHz

-3.5%

Typ.

-1.0%

Typ.

-1.5%

―

+3.5%

Typ.

+1.0%

Typ.

+1.5%

2

Ta= -40 to +85°C

V_DD= 1.8 to 5.5V

Ta= -40 to +105°C

V_DD= 1.8 to 5.5V

V_DD= 1.6 to 5.5V

Ta= -40 to +105°C

V_DD= 1.6 to 5.5V

16/24

PLL oscillation frequency

accuracy 2

With software adjustment

16/24

―

PLL oscillation start time

T_PLL

ms

1kHz Low-speed RC oscillator

(for WDT) frequency accuracy

f_RC1K

0.5

1

2.5

kHz

26/63

FEDL62Q1300-05

Input / Output pin 1

(V_DD=1.6 to 5.5V, V_SS=0V, Ta=−40 to +105^οC, unless otherwise specified)

Measur

Parameter

Symbol

VOH1

Condition

Min.

Typ.

Max.

Unit

ing

circuit

IOH1=-10mA

V_DD≥4.5V

V_DD

-1.5

V_DD

-0.5

―

Output voltage1

“H”/”L” level

(P00-P07)

IOH1=-1mA

V_DD≥1.6V

IOL1=+10mA

V_DD≥4.5V

(P10-P17)

(P20-P27)

―

1.5

VOL1

VOL2

(P30-P33)

IOL1=+1mA

V_DD≥1.6V

―

0.5

0.7

0.5

0.4

V

2

IOL2=+15mA

V_DD≥4.5V

IOL2=+8mA

V_DD≥3.0V

Output voltage2

“L” level

When Nch open

drain output

mode is selected

(P01-P07)

(P10-P17)

(P20-P27)

(P30-P33)

IOL2=+3mA

V_DD≥2.0V

IOL2=+2mA

V

―

0.4

_DD≥1.6V

27/63

FEDL62Q1300-05

Input / Output pin 2

(V_DD=1.6 to 5.5V, V_SS=0V, Ta=−40 to +105^οC, unless otherwise specified)

Measu

Parameter

Symbol

IOH1

Condition

Min.

Typ.

Max.

Unit

ring

circuit

V_DD≥4.5V

V_DD≥1.6V

-10*³*⁵

-1*³*⁵

―

“H” level output

current1 *⁶

1pin

Total of ‘P00-P07

andP10-P13

V_DD≥4.5V

-50*⁵

―

or

Total of ‘P14-P17,

P20-P27 and P30-P33

(Duty≤50%)

“H” level output

current *¹*⁴

IOH3

V_DD≥1.6V

-20*⁵

―

V_DD≥4.5V

V_DD≥1.6V

V_DD≥4.5V

V_DD≥1.6V

V_DD≥4.5V

V_DD≥3.0V

V_DD≥2.0V

V_DD≥1.6V

-100*⁵

-40*⁵

―

All pin total

(Duty≤50%)

10*³

1*³

15*³

8*³

3*³

2*³

“L” level output

current1 *⁶

1pin

IOL1

IOL2

(CMOS output mode)

―

mA

―

1pin

(Nch open drain output

mode)

―

“L” level output

current2 *⁶

―

3

Total of P00-P07 and

P10-P13

V

_DD≥4.5V

―

60

40

15

V_DD≥3.0V

V_DD≥2.0V

or

Total of P14-P17,

P20-P27 and P30-P33

(Nch open drain output

mode, duty≤50%)

“L” level output

IOL3

total current *²*⁴

V_DD≥1.6V

―

10

All pin total

(Nch open drain output

mode, duty≤50%)

V_DD≥4.5V

V_DD≥1.6V

―

120

20

Output leak

(P00-P07)

(P10-P17)

(P20-P27)

(P30-P33)

IOOH

IOOL

VOH=V_DD(High impedance mode)

―

+1

μA

VOL=V_SS(High impedance mode)

-1*⁵

―

*¹Sink-out current from V_DDto the output pin, which can guarantee the device operation.

*²Sink-in current from the output pin to V_SS, which can guarantee the device operation.

*³Do not exceed total current.

*⁴The total current is on the condition of Duty≤50%(same applies to IOH1).

When the duty>50% the total current is calculated by following formula.

Total current = IOL3 x 50/n (When the duty is n%)

<For an example> When IOL3=100mA and n=80%,

Total current = IOL3 x 50/80 = 62.5mA

Current allowed per 1pin is independent of the duty and specified as IOL1 and IOL2.

Do not apply current larger than Absolute Maximum Ratings.

*⁵The current flowing out the LSI through the pin is described in the negative number.

The applicable maximum current is the absolute value.

For example, -1mA means the maximum current 1mA flows out the LSI through the pin.

*⁶These values are satisfied with VOH1, VOL1 and VOL2.

28/63

FEDL62Q1300-05

Input / Output pin 3

(V_DD=1.6 to 5.5V, V_SS=0V, Ta=−40 to +105^οC, unless otherwise specified)

Measur

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

ing

circuit

IIH1

IIL1

VIH1=V_DD

―

1

Input current1

(RESET_N)

VIL1=V_SS

-1*¹

―

μA

kΩ

μA

IIL2

VIL2=V_SS(pull-up mode) ^*2

VIH2=V_DD(High impedance mode)

VIL2=V_SS(High impedance mode)

VIL1=V_SS(pull-up mode) ^*2

VIH1=V_DD(High impedance mode)

-1500*¹-300*¹-20*¹

V/IIL2

IIH2Z

IIL2Z

IIL3

3.7

―

-1*¹

-250*¹

22

10

―

80

1

Input current2

(P00/TEST0)

4

―

Input current3

(P01-P07)

(P10-P17)

(P20-P27)

(P30-P33)

-30*¹

100

―

-2*¹

800

1

V/IIL3

IIH3Z

kΩ

μA

―

IIL3Z

VIL1=V_SS(High impedance mode)

-1*¹

―

Input voltage1

(RESET_N)

(P01-P07)

(P10-P17)

(P20-P27)

(P30-P33)

0.7

x V_DD

VIH1

―

V_DD

0.3

x V_DD

VIL1

―

0

―

V

5

0.7

x V_DD

VIH2

VIL2

―

V_DD

Input voltage2

(P00/TEST0)

0.25

x V_DD

0

Pin capacitance

(RESET_N)

(P00/TEST0)

(P01-P07)

f = 10kHz

Ta = +25°C

CPIN

―

10

pF

―

(P10-P17)

(P20-P27)

(P30-P33)

*¹The current flowing out the LSI through the pin is described in the negative number.

The applicable maximum current is the absolute value.

For example, -1mA means the maximum current 1mA flows out the LSI through the pin.

^*2Measurement conditions: Typ. : V_DD= 3.0V, Max. : V_DD= 1.6V, Min. : V_DD= 5.5V

29/63

FEDL62Q1300-05

Synchronous Serial Port

Slave mode

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=−40 to +105^οC, unless otherwise specified)

Parameter

SCK input cycle

SCK input pulse width

Symbol

t_SCYC

t_SW

Condition

Min.

Typ.

―

Max.

―

Unit

µs

―

1 *²

0.5 *³

100+

V_DD=2.4 to 5.5V

―

ns

HSCLK*¹×3

200+

SOUT output delay time

SIN input setup time

t_SD

V_DD=1.8 to 5.5V

―

HSCLK*¹×3

HSCLK*¹

x1

t_SS

t_SH

―

80+

SIN input hold time

HSCLK*¹×3

*¹Cycle of high speed clock

*²Need input cycles of HSCLK x8 or longer

*³Need input cycles of HSCLK x4 or longer

t_SCYC

t_SW

0.7×V_DD

0.3×V_DD

SUn_SCLK*

t_SD

0.7×V_DD

0.3×V_DD

SUn_SOUT*

t_SS

t_SH

0.7×V_DD

0.3×V_DD

SUn_SIN*

* 2^ndto 8^thfunction of port, n=0~1

30/63

FEDL62Q1300-05

Master mode

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=−40 to +105^οC, unless otherwise specified)

Parameter

SCK output cycle

Symbol

t_SCYC

Condition

Min.

Typ.

Max.

Unit

ns

―

SCLK*¹

×0.4

―

SCLK*¹

×0.5

―

SCLK*¹

×0.6

100

160

―

SCK output pulse width

t_SW

t_SD

t_SS

t_SH

―

ns

V_DD=2.4 to 5.5V

V_DD=1.8 to 5.5V

V_DD=2.4 to 5.5V

V_DD=1.8 to 5.5V

V_DD=2.4 to 5.5V

V_DD=1.8 to 5.5V

ns

SOUT output delay time

SIN input setup time

SIN input hold time

―

120

180

80

―

100

―

*¹Clock cycle selected by bit12~8(SnCK4~0) of the serial port n mode register (SIOnMOD)

V_DD≥2.4V: min250ns , V_DD≥1.8V: min500ns

t_SCYC

t_SW

0.7×V_DD

0.3×V_DD

SUn_SCLK*

SUn_SOUT*

SUn_SIN*

t_SD

0.7×V_DD

0.3×V_DD

t_SS

t_SH

0.7×V_DD

0.3×V_DD

* 2^ndto 8^thfunction of port, n=0~1

31/63

FEDL62Q1300-05

I²C Bus Interface

Standard Mode (100k bit/s)

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=−40 to +105^οC, unless otherwise specified)

Parameter

SCL clock frequency

SCL hold time

(start/restart condition)

SCL ”L” level time

SCL ”H” level time

SCL setup time

(restart condition)

SDA hold time

Symbol

Condition

Min.

0

Typ.

―

Max.

100

Unit

kHz

f_SCL

―

t_HD:STA

―

4.0

―

µs

t_LOW

t_HIGH

―

4.7

4.0

―

µs

t_SU:STA

―

4.7

―

µs

t_HD:DAT

t_SU:DAT

―

0

0.25

―

µs

SDA setup time

(stop condition)

Bus-free time

t_SU:STO

―

4.0

―

µs

t_BUF

―

4.7

―

When using the I²C as the master, configure the I²C master n mode register (I2MnMOD) and I²C bus 0 mode register

(master side, I2UM0MOD) so that meet these specifications.

Start

Condition

Re-start

Condition

Stop

Condition

0.7×V_DD

0.3×V_DD

I2CU0_SDA

I2CM0_SDA

0.7×V_DD

0.3×V_DD

I2CU0_SCL

I2CM0_SCL

t_SU:STO

t_BUF

t_HD:STA

t_LOW

t_SU:STAt_HD:STA

t_SU:DATt_HD:DAT

t_HIGH

32/63

FEDL62Q1300-05

Fast Mode (400k bit/s)

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=−40 to +105^οC, unless otherwise specified)

Parameter

SCL clock frequency

SCL hold time

(start/restart condition)

SCL ”L” level time

SCL ”H” level time

SCL setup time

(restart condition)

SDA hold time

Symbol

Condition

Min.

0

Typ.

―

Max.

400

Unit

kHz

f_SCL

―

t_HD:STA

―

0.6

―

µs

t_LOW

t_HIGH

―

1.3

0.6

―

µs

t_SU:STA

―

0.6

―

µs

t_HD:DAT

t_SU:DAT

―

0

0.1

―

µs

SDA setup time

(stop condition)

Bus-free time

t_SU:STO

―

0.6

―

µs

t_BUF

―

1.3

―

When using the I²C as the master, configure the I²C master n mode register(I2MnMOD) and I²C bus 0 mode register

(master side, I2UM0MOD) so that meet these specifications.

Start

Condition

Re-start

Condition

Stop

Condition

0.7×V_DD

0.3×V_DD

I2CU0_SDA

I2CM0_SDA

0.7×V_DD

0.3×V_DD

I2CU0_SCL

I2CM0_SCL

t_SU:STO

t_BUF

t_HD:STA

t_LOW

t_SU:STAt_HD:STA

t_SU:DATt_HD:DAT

t_HIGH

33/63

FEDL62Q1300-05

1Mbps Mode (1M bit/s)

(V_DD=2.7 to 5.5V, V_SS=0V, Ta=−40 to +105^οC, unless otherwise specified)

Parameter

SCL clock frequency

SCL hold time

(start/restart condition)

SCL ”L” level time

SCL ”H” level time

SCL setup time

(restart condition)

SDA hold time

Symbol

Condition

Min.

0

Typ.

―

Max.

1000

Unit

kHz

f_SCL

―

t_HD:STA

―

0.26

―

µs

t_LOW

t_HIGH

―

0.5

0.26

―

µs

t_SU:STA

―

0.26

―

µs

t_HD:DAT

t_SU:DAT

―

0

0.1

―

µs

SDA setup time

(stop condition)

Bus-free time

t_SU:STO

―

0.26

―

µs

t_BUF

―

0.5

―

When using the I²C as the master, configure the I²C master n mode register(I2MnMOD) and I²C bus 0 mode register

(master side, I2UM0MOD) so that meet these specifications.

Start

Condition

Re-start

Condition

Stop

Condition

0.7×V_DD

0.3×V_DD

I2CU0_SDA

I2CM0_SDA

0.7×V_DD

0.3×V_DD

I2CU0_SCL

I2CM0_SCL

t_SU:STO

t_BUF

t_HD:STA

t_LOW

t_SU:STAt_HD:STA

t_SU:DATt_HD:DAT

t_HIGH

34/63

FEDL62Q1300-05

Reset

(V_DD=1.6 to 5.5V, V_SS=0V, Ta=−40 to +105^οC, unless otherwise specified)

Measur

ing

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

circuit

Reset pulse width^*2

P00 ”H” level setup time^*1

P00 ”H” level hold time^*1

P_RST

t_SP00

t_HP00

―

2

1

―

ms

1

^*1： except ISP mode. Refer to the User’s manual “25.4 In-System Programing Function” for the timing in ISP mode.

^*2： VDD=1.6V or over at power on

VIH1

VIL1

RESET_N

*2

P_RST

“H” level or “L” level

“H” level input

t_SP00t_HP00

P00/TEST0

Note:



RESET_N input shorter pulse than the Reset pulse width (P_RST) valid time should be avoided.

The shorter pulse input may cause unexpected behavior.

35/63

FEDL62Q1300-05

Slope of Power supply and Power On Reset

(VSS =0V, −40 to +105^οC, unless otherwise specified)

Measur

ing

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

circuit

Power on rising slope

Power on falling slope

S_VR

S_VF

―

60

2

V/ms

Power on reset detection

voltage

V_PORR

V_PORF

At Power up (rising)

At Power down (falling)

1.47

1.33

1.57

1.49

1.80

1.58

V

1

Power on reset minimum

pulse width

P_POR

V_INIT

―

200

1.8

―

μs

Power on voltage

At power on

V

CPU operation start time

(from the release of reset to

the CPU starts to run）

t_CPUI

―

11

16

―

ms

―

At Power supply voltage level change

S_VR

At Power supply restart

S_VF

S_VR

V_DD

V_INIT

V_PORR

V_PORF

0V

P_POR

t_CPUI

At Power off

At power on

Note:



If a pulse shorter than the Power on reset minimum pulse width is asserted to V_DD, it may cause the

MCU malfunction.

Apply prevent measurement such as bypass capacitors or external reset input, and so on.

Start the high-speed clock when the V_DDis within the operating voltage.



36/63

FEDL62Q1300-05

VLS

(V_DD=1.6 to 5.5V, V_SS=0V, Ta=−40 to +105^οC, unless otherwise specified)

Condition

VLS0LV *¹

Measuring

circuit

Parameter

Symbol

Min.

Typ.

Max.

Unit

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

I_VLS

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

3.86

3.84

3.57

3.55

2.94

2.92

2.85

2.83

2.75

2.73

2.66

2.64

2.56

2.54

2.46

2.44

2.37

2.35

1.98

1.96

1.89

1.87

1.79

1.77

―

4.06

4.00

3.76

3.70

3.11

3.05

3.01

2.95

2.91

2.85

2.81

2.75

2.71

2.65

2.61

2.55

2.51

2.45

2.11

2.05

2.01

1.95

1.91

1.85

50

4.26

4.16

3.95

3.85

3.28

3.18

3.17

3.07

2.97

2.96

2.86

2.76

2.66

2.65

2.55

2.24

2.14

2.13

2.03

1.93

―

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

VLS threshold

voltage *²

V

1

VLS Current

―

nA

*¹Bit3~Bit0 of voltage level detection circuit 0 level register (VLS0LV).

*²The Data VLS0LV = 0CH~0FH is not available to use, if the data is specified it will the same spec as that 0BH is

specified.

Analog Comparator

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105^oC, unless otherwise specified)

Measuring

Parameter

Symbol

V_CMR

Condition

Min.

Typ.

Max.

Unit

circuit

Comparator same

phase input

voltage range

V_DD

-1.5

―

0.1

―

V

Comparator0

input offset

V_CMOF

Ta=+25 ^oC, V_DD=5.0V

―

5

―

mV

V

1

Comparator

Reference

Voltage

―

V_CMREF

0.75

0.8

0.85

37/63

FEDL62Q1300-05

Successive Approximation Type A/D Converter

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105^oC, unless otherwise specified)

Parameter

Resolution

Overall error

Symbol

n_AD

―

Condition

―

Min.

―

-3.5

-4

Typ.

―

1.2

―

Max.

10

3.5

4

Unit

bit

4.5V≤Reference voltage*¹≤5.5V

2.7V≤ Reference voltage*¹≤5.5V

2.2V≤ Reference voltage*¹＜2.7V

1.8V≤ Reference voltage*¹＜2.2V

Reference voltage =Internal

reference voltage

-6

―

6

Integral non-linearity

error

INL_AD

-10

―

10

-15

―

15

2.7V≤ Reference voltage*¹≤5.5V

2.2V≤ Reference voltage*¹＜2.7V

1.8V≤ Reference voltage*¹＜2.2V

Reference voltage =Internal

reference voltage

-3

-5

-9

―

3

5

9

LSB

Differential non-linearity

error

DNL_AD

-14

―

14

Zero-scale error

Full-scale error

ZSE

FSE

V_REF

V_REFI

RI≤1kΩ

-6

―

6

RI≤1kΩ

6

A/D reference voltage

Internal reference voltage

―

1.8

1.5

2.25

4.5

18

―

V_DD

1.6

427

V

―

1.55

―

4.5V≤V_DD≤5.5V

Conversion time

t_CONV

μs

2.2V≤V_DD≤5.5V

1.8V≤V_DD≤5.5V

―

*¹: V_DDor P23/V_REFis selected for the reference voltage of Successive Approximation Type A/D Converter.

The current flows during the ADC sampling as it takes charging. Make the output impedance of the analog signal source 1kΩ

or smaller. Also, putting 0.1uF capacitor on the ADC input pin is recommended to reduce the noise.

V_DD

V_DDL

1.0μF

A

RI≤1kΩ

0.1μF

-

1.0μF

AINn

+

Analog input

V_SS

38/63

FEDL62Q1300-05

D/A Converter

Parameter

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105^oC, unless otherwise specified)

Symbol

n_DA

Condition

―

Min.

―

Typ.

―

Max.

8

Unit

bit

Resolution

Conversion cycle

tc

―

10

―

μs

Integral non-linearity error

INL_DA

RL=4MΩ

-2

―

2

LSB

Differential non-linearity

error

DNL_DA

Ro

RL=4MΩ

―

-1

3

―

1

9

Output impedance

6

kΩ

Reference Voltage Output

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105^oC, unless otherwise specified)

Parameter

Output voltage

Output impedance

Symbol

V_REFO

R_VREFO

Condition

Min.

―

Typ.

1.55

―

Max.

―

500

Unit

V

kΩ

―

Flash Memory

(V_SS= 0V)

Unit

Parameter

Symbol

T_OP

Condition

Data flash memory, At write/erase

Flash ROM, At write/erase

At write/erase

Range

-40 to +85

0 to +40

+1.8 to +5.5

10000

100

Operating temperature

Operating voltage

°C

V

V_DD

CEPD

CEPP

Data Flash (4Kbyte)

Program Flash

Maximum rewrite count

times

Program Flash

Block erase

16K

All area

1K

―

B

Data Flash

Erase unit

Program Flash

Sector erase

Data Flash

128

Block erase /

Sector erase

Program Flash

Data Flash

Program Flash

Data Flash

―

Erase time (Max.)

Write unit

50

ms

B

4

1

―

YDR

80

40

15

Write time (Max.)

μs

Data retention period

years

39/63

FEDL62Q1300-05

Measuring circuit

Measuring circuit 1

C_V:1.0μF

C_L:1.0μF

V_DD

V_DDL

V_SS

A

C_V

C_L

Measuring circuit 2

(*2)

VIH

V

(*1)

Current

load

VIL

V_DD

V_DDL

V_SS

(*1) Input logic circuit to determine the specified measuring conditions

(*2) Measured connecting specified pins

Measuring circuit 3

VIH

(*2)

A

(*1)

VIL

V_DD

V_DDL

V_SS

(*1) Input logic circuit to determine the specified measuring conditions

(*2) Measured connecting specified pins

40/63

FEDL62Q1300-05

Measuring circuit 4

(*2)

A

V_DD

V_SS

V_DDL

(*2) Measured connecting specified pins

Measuring circuit 5

VIH

(*1)

VIL

V_DD

V_DDL

V_SS

(*1) Input logic circuit to determine the specified measuring conditions

41/63

FEDL62Q1300-05

Characteristics graphs

These Graphs on the following pages are references for designing an application.

42/63

FEDL62Q1300-05

IOH vs V_DD-VOH1 (V_DD=5V TYP.)

IOH vs VDD-VOH1 (VDD=5V TYP.)

-40[℃]

25[℃]

85[℃]

105[℃]

5

4

3

2

1

0

-60

-50

-40

-30

-20

-10

0

IOH[mA]

IOH vs V_DD-VOH1 (V_DD=3V TYP.)

IOH vs VDD-VOH1 (VDD=3V TYP.)

-40[℃]

25[℃]

85[℃]

105[℃]

3

2.5

2

1.5

1

0.5

0

-30

-25

-20

-15

-10

-5

0

IOH[mA]

43/63

FEDL62Q1300-05

IOL vs VOL1 (V_DD=5V TYP.)

IOL vs VOL1 (VDD=5V TYP.)

-40[℃]

25[℃]

85[℃]

105[℃]

5

4

3

2

1

0

10

20

30

40

50

IOL[mA]

IOL vs VOL1 (V_DD=3V TYP.)

IOL vs VOL1 (VDD=3V TYP.)

-40[℃]

25[℃]

85[℃]

105[℃]

3

2.5

2

1.5

1

0.5

0

5

10

15

20

IOL[mA]

44/63

FEDL62Q1300-05

IOL vs VOL2 (V_DD=5V TYP.)

IOL vs VOL2 (VDD=5V TYP.)

-40[℃]

25[℃]

85[℃]

105[℃]

5

4

3

2

1

0

20

40

60

80

100

IOL[mA]

IOL vs VOL2 (V_DD=3V TYP.).

IOL vs VOL2 (VDD=3V TYP.)

-40[℃]

25[℃]

85[℃]

105[℃]

3

2.5

2

1.5

1

0.5

0

10

20

30

40

50

IOL[mA]

45/63

FEDL62Q1300-05

V_DDvs IIL2 (TYP. VIL2=V_SS)

VDD vs IIL2 (TYP. VIL2=VSS)

-40℃

25℃

85℃

105℃

0

-100

-200

-300

-400

-500

-600

-700

1

2

3

4

5

6

VDD[V]

Pull-up resistor

V_DDvs V_DD/IIL2 (TYP. VIL2=V_SS)

Pull-up resistor

VDD vs VDD/IIL2 (TYP. VIL2=VSS)

-40℃

25℃

85℃

105℃

14

12

10

8

6

4

2

0

1

2

3

4

5

6

VDD[V]

46/63

FEDL62Q1300-05

V_DDvs IIL3 (TYP. VIL3=V_SS)

VDD vs IIL3 (TYP. VIL3=VSS)

-40℃

25℃

85℃

105℃

0

-50

-100

-150

-200

1

2

3

4

5

6

VDD[V]

Pull-up resistor

V

_DDvs V_DD/IIL3 (TYP. VIL3=V_SS)

Pull-up resistor

VDD vs VDD/IIL3 (TYP. VIL3=VSS)

-40℃

25℃

85℃

105℃

350

300

250

200

150

100

50

0

1

2

3

4

5

6

VDD[V]

47/63

FEDL62Q1300-05

Product： ML62Q1323, ML62Q1324, ML62Q1325, ML62Q1333, ML62Q1334, ML62Q1335

Current consumption vs operating frequency of CPU

V_DD=3V, temp=25℃ CPU 16MHz Wait mode (TYP.)

Stop the clock supply to peripherals.

Current consumption VS operating frequency of CPU

VDD=3V, temp=25^oC CPU 16MHz Wait mode (TYP.)

Stop the clock supply to peripherals.

3.5

3

2.5

2

1.5

1

0.5

0

5

10

15

20

operating frequency of CPU [MHz]

V

_DD=3V, temp=25℃ CPU 16MHz no Wait mode (TYP.)

Current consumption VS operating frequency of CPU

VDD=3V, temp=25^oC CPU 16MHz no Wait mode (TYP.)

Stop the clock supply to peripherals.

2.5

2

1.5

1

0.5

0

2

4

6

8

10

operating frequency of CPU [MHz]

48/63

FEDL62Q1300-05

Product： ML62Q1323, ML62Q1324, ML62Q1325, ML62Q1333, ML62Q1334, ML62Q1335

Current consumption vs operating frequency of CPU

V_DD=3V, temp=25℃ CPU 24MHz Wait mode (TYP.)

Stop the clock supply to peripherals.

Current consumption VS operating frequency of CPU

VDD=3V, temp=25^oC CPU 24MHz Wait mode (TYP.)

Stop the clock supply to peripherals.

5

4

3

2

1

0

5

10

15

20

25

30

operating frequency of CPU [MHz]

V

_DD=3V, temp=25℃ CPU 24MHz no Wait mode (TYP.)

Current consumption VS operating frequency of CPU

VDD=3V, temp=25^oC CPU 24MHz no Wait mode (TYP.)

Stop the clock supply to peripherals.

2

1.5

1

0.5

0

1

2

3

4

5

6

7

operating frequency of CPU [MHz]

49/63

FEDL62Q1300-05

Product： ML62Q1345, ML62Q1346, ML62Q1347, ML62Q1365, ML62Q1366, ML62Q1367

Current consumption vs operating frequency of CPU

V_DD=3V, temp=25°C CPU 16MHz Wait mode (TYP.)

Stop the clock supply to peripherals.

Current consumption VS operating frequency of CPU

VDD=3V, temp=25^oC CPU 16MHz Wait mode (TYP.)

Stop the clock supply to peripherals.

5

4

3

2

1

0

5

10

15

20

operating frequency of CPU [MHz]

V_DD=3V, temp=25°C CPU 16MHz no Wait mode (TYP.)

Current consumption VS operating frequency of CPU

VDD=3V, temp=25^oC CPU 16MHz no Wait mode (TYP.)

Stop the clock supply to peripherals.

3

2.5

2

1.5

1

0.5

0

2

4

6

8

10

operating frequency of CPU [MHz]

50/63

FEDL62Q1300-05

Product： ML62Q1345, ML62Q1346, ML62Q1347, ML62Q1365, ML62Q1366, ML62Q1367

Current consumption vs operating frequency of CPU

V_DD=3V, temp=25 ^oC CPU 24MHz Wait mode (TYP.)

Stop the clock supply to peripherals.

Current consumption VS operating frequency of CPU

VDD=3V, temp=25^oC CPU 24MHz Wait mode (TYP.)

Stop the clock supply to peripherals.

7

6

5

4

3

2

1

0

5

10

15

20

25

30

operating frequency of CPU [MHz]

V_DD=3V, temp=25 ^oC CPU 24MHz no Wait mode (TYP.)

Current consumption VS operating frequency of CPU

VDD=3V, temp=25^oC CPU 24MHz no Wait mode (TYP.)

Stop the clock supply to peripherals.

2.5

2

1.5

1

0.5

0

1

2

3

4

5

6

7

operating frequency of CPU [MHz]

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FEDL62Q1300-05

Consumption current of ADC vs operating voltage

PLL frequency=16MHz temp=25 ^oC ch0 V_REF=V_DD

consumption current of ADC

(PLL frequency=16MHz temp=25^oC ch0 VREF=VDD )

1.2

1

0.8

0.6

0.4

0.2

0

2

2.5

3

3.5

VDD [V]

4

4.5

5

5.5

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FEDL62Q1300-05

TEMP vs Low-speed RC oscillator frequency accuracy 1

without software adjustment (Typ.)

Low-speed RC oscillator frequency accuracy 1

without software adjustment (Typ.)

VDD=1.8V

VDD=3V

VDD=5.5V

4

3

2

1

0

-1

-2

-3

-4

-40

-20

0

20

40

Temp[^oC]

60

80

100

TEMP vs PLL oscillator frequency accuracy 1

without software adjustment (24MHz Typ.)

PLL oscillator frequency accuracy 1

without software adjustment (24MHz Typ.)

VDD=1.8V

VDD=3V

VDD=5.5V

4

3

2

1

0

-1

-2

-3

-4

-40

-20

0

20

40

60

80

100

Temp[^oC]

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FEDL62Q1300-05

PACKAGE DIMENSIONS

ML62Q1323/1324/1325 16pin SSOP Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,

before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package

code and desired mounting conditions (reflow method, temperature and times).

54/63

FEDL62Q1300-05

ML62Q1323/1324/1325 16pin WQFN Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,

before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package

code and desired mounting conditions (reflow method, temperature and times).

Note for the package with exposed die pad

The die pad is exposed on the bottom of WQFN package. Make the die pad electrically open when soldering onto the PCB.

55/63

FEDL62Q1300-05

ML62Q1333/1334/1335 20pin TSSOP Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,

before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package

code and desired mounting conditions (reflow method, temperature and times).

56/63

FEDL62Q1300-05

ML62Q1333/1334/1335 20pin SSOP Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,

before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package

code and desired mounting conditions (reflow method, temperature and times).

57/63

FEDL62Q1300-05

ML62Q1345/1346/1347 24pin WQFN Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,

before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package

code and desired mounting conditions (reflow method, temperature and times).

Note for the package with exposed die pad

The die pad is exposed on the bottom of WQFN package. Make the die pad electrically open when soldering onto the PCB.

58/63

FEDL62Q1300-05

ML62Q1365/1366/1367 32pin TQFP Package

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,

before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package

code and desired mounting conditions (reflow method, temperature and times).

59/63

FEDL62Q1300-05

ML62Q1365/1366/1367 32pin WQFN Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,

before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package

code and desired mounting conditions (reflow method, temperature and times).

Note for the package with exposed die pad

The die pad is exposed on the bottom of WQFN package. Make the die pad electrically open when soldering onto the PCB.

60/63

FEDL62Q1300-05

REVISION HISTORY

Page

Previous Current

Document

No.

Date

Description

Edition

FEDL62Q1300-01

Nov 15, 2018

Sep 27, 2019

-

1^stRevision.

Changed the products status (Table 1 ML62Q1300 Group

Product List)

1

-

23

27

49

Added Current Consumption 1

26

46

Added comment “*6” to the IOHL.

Updated 24MHz Characteristics graph

FEDL62Q1300-02

Added ML62Q1323/ML62Q1324/ML62Q1325/ML62Q1333/

ML62Q1334/ML62Q1335 Current consumption VS operating

frequency of CPU

-

46,47

*

Correction of errors

21

Changed termination of unused pins

Added parameter “Operating temperature(Chip-Junction)”

in Recommended Operating Conditions

22



23

35

Added thermal characteristics section

34

Added comments and notes to the reset characteristics

FEDL62Q1300-03

Mar 25, 2020

Revised overall of “Power On Reset” section as “Slope of

Power supply and Power On Reset” section.

The major revisions are

34

36

Added definitions of Power on rising/falling slope, Power on

voltage, CPU operation start time, and added Note.

*

4,8,9

22

*

4,8,9

22

Corrected typo

Changed comment for UART.

FEDL62Q1300-04

FEDL62Q1300-05

Nov 15, 2020

May 19, 2022

Corrected the operating temperature (Chip-Junction).

Changed company name

-

1,6,12,16

,23,57



Add SSOP20

1

Added Notes in general description section.

Added Notes for product usage

Corrected Typo



62



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FEDL62Q1300-05

Notes for product usage

Notes on this page are applicable to the all microcontroller products.

For individual notes on each LAPIS Technology microcontroller product, refer to [Note]

in the chapters of each user's manual.

The individual notes of each user’s manual take priority over those contents in this page if they are different.

1. HANDLING OF UNUSED INPUT PINS

Fix the unused input pins to the power pin or GND to prevent to cause the device performing wrong operation or

increasing the current consumption due to noise, etc. If the handlings for the unused pins are described in the chapters,

follow the instruction.

2. STATE AT POWER ON

At the power on, the data in the internal registers and output of the ports are undefined until the power supply voltage

reaches to the recommended operating condition and "L" level is input to the reset pin.

On LAPIS Technology microcontroller products that have the power on reset function, the data in the internal registers

and output of the ports are undefined until the power on reset is generated.

Be careful to design the application system does not work incorrectly due to the undefined data of internal registers and

output of the ports.

3. ACCESS TO UNUSED MEMORY

If reading from unused address area or writing to unused address area of the memory, the operations are not guaranteed.

4. CHARACTERISTICS DIFFERENCE BETWEEN THE PRODUCTS

Electrical characteristics, noise tolerance, noise radiation amount, and the other characteristics are different from each

microcontroller product.

When replacing from other product to LAPIS Technology microcontroller products, please evaluate enough the

apparatus/system which implemented LAPIS Technology microcontroller products.

5. USE ENVIRONMENT

When using this product in a high humidity environment and an environment where dew condensation, take

moisture-proof measures.

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FEDL62Q1300-05

Notes

1) The information contained herein is subject to change without notice.

2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals, application notes, etc.), and

ensure that usage conditions (absolute maximum ratings, recommended operating conditions, etc.) are within the ranges specified. LAPIS

Technology disclaims any and all liability for any malfunctions, failure or accident arising out of or in connection with the use of LAPIS

Technology Products outside of such usage conditions specified ranges, or without observing precautions. Even if it is used within such

usage conditions specified ranges, semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent

personal injury, fire or the other damage from break down or malfunction of LAPIS Technology Products, please take safety at your own

risk measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing

backups and fail-safe procedures. You are responsible for evaluating the safety of the final products or systems manufactured by you.

3) Descriptions of circuits, software and other related information in this document are provided only to illustrate the standard operation of

semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software,

and information in the design of your product or system. And the peripheral conditions must be taken into account when designing circuits

for mass production. LAPIS Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising

from the use of these circuits, software, and other related information.

4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Technology or any third

party with respect to LAPIS Technology Products or the information contained in this document (including but not limited to, the Product

data, drawings, charts, programs, algorithms, and application examples、etc.). Therefore LAPIS Technology shall have no responsibility

whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information.

5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer systems,

gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our Products in applications requiring a

high degree of reliability (as exemplified below), please be sure to contact a LAPIS Technology representative and must obtain written

agreement: transportation equipment (cars, ships, trains, etc.), primary communication equipment, traffic lights, fire/crime prevention,

safety equipment, medical systems, servers, solar cells, and power transmission systems, etc. LAPIS Technology disclaims any and all

liability for any losses and damages incurred by you or third parties arising by using the Product for purposes not intended by us. Do not use

our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and

submarine repeaters, etc.

6) The Products specified in this document are not designed to be radiation tolerant.

7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this document. However, LAPIS

Technology does not warrant that such information is error-free and LAPIS Technology shall have no responsibility for any damages arising

from any inaccuracy or misprint of such information.

8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive. LAPIS

Technology shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.

9) When providing our Products and technologies contained in this document to other countries, you must abide by the procedures and

provisions stipulated in all applicable export laws and regulations, including without limitation the US Export Administration Regulations

and the Foreign Exchange and Foreign Trade Act..

10) Please contact a ROHM sales office if you have any questions regarding the information contained in this document or LAPIS Technology's

Products.

11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Technology.

(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.

.

2-4-8 Shinyokohama, Kouhoku-ku,

Yokohama 222-8575, Japan

http://www.lapis-tech.com/en/

63/63


型号：	ML62Q1335
厂家：	ROHM
描述：	ML62Q1300系列是内置16位CPU nX-U16/100、并集成了程序存储器（FLASH存储器）、数据存储器（RAM）、DATA FLASH、乘除法运算器、CRC运算器、DMA控制器、时钟发生电路、定时器、通用端口、UART、同步串行端口、I2C总线（主/从）、蜂鸣器、电压电平检测功能（VLS）、逐次比较型A/D转换器、D/A转换器、模拟比较器、安全功能等丰富外围功能的高性能CMOS 16位微控制器。16位CPU nX-U16/100可通过流水线架构的并行处理实现一个时钟周期一个指令的高效指令执行。ML62Q1300系列具有片上调试功能，可在开发板上进行软件调试及软件改写。另外还具有ISP（In-System Programming）功能，可轻松实现在量产生产线上的FLASH写入功能。时钟生产线控制器微控制器存储比较器转换器
文件：	总63页 (文件大小：2441K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ML62Q1335 [ROHM]

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