ML62Q1733C_技术文档

FEDL62Q1700C-03

Issue Date: May 19, 2022

ML62Q1700C Group

16-bit micro controller

GENERAL DESCRIPTION

ML62Q1700C Group is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU nX-U16/100 and

integrated with program memory (Flash memory), data memory (RAM), data Flash and rich peripheral functions such as the

multiplier/divider, CRC generator, DMA controller, Clock generator, Simplified RTC, Timer, General Purpose Ports, UART,

Synchronous serial port, I²C bus interface unit (Master, Slave), Buzzer, Voltage Level Supervisor (VLS), Successive

approximation type A/D converter, D/A converter, Analog comparator, LCD driver, Safety function (IEC60730/60335 Class B),

and so on.

The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by pipeline architecture parallel

processing.

The built-in on-chip debug function enables debugging and programming the software. Also, ISP (In-System Programming)

function supports the Flash programming in production line.

The ML62Q1700C Group has five packages (52pin - 80pin) and ten kinds of memory sizes (96Kbyte - 128Kbyte).

Table 1 ML62Q1700C Group Product List

52pin

TQFP52

64pin

QFP64

TQFP64

80pin

QFP80

Program

memory

Data memory

(RAM)

Data Flash

4Kbyte

128Kbyte

96Kbyte

ML62Q1714C

ML62Q1713C

ML62Q1724C

ML62Q1723C

ML62Q1734C

ML62Q1733C

8Kbyte

Please see the page 59 “Notes for product usage” and the page 60 “Notes” in this document on use with this ML62Q1700C group.

FEATURES

• CPU

− 16-bit RISC CPU: nX-U16/100(A35 core)

− Instruction system: 16-bit length instructions

‒ Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,

bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on

‒ Built-in On-chip debug function

‒ Built-in ISP (In-System Programming) function

‒ Minimum instruction execution time

Approximately 30.5μs (at 32.768 kHz system clock)

Approximately 62.5ns/41.6ns (at 16 MHz/24MHz system clock)

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FEDL62Q1700C-03

• Coprocessor for multiplication and division

− Multiplication

: 16bit × 16bit (operation time: 4 cycles)

: 32bit ÷ 16bit (operation time: 8 cycles)

: 32bit ÷ 32bit (operation time: 16 cycles)

− Division

− Multiply-accumulate (non-saturating): 16bit × 16bit + 32bit (operation time: 4 cycles)

− Multiply-accumulate (saturating): 16bit × 16bit + 32bit (operation time: 4 cycles)

− Signed or Unsigned is selectable

• Operating voltage and temperature

‒ Operating voltage: V_DD= 1.6 to 5.5 V (V_DDshould be 1.8V or over at Power-on)

‒ Operating temperature: -40 °C to +105 °C

• Internal memory

‒ Program memory area

Rewrite count: 100 cycles

Write unit: 32bit(4byte)

Erase unit: 16Kbyte/1Kbyte

Erase/Write temperature: 0 °C to +40 °C

‒ Data Flash memory area

Rewrite count 10,000 cycles

Write unit: 8bit(1byte)

Erase unit: all area/128byte

Erase/Write temperature: -40 °C to +85 °C

Back Ground Operation (CPU can work while erasing and rewriting)

This product uses Super Flash® technology licensed from Silicon Storage Technology, Inc.

Super Flash® is a registered trademark of Silicon Storage Technology, Inc.

‒ Data RAM area

Rewrite unit: 8bit/16bit (1byte/2byte)

Parity check function is available (interrupt / reset are generatable at Parity error)

• Clock generation circuit

‒ Low-speed clock (LSCLK)

Internal low-speed RC oscillation: Approximately 32.768 kHz

External low-speed clock input: Approximately 32.768 kHz

External low-speed crystal oscillation: 32.768 kHz crystal resonator is connectable

3 selectable crystal oscillation mode (Tough, Normal, and Low current consumption)

⋅

Tough mode: Largest oscillation allowance to make highest resistance against leakage between the pins

Normal mode: Normal oscillation allowance and current consumption

Low current consumption mode: Smallest oscillation allowance to make lower current consumption

‒ High-speed clock (HSCLK)

PLL oscillation: 2 selectable oscillation frequency (24MHz and 16MHz) by code option

‒ Watch Dog Timer (WDT): built-in independent clock for WDT (RC1K: Approximately 1kHz)

• Reset

‒ Reset by reset input pin

‒ Reset by Power-On Reset

‒ Reset by WDT overflow

‒ Reset by WDT invalid clear

‒ Reset by RAM parity error

‒ Reset by unused ROM area access (instruction access)

‒ Reset by voltage level supervisor (VLS)

‒ Software reset by BRK instruction (reset CPU only)

‒ Reset the peripherals individually

‒ Collective reset to the all control pins and peripheral circuits

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FEDL62Q1700C-03

• Power management

‒ HALT mode: CPU stops executing instruction, peripheral circuits continue working

‒ HALT-H mode: CPU stops executing instruction, high-speed clock oscillation stops and peripheral circuits continue

working with low-speed clock

‒ HALT-C mode: CPU stops executing instruction, high-speed clock oscillation stops and peripheral circuits working with

low-speed clock remain previous states. Peripheral circuits can work only watchdog timer, external interrupt, low-speed

time base counter, 16-bit timers, crystal oscillation circuit, and LCD driver.

‒ STOP mode: CPU and peripheral circuits stops executing instruction, both high-speed oscillation and low-speed

oscillation stop.

‒ STOP-D mode: CPU and peripheral circuits stops executing instruction, both high-speed oscillation and low-speed

oscillation stop. The internal logic voltage (V_DDL) goes down to reduce the current consumption (RAM data is retained).

‒ Clock gear: High-speed system clock frequency can be changed (1/1, 1/2, 1/4, 1/8, 1/16 or 1/32 of HSCLK)

‒ Block Control Function: Powers down the unused function blocks (reset the block or stop supplying the clock)

• Interrupt controller

− External interrupt ports: max. 12

− Non-maskable interrupt source: 1 (Internal sources: WDT)

− Maskable interrupt sources: max. 43

− Four step interrupt levels

• Watchdog timer (WDT)

‒ Selectable Operating clock: select RC1K or LSCLK by code option

‒ Overflow period: 8selectable (7.8ms, 15.6ms, 31.3ms, 62.5ms, 125ms, 500ms, 2s and 8s)

‒ Selectable window function (enable or disable): configurable clear enable period (50% or 75% of overflow period)

‒ Selectable WDT operation: select Enable or Disable by code option

‒ Readable WDT counter: WDT counter monitor function

• DMA (Direct Memory Access) controller

− Channel: 2channel

− Transfer unit: 8bit/16bit

− Transfer count: 1 to 1024

− Transfer cycle: 2 cycle transfer

− Transfer address: Fixed addressing mode, inclement addressing mode, and decrement addressing mode

− Transfer target: Special Function Register (SFR)/RAM  SFR/RAM (Transfer from/to Flash is not supported)

− Transfer request: External pins, Serial communication unit, Successive approximation type A/D converter, 16bit timer,

and Functional timer

• Low-speed Time base counter

− Generate 8 frequency (128Hz to1Hz) internal pulse signals by dividing the Low-speed clock (LSCLK)

− Selectable 3 interrupts from eight frequency internal pulse signals

− 1Hz or 2Hz output from general purpose port

− Built-in Frequency adjust function: Adjust range: Approximately -488ppm to +488ppm, adjust resolution:

Approximately 0.119ppm

• Simplified RTC

− Channel: 1channel

− Count by a unit for one second from "00 min. 00 sec" to "59 min. 59 sec"

− Selectable Periodical interrupt request from four periods (0.5s, 1s, 30s or 60s)

− Built-in minute and second writing error protraction function

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FEDL62Q1700C-03

• Functional timer

− Channel: 6channel

− Built-in timer, capture, and PWM function by 16 bit counter

− One shot mode is available

− Two types of PWM output with the same period and different duties, and complementary PWM output with the dead time

− Monitor input signal duty and the period by capture function

− Generate periodical interrupts, duty interrupts, and interrupts coincided with set value

− Counter Start, Stop, Counter clear triggered by an external inputs or Timer

− Generate Emergency stop and emergency stop interrupt triggered by an external input

− Same start/stop among different channels of the functional timer

− Selectable counter clock (external clock or divided by 1 to 128 of LSCLK or HSCLK) for each channels

• 16-bit General timers

− Channel: 6channel

‒ 8 bits timer mode and 16-bit timer mode

− Same start/stop among different channels of 16bit (8bit) timer

‒ Timer output (toggled by overflow)

− Selectable counter clock (external clock or divided by 1 to 128 of LSCLK or HSCLK) for each channels

• Serial communication unit

− Synchronous Serial Port (SSIO) mode or UART mode is selectable

− Channel: Max. 4channel

< Synchronous Serial Port mode>

‒ Selectable from Master and Slave

‒ Selectable from LSB first or MSB first

‒ Selectable 8-bit length or 16-bit length

< UART mode>

‒ Full-duplex communication mode and half-duplex communication mode

‒ 5 to 8 bit length, parity or no parity, odd parity or even parity, 1 stop bit or 2 stop bits

‒ Selectable from Positive logic or Negative logic

‒ Selectable from LSB first or MSB first

‒ Configurable wide range communication speed

32.768kHz operation clock: 1 bit/s to 4,800 bit/s

24MHz operation clock: 600 bit/s to 3M bit/s

16MHz operation clock: 300 bit/s to 2M bit/s

‒ Built-in baud rate generator

• I2C bus unit (Master / Slave)

‒ Selectable from Master mode or Slave mode

‒ Channel: 1channel

< Master function >

‒ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)

‒ Handshake (Clock synchronization)

‒ 7bit address format (10bit address format is supported)

< Slave function >

‒ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode (1Mbit/s)

‒ Clock stretch function

‒ 7bit address format

• I2C bus Master

‒ Channel: 2channel

‒ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode (1Mbit/s)

‒ Handshake (Clock synchronization)

‒ 7bit address format (10bit address format is supported)

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FEDL62Q1700C-03

• General-purpose ports (GPIO)

‒ I/O port: Max. 69 (Including one pin for on-chip debug and pins for other shared functions)

‒ Input port: Max. 2 (Including a shared function)

‒ External interrupt port: Max. 12

‒ LED driver port: Max. 68

‒ Carrier frequency output function (for IR communication)

• Successive approximation type A/D converter (SA-ADC)

‒ Channel: Max.12channel

‒ Resolution: 10bit

‒ Conversion time: Min. 2.25μs / channel (When the conversion clock is 8MHz)

‒ Reference voltages are selectable

(V_DDpin / Internal reference voltage (V_REFI= Approximately 1.55V) / External reference voltage (V_REFpin))

‒ Selected channel repeat conversion

‒ dedicated result register for each channel

‒ Interrupt determining by upper limit or lower limit threshold of conversion result

•

Voltage Level Supervisor (VLS)

‒ Accuracy: ±4%

‒ Threshold voltage: 12 selectable (from 1.85V to 4.00V)

‒ Functional Voltage level detection reset (VLS reset)

‒ Functional Voltage level detection interrupt (VLS0 interrupt)

Analog comparator

‒ Channel: 2channel

‒ Selectable interrupt from the comparator output (rising edge or falling edge)

‒ Selectable from sampling or without sampling

‒ Comparable with external 2 inputs

‒ Comparable with external input and internal reference voltage (0.8V)

•

D/A converter

‒ Channel: 1channel

‒ Resolution: 8bit

‒ Output impedance: 6k ohm (Typ.)

‒ R-2R ladder type

Buzzer

‒ 4 buzzer mode (Continuous sound, Single sound, Intermittent sound 1 and Intermittent sound 2)

‒ 8frequencies (4.096kHz to 293Hz)

‒ 15 step duty (1/16 to 15/16)

‒ Selectable from positive logic buzzer output or negative logic buzzer output

CRC (Cyclic Redundancy Check) generator

‒ Generation equation: X¹⁶+X¹²+X⁵+1

‒ Selectable from LSB first or MSB first

‒ Built-in Automatic program memory CRC calculation mode in HALT mode

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FEDL62Q1700C-03

•

LCD driver

‒ Max. 360 dots (45seg x 8 com) ^*1

ML62Q1713C/1714C:

ML62Q1723C/1724C:

ML62Q1733C/1734C:

27seg×8com (com Max.), 32seg×3com (seg Max.)

35seg×8com (com Max.), 40seg×3com (seg Max.)

45seg×8com (com Max.), 50seg×3com (seg Max.)

^*1: Five pins are shared for common or segment, selectable by setting a SFR

‒ 1/3 bias (built-in bias generation circuit)

‒ Frame frequency (Approximately. 32Hz，38Hz，64Hz，75Hz，128Hz and 150Hz)

‒ Four bias generation modes (Internal voltage boost, External capacitive voltage divide, Internal capacitive voltage divide

and External supply voltages)

‒ Contrast adjustment (32 steps) is available in the Internal voltage boost mode.

•

Safety Function (IEC60730/60335 Class B)

‒ Automatic switching to the internal low-speed RC oscillation in case the low-speed crystal oscillation stopped

‒ RAM/SFR guard

‒ Automatic program memory CRC calculation

‒ RAM parity error detection

‒ ROM unused area access reset (instruction access)

‒ Clock mutual monitoring

‒ WDT counter monitoring

‒ SA-ADC test

‒ UART test

‒ Synchronous serial I/O test

‒ I²C bus test

‒ GPIO test

• Shipping package

‒ 52-pin plastic TQFP

ML62Q1713C/1714C - xxxTB （Blank part: ML62Q1713C/1714C -NNNTB）

‒ 64-pin plastic TQFP

ML62Q1723C/1724C - xxxTB （Blank part: ML62Q1723C/1724C -NNNTB）

‒ 64-pin plastic QFP

ML62Q1723C/1724C - xxxGA （Blank part: ML62Q1723C/1724C -NNNGA）

‒ 80-pin plastic QFP

ML62Q1733C/1734C - xxxGA （Blank part: ML62Q1733C/1734C -NNNGA）

xxx: ROM code number

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FEDL62Q1700C-03

ML62Q1700C Group how to read the part number

ML 62 Q 17 3 4C – xxx TB

Package Type

GA

TB

: QFP

: TQFP

ROM Code Number

NNN : Blank

xxx

: Custom Code Number

Program Memory Size

3

4

: 96Kbyte

: 128Kbyte

Pin Count

1

2

3

: 52pin

: 64pin

: 80pin

Group Name

17xxC : 1700C Group

Program Memory Type

Q

: Flash Memory

CPU Type

62

: 16-bit CPU nX-U16/100

LAPIS Semiconductor Logic Product

Figure 1 ML62Q1700C Group Part Number

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FEDL62Q1700C-03

ML62Q1700C Group Main Function Listtruc

Table 2 ML62Q1700C Group Main Function List

LCD drive pin

Interrupt

Timer

Serial

Analog

Part number

ML62Q1713C

ML62Q1714C

ML62Q1723C

ML62Q1724C

ML62Q1733C

ML62Q1734C

52

64

80

41 40

53 52

69 68

27

33

10

3

4

3

1

2

5

3

35

45

5

6

1

2

12

2

4

1

35

12

*1: One 16-bit timer is configurable as two 8bit timers

*2: Synchronous Communication unit includes UART mode and Synchronous Serial Port mode. UART mode and

Synchronous Serial Port cannot be used at the same time in the same channel.

*3: Shared with pins for crystal oscillation

*4: The LCD common/segment shared pins are shared for common or segment, selectable by setting a SFR

*5: All LCD drive pins are shared with general purpose I/O ports.

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FEDL62Q1700C-03

BLOCK DIAGRAM

CPU (nX-U16/100)

ECSR1～3

DSR/CSR

PC

EPSW1～3

ELR1～3

LR

Multiplier/Divider

(Coprocessor)

GREG

0 ～15

PSW

EA

Timing

Controller

ALU

SP

Program

Memory

(FLASH)

BUS

Controller

Instruction

Decoder

Instruction

Register

On-Chip

ICE

V_DD

V_SS

SU0~3_SCLK*

SU0~3_SIN*

INT

Power

Circuit

SU0~3_SOUT0*

V_DDL

RAM

V_REFO

*

Serial

Communication

SU0~3_RXD0*

SU0~3_TXD0*

SU0~3_RXD1*

SU0~3_TXD1*

Unit *¹

Data FLASH

SYSTEM

RESET_N

TEST0*²

INT

FLASH

Controller

Clock

Generation

Circuit

INT

OUTLSCLK*

OUTHSCLK*

I²C Bus

Unit

I2CU0_SDA*

I2CU0_SCL*

Low-speed

RC

Oscillation

Interrupt

INT

I²C Bus

Master

I2CM0~1_SDA*

I2CM0~1_SCL*

INT

High-speed

PLL

Oscillation

WDT

VLS

16-Bit

Timer

TMH0~5OUT*

INT

RC

Oscillation

(for WDT)

INT

EXTRIG0～7

FTM0~5P*

FTM0~5N*

Low-speed

Crystal

Oscillation

Functional

Timer

DMA

Controller

XT0*³

XT1*³

INT

V_DD

V_SS

V_REF

CRC

Generator

A/D

Converter

Low Speed

Time Base

Counter

TBCOUT0*

TBCOUT1*

AIN0 to AIN11*

INT

Analog

Comparator

Simplified

RTC

CMP0~1P*

CMP0~1M*

BZ0P*

BZ0N*

Buzzer

D/A

Converter

DACOUT0*

Safety

Function

INT

PX0~PX7

(X= 0~9,A,B)

PI00,PI01

GPIO

(External

Interrupt)

V_L1,V_L2,V_L3

C₁,C₂

LCD

Bias

Reset

Function

EXI0~11

COM0~COM2

COM3~COM7/

SEG5~SEG61

LCD

Driver

*

: Indicates the shared function of general ports.

*1 : Shared UART and Synchronous Serial Port.

*2 : Not available as the input port when connecting to the on-chip debug emulator.

*3 : Not available as the input port when connecting to the crystal resonator.

Figure 2 ML62Q1700C Group Block Diagram

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FEDL62Q1700C-03

PIN CONFIGURATION

The pin names in the pin-layout indicate 1st-function or LCD function. Refer to Table-3 or Table-4 about other functions.

Pin Layout of 52pin TQFP Package

39

27

P41/SEG48

P30/SEG49

P31/SEG50

P32/SEG51

P33/SEG52

P60/SEG53

P61/SEG54

P62/SEG55

P63/SEG56

P64/EXI9/SEG57

P65/SEG58

P66/SEG59

P43

P51/SEG6

P50/EXI8/SEG5

P13/COM7/SEG4

P12/COM6/SEG3

P11/COM5/SEG2

P10/COM4/SEG1

P07/COM3/SEG0

P06/COM2

TOP VIEW

TQFP52

P05/COM1

P04/EXI2/EXTRG2/COM0

V

L3

L2

L1

V

1

13

Figure 3 Pin Layout of 52pin TQFP52 Package

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FEDL62Q1700C-03

Pin Layout of 64pin TQFP/QFP Package

48

33

P40/SEG47

P41/SEG48

P30/SEG49

P31/SEG50

P32/SEG51

P33/SEG52

P60/SEG53

P61/SEG54

P62/SEG55

P63/SEG56

P64/EXI9/SEG57

P65/SEG58

P66/SEG59

P67/SEG60

P42/SEG61

P43

P53/SEG8

P52/SEG7

P51/SEG6

P50/EXI8/SEG5

P13/COM7/SEG4

P12/COM6/SEG3

P11/COM5/SEG2

P10/COM4/SEG1

P07/COM3/SEG0

P06/COM2

TOP VIEW

TQFP64/QFP64

P05/COM1

P04/EXI2/EXTRG2/COM0

P70

V

L3

L2

L1

V

1

16

Figure 4 Pin Layout of 64pin TQFP/QFP Package

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FEDL62Q1700C-03

Pin Layout of 80pin QFP Package

60

41

PB2/SEG43

PB3/SEG44

PB4/SEG45

PB5/SEG46

P40/SEG47

P41/SEG48

P30/SEG49

P31/SEG50

P32/SEG51

P33/SEG52

P60/SEG53

P61/SEG54

P62/SEG55

P63/SEG56

P64/EXI9/SEG57

P65/SEG58

P66/SEG59

P67/SEG60

P42/SEG61

P43

P96/SEG15

P95/SEG14

P94/SEG13

P93/SEG12

P53/SEG8

P52/SEG7

P51/SEG6

P50/EXI8/SEG5

P13/COM7/SEG4

P12/COM6/SEG3

P11/COM5/SEG2

P10/COM4/SEG1

P07/COM3/SEG0

P06/COM2

TOP VIEW

QFP80

P05/COM1

P04/EXI2/EXTRG2/COM0

P70

VL3

VL2

VL1

1

20

Figure 5 Pin Layout of 80pin QFP Package

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FEDL62Q1700C-03

PIN LIST

Table 3 Pin List (1/3)

Pin No.

Pin name

(1^stfunc)

1^stfunc.

others

2^ndfunc.

SIU

3^rdfunc.

SIU

4^thfunc.

I²C

5^thfunc.

Timer

6^thfunc.

others

7^thfunc.

others

8^thfunc.

ADC

3

4

5

1

2

6

7

8

3

4

5

1

2

6

7

8

3

4

5

1

2

6

7

8

V_DD

V_SS

-

V_DDL

-

XT0

PI00

-

XT1

PI01

-

RESET_N

P00

RESET_N

TEST0

DACOUT0

-

P01

FTM3P

TBCOUT0

TBCOUT1

EXI0

EXTRG0

SU0_RXD0

SU0_SIN

9

11 14

P02

P03

-

I2CU0_SCL

FTM0P

FTM0N

OUTLSCLK

OUTHSCLK

CMP0M

CMP0P

-

EXI1

EXTRG1

SU0_TXD0

SU0_SOUT

10 12 15

17 21 25

SU0_TXD1 I2CU0_SDA

AIN11

EXI2

EXTRG2

COM0

P04

SU0_SCLK

-

I2CU0_SCL TMH0OUT

-

18 22 26

19 23 27

P05

P06

COM1

COM2

-

I2CM0_SDA

COM3

SEG0

20 24 28

21 25 29

22 26 30

23 27 31

24 28 32

P07

P10

P11

P12

P13

SU0_RXD1 SU0_RXD0 I2CM0_SCL

-

COM4

SEG1

SU0_TXD1

SU0_SCLK

-

COM5

SEG2

-

COM6

SEG3

SU0_RXD0

SU0_SIN

-

TMH4OUT

TMH1OUT

-

COM7

SEG4

SU0_TXD0

SU0_SOUT

SU0_TXD1

TMH3OUT

27 35 45

28 36 46

29 37 47

P14

P15

P16

SEG22

SEG23

SEG24

-

I2CU0_SDA

SU1_SCLK

I2CU0_SCL TMH5OUT

EXI3

30 38 48

31 39 49

32 40 50

P17

P20

P21

EXTRG3

SEG25

SU0_RXD1 SU0_RXD0

-

FTM1P

FTM1N

FTM2P

TBCOUT0

TBCOUT1

OUTLSCLK

BZ0P

BZ0N

-

AIN0

AIN1

AIN2

SEG26

SU0_TXD1

-

EXI4

EXTRG4

SEG27

SU1_RXD0

SU1_SIN

SU1_TXD0

SU1_SOUT

33 41 51

34 42 52

P22

P23

SEG28

SU1_TXD1 I2CM0_SDA

FTM2N

OUTHSCLK

-

AIN3

V_REFO

EXI5

EXTRG5

SEG29

V_REF

SU1_SCLK

-

I2CM0_SCL TMH2OUT

SU1_RXD0

SU1_SIN

35 43 53

36 44 54

P24

P25

SEG30

SEG31

-

AIN4

AIN5

SU1_TXD0

SU1_SOUT

SU1_TXD1

EXI6

37 45 55

38 46 56

P26

P27

EXTRG6

SEG32

SU1_RXD1 SU1_RXD0 I2CU0_SDA

FTM3P

FTM3N

TBCOUT0

TBCOUT1

BZ0P

BZ0N

AIN6

AIN7

EXI7

EXTRG7

SEG33

SU2_SCLK

SU1_TXD1

I2CU0_SCL

*1

*1: No assignment to products of 52 PIN-and 80 PIN package.

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Table 3 Pin List (2/3)

Pin No.

Pin name

(1^stfunc)

1^stfunc.

others

2^ndfunc.

SIU

3^rdfunc.

SIU

4^thfunc.

I²C

5^thfunc.

Timer

6^thfunc.

others

7^thfunc.

others

8^thfunc.

ADC

41 51 67

42 52 68

43 53 69

44 54 70

P30

P31

P32

P33

P40

P41

SEG49

SEG50

SEG51

SEG52

SEG47

SEG48

-

TBCOUT0

TBCOUT1

SU1_RXD1 SU1_RXD0

-

SU1_TXD1

-

TMH3OUT

-

49 65

-

40 50 66

SU3_TXD1

*1

-

63 79

P42

SEG61

-

52 64 80

P43

P44

P45

P46

-

TBCOUT0

TBCOUT1

AIN10

-

9

12

-

FTM3N

-

10 13

13 16

-

I2CU0_SDA

FTM1N

I2CU0_SCL

*1

11 14 17

P47

P50

-

SU0_SCLK

-

FTM1P

-

EXI8

SEG5

25 29 33

26 30 34

-

P51

P52

P53

SEG6

SEG7

SEG8

-

31 35

32 36

SU2_RXD1 SU2_RXD0

-

33 43

34 44

P54

P55

SEG20

SEG21

-

*1

SU2_TXD1

*1

-

SU2_RXD0

SU2_SIN

*1

39 47 57

P56

P57

SEG34

SEG35

-

SU2_TXD0

SU2_SOUT

*1

SU2_TXD1

*1

-

48 58

45 55 71

46 56 72

47 57 73

48 58 74

P60

P61

P62

P63

SEG53

SEG54

SEG55

SEG56

-

I2CM1_SCL

-

I2CM1_SDA

-

FTM4N

FTM4P

CMP1P

CMP1M

EXI9

SEG57

SU3_RXD0

SU3_SIN

49 59 75

P64

-

FTM5P

-

SU3_TXD0

SU3_SOUT

50 60 76

51 61 77

P65

P66

P67

SEG58

SEG59

SEG60

SU3_TXD1

-

FTM5N

-

AIN8

AIN9

-

SU3_SCLK

-

SU3_RXD1 SU3_RXD0

-

62 78

20 24

*1

P70

V_L3

V_L2

V_L1

C₂

-

16 19 23

15 18 22

14 17 21

13 16 20

12 15 19

-

C₁

-

18

P76

EXI10

-

*1: No assignment to products of 52 PIN-package.

14/60

FEDL62Q1700C-03

Table 3 Pin List (3/3)

Pin No.

Pin name

(1^stfunc)

1^stfunc.

others

2^ndfunc.

SIU

3^rdfunc.

SIU

4^thfunc.

I²C

5^thfunc.

Timer

6^thfunc.

others

7^thfunc.

others

8^thfunc.

ADC

-

9

P80

P81

P82

P93

P94

P95

P96

PA1

PA2

-

10

11

37

38

39

40

41

42

-

SEG12

SEG13

SEG14

SEG15

-

EXI11

SEG36

SU2_SCLK

*1

59

PA3

-

60

61

62

63

64

PA4

PB2

PB3

PB4

PB5

SEG37

SEG43

SEG44

SEG45

SEG46

-

*1: No assignment to products of 52 PIN and 64 PIN-packages.

15/60

FEDL62Q1700C-03

PIN DESCRIPTION

Table 4 Pin Description (1/7)

Function

Power

Signal name

Pin name

I/O

-

Description

Negative power supply pin (-)

Positive power supply pin (+). Connect a capacitor C_V

between this pin and V_SS

Logic

-

V_SS

-

V_DD

-

.

Power supply pin for internal logic (internal regulator’s

output). Connect a capacitor C_V(1μF) between this pin

and V_SS.

-

V_DDL

-

Input pin for testing. Also, used for on-chip debug

interface or ISP function.

P00 is initialized as pull-up input mode by the system

reset.

Test

TEST0

V_REFO

P00

P23

I/O

-

Reference voltage output.

Reset input.

Applying “L” level shifts the MCU in system reset

mode.

RESET_N

I

Applying “H” level shifts the CPU in program running

mode.

Negative

Used for on-chip debug interface and ISP function.

No pull-up resistor is installed.

System

Low-speed crystal oscillation pins

Connect 32.768kHz crystal resonator and have

capacitors between the pin and V_SS.

XT0

XT1

XT0

XT1

I

-

O

P02

P21

P03

P22

OUTLSCLK

OUTHSCLK

O

Low-speed clock output.

-

High-speed clock output.

General purpose input.

General input port

(GPI)

PI00, PI01

XT0, XT1

I

Not available as general inputs when using the crystal Positive

resonator.

General purpose I/O port

- High-impedance

- Input with Pull-UP (initial value)

- Input without Pull-UP

- CMOS output

P00

I/O

Positive

- N-channel open drain output

Not available to use as I/O pin when using for on-chip

debug interface or ISP function.

P01 – P07

P10 – P17

P20 – P27

P30 – P33

P40 – P47

P50 – P57

P60 – P67

P70, P76

P01 – P07

P10 – P17

P20 – P27

P30 – P33

P40 – P47

P50 – P57

P60 – P67

P70, P76

General port

(GPIO)

General I/O port

- High-impedance (initial value)

- Input with Pull-UP

- Input without Pull-UP

- CMOS output

- N-channel open drain output

I/O

Positive

P80 – P82

P93 – P96

PA1 – PA4

PB2 – PB5

P80 – P82

P93 – P96

PA1 – PA4

PB2 – PB5

16/60

FEDL62Q1700C-03

Logic

Table 4 Pin Description (2/7)

Function

Signal name

SU0_TXD0

Pin name

I/O

Description

P03

P13

P02

P07

P12

P17

P03

P10

P13

P20

P07

P17

P22

P25

P21

P24

P26

P32

P22

P25

P27

P33

P26

P32

P57

P54

P56

P55

P57

P54

P65

P64

P67

P42

P65

P67

O

Serial communication unit0 UART0 data output

Positive

Serial communication unit0 Full-duplex data input

Serial communication unit0 UART0 data input

SU0_RXD0

SU0_TXD1

I

Positive

Serial communication unit0 Full-duplex data output

Serial communication unit0 UART1 data output

O

Positive

SU0_RXD1

SU1_TXD0

I

Serial communication unit0 UART1 data input

Serial communication unit1 UART0 data output

Positive

O

Serial communication unit1 Full-duplex data input

Serial communication unit1 UART0 data input

SU1_RXD0

SU1_TXD1

I

Positive

UART

Serial communication unit1 Full-duplex data output

Serial communication unit1 UART1 data output

O

SU1_RXD1

SU2_TXD0

SU2_RXD0

I

O

I

Serial communication unit1 UART1 data input

Serial communication unit2 UART0 data output

Positive

Serial communication unit2 Full-duplex data input

Serial communication unit2 UART0 data input

Serial communication unit2 Full-duplex data output

Serial communication unit2 UART1 data output

SU2_TXD1

O

Positive

SU2_RXD1

SU3_TXD0

I

Serial communication unit2 UART1 data input

Serial communication unit3 UART0 data output

Positive

O

Serial communication unit3 Full-duplex data input

Serial communication unit3 UART0 data input

SU3_RXD0

I

Positive

Serial communication unit3 Full-duplex data output

Serial communication unit3 UART1 data output

SU3_TXD1

SU3_RXD1

O

I

Positive

Serial communication unit3 UART1 data input

17/60

FEDL62Q1700C-03

Logic

Table 4 Pin Description (3/7)

Function

Signal name

SU0_SIN

Pin name

I/O

Description

P02

P12

P04

P11

P47

P03

P13

P21

P24

P16

P23

P22

P25

P56

P27

PA3

Serial communication unit0 Synchronous serial data

input

I

Positive

Serial communication unit0 Synchronous serial clock

I/O

SU0_SCLK

I/O

Positive

Serial communication unit0 Synchronous serial data

output

SU0_SOUT

SU1_SIN

O

I

Positive

Serial communication unit1 Synchronous serial data

input

Serial communication unit1 Synchronous serial clock

I/O

SU1_SCLK

I/O

Synchronous

Serial Port

Serial communication unit1 Synchronous serial data

output

SU1_SOUT

SU2_SIN

O

I

Positive

Serial communication unit2 Synchronous serial data

Serial communication unit2 Synchronous serial clock

I/O

SU2_SCLK

I/O

Serial communication unit2 Synchronous serial data

output

SU2_SOUT

SU3_SIN

P57

P64

P66

P65

O

I

Positive

Serial communication unit3 Synchronous serial data

input

Serial communication unit3 Synchronous serial clock

I/O

SU3_SCLK

SU3_SOUT

I/O

O

Serial communication unit3 Synchronous serial data

output

P03

P15

P26

P46

P02

P04

P16

P27

P47

P06

I²C Unit0 (Master and Salve) Data I/O

I/O N-channel open drain

I2CU0_SDA

I2CU0_SCL

Positive

Connect a pull-up resistor externally

I²C Unit0 (Master and Salve) Clock I/O

I/O N-channel open drain output

Connect a pull-up resistor externally

I²C Bus

I²C Master0 Data I/O pin

I/O N-channel open drain output

Connect a pull-up resistor externally

I2CM0_SDA

I2CM0_SCL

I2CM1_SDA

I2CM1_SCL

Positive

P22

P07

P23

I²C Master0 Clock I/O

I/O N-channel open drain output

Connect a pull-up resistor externally

I²C Master1 Data I/O

P61

P60

I/O N-channel open drain output

Connect a pull-up resistor externally

I²C Master1 Clock I/O

I/O N-channel open drain output

Connect a pull-up resistor externally

18/60

FEDL62Q1700C-03

Table 4 Pin Description (4/7)

Function

Signal name

FTM0P

Pin name

I/O

O

Description

Functional Timer0 P output

Logic

P02

P03

P17

P47

P20

P46

P21

P22

P01

P26

P27

P44

P63

P62

P64

P65

P02

P03

P04

P17

P21

P23

P26

P27

P04

P13

P23

P13

P33

P12

P16

P02

P03

P01

P17

P26

P31

P43

P01

P20

P27

P31

P43

P17

P26

P20

P27

Positive

Negative

FTM0N

O

Functional Timer0 N output

FTM1P

FTM1N

O

Functional Timer1 P output

Positive

Functional Timer1 N output

Negative

FTM2P

FTM2N

O

Functional Timer2 P output

Functional Timer2 N output

Positive

Negative

FTM3P

FTM3N

O

Functional Timer3 P output

Functional Timer3 N output

Positive

Negative

Functional Timer

(FTM)

FTM4P

FTM4N

O

I

Functional Timer4 P output

Positive

Functional Timer4 N output

Negative

FTM5P

Functional Timer5 P output

Positive

FTM5N

Functional Timer5 N output

Negative

EXTRG0

EXTRG1

EXTRG2

EXTRG3

EXTRG4

EXTRG5

EXTRG6

EXTRG7

TMH0OUT

TMH1OUT

TMH2OUT

Functional Timer event trigger input

16bit General Timer 0 output

-

I

-

I

-

I

-

I

-

I

-

I

-

I

-

O

Positive

16bit General Timer 1 output

16bit General Timer 2 output

TMH3OUT

O

16bit General Timer 3 output

Positive

16-bit Timer

TMH4OUT

TMH5OUT

EXTRG0

O

I

16bit General Timer 4 output

16bit General Timer 5 output

16bit Timer trigger input

Positive

-

EXTRG1

I

16bit Timer trigger input

TBCOUT0

TBCOUT1

O

The low speed time base counter output signal

1Hz/2Hz clock for the Simplified RTC

Positive

Low-speed

Time Base Counter

(LTBC)

BZ0P

BZ0N

O

Buzzer output (positive phase)

Buzzer output (negative phase)

Positive

Buzzer

Negative

19/60

FEDL62Q1700C-03

Table 4 Pin Description (5/7)

Function

Signal name

EXI0

Pin name

I/O

I

Description

External Interrupt 0 Input

Logic

P02

P03

P04

P17

P21

P23

P26

P27

P50

P64

P76

PA3

P23

P17

P20

P21

P22

P24

P25

P26

P27

P65

P66

P43

P03

P02

P62

P63

P01

-

EXI1

I

External Interrupt 1 Input

External Interrupt 2 Input

External Interrupt 3 Input

External Interrupt 4 Input

External Interrupt 5 Input

External Interrupt 6 Input

External Interrupt 7 Input

External Interrupt 8 Input

External Interrupt 9 Input

External Interrupt 10 Input

External Interrupt 11 Input

SA-ADC external reference voltage input

SA-ADC channel 0 input

EXI2

I

EXI3

I

EXI4

I

EXI5

I

External Interrupt

EXI6

I

EXI7

I

EXI8

I

EXI9

I

EXI10

EXI11

V_REF

I

-

I

AIN0

AIN1

I

SA-ADC channel 1 input

AIN2

I

SA-ADC channel 2 input

AIN3

I

SA-ADC channel 3 input

AIN4

I

SA-ADC channel 4 input

Successive

approximation type

A/D converter

AIN5

I

SA-ADC channel 5 input

AIN6

I

SA-ADC channel 6 input

AIN7

I

SA-ADC channel 7 input

AIN8

I

SA-ADC channel 8 input

AIN9

I

SA-ADC channel 9 input

AIN10

AIN11

CMP0P

CMP0M

CMP1P

CMP1M

DACOUT0

I

SA-ADC channel 10 input

SA-ADC channel 11 input

Comparator input 0 (noninverting input)

Comparator input 0 (inverting input)

Comparator input 1 (noninverting input)

Comparator input 1 (inverting input)

D/A converter 0 output

I

Analog comparator

D/A converter

I

O

20/60

FEDL62Q1700C-03

Table 4 Pin Description (6/7)

Pin name

Function

Signal name

COM0

I/O

-

Description

Logic

P04

P05

P06

P07

P10

P11

P12

P13

P50

P51

P52

P53

P93

P94

P95

P96

P54

P55

P14

P15

P16

P17

P20

P21

P22

P23

P24

P25

P26

P27

P56

P57

PA3

PA4

PB2

Common output

-

COM1

COM2

COM3/SEG0

COM4/SEG1

COM5/SEG2

COM6/SEG3

COM7/SEG4

SEG5

Common/Segment output shared

Segment output

SEG6

Segment output

SEG7

Segment output

SEG8

Segment output

SEG12

Segment output

SEG13

Segment output

SEG14

Segment output

SEG15

Segment output

SEG20

Segment output

LCD driver

SEG21

Segment output

SEG22

Segment output

SEG23

Segment output

SEG24

Segment output

SEG25

Segment output

SEG26

Segment output

SEG27

Segment output

SEG28

Segment output

SEG29

Segment output

SEG30

Segment output

SEG31

Segment output

SEG32

Segment output

SEG33

Segment output

SEG34

Segment output

SEG35

Segment output

SEG36

Segment output

SEG37

Segment output

SEG43

Segment output

21/60

FEDL62Q1700C-03

Table 4 Pin Description (7/7)

Function

Signal name

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

Pin name

I/O

-

Description

Logic

PB3

PB4

PB5

P40

P41

P30

P31

P32

P33

P60

P61

P62

P63

P64

P65

P66

P67

P42

Segment output

-

LCD driver

-

LCD bias power source generation

capacitor connection

C₁, C₂

-

LCD bias power source.

V_L1~V_L3

-

Connect the capacitors (C_L1, C_L2, C_L3) between the

pin and Vss.

-

22/60

FEDL62Q1700C-03

TERMINATION OF UNUSED PINS

Table 5 Termination of unused pins

Recommended pin termination

Connect to V_DD

Connect to V_DDwith initial state (pulled-up input mode)

RESET_N

P00/TEST0

XT0/PI00, XT1/PI01

P01 to P07

P10 to P17

P20 to P27

P30 to P33

P40 to P47

P50 to P57

P60 to P67

P70, P76

.

Open with initial state(Hi-impedance)

P80 to P82

P93 to P96

PA1 to PA4

PB2 to PB5

C₁, C₂

Open

V_L1, V_L2

It is recommended to connect to V_DDthrough a resistor

(1kΩ or more).

V_L3

[Note]



Terminate unused input pins according to the table 5 in order to avoid unexpected through-current in the

pins.

23/60

FEDL62Q1700C-03

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(V_SS= 0V)

Parameter

Symbol

Condition

Ta = +25°C

Rating

Unit

V

Power supply voltage 1

Power supply voltage 2

Power supply voltage 3

Power supply voltage 4

Input voltage

V_DD

V_DDL

V_L3

-0.3 to +6.5

-0.3 to +2.0

V

-0.3 to +6.5

V

V_L1, V_L2

V_IN

-0.3 to V_L3+0.3*¹

-0.3 to V_DD+0.3*¹

V

Output voltage1

V_OUT1

V

Output voltage2

(COM0~COM7, SEG0~SEG61)

V_OUT2

I_OUTH

-0.3 to +6.5

V

Ta = +25°C

1pin

Total

1pin

-40*²

-180*²

+40

“H” level output current

“L” level output current

mA

Ta = +25°C

I_OUTL

mA

Total

+180

Power dissipation

Storage temperature

*¹6.5V or lower

PD

1

W

T_STG

-

-55 to +150

°C

*²The current flowing out the LSI through the pin is described in the negative number.

The applicable maximum current is the absolute value.

For example, -1mA means the maximum current 1mA flows out the LSI through the pin.

[Note]



Use the product within absolute maximum ratings. The absolute maximum ratings are conditions which

may physically deteriorate the quality of product.

Recommended Operating Conditions

(V_SS= 0V)

Unit

Parameter

Operating temperature (Ambient)

Operating temperature (Chip-Junction)

Operating voltage 1

Symbol

Ta

Condition

Range

-40 to +105

-40 to +115

1.6 to 5.5

2.7 to 5.5

2/3 x V_L3

-

°C

V

Tj

-

V_DD

V_L3

-

Operating voltage 2

External supply method

V_DD= 1.6 to 5.5V

V_DD= 1.8 to 5.5V

-

V

Operating voltage 3

V_L2

V

Operating voltage 4

V_L1

1/3 x V_L3

V

30k to 4M

30k to 25M

1.0 ±30%

Operating frequency (CPU)

V_DDLpin external capacitance

f_OP

C_L

Hz

μF

V_L1, V_L2, V_L3pin

external capacitance

C_L1,C_L2,

C_L3

0.47±30% or

1.0±30%

-

0.47±30% or

1.0±30%

C₁and C₂pin external capacitance

C₁₂

μF

24/60

FEDL62Q1700C-03

Thermal characteristics

The maximum chip-junction temperature, T_jmax, may be calculated using the following equation.

푇

ꢀ 푚ꢀꢁ

= 푇

+ 푃_{퐷 푚ꢀꢁ}× 휃

푗 푚ꢀꢁ

푇

ꢀ 푚ꢀꢁ 푗ꢀ

: maximum ambient temperature

푃_{퐷 푚ꢀꢁ}∶ LSI maximum power dissipation

: Package junction to ambient thermal resistance

휃

푗ꢀ

Design a Mounting board by considering heat radiation such as power dissipation and ambient temperature to satisfy the

recommended conditions.

The following table shows each package’s thermal resistance for thermal design reference estimated by simulation based on the

PCB (printed circuit board) conditions define as a below.

Value

Parameter

Symbol

Package type

Unit

L1

L2

TQFP52

TQFP64

QFP64

QFP80

61.7

63.2

47.2

55.5

56.7

58.2

43.3

51.6

Thermal

resistance

θ_ja

^oC/W

PCB conditions:

PCB name

L1

L2

Unit

mm

PCB size （L / W / T）

Number of layers

Wiring density

114.3 / 76.2 / 1.6

1

114.3 / 76.2 / 1.6

2

layer

―

60% (top layer)

60% (top and bottom layer)

Wind condition

No wind (0m/s)

―

25/60

FEDL62Q1700C-03

Current Consumption

(V_DD=1.6 to 5.5V, V_SS=0V, Ta=-40 to +105^oC, unless otherwise specified)

Measuri

Parameter

Symbol

IDD0

Condition

Min.

Typ.*³

Max.

Unit

ng

circuit

Ta = -40 to

+85 ^oC

-

34

68

38

74

42

80

42

80

40

76

CPU is in STOP-D state.

All oscillations are stopped.

Supply current 0

Supply current 1

Supply current 2-1

Supply current 2-2

Supply current 2-3

0.8

μA

Ta = -40 to

+105 ^oC

Ta = -40 to

+85 ^oC

CPU is in STOP state.

All oscillations are stopped.

IDD1

1.2

4.0

3.0

2.2

μA

Ta = -40 to

+105 ^oC

Ta = -40 to

+85 ^oC

Low-speed RC32K Oscillating.^*1

CPU is in HALT state.

IDD2-1

IDD2-2

IDD2-3

Ta = -40 to

+105 ^oC

PLL oscillation is stopped.

Ta = -40 to

+85 ^oC

Low-speed Crystal Oscillating.^*1*4

CPU is in HALT state.

Ta = -40 to

+105 ^oC

PLL oscillation is stopped.

1

Ta = -40 to

+85 ^oC

Low-speed Crystal Oscillating.^*1*4

CPU is in HALT-C state.

μA

Ta = -40 to

+105 ^oC

PLL oscillation is stopped.

CPU: Running with low-speed

RC32K oscillation clock*¹*²

PLL oscillation is stopped.

Ta = -40 to

+105 ^oC

Supply current 3

Supply current 4

IDD3

IDD4

-

17

104

4.0

CPU: Running with 16MHz PLL

oscillating clock*¹*²

Ta = -40 to

+105 ^oC

3.2

PLL 16MHz is oscillating.

V_DD=1.8~5.5V

mA

CPU: Running with 24MHz PLL

oscillating clock*¹*²

Ta = -40 to

+105 ^oC

Supply current 5

IDD5

-

4.5

5.2

PLL 24MHz is oscillating.

V_DD=1.8~5.5V

*¹LTBC and WDT is operating, Significant bits of BCKCON0-3 and BRECON0-3 registers are all “1”

*²CPU running in wait mode

*³On the condition of VDD=3.0V, Ta=+25 ^oC

*⁴When the noise filter is not used in the low power consumption mode

26/60

FEDL62Q1700C-03

Low-speed Crystal Oscillation

(V_DD=1.6 to 5.5V, V_SS=0V, Ta=-40 to +105^oC, unless otherwise specified)

Range

Parameter

Symbol

Condition

Unit

Min.

Typ.

Max.

Crystal oscillation

frequency *¹*²

f_XTL

-

32.768

-

kHz

s

Crystal oscillation start

time

T_XTL

-

2

*¹: The oscillation frequency is determined by the oscillation circuit, crystal resonator and the external capacitance

(C_GL/C_DL). As those parameters changes depending the crystal resonator, it requires evaluation on the actual PCB

circuit for matching. Ask crystal resonator makers for matching and confirm the oscillation characteristics.

*²: The quality of oscillation characteristics might be lost, depending on material of PCB, condition of wiring

capacitance or parasitic capacitance on the external circuits. Note for designing the external circuit.

- Make the wires on the external circuit as short as possible.

- Place the crystal resonator and oscillation circuit as close to the MCU as possible and make the wires between

the external capacitance and crystal resonator as short as possible.

- Ensure no signal line flowing big current runs near the oscillation circuit.

- Ensure no signal line runs under and near the oscillation circuit.

- Make ground of external capacitance the same as MCU ground V_SSpin and connect them to the ground that has

low variation of current and voltage.

- The quality of oscillation characteristics might be lost depending on operating environment due to moisture

absorption of PCB and condensation of PCB surface, recommended to have measures such as covering the

oscillation circuit with resin.

Low-speed Crystal Oscillation external circuit example

XT0

XT1

V_SS

Crystal resonator

(32.768kHz）

C_DL

C_GL

External Clock Input

(V_DD=1.6 to 5.5V, V_SS=0V, Ta=-40 to +105^oC, unless otherwise specified)

Range

Parameter

Symbol

Condition

Unit

Min.

Typ.

Max.

Typ.

-1.0%

Typ.

+1.0%

Input Frequency

Input pulse width

f_EXCK

-

32.768

kHz

s

1/fEXCK

x 0.4

1/fEXCK

x 0.6

t_EXCKW

-

27/60

FEDL62Q1700C-03

On-chip Oscillator

(V_DD=1.6 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Measuri

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

ng

circuit

Typ.

-1.0%

Typ.

+1.0%

Ta= +25°C

32.768

16/24

V_DD= 1.8 to 5.5V

Typ.

-2.5%

Typ.

+2.5%

Ta= -40 to +85°C

V_DD= 1.8 to 5.5V

Low-speed RC oscillator

frequency accuracy 1

f_RCL1

Typ.

-3.0%

Typ.

+3.0%

Ta= -40 to +105°C

V_DD= 1.8 to 5.5V

Without software adjustment

kHz

Typ.

-3.5%

Typ.

+3.5%

V_DD= 1.6 to 1.8V

Typ.

-1.0%

Typ.

+1.0%

Ta= -40 to +85°C

V_DD= 1.8 to 5.5V

Low-speed RC oscillator

frequency accuracy 2

With software adjustment

f_RCL2

f_PLL1

f_PLL2

Typ.

-1.5%

Typ.

+1.5%

Ta= -40 to +105°C

V_DD= 1.8 to 5.5V

1

Typ.

-2.5%

Typ.

+2.5%

Ta= -40 to +85°C

V_DD= 1.8 to 5.5V

PLL oscillation frequency

accuracy 1

Without software adjustment

Typ.

-3.0%

Typ.

+3.0%

Ta= -40 to +105°C

V_DD= 1.8 to 5.5V

16/24

Typ.

-3.5%

Typ.

+3.5%

V_DD= 1.6 to 5.5V

16/24

MHz

Typ.

-1.0%

Typ.

+1.0%

Ta= -40 to +85°C

V_DD= 1.8 to 5.5V

16/24

PLL oscillation frequency

accuracy 2

Typ.

-1.5%

Typ.

+1.5%

Ta= -40 to +105°C

V_DD= 1.8 to 5.5V

With software adjustment

16/24

PLL oscillation start time

T_PLL

V_DD= 1.6 to 5.5V

-

2

ms

1kHz Low-speed RC oscillator

(for WDT) frequency accuracy

Ta= -40 to +105°C

V_DD= 1.6 to 5.5V

f_RC1K

0.5

1

2.5

kHz

28/60

FEDL62Q1700C-03

Input / Output pin 1

(V_DD=1.6 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Measur

Symbol

VOH1

ing

circuit

Parameter

Condition

Min.

Typ.

Max.

Unit

Output voltage1

“H”/“L” level

(P00-P07)

(P10-P17)

(P20-P27)

(P30-P33)

(P40-P47)

(P50-P57)

(P60-P67)

(P70, P76)

(P80-P82)

(P93-P96)

(PA1-PA4)

(PB2-PB5)

IOH1=-10mA

V_DD≥4.5V

V_DD

-1.5

-

IOH1=-1mA

V_DD≥1.6V

V_DD

-0.5

IOL1=+10mA

V_DD≥4.5V

-

1.5

0.5

VOL1

IOL1=+1mA

V_DD≥1.6V

V

2

Output voltage2

“L” level

IOL2=+15mA

-

0.7

0.5

V_DD≥4.5V

(P01-P07)

(P10-P17)

(P20-P27)

(P30-P33)

(P40-P47)

(P50-P57)

(P60-P67)

(P70, P76)

(P80-P82)

(P93-P96)

(PA1-PA4)

(PB2-PB5)

IOL2=+8mA

V_DD≥3.0V

When N-ch open

drain output

VOL2

mode is selected

IOL2=+3mA

-

0.4

V_DD≥2.0V

IOL2=+2mA

0.4

-

V_DD≥1.6V

IOH3M=-0.03mA

V_L3output

V_L3

-0.2

VOH3M

VOH3P

-

IOMH3P=+0.03mA

V_L2output

V_L2

+0.2

-

IOMH3M=-0.03mA

V_L2output

V_L2

-0.2

Output voltage 3

LCD COM/SEG

(COM0~COM7)

(SEG0~SEG61)

VOMH3M

VOML3P

VOML3M

VOL3P

-

V_L3= 3V,

V_L2= 2V,

V_L1= 1V

V

2

IOML3P=+0.03mA

V_L1output

V_L1

+0.2

-

IOML3M=-0.03mA

V_L1output

V_L1

-0.2

-

IOL3P=+0.03mA

V_SSoutput

-

0.2

29/60

FEDL62Q1700C-03

Input / Output pin 2

(V_DD=1.6 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Measu

Symbol

IOH1

ring

circuit

Parameter

Condition

Min.

Typ.

Max. Unit

V_DD≥4.5V

V_DD≥1.6V

-10*³*⁵

-1*³*⁵

-

“H” level output

current1 *⁶

1pin

Total of ‘P00-P07,

P10-P13, P44-P47,

P50-P53, P70, P76,

P80-P82，P93-P96’

or

Total of ‘P14-P17,

P20-P27, P30-P33,

P40-P43, P54-P57,

P60-P67, PA1-PA4，

PB2-PB5’

V_DD≥4.5V

V_DD≥1.6V

-90*⁵

-20*⁵

-

“H” level output

IOH3

total current1 *¹*⁴

(duty≤50%)

V_DD≥4.5V

V_DD≥1.6V

V_DD≥4.5V

V_DD≥1.6V

V_DD≥4.5V

V_DD≥3.0V

V_DD≥2.0V

V_DD≥1.6V

-180*⁵

-40*⁵

-

All pin totals

(duty≤50%)

-

10*³

1*³

15*³

8*³

3*³

2*³

“L” level output

current1 *⁶

1pin (CMOS output

mode)

IOL1

IOL2

mA

“L” level output

current2 *⁶

1pin (N-ch open drain

output mode)

Total of P00-P07,

P10-P13, P44-P47,

P50-P53, P70, P76,

P80-P82, P93-P96’

or

Total of ‘P14-P17,

P20-P27, P30-P33,

P40-P43, P54-P57,

P60-P67, PA1-PA4,

PB2-PB5’

V_DD≥4.5V

V_DD≥3.0V

V_DD≥2.0V

V_DD≥1.6V

-

90

40

15

10

3

“L” level output

total current *²*⁴

IOL3

(N-ch open drain output

mode, duty≤50%)

All pin totals

(N-ch open drain output

mode, duty≤50%)

V_DD≥4.5V

-

180

20

V_DD<2.0V

Output leak

(P00-P07)

(P10-P17)

(P20-P27)

(P30-P33)

(P40-P47)

(P50-P57)

(P60-P67)

(P70, P76)

(P80-P82)

(P93-P96)

(PA1-PA4)

(PB2-PB5)

IOOH

IOOL

VOH=V_DD(High impedance mode)

VOL=V_SS(High impedance mode)

-

+1

μA

-1*⁵

-

30/60

FEDL62Q1700C-03

*¹Sink-out current from V_DDto the output pin, which can guarantee the device operation.

*²Sink-in current from the output pin to V_SS, which can guarantee the device operation.

*³Do not exceed total current.

*⁴The total current is on the condition of Duty≤50% (same applies to IOH1).

When the duty ＞50% the total current is calculated by following formula.

Total current = IOL3 x 50/n (When the duty is n%)

<For an example> When IOL3=100mA and n=80%,

Total current = IOL3 x 50/80 = 62.5mA

Current allowed per 1pin is independent of the duty and specified as IOL1 and IOL2.

Do not apply current larger than Absolute Maximum Ratings.

*⁵The current flowing out the LSI through the pin is described in the negative number.

The applicable maximum current is the absolute value.

For example, -1mA means the maximum current 1mA flows out the LSI through the pin.

*⁶VOH1, VOL1, and VOL2 are satisfied with this spec.

31/60

FEDL62Q1700C-03

Input / Output pin 3

(V_DD=1.6 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Measur

Symbol

ing

circuit

Parameter

Condition

Min.

Typ.

Max.

Unit

IIH1

IIL1

IIL2

V/IIL2

IIH2Z

IIL2Z

VIH1=V_DD

VIL1=V_SS

-

1

-

Input current1

(RESET_N)

-1*¹

μA

VIL2=V_SS(pull-up mode) *²

VIH2=V_DD(High impedance mode)

VIL2=V_SS(High impedance mode)

-1500*¹-300*¹-20*¹

3.7

-

10

-

80

1

-

kΩ

Input current2

(P00/TEST0)

-1*¹

μA

Input current3

(P01-P07)

(P10-P17)

(P20-P27)

(P30-P33)

(P40-P47)

(P50-P57)

(P60-P67)

(P70, P76)

(P80-P82)

(P93-P96)

(PA1-PA4)

(PB2-PB5)

Input current4

(PI00-PI01)

Input voltage1

(RESET_N)

(P01-P07)

(P10-P17)

(P20-P27)

(P30-P33)

(P40-P47)

(P50-P57)

(P60-P67)

(P70, P76)

(P80-P82)

(P93-P96)

(PA1-PA4)

(PB2-PB5)

(PI00-PI01)

IIL3

VIL1=V_SS(pull-up mode) *²

-250*¹

-30*¹

-2*¹

4

V/IIL3

VIL1= V_SS(pull-up mode) *²

22

100

800

kΩ

IIH3Z

IIL3Z

VIH1=V_DD(High impedance mode)

VIL1=V_SS(High impedance mode)

-

1

-

μA

-1*¹

IIH4

IIL4

VIH1=V_DD

VIL1=V_SS

-

1

-

-1^*1

0.7

x V_DD

VIH1

-

V_DD

V

5

0.3

x V_DD

VIL1

-

0

-

0.7

x V_DD

VIH2

VIL2

-

V_DD

Input voltage2

(P00/TEST0)

0.25

×V_DD

0

Pin capacitance

(RESET_N)

(P00/TEST0)

(P01-P07)

(P10-P17)

(P20-P27)

(P30-P33)

(P40-P47)

(P50-P57)

(P60-P67)

(P70, P76)

(P80-P82)

(P93-P96)

(PA1-PA4)

(PB2-PB5)

(PI00-PI01)

f = 10kHz

Ta = +25°C

CPIN

-

10

pF

-

^*1The current flowing out the LSI through the pin is described in the negative number. The applicable maximum current

is the absolute value. For example, -1mA means the maximum current 1mA flows out the LSI through the pin.

^*2Measurement conditions: Typ.: V_DD= 3.0V, Max.: V_DD= 1.6V, Min.: V_DD= 5.5V

32/60

FEDL62Q1700C-03

Synchronous Serial Port

Slave mode

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Symbol

t_SCYC

t_SW

Parameter

Condition

Min.

1 *²

0.5 *³

Typ.

Max.

Unit

μs

SCK input cycle

-

SCK input pulse width

μs

100+

V

_DD=2.4 to 5.5V

-

ns

HSCLK*¹×3

SOUT output delay time

SIN input setup time

t_SD

200+

V_DD=1.8 to 5.5V

-

HSCLK*¹×3

HSCLK*¹

x1

t_SS

t_SH

-

80+

SIN input hold time

HSCLK*¹×3

*¹Cycle of high speed clock

*²Need input cycles of HSCLK x8 or longer

*³Need input cycles of HSCLK x4 or longer

t_SCYC

t_SW

0.7×V_DD

SUn_SCLK*

0.3×V_DD

t_SD

0.7×V_DD

0.3×V_DD

SUn_SOUT*

t_SS

t_SH

0.7×V_DD

0.3×V_DD

SUn_SIN*

*：2^ndto 8^thfunction of port, n=0~3

33/60

FEDL62Q1700C-03

Master mode

Parameter

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Symbol

t_SCYC

Condition

-

Min.

Typ.

SCLK*¹

Max.

Unit

ns

SCK output cycle

-

SCLK*¹

×0.4

SCLK*¹

×0.5

SCLK*¹

×0.6

SCK output pulse width

t_SW

t_SD

t_SS

t_SH

-

ns

V_DD=2.4 to 5.5V

V_DD=1.8 to 5.5V

V_DD=2.4 to 5.5V

V_DD=1.8 to 5.5V

V_DD=2.4 to 5.5V

V_DD=1.8 to 5.5V

-

100

ns

SOUT output delay time

SIN input setup time

SIN input hold time

-

160

120

180

80

-

100

*¹Clock cycle selected by bit12~8(SnCK4~0) of the serial port n mode register (SIOnMOD)

V_DD≥2.4V: min250ns, V_DD≥1.8V: min500ns

t_SCYC

t_SW

0.7×V_DD

SUn_SCLK*

SUn_SOUT*

SUn_SIN*

0.3×V_DD

t_SD

0.7×V_DD

0.3×V_DD

t_SS

t_SH

0.7×V_DD

0.3×V_DD

*：2^ndto 8^thfunction of port, n=0~3

34/60

FEDL62Q1700C-03

I²C Bus Interface

Standard Mode 100kbps

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Symbol

Parameter

Condition

-

Min.

0

Typ.

-

Max.

100

Unit

kHz

SCL clock frequency

f_SCL

SCL hold time

(start/restart condition)

t_HD:STA

-

4.0

-

μs

SCL “L” level time

SCL “H” level time

t_LOW

t_HIGH

-

4.7

4.0

-

μs

SCL setup time

(restart condition)

t_SU:STA

-

4.7

-

μs

SDA hold time

SDA setup time

t_HD:DAT

t_SU:DAT

-

0

-

μs

0.25

SDA setup time

(stop condition)

t_SU:STO

-

4.0

-

μs

Bus-free time

t_BUF

-

4.7

-

μs

When using the I²C as the master, configure the I²C master n mode register (I2MnMOD) and I²C bus 0 mode register

(master side, I2UM0MOD) so that meet these specifications.

Start

Condition

Re-start

Condition

Stop

Condition

I2CUn_SDA

I2CMn_SDA

0.7×V_DD

0.3×V_DD

0.7×V_DD

0.3×V_DD

I2CUn_SCL

I2CMn_SCL

t_SU:STO

t_BUF

t_HD:STA

t_LOW

t_SU:STAt_HD:STA

t_SU:DATt_HD:DAT

t_HIGH

n：0 to 1

35/60

FEDL62Q1700C-03

Fast Mode 400kbps

Parameter

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Symbol

Condition

-

Min.

0

Typ.

-

Max.

400

Unit

kHz

SCL clock frequency

f_SCL

SCL hold time

(start/restart condition)

t_HD:STA

-

0.6

-

μs

SCL “L” level time

SCL “H” level time

t_LOW

t_HIGH

-

1.3

0.6

-

μs

SCL setup time

(restart condition)

t_SU:STA

-

0.6

-

μs

SDA hold time

SDA setup time

t_HD:DAT

t_SU:DAT

-

0

-

μs

0.1

SDA setup time

(stop condition)

t_SU:STO

t_BUF

-

0.6

1.3

-

μs

Bus-free time

When using the I²C as the master, configure the I²C master n mode register (I2MnMOD) and I²C bus 0 mode register

(master side, I2UM0MOD) so that meet these specifications.

Start

Condition

Re-start

Condition

Stop

Condition

I2CUn_SDA

I2CMn_SDA

0.7×V_DD

0.3×V_DD

0.7×V_DD

0.3×V_DD

I2CUn_SCL

I2CMn_SCL

t_SU:STO

t_BUF

t_HD:STA

t_LOW

t_SU:STAt_HD:STA

t_SU:DATt_HD:DAT

t_HIGH

n：0 to 1

36/60

FEDL62Q1700C-03

1Mbps Mode

Parameter

(V_DD=2.7 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Symbol

Condition

-

Min.

0

Typ.

-

Max.

1000

Unit

kHz

SCL clock frequency

f_SCL

SCL hold time

(start/restart condition)

t_HD:STA

-

0.26

-

μs

SCL “L” level time

SCL “H” level time

t_LOW

t_HIGH

-

0.5

-

μs

0.26

SCL setup time

(restart condition)

t_SU:STA

-

0.26

-

μs

SDA hold time

SDA setup time

t_HD:DAT

t_SU:DAT

-

0

-

μs

0.1

SDA setup time

(stop condition)

t_SU:STO

t_BUF

-

0.26

0.5

-

μs

Bus-free time

When using the I²C as the master, configure the I²C master n mode register (I2MnMOD) and I²C bus 0 mode register

(master side, I2UM0MOD) so that meet these specifications.

Start

Condition

Re-start

Condition

Stop

Condition

I2CUn_SDA

I2CMn_SDA

0.7×V_DD

0.3×V_DD

0.7×V_DD

0.3×V_DD

I2CUn_SCL

I2CMn_SCL

t_SU:STO

t_BUF

t_HD:STA

t_LOW

t_SU:STAt_HD:STA

t_SU:DATt_HD:DAT

t_HIGH

n：0 to 1

37/60

FEDL62Q1700C-03

Reset

(V_DD=1.6 to 5.5V, V_SS=0V, Ta=-40 to +105^oC, unless otherwise specified)

Measur

Symbol

ing

circuit

Parameter

Condition

Min.

Typ.

Max.

Unit

Reset pulse width^*2

P00 “H” level setup time^*1

P00 “H” level hold time^*1

P_RST

t_SP00

t_HP00

-

2

1

-

ms

1

*¹: The specification is for except the ISP mode. See Chapter 25.4 “In-System Programing Function” in the User’s

Manual for the timing in ISP mode.

*²: It means the time after the voltage of V_DDreached to 1.6V or higher in the case of power on.

VIH1

RESET_N

VIL1

P_RST

VIH2

“H” level or “L” level

“H” level input

“H” level or “L” level

P00/TEST0

t_SP00

t_HP00

[Note]



Do not drive a pulse into the RESET_N pin that has the pulse width shorter than the Reset pulse width

(P_RST), otherwise unexpected operation may possibly happen.

38/60

FEDL62Q1700C-03

Slope of Power supply and Power on Reset

(V_SS=0V, Ta=-40 to +105^oC, unless otherwise specified)

Measur

Symbol

ing

circuit

Parameter

Condition

Min.

Typ.

Max.

Unit

Power on rising slope

Power on falling slope

S_VR

S_VF

-

60

2

V/ms

V

-

V_PORR

V_PORF

Power up (rising)

Power down (falling)

1.47

1.33

1.57

1.49

1.80

1.58

Power on reset detection

voltage

1

-

V

Power on reset minimum

pulse width

P_POR

V_INIT

-

200

1.8

-

µs

V

Power supply voltage

At power on

CPU operation start time

(from the release of reset to

the CPU starts to run）

t_CPUI

-

11

16

-

ms

At Power supply voltage level change

S_VF

S_VR

At Power supply restart

S_VF

S_VR

V_DD

V_INIT

V_PORR

V_PORF

0V

P_POR

t_CPUI

At Power on

At Power off

[Note]



If a pulse shorter than the Power on reset minimum pulse width is asserted to V_DD, it may cause the MCU

malfunction.

Apply prevent measurement such as bypass capacitors or external reset input, and so on.

Start the high-speed clock when the V_DDis within the operating voltage.



39/60

FEDL62Q1700C-03

VLS

(V_DD=1.6 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Condition

VLS0LV *¹

Measuring

circuit

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

I_VLS

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

3.86

3.84

3.57

3.55

2.94

2.92

2.85

2.83

2.75

2.73

2.66

2.64

2.56

2.54

2.46

2.44

2.37

2.35

1.98

1.96

1.89

1.87

1.79

1.77

-

4.06

4.00

3.76

3.70

3.11

3.05

3.01

2.95

2.91

2.85

2.81

2.75

2.71

2.65

2.61

2.55

2.51

2.45

2.11

2.05

2.01

1.95

1.91

1.85

50

4.26

4.16

3.95

3.85

3.28

3.18

3.17

3.07

2.97

2.96

2.86

2.76

2.66

2.65

2.55

2.24

2.14

2.13

2.03

1.93

-

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

VLS threshold

voltage *²

V

1

VLS Current

-

nA

*¹Bit3~Bit0 of voltage level detection circuit 0 level register (VLS0LV).

*²The Data VSL0LV = 0CH~0FH is not available to use, if the data is specified it will the same spec as that 0BH is

specified.

Analog Comparator

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105^oC, unless otherwise specified)

Measuring

Symbol

V_CMR

Parameter

Condition

Min.

Typ.

Max.

Unit

circuit

Comparator same

phase input

voltage range

V_DD

-1.5

-

0.1

-

V

Comparator0 input

offset

1

V_CMOF

Ta=+25 ^OC、V_DD=5.0V

-

5

-

mV

V

Comparator

Reference Voltage

V_CMREF

-

0.75

0.8

0.85

40/60

FEDL62Q1700C-03

Successive Approximation Type A/D Converter

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105^oC, unless otherwise specified)

Symbol

Parameter

Resolution

Overall error

Condition

-

Min.

-

Typ.

Max.

10

3.5

4

Unit

bit

n_AD

-

4.5V≤V_REFP*¹≤5.5V

2.7V≤V_REFP*¹≤5.5V

2.2V≤V_REFP*¹<2.7V

1.8V≤V_REFP*¹<2.2V

V_REFP=Internal reference voltage

2.7V≤V_REFP*¹≤5.5V

2.2V≤V_REFP*¹<2.7V

1.8V≤V_REFP*¹<2.2V

V_REFP=Internal reference voltage

RI≤1kΩ

-3.5

-4

1.2

-

-6

-

6

Integral non-linearity error

INL_AD

-10

-15

-3

-

10

15

3

-

LSB

-5

-

5

Differential non-linearity

error

DNL_AD

-9

-

9

-14

-6

-

14

6

Zero-scale error

Full-scale error

ZSE

FSE

V_REF

V_REFI

-

RI≤1kΩ

-6

-

6

A/D reference voltage

Internal reference voltage

-

1.8

1.5

2.25

4.5

18

-

V_DD

1.6

427

V

-

1.55

4.5V≤V_DD≤5.5V

2.2V≤V_DD≤5.5V

1.8V≤V_DD≤5.5V

-

Conversion time

t_CONV

μs

*¹: V_DDor P23/V_REFis selected for the reference voltage of Successive Approximation Type A/D Converter.

The current flows during the ADC sampling as it takes charging. Make the output impedance of the analog signal source 1kΩ

or smaller. Also, putting 0.1uF capacitor on the ADC input pin is recommended to reduce the noise.

V_DD

V_DDL

1.0μF

A

RI≤1kΩ

-

1.0μF

AINx

Analog input

+

V_SS

0.1μF

41/60

FEDL62Q1700C-03

D/A Converter

Parameter

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105^oC, unless otherwise specified)

Symbol

n_DA

Condition

Min.

-

Typ.

Max.

Unit

bit

Resolution

-

8

-

Conversion cycle

tc

-

10

-2

μs

Integral non-linearity error

INL_DA

RL=4MΩ

2

LSB

Differential non-linearity

error

DNL_DA

Ro

RL=4MΩ

-1

3

-

1

9

DACEN bit of D/A converter enable

register =1

Output impedance

6

kΩ

Reference Voltage Output

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105^oC, unless otherwise specified)

Symbol

V_REFO

Parameter

Output voltage

Output impedance

Condition

Min.

Typ.

1.55

-

Max.

-

Unit

V

-

R_VREFO

500

kΩ

Flash Memory

(V_SS= 0V)

Unit

Symbol

T_OP

Parameter

Condition

Data flash memory, At write/erase

Flash ROM, At write/erase

At write/erase

Range

-40 to +85

0 to +40

Operating temperature

Operating voltage

°C

V

V_DD

+1.8 to +5.5

10000

100

CEPD

CEPP

Data Flash

Maximum rewrite count

times

Program Flash

Block erase

16K

-

B

Data Flash

all area

1K

Erase unit

Program Flash

Sector erase

-

B

ms

B

Data Flash

128

Block erase /

Sector erase

Erase time (Max.)

Write unit

50

Program Flash

Data Flash

Program Flash

Data Flash

-

4

1

-

80

40

15

Write time (Max.)

μs

Data retention period

YDR

years

42/60

FEDL62Q1700C-03

LCD Driver

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105^oC, unless otherwise specified)

Condition

Range

Typ.

Measuring

circuit

Symbol

Parameter

Unit

LCN^*1

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

Min.

Max.

0.950

0.975

1.000

1.025

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

V_L1x 2

V_L1x 3

Ta=+25 ^oC

C_{L1, L2, L3}=1.0μF

Typ.

-0.05

Typ.

+0.05

V_L1Voltage

V_L1

V

6

V_L2Voltage

V_L3Voltage

V_L2

V_L3

V_L1x 1.8

V_L1x 2.7

-

Ta=+25 ^oC

C_L1,C_L2,C_L3=1.0μF

C₁₂=1.0μF

V

Bias generation circuit

start-up time

t_BIAS

-

200

ms

^*1: Value in LCN4~LCN0 bits of bias control register (BIASCON)

43/60

FEDL62Q1700C-03

Measuring circuit

Measuring circuit 1

V_DD

V_DDL

V_SS

XT0

Crystal resonator

(32.768kHz）

C_GL

XT1

C_V:1.0μF

C_L:1.0μF

C_DL:12pF

C_GL:12pF

A

C_DL

C_V

C_L

Measuring circuit 2

(*2)

VIH

V

(*1)

Current

load

VIL

V_DD

V_DDL

V_SS

(*1) Input logic circuit to determine the specified measuring conditions

(*2) Measured connecting specified pins

Measuring circuit 3

VIH

(*2)

A

(*1)

VIL

V_DD

V_DDL

V_SS

(*1) Input logic circuit to determine the specified measuring conditions

(*2) Measured connecting specified pins

44/60

FEDL62Q1700C-03

Measuring circuit 4

(*2)

A

V_DD

V_SS

V_DDL

(*2) Measured connecting specified pins

Measuring circuit 5

VIH

(*1)

VIL

V_DD

V_DDL

V_SS

(*1) Input logic circuit to determine the specified measuring conditions

Measuring circuit 6

C1

C2

C₁₂

V_L3

V_DD

V_DDL

V_L1V_L2

V_SS

C_L1C_L2C_L3

45/60

FEDL62Q1700C-03

Characteristics graphs

These Graphs on the following pages are references for designing an application.

46/60

FEDL62Q1700C-03

IOH vs VDD-VOH1 (VDD=5V TYP.)

-40[℃]

25[℃]

85[℃]

105[℃]

5

4

3

2

1

0

-60

-50

-40

-30

-20

-10

0

IOH[mA]

IOH vs VDD-VOH1 (VDD=3V TYP.)

-40[℃]

25[℃]

85[℃]

105[℃]

3

2.5

2

1.5

1

0.5

0

-30

-25

-20

-15

-10

-5

0

IOH[mA]

47/60

FEDL62Q1700C-03

IOL vs VOL1 (VDD=5V TYP.)

-40[℃]

25[℃]

85[℃]

105[℃]

5

4

3

2

1

0

10

20

30

40

50

IOL[mA]

IOL vs VOL1 (VDD=3V TYP.)

-40[℃]

25[℃]

85[℃]

105[℃]

3

2.5

2

1.5

1

0.5

0

5

10

15

20

IOL[mA]

48/60

FEDL62Q1700C-03

IOL vs VOL2 (VDD=5V TYP.)

-40[℃]

25[℃]

85[℃]

105[℃]

5

4

3

2

1

0

20

40

60

80

100

IOL[mA]

IOL vs VOL2 (VDD=3V TYP.).

IOL vs VOL2 (VDD=3V TYP.)

-40[℃]

25[℃]

85[℃]

105[℃]

3

2.5

2

1.5

1

0.5

0

10

20

30

40

50

IOL[mA]

49/60

FEDL62Q1700C-03

VDD VS IIL2 (TYP. VIL2=VSS)

VDD vs IIL2 (TYP. VIL2=VSS)

-40℃

25℃

85℃

105℃

0

-100

-200

-300

-400

-500

-600

-700

1

2

3

4

5

6

VDD[V]

Pull-up resistor

VDD VS VDD/IIL2 (TYP. VIL2=VSS)

Pull-up resistor

VDD vs VDD/IIL2 (TYP. VIL2=VSS)

-40℃

25℃

85℃

105℃

14

12

10

8

6

4

2

0

1

2

3

4

5

6

VDD[V]

50/60

FEDL62Q1700C-03

VDD VS IIL3 (TYP. VIL3=VSS)

VDD vs IIL3 (TYP. VIL3=VSS)

-40℃

25℃

85℃

105℃

0

-50

-100

-150

-200

1

2

3

4

5

6

VDD[V]

Pull-up resistor

VDD VS VDD/IIL3 (TYP. VIL3=VSS)

Pull-up resistor

VDD vs VDD/IIL3 (TYP. VIL3=VSS)

-40℃

25℃

85℃

105℃

350

300

250

200

150

100

50

0

1

2

3

4

5

6

VDD[V]

51/60

FEDL62Q1700C-03

Consumption current of ADC VS operating voltage

PLL frequency=16MHz temp=25^oC ch0 VREF=VDD

consumption current of ADC

(PLL frequency=16MHz temp=25^oC ch0 VREF=VDD )

1.2

1

0.8

0.6

0.4

0.2

0

2

2.5

3

3.5

VDD [V]

4

4.5

5

5.5

52/60

FEDL62Q1700C-03

TEMP VS Low-speed RC oscillator frequency accuracy 1

without software adjustment (Typ.)

Low-speed RC oscillator frequency accuracy 1

without software adjustment (Typ.)

VDD=1.8V

VDD=3V

VDD=5.5V

4

3

2

1

0

-1

-2

-3

-4

-40

-20

0

20

40

Temp[^oC]

60

80

100

TEMP VS PLL oscillator frequency accuracy 1

without software adjustment (24MHz Typ.)

PLL oscillator frequency accuracy 1

without software adjustment (24MHz Typ.)

VDD=1.8V

VDD=3V

VDD=5.5V

4

3

2

1

0

-1

-2

-3

-4

-40

-20

0

20

40

60

80

100

Temp[^oC]

53/60

FEDL62Q1700C-03

PACKAGE DIMENSIONS

52pin TQFP Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,

before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package

code and desired mounting conditions (reflow method, temperature and times).

54/60

FEDL62Q1700C-03

64pin TQFP Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,

before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package

code and desired mounting conditions (reflow method, temperature and times).

55/60

FEDL62Q1700C-03

64pin QFP Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,

before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package

code and desired mounting conditions (reflow method, temperature and times).

56/60

FEDL62Q1700C-03

80pin QFP Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,

before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package

code and desired mounting conditions (reflow method, temperature and times).

57/60

FEDL62Q1700C-03

REVISION HISTORY

Page

Document

No.

Date

Description

Current

Edition

FEDL62Q1700C-01

Nov 15, 2019

-

1^stRevision.

Changed comment for UART.

4, 8

23

4, 8

23

Changed note for Termination of unused pins.

Added parameter “Operating temperature (Chip-Junction)”

in Recommended Operating Conditions

24

Removed the section “Operation Confirmed Crystal

Unit(32.768kHz)”.

This section is mentioned in Applications Note;

“Operation-confirmed oscillator for ML62Q1000 series”.

FEDL62Q1700C-02

Jul 28, 2020

25

-

39

*

25

39

*

Added thermal characteristics section

Changed note for Slope of Power supply and Power on Reset.

Corrected typo

-

Changed company name

1

Added Notes in general description section.

Updated TERMINATION OF UNUSED PINS

Added Notes for product usage

FEDL62Q1700C-03

May 19, 2022

23

-

23

59

58/60

FEDL62Q1700C-03

Notes for product usage

Notes on this page are applicable to the all microcontroller products.

For individual notes on each LAPIS Technology microcontroller product, refer to [Note]

in the chapters of each user's manual.

The individual notes of each user’s manual take priority over those contents in this page if they are different.

1. HANDLING OF UNUSED INPUT PINS

Fix the unused input pins to the power pin or GND to prevent to cause the device performing wrong operation or

increasing the current consumption due to noise, etc. If the handlings for the unused pins are described in the chapters,

follow the instruction.

2. STATE AT POWER ON

At the power on, the data in the internal registers and output of the ports are undefined until the power supply voltage

reaches to the recommended operating condition and "L" level is input to the reset pin.

On LAPIS Technology microcontroller products that have the power on reset function, the data in the internal registers

and output of the ports are undefined until the power on reset is generated.

Be careful to design the application system does not work incorrectly due to the undefined data of internal registers and

output of the ports.

3. ACCESS TO UNUSED MEMORY

If reading from unused address area or writing to unused address area of the memory, the operations are not guaranteed.

4. CHARACTERISTICS DIFFERENCE BETWEEN THE PRODUCTS

Electrical characteristics, noise tolerance, noise radiation amount, and the other characteristics are different from each

microcontroller product.

When replacing from other product to LAPIS Technology microcontroller products, please evaluate enough the

apparatus/system which implemented LAPIS Technology microcontroller products.

5. USE ENVIRONMENT

When using this product in a high humidity environment and an environment where dew condensation, take

moisture-proof measures.

59/60

FEDL62Q1700C-03

Notes

1) The information contained herein is subject to change without notice.

2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals, application

notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating conditions, etc.) are within

the ranges specified. LAPIS Technology disclaims any and all liability for any malfunctions, failure or accident arising out of

or in connection with the use of LAPIS Technology Products outside of such usage conditions specified ranges, or without

observing precautions. Even if it is used within such usage conditions specified ranges, semiconductors can break down and

malfunction due to various factors. Therefore, in order to prevent personal injury, fire or the other damage from break down

or malfunction of LAPIS Technology Products, please take safety at your own risk measures such as complying with the

derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures.

You are responsible for evaluating the safety of the final products or systems manufactured by you.

3) Descriptions of circuits, software and other related information in this document are provided only to illustrate the standard

operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other

use of the circuits, software, and information in the design of your product or system. And the peripheral conditions must be

taken into account when designing circuits for mass production. LAPIS Technology disclaims any and all liability for any

losses and damages incurred by you or third parties arising from the use of these circuits, software, and other related

information.

4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Technology

or any third party with respect to LAPIS Technology Products or the information contained in this document (including but

not limited to, the Product data, drawings, charts, programs, algorithms, and application examples、etc.). Therefore LAPIS

Technology shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising

out of the use of such technical information.

5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer systems,

gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our Products in applications

requiring a high degree of reliability (as exemplified below), please be sure to contact a LAPIS Technology representative

and must obtain written agreement: transportation equipment (cars, ships, trains, etc.), primary communication equipment,

traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems,

etc. LAPIS Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising by

using the Product for purposes not intended by us. Do not use our Products in applications requiring extremely high reliability,

such as aerospace equipment, nuclear power control systems, and submarine repeaters, etc.

6) The Products specified in this document are not designed to be radiation tolerant.

7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this document. However,

LAPIS Technology does not warrant that such information is error-free and LAPIS Technology shall have no responsibility

for any damages arising from any inaccuracy or misprint of such information.

8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.

LAPIS Technology shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws

or regulations.

9) When providing our Products and technologies contained in this document to other countries, you must abide by the

procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export

Administration Regulations and the Foreign Exchange and Foreign Trade Act..

10) Please contact a ROHM sales office if you have any questions regarding the information contained in this document or

LAPIS Technology's Products.

11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Technology.

(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.

2-4-8 Shinyokohama, Kouhoku-ku,Yokohama 222-8575, Japan

https://www.lapis-tech.com/en/

60/60


型号：	ML62Q1733C
厂家：	ROHM
描述：	搭载LCD驱动器段码式 ML62Q1700组 16bit微控制器 (工业设备用) 驱动控制器 CD 微控制器驱动器
文件：	总60页 (文件大小：2512K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ML62Q1733C [ROHM]

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