ML62Q2747 (新产品)

FEDL62Q2700-01

Issue Date: Feb 17, 2023

ML62Q2700 Group

16-bit micro controller

GENERAL DESCRIPTION

ML62Q2700 Group is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU

nX-U16/100 and integrated with program memory(Flash memory), data memory(RAM), data Flash (Erase

unit:128byte, Write unit:1byte) and rich peripheral functions such as the multiplier/divider, CRC generator, Clock

generator, Timer, General Purpose Ports, UART, Synchronous serial port, I2C bus interface unit(Master, Slave),

Voltage Level Supervisor(VLS), Successive approximation type 12bit A/D converter, Audio playback function,

LCD driver, Safety function (IEC60730/60335 Class B) and so on.

The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by pipeline

architecture parallel processing.

The built-in on-chip debug function enables debugging and programming the software. Also, ISP (In-System

Programming) function supports the Flash programming in production line.

The ML62Q2700 Group has products as show in the Table1 with multiple package and memory size

combinations.

Table 1 Product List

Data

memory

(RAM)

48pin

TQFP48

WQFN48

52pin

TQFP52

64pin

QFP64

TQFP64

100pin

**QFP100

TQFP100

Program

memory

Data

Flash

80pin

QFP80

256Kbyte

192Kbyte

160Kbyte

96Kbyte

64Kbyte

－

*ML62Q2727

*ML62Q2726

*ML62Q2725

*ML62Q2723

*ML62Q2722

*ML62Q2737

*ML62Q2736

*ML62Q2735

－

**ML62Q2747

**ML62Q2746

**ML62Q2745

－

16Kbyte

8Kbyte

4Kbyte

－

*ML62Q2703

*ML62Q2702

*ML62Q2713

*ML62Q2712

－

*In development **QFP100 In development

Please see the last 2 pages “Notes for product usage” and “Notes” in this document on use with this product.

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FEDL62Q2700-01

ML62Q2700 Group

FEATURES

 CPU

– 16-bit RISC CPU : nX-U16/100 (A35 core)

– Instruction system : 16-bit length instructions

– Instruction set

: Transfer, arithmetic operations, comparison, logic operations, multiplication/division,

bit manipulations, bit logic operations, jump, conditional jump, call return stack

manipulations, arithmetic shift, and so on

– Built-in On-chip debug function (connect to the Lapis Technology on-chip debug emulator)

– Minimum instruction execution time : 1 count of system clock

Approximately 30.5 μs/62.5ns/41.6ns (at 32.768 kHz/16 MHz/24MHz system clock)

 Coprocessor for multiplication and division

– Signed or Unsigned is selectable

Parameter

Multiplication

Division

Expression

16bit × 16bit

32bit ÷ 16bit

32bit ÷ 32bit

Operation time [cycle]

4

8

16

Multiply-accumulate

(non-saturating, non-saturating)

16bit × 16bit + 32bit

4

 Operating voltage and temperature

– Operating voltage

: V_DD= 1.8 to 5.5 V

– Operating temperature : -40 °C to +105 °C

 Flash memory

Parameter

Erase/Write count

Write unit

Program memory area

Data Flash memory area

10,000 cycles

100 cycles

32bit(4byte)

8bit(1byte)

Erase unit

Erase/Write temperature

16Kbyte/1Kbyte

0 °C to +40 °C

all area/128byte

-40 °C to +85 °C

– Background Operation (CPU can work while erasing and rewriting to the Data Flash memory area.)

– The built-in on-chip debug function and ISP (In-System Programming) function enable Flash

programming

This product uses Super Flash® technology licensed from Silicon Storage Technology, Inc.

Super Flash® is a registered trademark of Silicon Storage Technology, Inc.

 Data RAM area

– Rewrite unit: 8bit/16bit (1byte/2byte)

– Parity check function is available (interrupt or reset is generatable at Parity error)

 Clock generation circuit

– Low-speed clock (LSCLK)

Internal low-speed RC oscillation (RC32K)

External low-speed clock input (EXT32K)

: Approximately 32.768 kHz

External low-speed crystal oscillation (XT32K) : Approximately 32.768 kHz,

4 selectable crystal oscillation mode

(Tough, Normal, Low power mode, and Ultra low

power mode)

– High-speed clock (HSCLK)

PLL oscillation: 3 selectable oscillation frequency (24MHz ,16MHz and 1MHz) by code option

– Watch Dog Timer (WDT): built-in independent clock for WDT (RC1K: Approximately 1.024kHz)

– High-speed time base clock (HTBCLK)

Generates a clock with a period of 2 to 8 times that of HSCLK as a peripheral clock.

 Reset

– System Resets by reset input pin, Power-On Reset, voltage level supervisor (VLS), WDT overflow, WDT

invalid clear, RAM parity error, and PC error (unused ROM area access (instruction access) )

– Software reset by BRK instruction (reset CPU only)

– Reset the peripherals individually/collectively by software

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FEDL62Q2700-01

ML62Q2700 Group

 Power management

– Optimal power management with various standby modes

– STOP/STOP-D mode(All clocks are stopped), HALT-D mode(clocks for System and part of the

peripheral block are stopped), HALT/HALT-H mode(clocks for System are stopped)

– HALT-D mode is suitable for long term standby, HALT-H mode is suitable for short term Intermittent

operation standby

– Invisual clock input control to the peripheral blocks by software

– High-speed clock frequency(HSCLK) is configurable (1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of PLL clock, Max

7steps)

– Clock gear: High-speed system clock frequency is changeable dynamically

(1/1, 1/2, 1/4, 1/8, 1/16, 1/32 of HSCLK, Max 6steps)

 Interrupt controller

– Non-maskable interrupt source

– Maskable interrupt sources

– Four step interrupt levels

– External interrupt ports

: 1 (Internal sources: WDT)

: 50 (included the external interrupt 9 sources)

: 8 (selectable from max.32 pins) with sampling filter

and edge(rise, fall, both) selection.

– Expanded external interrupt ports : Max. 4 with sampling filter and edge(rise, fall, both) selection.

 General-purpose ports (GPIO)

– I/O port : Max. 92 (Including pins for shared functions)

– Input port: Max. 3 (Including one pin for shared on-chip debug and two pins for shared low speed crystal

oscillation)

– Carrier frequency output function (for IR communication)

 Watchdog timer (WDT) : 1 channel

– Overflow period

: 8selectable (7.8，15.6，31.3，62.5，125，500，2000，8000[ms])

– Selectable window function (enable or disable): configurable clear enable period (50% or 75% of overflow

period) with invalid clear. When disable, Interrupts the first overflow and resets the second overflow.

When enable, reset occurs for the first overflow.

– Selectable WDT operation : select Enable or Disable by code option

– Selectable operation in HALT/HALT-H mode and HALT-D mode(Continue counting/Stop counting)

– Readable WDT counter: WDT counter monitor function

 Low-speed Time base counter(LTBC) : 2 channels

– Generate 8 frequency (128，64，32，16，8，4，2，1[Hz]) internal pulse signals by dividing the Low-speed

clock (LSCLK)

– 4 interrupts are generatable from 8 different frequencies internal pulse signals

– One of internal pulse signals selected to interrupt can be output from general purpose port (TBCO)

 Functional timer : Max. 8 channels

– Various modes (Continuous, One shot, capture, PWM with the same period and different duties, and

complementary PWM output with the dead time)

– Event trigger (external terminal, 16bit timer, functional timer, LTBC, RC1K)

– Selectable counter clock from various sources (divided by 1 to 8 of LSCLK, HSCLK, HTBCLK, external

clock)

 16-bit General timers : Max. 8 channels

– Timer output (toggled by overflow)

– Selectable counter clock from various sources (divided by 1 to 8 of LSCLK, HSCLK, HTBCLK, LTBC,

RC1K, and external clock)

– Timer X is shared with waiting for the stability of low-speed crystal oscillation

 Synchronous Serial Port : Max. 7 channels (with FIFO: 1 channel, without FIFO: 6 channel)

– FIFO: 4steps for each transmitting and receiving

– Selectable from Master and Slave

– Selectable from LSB first or MSB first

– Selectable 8-bit length or 16-bit length

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FEDL62Q2700-01

ML62Q2700 Group

 UART (Full-duplex communication mode): Max. 6 channels

– Selectable from 5 to 8bit length, parity or no parity, odd parity or even parity, 1 stop bit or 2 stop bits,

Positive logic or Negative logic, LSB first or MSB first

– Sampling filter for receiving data and start bit

– Built-in baud rate generator (HSCLK@16MHz: 4800bps to 920kbps, LSCLK: up to 2400bps)

 I²C bus : 3 channels

– Select from Master mode or Slave mode: 1 channel. Master mode only: 2 channel

– Standard mode (100 kbps), fast mode (400 kbps) and 1Mbps mode(1Mbps)

– 7bit address format

– Master mode: Handshake (Clock synchronization), 10bit slave address format is supported

– Slave mode: Clock stretch function,

 Successive approximation type 12bit A/D converter (SA-ADC) : input Max. 16 channels

– Conversion time: Min. 1.375μs / ch (When the V_DDis higher than 2.7V and the conversion clock is 16MHz)

– Reference voltages are selectable from VDD pin input voltage or External reference voltage (VREF pin)

– dedicated result register for each channel

– Continuous conversion, Trigger start, Interrupt determining by upper limit or lower limit threshold of

conversion result

 Voltage Level Supervisor (VLS) : 1 channel

– Threshold voltage: 15 selectable (from 1.85V to 4.00V)

– Functional Voltage level detection reset (VLS reset) or Functional Voltage level detection interrupt (VLS0

interrupt) is generatable

– Equipped with single mode / with sampling filter / low consumption operation

 Audio playback function

– Audio synthesis method： 4bit ADPCM2, 8bit-non-linear PCM, 8bit Straight PCM, 16bit Straight PCM

– Sampling frequency： 7.81kHz, 5.63kHz, 31.25kHz, 10.42kHz, 20.83kHz, 6.25kHz，12.50kHz, 25.00kHz.

 LCD driver

– Max. 480 dots (60seg x 8 com) ^*1

ML62Q2702/2703：

ML62Q2712/2713：

ML62Q2722/2723/2725/2726/2727：

ML62Q2735/2736/2737：

ML62Q2745/2746/2747：

24seg×8com (com Max.), 29seg×3com (seg Max.)

27seg×8com (com Max.), 32seg×3com (seg Max.)

35seg×8com (com Max.), 40seg×3com (seg Max.)

45seg×8com (com Max.), 50seg×3com (seg Max.)

60seg×8com (com Max.), 65seg×3com (seg Max.)

^*1: Five pins are shared for common or segment, selectable by setting a SFR

– 1/3 bias (built-in bias generation circuit)

– Frame frequency (Approximately. 32Hz，38Hz，64Hz，75Hz，128Hz and 150Hz)

– Four bias generation modes (Internal voltage boost, External capacitive voltage divide, Internal

capacitive voltage divide and External supply voltages)

– Contrast adjustment (16 steps) is available in the Internal voltage boost mode.

 CRC (Cyclic Redundancy Check) generator

– Generation equation: X¹⁶+X¹²+X⁵+1

– Selectable from LSB first or MSB first

– Built-in Automatic program memory CRC calculation mode in HALT mode

 Safety Function

– Automatic switching to the internal low-speed RC oscillation in case the low-speed crystal oscillation

stopped

– RAM/SFR guard

– Automatic program memory CRC calculation

– RAM parity error detection

– ROM unused area access reset (instruction access)

– Clock mutual monitoring, WDT counter monitoring

– SA-ADC test

– Communication loop back test (UART, Synchronous serial port, I²C bus(master))

– GPIO test

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FEDL62Q2700-01

ML62Q2700 Group

 Shipping package

Body size (including lead)

[mm × mm]

Pin pitch

[mm]

Package

Product name

48 pin plastic TQFP

48 pin plastic WQFN

52 pin plastic TQFP

64 pin plastic TQFP

64 pin plastic QFP

80 pin plastic QFP

100 pin plastic TQFP

100 pin plastic QFP

7.0 × 7.0 （9.0 × 9.0）

7.0 × 7.0 （－）

0.50

ML62Q2702/2703-xxxTB

ML62Q2702/2703-xxxGD

ML62Q2712/2713-xxxTB

0.50

0.65

0.50

0.80

0.65

0.50

0.65

10.0 × 10.0 （12.0 × 12.0）

14.0 × 14.0 （16.0 × 16.0）

14.0 × 20.0 （19.0 × 25.0）

ML62Q2722/2723/2725/2726/2727-xxxTB

ML62Q2722/2723/2725/2726/2727-xxxGA

ML62Q2735/2736/2737-xxxGA

ML62Q2745/2746/2747-xxxTB

ML62Q2745/2746/2747-xxxGA

xxx: ROM code number, (NNN: ROM code is blank)

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FEDL62Q2700-01

ML62Q2700 Group

How To Read The Part Number

ML 62 Q 27 4 7 – xxx TB

Package Type

GD ：WQFN

GA ：QFP

TB ：TQFP

ROM Code Number

NNN : Blank

XXX : Custom Code Number

Program Memory Size

2

3

5

6

7

：64KB

：96KB

：160KB

：192KB

：256KB

Pin Count

0

1

2

3

4

：48

：52

：64

：80

：100

Group Name

27xx： 2700 Group

Program Memory Type

Q

: Flash Memory

CPU Type

62 : 16bit CPU nX-U16/100

LAPIS Technology Logic Product

Figure 1 Part Number

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FEDL62Q2700-01

ML62Q2700 Group

Main Function List

Table 2 Main Function List

Interrupt

Timer

Communication Analog Other

Part number

ML62Q2702

48

35

39

24

27

20

23

10

ML62Q2703

32

ML62Q2712

52

6

6 12

2

11

2

ML62Q2713

ML62Q2722

ML62Q2723

3

ML62Q2725

ML62Q2726

ML62Q2727

ML62Q2735

ML62Q2736

ML62Q2737

ML62Q2745

ML62Q2746

ML62Q2747

64

51

35

32

36

12

1

3

5

3

5

9

1

2

1

2

1

41

80

65

85

45

60

8

8 16

6

4

16

100

^*1: Shared with pins for crystal oscillation and debug input.

^*2: The LCD common/segment shared pins are shared for common or segment, selectable by setting a SFR

^*3: All LCD drive pins are shared with general purpose I/O ports.

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FEDL62Q2700-01

ML62Q2700 Group

BLOCK DIAGRAM

CPU（nX-U16/100）

ECSR1～3

DSR/CSR

PC

EPSW1～3

ELR1～3

LR

Multiplier/Divider

(Coprocessor)

GREG

0 ～15

PSW

EA

Timing

ALU

Controller

SP

Program

Memory

（FLASH）

BUS

Controller

Instruction

Decoder

Instruction

Register

TEST1_N

TEST0

On-Chip ICE /

ISP

INT

SCKF0

SDIF0

SDOF0

SSNF0

VDD

VSS

RAM

Power

Circuit

SCLK0-2

SIN0-2

SSIO Unit

Data FLASH

VDDL

SOUT0-2

ESCLK0-2

ESIN0-2

ESOUT0-2

Reset

Function

RESET_N

FLASH

Controller

INT

RXD0-2

TXD0-2

Clock

Generation

Circuit

LCKO

HCKO

Interrupt

UART Unit

ERXD0-2

ETXD0-2

INT

Low-speed

RC

Oscillation

WDT

VLS

INT

SDAU0

SCLU0

I²C Bus

Unit

RC1K

Oscillation

SDAM0-1

SCLM0-1

INT

Low-speed

Crystal

Oscillation

LXT0

LXT1

CRC

Generator

16-bit

Timer

TMO0-6,

TMOX

INT

VREF

AINn

Functional

Timer

FTO0-7

FTO0-7N

SA-ADC

INT

Safety

Function

Low Speed

Time Base

Counter

TBCO

COM0～COM2

COM3～COM7/

SEG0～SEG4

SEG5～SEG64

LCD

Driver

PX0~PX7

(X=0-9, A, B)

GPIO

(External Interrupt)

*1

P01

PI0,PI1 ^*2

EXI0-12

ERCSB

ERSCK

ERSI

VOICE

Controler

ERSO

SOP

SON

*1 : Not available as the input port w hen connecting to the on-chip debug emulator.

*2 : Not available as the input port w hen connecting to the crystalresonator.

Figure 2 Block Diagram

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FEDL62Q2700-01

ML62Q2700 Group

PIN CONFIGURATION

▉

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

PB0/SEG41

PB1/SEG42

PB2/SEG43

PB3/SEG44

PB4/SEG45

PB5/SEG46

P40/SEG47

P41/SEG48

P30/SEG49

P31/SEG50

P32/SEG51

P33/SEG52

P60/SEG53

P61/SEG54

P62/SEG55

P63/SEG56

P64/EXI9/SEG57

P65/SEG58

P66/SEG59

P67/SEG60

P42/SEG61

PB6/SEG62

PB7/SEG63

P77/SEG64

P43

PA0/SEG17

P97/SEG16

P96/SEG15

P95/SEG14

P94/SEG13

P93/SEG12

P92/SEG11

P91/SEG10

P90/SEG9

P53/SEG8

P52/SEG7

ML62Q2745

ML62Q2746

ML62Q2747

P51/SEG6

P50/EXI8/SEG5

P13/COM7/SEG4

P12/COM6/SEG3

P11/COM5/SEG2

P10/COM4/SEG1

P07/COM3/SEG0

P06/COM2

P05/COM1

P04/EXI2/EXTRG2/COM0

P70

TQFP100

(Top View)

VL3

VL2

VL1

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

▉

Fig.3-1 100 pin TQFP

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FEDL62Q2700-01

ML62Q2700 Group

▉

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

50

PB3/SEG44

PB4/SEG45

PB5/SEG46

P40/SEG47

P41/SEG48

P30/SEG49

P31/SEG50

P32/SEG51

P33/SEG52

P60/SEG53

P61/SEG54

P62/SEG55

P63/SEG56

P64/EXI9/SEG57

P65/SEG58

P66/SEG59

P67/SEG60

P42/SEG61

PB6/SEG62

PB7/SEG63

P96/SEG15

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

P95/SEG14

P94/SEG13

P93/SEG12

P92/SEG11

P91/SEG10

P90/SEG9

P53/SEG8

ML62Q2745

ML62Q2746

ML62Q2747

P52/SEG7

P51/SEG6

P50/EXI8/SEG5

P13/COM7/SEG4

P12/COM6/SEG3

P11/COM5/SEG2

P10/COM4/SEG1

P07/COM3/SEG0

P06/COM2

QFP100

(Top View)

P05/COM1

P04/EXI2/EXTRG2/COM0

P70

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

▉

Fig.3-2 100 pin QFP

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FEDL62Q2700-01

ML62Q2700 Group

▉

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

PB2/SEG43

PB3/SEG44

PB4/SEG45

PB5/SEG46

P40/SEG47

P41/SEG48

P30/SEG49

P31/SEG50

P32/SEG51

P33/SEG52

P60/SEG53

P61/SEG54

P62/SEG55

P63/SEG56

P64/EXI9/SEG57

P65/SEG58

P66/SEG59

P67/SEG60

P42/SEG61

P43

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

P96/SEG15

P95/SEG14

P94/SEG13

P93/SEG12

P53/SEG8

P52/SEG7

P51/SEG6

P50/EXI8/SEG5

P13/COM7/SEG4

P12/COM6/SEG3

P11/COM5/SEG2

P10/COM4/SEG1

P07/COM3/SEG0

P06/COM2

ML62Q2735

ML62Q2736

ML62Q2737

QFP80

(Top View)

P05/COM1

P04/EXI2/EXTRG2/COM0

P70

VL3

VL2

VL1

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

▉

Fig.3-3 80 pin QFP

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FEDL62Q2700-01

ML62Q2700 Group

Fig.3-4 64 pin TQFP/QFP

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FEDL62Q2700-01

ML62Q2700 Group

Fig.3-5 52 pin TQFP

13/55

FEDL62Q2700-01

ML62Q2700 Group

36 35 34 33 32 31 30 29 28 27 26 25

▉

P30/SEG49 37

P31/SEG50 38

P32/SEG51 39

P33/SEG52 40

P60/SEG53 41

P61/SEG54 42

P62/SEG55 43

P63/SEG56 44

P64/EXI9/SEG57 45

P65/SEG58 46

P66/SEG59 47

P43 48

24 P50/EXI8/SEG5

23 P13/COM7/SEG4

22 P12/COM6/SEG3

21 P11/COM5/SEG2

20 P10/COM4/SEG1

19 P07/COM3/SEG0

18 P06/COM2

ML62Q2702

ML62Q2703

WQFN48

(Top View)

17 P05/COM1

16 P04/EXI2/EXTRG2/COM0

15 VL3

14 VL2

13 VL1

▉

1

2

3

4

5

6

7

8

9

10 11 12

DIE PAD = NC

Fig.3-6 48 pin WQFN

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FEDL62Q2700-01

ML62Q2700 Group

Fig.3-7 48 pin TQFP

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FEDL62Q2700-01

ML62Q2700 Group

PIN LIST

Table 3 Pin List(1/3)

1^stfunc.

2^ndfunc.

3^rdfunc.

4^thfunc.

I²C

5^thfunc.

FTM

6^thfunc.

Timer

7^thfunc.

Pin No.

LSI

Career

frequency

output

EXI/

LCD/

ADC

CLKOUT/

LTBC

SSIO

UART

name

3

-

3

-

3

-

3

5

VDD

-

42 52 54

-

4

-

4

-

4

-

4

6

VSS

-

41 51 53

NC

-

5

1

2

6

7

8

9

5

1

2

6

7

8

9

5

1

2

6

7

8

5

1

2

6

7

8

5

1

2

6

7

8

7

3

VDDL

XT0

-

PI00

-

4

XT1

PI01

-

RESET_N

TEST1_N

P01/TEST0

P02

8

-

9

-

10

-

11 14 19 21

EXI0

SIN0

RXD0

SCLU0

FTO0

LCKO

EXI1

AIN11

10 10 12 15 20 22

16 17 21 25 30 32

P03

P04

●

SOUT0

SCLK0

TXD0

-

SDAU0

SCLU0

FTO0N

-

HCKO*¹

EXI2

COM0

-

TMO0

-

17 18 22 26 31 33

18 19 23 27 32 34

P05

P06

-

COM1

COM2

SIN2

-

SOUT2

SDAM0

COM3

SEG0

19 20 24 28 33 35

20 21 25 29 34 36

P07

P10

-

SCLK2

-

RXD0

TXD0

SCLM0

-

COM4

SEG1

EXI1

COM5

SEG2

21 22 26 30 35 37

22 23 27 31 36 38

P11

P12

●

SCLK0

SIN0

-

EXI6

COM6

SEG3

-

RXD0

TMO4

EXI7

COM7

SEG4

23 24 28 32 37 39

25 27 35 45 57 59

P13

P14

●

SOUT0

SDIF0

TXD0

-

TMO1

-

TMO3

EXI2

SEG22

-

ERSI*²

26 28 36 46 58 60

27 29 37 47 59 61

P15

P16

-

SEG23

SEG24

SSNF0

SCLK1

-

SDAU0

SCLU0

-

ERCSB*²

ERSO*²

SDOF0^*2

TMO5

EXI3

SEG25

AIN0

28 30 38 48 60 62

29 31 39 49 61 63

30 32 40 50 62 64

31 33 41 51 63 65

32 34 42 52 64 66

P17

P20

P21

P22

P23

-

●

-

RXD0

TXD0

RXD1

TXD1

-

FTO1

FTO1N

FTO2

FTO2N

-

SEG26

AIN1

-

TBCO

LCKO

HCKO*¹

-

EXI4

SEG27

AIN2

SIN1

SOUT1

SCLK1

-

AIN3

SEG28

●

-

SDAM0

SCLM0

EXI5

SEG29

VREF

TMO2

SEG30

AIN4

33 35 43 53 65 67

34 36 44 54 66 68

P24

P25

-

SIN1

RXD1

TXD1

-

SEG31

AIN5

●

SOUT1

EXI6

SEG32

AIN6

35 37 45 55 67 69

P26

-

RXD1

SDAU0

SCLU0

FTO3

-

EXI7

SEG33

AIN7

36 38 46 56 68 70

P27

●

-

TXD1

FTO3N

TBCO

^*1: Assign each function; HCKO to only one LSI pin.

^*2: No assignment to products of 100 PIN, 80 PIN and 64 PIN-packages.

16/55

FEDL62Q2700-01

ML62Q2700 Group

Table 3 Pin List(2/3)

1^stfunc.

2^ndfunc.

3^rdfunc.

4^thfunc.

I²C

5^thfunc.

FTM

6^thfunc.

7^thfunc.

Pin No.

LSI

name

Career

frequency

output

EXI/

LCD/

ADC

CLKOUT/

LTBC/

SFMIF

Timer/

SOUND

SSIO

UART

37 41 51 67 84 86

38 42 52 68 85 87

39 43 53 69 86 88

40 44 54 70 87 89

P30

P31

P32

P33

P40

P41

P42

P43

-

SEG49

ESIN1

-

EXI1

SEG50

ESOUT1

-

TBCO

-

SEG51

ESCLK1

RXD1

TXD1

ETXD2

ERXD2

ETXD0

-

EXI2

SEG52

●

-

TMO3

-

49 65 82 84

40 50 66 83 85

63 79 96 98

SEG47

-

EXI0

SEG48

-

SEG61

EXI7

AIN10

48 52 64 80 100

2

-

TBCO

-

9

12 17 19

P44

P45

P46

P47

-

EXI2

EXI3

EXI4

EXI5

-

ERXD1

-

FTO3N

-

10 13 18 20

13 16 21 23

-

ETXD1

-

SDAU0

SCLU0

FTO1N

FTO1

11 14 17 22 24

SCLK0

EXI8

SEG5

24 25 29 33 38 40

P50

P51

P52

P53

P54

P55

P56

-

SCKF0

SDOF0

SDIF0

SSNF0

SCKF0

SDOF0

SIN2

-

ERSCK

EXI3

SEG6

-

26 30 34 39 41

-

ERSO

EXI4

SEG7

-

31 35 40 42

32 36 41 43

33 43 55 57

34 44 56 58

ERXD1

ETXD1

RXD2

TXD2

RXD2

-

ERSI

EXI5

SEG8

-

ERCSB

EXI0

SEG20

FTO7

FTO7N

-

TMOX

-

EXI1

SEG21

-

SEG34

AIN12*³

39 47 57 69 71

48 58 70 72

SEG35

AIN13*³

-

P57

P60

P61

P62

P63

-

SOUT2

ESIN2

ESOUT2

ESCK2

-

TXD2

-

41 45 55 71 88 90

42 46 56 72 89 91

43 47 57 73 90 92

44 48 58 74 91 93

SEG53

-

SCLM1

-

EXI3

SEG54

SDAM1

-

SOP

SON

-

SEG55

-

FTO4N

FTO4

EXI4

SEG56

EXI9

SEG57

45 49 59 75 92 94

46 50 60 76 93 95

47 51 61 77 94 96

P64

P65

-

ESIN0

ERXD0

ETXD0

-

FTO5

-

EXI5

SEG58

AIN8

ESOUT0

FTO5N

SEG59

AIN9

P66

P67

-

ESCLK0

-

FTO6

-

EXI6

SEG60

-

62 78 95 97

20 24 29 31

ERXD0

FTO6N

P70

VL3

VL2

VL1

C2

-

EXI0

-

TMO6

-

15 16 19 23 28 30

16 15 18 22 27 29

13 14 17 21 26 28

12 13 16 20 25 27

11 12 15 19 24 26

-

C1

-

18 23 25

P76

EXI10

-

99

1

P77

SEG64

^*3: The pins of name with AIN12 or AIN13 are not assigned to products of 64 PIN-packages.

17/55

FEDL62Q2700-01

ML62Q2700 Group

Table 3 Pin List(3/3)

1^stfunc.

2^ndfunc.

3^rdfunc.

4^thfunc.

I²C

5^thfunc.

FTM

6^thfunc.

Timer

7^thfunc.

Pin No.

LSI

name

Career

frequency

output

EXI/

LCD/

ADC

CLKOUT/

LTBC

SSIO

UART

-

9

11

P80

P81

P82

P83

P84

P85

P86

P87

P90

P91

P92

P93

P94

P95

P96

P97

PA0

PA1

PA2

-

EXI6

EXI7

-

ESIN1

ERXD1

-

10 10 12

11 11 13

ESOUT1

ETXD1

-

ESCLK1

-

12 14

13 15

14 16

15 17

16 18

42 44

43 45

44 46

-

ERXD2

-

ETXD2

-

FTO7

-

FTO7N

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

-

37 45 47

38 46 48

39 47 49

40 48 50

ESIN1

ERXD1

FTO6

ESOUT1

ETXD1

FTO6N

ESCLK1

-

49 51

50 52

53 55

54 56

EXI11

SEG36

AIN14

-

59 71 73

PA3

-

SCLK2

-

FTO7

-

SEG37

AIN15

-

60 72 74

PA4

-

FTO7N

-

73 75

74 76

75 77

76 78

77 79

PA5

PA6

PA7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

-

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

SEG62

SEG63

-

61 78 80

62 79 81

63 80 82

64 81 83

ESIN2

ERXD2

ESOUT2

ETXD2

ESCLK2

-

ERXD2

-

97 99

98 100

-

18/55

FEDL62Q2700-01

ML62Q2700 Group

PIN DESCRIPTION

“I/O” Field in the below table define the pin type (“-“ : power supply pin, “I” : Input pin, “O” : Out put pin, “I/O” bi-directional pin)

Table 4 Pin Description (1/5)

Functional pin

Function

Power

LSI pin name

I/O

Description

name

Negative power supply pin (-)

Define the potential of this terminal as V_SS

－

VSS

－

Positive power supply pin (+).

－

VDD

－

Connect a capacitor C_V(more than 1µF) between this pin and

VSS. Define the potential of this terminal as V_DD.

Power supply for internal logic (internal regulator’s output).

Connect a capacitor C_L(1μF) between this pin and VSS_.

VDDL

Input/output for testing

P01/

TEST0

This pin which is shared with P00 is used as on-chip debug

interface and ISP function and is initialized as pull-up input mode

by the system reset.

TEST0

I/O

Debug

ISP

Input for testing

TEST1_N

RESET_N

TEST1_N

RESET_N

I

This pin is used as on-chip debug interface and ISP function and

is initialized as pull-up input mode by the system reset.

Reset input.

Applying “L” level shifts the MCU in system reset mode.

Applying “H” level shifts the CPU in program running mode.

No pull-up resistor is installed.

Reset

Not used

NC

－

Open

General purpose input.

PI00, PI01

XT0, XT1

I

- High-impedance (initial value)

- Input without Pull-up

General

input port

(GPI)

General purpose input.

- Input with Pull-up (initial value)

- Input without Pull-up

Not available as general inputs when using the on-chip debug

interface or ISP function.

P01/

TEST0

P01

I

P02～P07

P10～P17

P20～P27

P30～P33

P40～P47

P50～P57

P60～P67

P02～P07

P10～P17

P20～P27

P30～P33

P40～P47

P50～P57

P60～P67

General purpose input/output

- High-impedance (initial value)

- Input with Pull-up

- Input without Pull-up

- CMOS output

General port

(GPIO)

I/O

P70, P76～P77 P70, P76～P77

- N channel (N-ch) open drain output

P80～P87

P90～P97

PA0～PA7

PB0～PB7

XT0

P80～P87

P90～P97

PA0～PA7

PB0～PB7

XT0

I

Connect to the Low speed crystal resonator

Connect 32.768kHz crystal resonator and connect capacitors

between the pin and V_SS. When inputting a square wave,

Connect to XT1 pin

Clock Input

XT1

I/O

HCKO

LCKO

P03 P22

P02 P21

O

High-speed clock output.

Low-speed clock output.

Clock Output

(7^thfunc.)

P20 P27 P31

P43

TBCO

O

Low-speed time base counter output.

Career

frequency

output

P03 P11 P13

P20 P22 P25

P27 P33

―

O

Career frequency output

19/55

FEDL62Q2700-01

ML62Q2700 Group

Table 4 Pin Description (2/5)

I/O

Functional

pin name

Function

LSI pin name

Description

EXI0

EXI1

EXI2

EXI3

EXI4

EXI5

EXI6

EXI7

EXI8

P02 P41 P54 P70

P03 P31 P55 P50

P04 P33 P14 P44

P17 P61 P51 P45

P21 P63 P52 P46

P23 P65 P53 P47

P26 P67 P12 P80

P27 P43 P13 P81

P50

I

O

External Maskable Interrupt 0 Input

External Maskable Interrupt 1 Input

External Maskable Interrupt 2 Input

External Maskable Interrupt 3 Input

External Maskable Interrupt 4 Input

External Maskable Interrupt 5 Input

External Maskable Interrupt 6 Input

External Maskable Interrupt 7 Input

External Maskable Interrupt 8 Input

External Maskable Interrupt 9 Input

External Maskable Interrupt 10 Input

External Maskable Interrupt 11 Input

16bit General Timer 0 output

16bit General Timer 1 output

16bit General Timer 2 output

16bit General Timer 3 output

16bit General Timer 4 output

16bit General Timer 5 output

16bit General Timer 6 output

16bit General Timer X output

Functional Timer0 P output

Functional Timer0 N output

Functional Timer1 P output

Functional Timer1 N output

Functional Timer2 P output

Functional Timer2 N output

Functional Timer3 P output

Functional Timer3 N output

Functional Timer4 P output

Functional Timer4 N output

Functional Timer5 P output

Functional Timer5 N output

Functional Timer6 P output

Functional Timer6 N output

Functional Timer7 P output

Functional Timer7 N output

External

Interrupt

(1^stfunc.)

EXI9

P64

P76

PA3

P04

P13

P23

P13 P33

P12

P16

P70

P54

P02

P03

P17 P47

P20 P46

P21

EXI10

EXI11

TMO0

TMO1

TMO2

TMO3

TMO4

TMO5

TMO6

TMOX

FTO0

FTO0N

FTO1

FTO1N

FTO2

FTO2N

FTO3

FTO3N

FTO4

FTO4N

FTO5

FTO5N

FTO6

FTO6N

FT71

16bit General

Timer

(6^thfunc.)

P22

P01 P26

P27 P44

P63

P62

P64

Functional

Timer

(5^thfunc.)

P65

P66 P93

P67 P94

P54 P86 PA3

P55 P87 PA4

P02

FTO7N

P04

P16

P27

P47

P03

P15

P26

SCLU0

SDAU0

I/O

I²C Unit0 Clock input/output

I²C Unit0 Data input/output

I²C Bus

(4^thfunc.)

P46

P07

P23

P06

P22

SCLM0

SDAM0

I/O

I²C Master0 Clock input/output

SCLM1

SDAM1

P60

P61

I/O

I²C Master1 Clock input/output

I²C Master1 Data input/output

20/55

FEDL62Q2700-01

ML62Q2700 Group

Table 4 Pin Description (3/5)

I/O

Functional

pin name

Function

LSI pin name

Description

RXD0

TXD0

P02 P07 P12 P17

P03 P10 P13 P20

P21 P24 P26 P32

P22 P25 P27 P33

P54 P56

I

O

I

UART0 received data input

UART0 transmission data output

UART1 received data input

RXD1

TXD1

O

I

UART1 transmission data output

UART2 received data input

RXD2

TXD2

P55 P57

O

I

UART2 transmission data output

Expanded UART0 received data input

UART

(3^rdfunc.)

ERXD0

ETXD0

ERXD1

ETXD1

ERXD2

ETXD2

SCKF0

SDIF0

P64 P67

P42 P65

O

I

Expanded UART0 transmission data output

Expanded UART1 received data input

Expanded UART1 transmission data output

Expanded UART2 received data input

Expanded UART2 transmission data output

Synchronous serial0 (with FIFO) clock input/output

Synchronous serial0 (with FIFO) data input

Synchronous serial0 (with FIFO) data output

Synchronous serial0 (with FIFO) slave select input/output

Synchronous serial0 clock input/output

Synchronous serial0 data input

P44 P52 P80 P93

P45 P53 P81 P94

P41 P83 PB2 PB5

P40 P84 PB3

P50 P54

O

I

O

I/O

I

P14 P52

SDOF0

SSNF0

SCLK0

SIN0

P51 P55

O

I/O

I

P15 P53

P04 P11 P47

P02 P12

SOUT0

SCLK1

SIN1

P03 P13

O

I/O

I

Synchronous serial0 data output

P16 P23

Synchronous serial1 clock input/output

Synchronous serial1 data input

P21 P24

SOUT1

SCLK2

SIN2

P22 P25

O

I/O

I

Synchronous serial1 data output

Synchronous

Serial Port

(2^ndfunc.)

P07 PA3

Synchronous serial2 clock input/output

Synchronous serial2 data input

P05 P56

SOUT2

ESCLK0

ESIN0

ESOUT0

ESCLK1

ESIN1

ESOUT1

ESCLK2

ESIN2

ESOUT2

P06 P57

O

I/O

I

Synchronous serial2 data output

P66

Expanded Synchronous serial0 clock input/output

Expanded Synchronous serial0 data input

Expanded Synchronous serial0 data output

Expanded Synchronous serial1 clock input/output

Expanded Synchronous serial1 data input

Expanded Synchronous serial1 data output

Expanded Synchronous serial2 clock input/output

Expanded Synchronous serial2 data input

Expanded Synchronous serial2 data output

P64

P65

O

I/O

I

P32 P82 P95

P30 P80 P93

P31 P81 P94

P62 PB4

O

I/O

I

P60 PB2

P61 PB3

O

Audio

SOP

P61

O

P-side output of PWM for audio

Playback

Function

(6^thfunc.)

SON

P62

O

N-side output of PWM for audio

Serial clock input and output of external serial flash memory for

audio

ERSCK

P50

O

Serial

Serial data output of external serial flash memory for audio

Serial data input for external serial flash memory for audio

ERSO

ERSI

P51

P52

O

I

Memory

Inferface

(7^thfunc.)

Chip select input/output of external serial flash memory for

audio

ERCSB

VREF

P53

P23

O

I

SA-ADC external reference voltage input

Define the potential of reference voltage for SA-ADC as V_REF

Successive

approximation

type A/D

P17 P20 P21 P22

P24 P25 P26 P27

P65 P66 P43 P03

P56 P57 PA3 PA4

converter

AIN0~AIN15

I

SA-ADC channel 0 to 13 analog input

(SA-ADC)

(1^stfunc.)

21/55

FEDL62Q2700-01

ML62Q2700 Group

Table 4 Pin Description (4/5)

I/O

Functional

pin name

Function

LSI pin name

Description

COM0

COM1

P04

P05

P06

P07

P10

P11

P12

P13

P50

P51

P52

P53

P90

P91

P92

P93

P94

P95

P96

P97

PA0

PA1

PA2

P54

P55

P14

P15

P16

P17

P20

P21

P22

P23

P24

P25

P26

P27

P56

P57

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

-

Common output

COM2

COM3/SEG0

COM4/SEG1

COM5/SEG2

COM6/SEG3

COM7/SEG4

SEG5

Common/Segment output shared

Segment output

SEG6

Segment output

SEG7

Segment output

SEG8

Segment output

SEG9

Segment output

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

Segment output

LCD Driver

Segment output

22/55

FEDL62Q2700-01

ML62Q2700 Group

Table 4 Pin Description (5/5)

I/O

Functional

pin name

Function

LSI pin name

Description

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

SEG62

SEG63

SEG64

PB3

PB4

PB5

P40

P41

P30

P31

P32

P33

P60

P61

P62

P63

P64

P65

P66

P67

P42

PB6

PB7

P77

-

Segment output

LCD Driver

LCD bias power source generation

capacitor connection

C1, C2

-

LCD bias power source.

Connect the capacitors (C_L1, C_L2, C_L3) between the pin and Vss.

VL1 ~ VL3

23/55

FEDL62Q2700-01

ML62Q2700 Group

TERMINATION OF UNUSED PINS

Table 5 shows the processing of unused pins.

Table 5 Termination of unused pins

pin termination

NC

Open

RESET_N

TEST1_N

P01/TEST0

XT0, XT1

P02 ~ P07

P10 ~ P17

P20 ~ P27

P30 ~ P33

P50 ~ P57

P60 ~ P67

P70, P76, P77

P80 ~ P87

P90 ~ P97

PA0 ~ PA7

PB0 ~ PB7

Connect to V_DD

Open the pin with the initial condition of pulled-up input mode

Open the pins with the initial condition of Hi-impedance mode.

Open

C1, C2

VL1, VL2

Open

It is recommended to connect to V_DDthrough a resistor

(1kΩ or more).

VL3

[Note]



Terminate unused input pins according to the table 5 in order to avoid unexpected through-current in the

pins.

24/55

FEDL62Q2700-01

ML62Q2700 Group

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(V_SS= 0V)

Parameter

Symbol

V_DD

Condition

Ta = +25°C

Rating

Unit

V

Power supply voltage 1

Power supply voltage 2

Power supply voltage 3

Power supply voltage 4

Input voltage

-0.3 to +6.5

-0.3 to +2.0

V_DDL

V

V_L3

-0.3 to +6.5

V

V_L1, V_L2

V_IN

-0.3～V_L3+0.3*^１

-0.3 to V_DD+0.3*¹

V

Output voltage1

V_OUT1

V

Output voltage2

(COM0 ~ COM7,

SEG0 ~ SEG64)

V_OUT2

-0.3 to +6.5

V

Ta = +25°C

1pin

Total

1pin

Total

-40*²

-180*²

+40

“H” level output current

“L” level output current

I_OUTH

I_OUTL

mA

Ta = +25°C

+180

Power dissipation

PD

1

W

Storage temperature

T_STG

―

-55 to +150^*3

°C

*1: 6.5V or lower

*2: The current flowing out the LSI through the pin is described in the negative number.

The applicable maximum current is the absolute value.

For example, -1mA means the maximum current 1mA flows out the LSI through the pin.

*3: Please observe a storage conditions shown in the document “Board Mounting (soldering)” about the storage conditions until

implementation.

[Note]



Stresses above the absolute maximum ratings listed in the above table may cause permanent damage to

the device.

These are stress ratings only and functional operation of the device at these conditions is not implied.

Recommended Operating Conditions

(V_SS= 0V)

Unit

Parameter

Operating temperature (Ambient)

Operating temperature (Chip-Junction)

Operating voltage 1

Symbol

Ta

Condition

Range

-40 to +105

-40 to +115

1.8 to 5.5

2.7 to 5.5

2/3 x V_L3

―

°C

V

Tj

―

V_DD

V_L3

V_L2

V_L1

f_OP

―

Operating voltage 2

External supply method

V_DD= 1.8 to 5.5V

―

V

Operating voltage 3

V

Operating voltage 4

1/3 x V_L3

V

Operating frequency (CPU)

V_DDLpin external capacitance

30k to 25M

1.0 ±30%

Hz

μF

C_L

V_L1, V_L2, V_L3pin

external capacitance

C_L1, C_L2,

C_L3

0.47 ±30% or

1.0 ±30%

―

μF

0.47 ±30% or

1.0 ±30%

C₁and C₂pin external capacitance

C₁₂

25/55

FEDL62Q2700-01

ML62Q2700 Group

Thermal characteristics

The maximum chip-junction temperature, T_jmax, may be calculated using the following equation.

ꢀ

ꢁ ꢂꢃꢄ

= ꢀ

+ ꢅ_{ꢆ ꢂꢃꢄ}× ꢇ

ꢃ ꢂꢃꢄ ꢁꢃ

ꢀ

ꢃ ꢂꢃꢄ

: maximum ambient temperature

ꢅ_{ꢆ ꢂꢃꢄ}∶ LSI maximum power dissipation

: Package junction to ambient thermal resistance

ꢇ

ꢁꢃ

Design a Mounting board by considering heat radiation such as power dissipation and ambient temperature to

satisfy the recommended conditions.

The following table shows the each package’s thermal resistance for thermal design reference estimated by

simulation based on the PCB (printed circuit board) conditions define as a below.

Value

Parameter

Symbol

Package type

Unit

L1

L2

TQFP48

WQFN48

TQFP52

TQFP64

QFP64

60.2

31.1

61.7

63.2

47.2

55.5

48.0

104.7

56.9

27.4

56.7

58.2

43.3

51.6

43.3

101.3

Thermal

resistance

θ_ja

°C/W

QFP80

TQFP100

QFP100

PCB conditions:

PCB name

PCB size (L / W / T)

Number of layer

Wiring density

L1

L2

Unit

mm

layer

―

114.3 / 76.2 / 1.6

1

114.3 / 76.2 / 1.6

2

60% (top layer)

60% (top and bottom layer)

Wind condition

No wind (0m/s)

―

26/55

FEDL62Q2700-01

ML62Q2700 Group

Current Consumption 1

Product： ML62Q2725, ML62Q2726, ML62Q2727, ML62Q2735, ML62Q2736, ML62Q2737,

ML62Q2745, ML62Q2746, ML62Q2747

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Condition

Max.

Parameter

Min.

Typ.^*2

Operating mode

circuit state ^*1

Tj≤

+95^oC

Tj≤

+115^oC

IDD0

IDD1

STOP-D

STOP

All clocks are stopped.

―

0.55

0.7

30

45

65

90

μA

RC32K is oscillating.

XT32K/PLL are stopped.

IDD2-0R

HALT-D

HALT

―

0.9

30

65

μA

XT32K is oscillating with

LP mode, without

noise-filter.

RC32K/PLL are stopped.

IDD2-0X

―

1.25

30

70

μA

RC32K is oscillating.

XT32K/PLL are stopped.

IDD2-1R

IDD3

―

1.1

11

45

100

110

μA

CPU running in

wait-mode

SYSCLK=32.768kHz

RC32K is oscillating.

XT32K/PLL are stopped.

―

1

PLL is oscillating as

PLL1M mode.

HSCLK = 1MHz

IDD4-H1

IDD4-H16

IDD5-H16

IDD5-H24

―

0.23

0.33

2.4

―

0.48

0.63

3.3

mA

CPU running in

wait-mode

SYSCLK=1MHz

PLL is oscillating as

PLL16M mode.

HSCLK = 16MHz

CPU running in

wait-mode

SYSCLK=16MHz

PLL is oscillating as

PLL16M mode.

HSCLK = 16MHz

CPU running in

wait-mode

PLL is oscillating as

PLL24M mode.

3.5

4.5

SYSCLK=24MHz

HSCLK = 24MHz

*1: LTBC0 and WDT is operating except IDD0/1, and all clocks peripheral circuits are stopped by block control. LSCLK1

is stopped. The code option VLMD is "1".

*2: On the condition of V_DD=3.0V, Ta=+25°C

27/55

FEDL62Q2700-01

ML62Q2700 Group

Current Consumption 2 (TBD )

Product： ML62Q2702, ML62Q2703, ML62Q2712, ML62Q2713, ML62Q2722, ML62Q2723

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Condition

Max.

Parameter

Min.

Typ.^*2

Operating mode

circuit state ^*1

Tj≤

+95^oC

Tj≤

+115^oC

0.47

(TBD)

IDD0

IDD1

STOP-D

STOP

All clocks are stopped.

―

(TBD)

μA

(TBD)

RC32K is oscillating.

XT32K/PLL are stopped.

0.77

(TBD)

IDD2-0R

HALT-D

XT32K is oscillating with

LP mode, without

noise-filter.

RC32K/PLL are stopped.

IDD2-0X

HALT-D

HALT

―

(TBD)

μA

RC32K is oscillating.

XT32K/PLL are stopped.

IDD2-1R

IDD3

―

(TBD)

μA

CPU running in

wait-mode

SYSCLK=32.768kHz

RC32K is oscillating.

XT32K/PLL are stopped.

―

1

PLL is oscillating as

PLL1M mode.

HSCLK = 1MHz

IDD4-H1

IDD4-H16

IDD5-H16

IDD5-H24

―

(TBD)

―

(TBD)

mA

CPU running in

wait-mode

SYSCLK=1MHz

PLL is oscillating as

PLL16M mode.

HSCLK = 16MHz

CPU running in

wait-mode

SYSCLK=16MHz

PLL is oscillating as

PLL16M mode.

HSCLK = 16MHz

2.4

(TBD)

CPU running in

wait-mode

SYSCLK=24MHz

PLL is oscillating as

PLL24M mode.

HSCLK = 24MHz

3.4

(TBD)

*1: LTBC0 and WDT is operating except IDD0/1, and all clocks peripheral circuits are stopped by block control. LSCLK1

is stopped. The code option VLMD is "1".

*2: On the condition of V_DD=3.0V, Ta=+25°C

28/55

FEDL62Q2700-01

ML62Q2700 Group

Low speed Crystal Oscillation

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Parameter

Crystal oscillation frequency *¹*²

Symbol

f_XTL

Condition

Min.

―

Typ.

32.768

―

Max.

―

Unit

kHz

s

―

Crystal oscillation start time

T_XTL

―

2

*1: The oscillation frequency is determined by the oscillation circuit, crystal resonator and the external capacitance (C_GL/C_DL). As

those parameters changes depending the crystal resonator, it requires evaluation on the actual PCB circuit for matching. Ask

crystal resonator makers for matching and confirm the oscillation characteristics.

*2: The quality of oscillation characteristics might be lost, depending on material of PCB, condition of wiring capacitance or

parasitic capacitance on the external circuits. Note for designing the external circuit.

- Make the wires on the external circuit as short as possible.

- Place the crystal resonator and oscillation circuit as close to the MCU as possible and make the wires between the external

capacitance and crystal resonator as short as possible.

- Ensure no signal line flowing big current runs near the oscillation circuit.

- Ensure no signal line runs under and near the oscillation circuit.

- Make ground of external capacitance the same as MCU ground V_SSpin and connect them to the ground that has low

variation of current and voltage.

- The quality of oscillation characteristics might be lost depending on operating environment due to moisture absorption of

PCB and condensation of PCB surface, recommended to have measures such as covering the oscillation circuit with

resin.

Low speed Crystal Oscillation external circuit example

XT0

XT1

V_SS

Crystal resonator

(32.768kHz)

C_GL

C_DL

External Clock Input

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Parameter

Symbol

f_EXCK

Condition

Min.

Typ.

Max.

Unit

Typ.

-1.0%

Typ.

+1.0%

Input Frequency

―

32.768

kHz

Input pulse width

t_EXCKW

―

14.5

―

μs

29/55

FEDL62Q2700-01

ML62Q2700 Group

On-chip Oscillator

Parameter

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Measuring

circuit

Symbol

f_RCL1

Condition

Min.

Typ.

Max.

Unit

Typ.

-1.5%

Typ.

+1.5%

Ta= -40 to +85°C

except HALT-D mode

RC32K frequency

32.768

kHz

Typ.

-10%

Typ.

+10%

f_RCL2

HALT-D mode

24.002560

16.007168

0.999424

Typ.

-1.5%

Typ.

+1.5%

Ta= -40 to +85°C

PLL oscillation frequency

PLL oscillation start time

f_PLL1

MHz

ms

with RC32K

―

2

1

wake-up from HALT-H

VLMD=0

no temperature variation

between before/after

HALT-H

T_PLL

―

300

μs

Typ.

-15%

Typ.

+15%

Ta= -20 to +85°C

Ta= -40 to +105°C

RC1K frequency

(for WDT)

f_RC1K

1.024

kHz

Typ.

-25%

Typ.

+25%

*: The frequency is the factory default specification. It may vary depending on the board mounting.

30/55

FEDL62Q2700-01

ML62Q2700 Group

Input / Output pin 1

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Measur

Parameter

Symbol

VOH1

Condition

Min.

Typ.

Max.

Unit

ing

circuit

IOH1=-10mA

V_DD≥4.5V

IOH1=-1mA

V_DD≥1.8V

IOL1=+10mA

V_DD≥4.5V

IOL1=+1mA

V_DD≥1.8V

V_DD

-1.5

V_DD

-0.5

―

Output voltage1

“H”/“L” level

(all input/output port)

―

1.5

0.5

VOL1

IOL2=+15mA

V_DD≥4.5V

―

0.7

0.5

0.4

―

V

2

IOL2=+8mA

V_DD≥3.0V

Output voltage2

“L” level

(all input/output port

except P01/TEST0)

When N-ch open

drain output mode

is selected

VOL2

IOL2=+3mA

V_DD≥2.0V

IOL2=+2mA

V_DD≥1.8V

IOH3M=-0.03mA

V_L3output

V_L3

-0.2

VOH3M

VOMH3P

VOMH3M

VOML3P

VOML3M

VOL3P

IOMH3P=+0.03mA

V_L2output

V_L2

+0.2

―

IOMH3M=-0.03mA

V_L2output

V_L2

-0.2

Output voltage 3

LCD COM/SEG

(COM0~COM7)

(SEG0~SEG64)

―

V_L3=3V,

V_L2=2V,

V_L1=1V

V

2

IOML3P=+0.03mA

V_L1

+0.2

―

V_L1output

IOML3M=-0.03mA

V_L1output

V_L1

-0.2

―

IOL3P=+0.03mA

V_SSoutput

―

0.2

31/55

FEDL62Q2700-01

ML62Q2700 Group

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Measuri

ng circuit

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

IIH1

IIL1

VIH1=V_DD

VIL1=V_SS

―

1

―

Input current1

(RESET_N)

-1^*1

μA

kΩ

μA

kΩ

IIL2

VIL2=V_SS(pull-up mode) *²

VIH2=V_DD(High impedance mode)

VIL2=V_SS(High impedance mode)

VIL1=V_SS(pull-up mode) *²

VIL1= V_SS(pull-up mode) *²

VIH1=V_DD(High impedance mode)

VIL1=V_SS(High impedance mode)

VIH1=V_DD

-1500^*1-300^*1

-20^*1

80

1

V/IIL2

IIH2Z

IIL2Z

IIL3

3.7

―

10

―

Input current2

(P01/TEST0)

-1^*1

-250^*1

22

―

4

-30^*1

100

―

-2^*1

800

1

Input current3

(all input port except

RESET_N, TEST1N,

P01/TEST0,

V/IIL3

IIH3Z

IIL3Z

IIH4

―

input/output port)

-1^*1

―

μA

―

1

Input current4

(PI00, PI01)

IIL4

VIL1=V_SS

-1^*1

―

0.7

×V_DD

VIH1

VIL1

―

V_DD

Input voltage1

(all input port,

input/output port)

V

5

0.3

×V_DD

―

0

―

Pin capacitance

(all input port,

input/output port)

f = 10kHz

Ta = 25^oC

CPIN

―

10

pF

―

*1: The current flowing out the LSI through the pin is described in the negative number. The applicable maximum current is the

absolute value. For example, -1mA means the maximum current 1mA flows out the LSI through the pin.

*2: Measurement conditions: Typ: V_DD= 3.0V, Max: V_DD= 1.8V, Min: V_DD= 5.5V

32/55

FEDL62Q2700-01

ML62Q2700 Group

Input / Output pin 2

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Measu

ring

circuit

Symb

ol

Parameter

Condition

Min.

Typ.

Max.

Unit

mA

μA

V_DD≥4.5V

V_DD≥1.8V

V_DD≥4.5V

V_DD≥1.8V

V_DD≥4.5V

V_DD≥1.8V

V_DD≥4.5V

V_DD≥1.8V

V_DD≥4.5V

V_DD≥3.0V

V_DD≥2.0V

V_DD≥1.8V

V_DD≥4.5V

V_DD≥3.0V

V_DD≥2.0V

V_DD≥1.8V

V_DD≥4.5V

V_DD≥1.8V

-10*³*⁵

-1*³*⁵

-90*⁵

-20*⁵

-180*⁵

-40*⁵

―

“H” level output

current1 *⁶

IOH1

IOH3

IOL1

IOL2

1pin

―

Total of group A or B ^**

(duty ≤ 50%)

―

“H” level output total

current1 *¹*⁴

―

All pin total

(duty ≤ 50%)

―

10*³

1*³

15*³

8*³

3*³

2*³

90

“L” level output

current1 *⁶

1pin

(CMOS output mode)

―

1pin

(N-ch open drain output

mode)

―

“L” level output

current2 *⁶

3

―

Total of group A or B ^**

(N-ch open drain output

mode, duty≤50%)

―

40

―

15

“L” level output total

current *²*⁴

IOL3

―

10

All pin total

―

180

20

(N-ch open drain output

mode, duty≤50%)

―

IOOH

IOOL

VOH=V_DD(High impedance mode)

VOL=V_SS(High impedance mode)

―

+1

―

Output leak

(all input/output port)

-1*⁵

**: Group A is “P02 to P07, P10 to P17 and P52 to P57”, group B is “P20 to P27, P30 to P37, P60 to P62 and P70 to P73”.

*1: Sink-out current from V_DDto the output pin, which can guarantee the device operation.

*2: Sink-in current from the output pin to V_SS, which can guarantee the device operation.

*3: Do not exceed total current.

*4: The total current is on the condition of Duty≤50% (same applies to IOH1).

When the duty ＞50% the total current is calculated by following formula.

Total current = IOL3 x 50/n (When the duty is n%)

<For an example> When IOL3=100mA and n=80%,

Total current = IOL3 x 50/80 = 62.5mA

Current allowed per 1pin is independent of the duty and specified as IOL1 and IOL2.

Do not apply current larger than Absolute Maximum Ratings.

*5: The current flowing out the LSI through the pin is described in the negative number. The applicable maximum current is the

absolute value.

For example, -1mA means the maximum current 1mA flows out the LSI through the pin.

*6: These values are satisfied with VOH1, VOL1 and VOL2.

33/55

FEDL62Q2700-01

ML62Q2700 Group

I²C Bus Interface

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Condition / Rating

Parameter

Symbol

Standard Mode

Fast Mode

Typ.

1Mbps Mode

Unit

Min.

Typ.

Max.

Min.

1.8

Max.

5.5

Min.

Typ.

Max.

Operating Voltage

V_DD

f_SCL

t_HD:STA

t_LOW

1.8

0

―

5.5

100

―

2.7

0

―

5.5

1000

―

V

kHz

μs

SCL clock frequency

―

0

400

―

SCL hold time

(start/restart condition)

4.0

4.7

4.0

4.7

0

0.6

1.3

0.6

0

0.26

0.5

0.26

0

SCL “L” level time

SCL “H” level time

―

t_HIGH

―

SCL setup time

(restart condition)

t_SU:STA

t_HD:DAT

t_SU:DAT

t_SU:STO

t_BUF

―

SDA hold time

SDA setup time

―

0.25

4.0

4.7

―

0.1

0.6

1.3

0.1

0.26

0.5

―

SDA setup time

(stop condition)

―

Bus-free time

―

When using the I²C as the master, configure the I²C master 0 mode register(I2M0MOD) and I²C bus 0 mode register

(master side, I2U0MOD) so that meet these specifications.

Re-start

Condition

Start

Condition

Stop

Condition

SDAU0

SDAM0

70%

30%

70%

30%

70%

30%

SCLU0

SCLM0

70%

30%

70%

30%

t_HD:STA

t_LOWt_HIGH

t_SU:STAt_HD:STA

t_SU:DATt_HD:DATt_SU:STOt_BUF

34/55

FEDL62Q2700-01

ML62Q2700 Group

Synchronous Serial Port

Slave mode

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Parameter

Symbol

t_SCYC

t_SW

Condition

Min.

1^*1

Typ.

Max.

Unit

μs

ns

SCLK input cycle

―

SCLK input pulse width

t_SCYCx 0.4

―

V_DD≥2.4V

V_DD≥1.8V

―

80

50

―

100

200

―

SOUT output delay time

t_SD

―

ns

SIN input setup time

SIN input hold time

t_SS

t_SH

―

ns

―

ns

*1: Need input cycles of SYSCLK x 4 or longer

Master mode

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Parameter

Symbol

t_SCYC

t_SW

Condition

Min.

Typ.

SCLK^*2

Max.

Unit

V_DD≥2.4V

250

―

ns

SCLK output cycle

SCLK output pulse width

SOUT output delay time

V_DD≥1.8V

―

500

t_SCYC×0.4

―

t_SCYC×0.6

100

160

―

ns

t_SCYC×0.5

V_DD≥2.4V

V_DD≥1.8V

V_DD≥2.4V

V_DD≥1.8V

V_DD≥2.4V

V_DD≥1.8V

―

t_SD

―

120

SIN input setup time

SIN input hold time

t_SS

180

―

80

―

t_SH

100

―

*2: Clock cycle selected by bit12 to 8(S0CK4 to 0) of the serial port 0 mode register (SIO0MOD)

t_SCYC

t_SW

70%

SCLK

SOUT

SIN

30%

t_SD

70%

30%

70%

30%

t_SS

t_SH

70%

30%

70%

30%

35/55

FEDL62Q2700-01

ML62Q2700 Group

Synchronous Serial Port with FIFO

Slave mode

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Parameter

Symbol

t_SCYC

t_SW

Condition

Min.

1^*1

Typ.

Max.

Unit

μs

ns

SCKF input cycle

―

SCKF input pulse width

t_SCYCx 0.4

―

V_DD≥2.4V

V_DD≥1.8V

―

80

50

―

100

200

―

SDOF output delay time

t_SD

―

ns

SDIF input setup time

SDIF input hold time

t_SS

t_SH

―

ns

―

ns

*1: Need input cycles of SYSCLK x 4 or longer

Master mode

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Parameter

Symbol

t_SCYC

t_SW

Condition

Min.

Typ.

SCLK^*2

Max.

Unit

V_DD≥2.4V

250

―

ns

SCKF output cycle

SCKF output pulse width

SDOF output delay time

V_DD≥1.8V

―

500

t_SCYC×0.4

―

t_SCYC×0.6

100

160

―

ns

t_SCYC×0.5

V_DD≥2.4V

V_DD≥1.8V

V_DD≥2.4V

V_DD≥1.8V

V_DD≥2.4V

V_DD≥1.8V

―

t_SD

―

120

SDIF input setup time

SDIF input hold time

t_SS

180

―

80

―

t_SH

100

―

*2: Clock cycle selected by bit9 to 0(SF0BR9 to 0) of the SIOF0 baud rate register (SF0BRR)

t_SCYC

t_SW

70%

SCKF0

SDOF0

SDIF0

30%

t_SD

70%

30%

70%

30%

t_SS

t_SH

70%

30%

70%

30%

36/55

FEDL62Q2700-01

ML62Q2700 Group

ISP interface

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Parameter

Symbol

t_TCYC

t_TW

Condition

Min.

Typ.

Max.

660

―

Unit

ns

TEST1_N clock input cycle

TEST1_N input pulse width

―

400

―

t_TCYCx 0.4

―

V_DD≥2.4V

V_DD≥1.8V

―

80

50

―

80

TEST0 output delay time

t_TD

―

200

―

TEST0 input setup time

TEST0 input hold time

t_TS

t_TH

―

t_TCYC

t_TW

70%

TEST1_N

TEST0（出力）

TEST0（入力）

30%

t_TD

70%

30%

70%

30%

t_TS

t_TH

70%

30%

70%

30%

EXl0~7 Timer Clock Input

(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified)

Parameter

Symbol

f_EXI

Condition

Min.

―

Typ.

―

Max.

3

Unit

MHz

ns

Input Frequency

Input pulse width

―

t_WEXI

135

―

37/55

FEDL62Q2700-01

ML62Q2700 Group

Reset

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Measuring

circuit

Parameter

Symbol

P_RST

Condition

Min.

10

Typ.

Max.

Unit

Reset pulse width^*1

―

μs

1

RESET_N

VIH1

VIL1

P_RST

[Note]



RESET_N input shorter pulse than the Reset pulse width (P_RST) valid time should be avoided.

The shorter pulse input may cause unexpected behavior.

Slope of Power supply and Power On Reset

(V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Measuring

circuit

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Power on rising slope

Power on falling slope

S_VR

S_VF

―

60

2

V/ms

V

―

V_PORR

V_PORF

At Power up (rising)

At Power down (falling)

1.50

1.35

1.63

1.60

1.80

1.75

1

Power on reset detection voltage

V

Power on reset minimum pulse

width

P_POR

―

500

13

―

μs

CPU operation start time

(from the release of reset to the

CPU starts to run)

t_CPUI

21

35

ms

―

At Power supply voltage level change

S_VR

At Power supply restart

S_VF

S_VR

V_DD

1.8V

V_PORR

V_PORF

0V

P_POR

t_CPUI

At power on

At Power off

[Note]



If a pulse shorter than the Power on reset minimum pulse width is asserted to V_DD, it may cause the MCU

malfunction. Apply prevent measurement such as bypass capacitors or external reset input, and so on.

Set V_DDto 1.8V or higher before starting CPU operation.



38/55

FEDL62Q2700-01

ML62Q2700 Group

VLS

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Falling

V_VLSF

Rising

V_VLSR

Condition

VLS0LV^*1

Measuring

circuit

Parameter

Symbol

Unit

Min.

Typ.

Max.

Min.

Typ.

Max.

0H

1H

2H

3H

4H

5H

6H

7H

8H

9H

AH

BH

CH

DH

EH

3.83

3.53

2.92

2.84

2.72

2.65

2.55

2.43

2.35

2.25

2.15

2.07

1.96

1.87

1.77

3.99

3.68

3.05

2.96

2.84

2.76

2.66

2.54

2.45

2.35

2.24

2.16

2.05

1.95

1.85

4.15

3.83

3.18

3.08

2.96

2.87

2.77

2.65

2.55

2.45

2.33

2.25

2.14

2.03

1.93

3.84

3.55

2.94

2.85

2.74

2.66

2.56

2.45

2.36

2.27

2.16

2.08

1.98

1.89

1.78

4.05

3.74

3.10

3.01

2.89

2.80

2.70

2.58

2.49

2.39

2.28

2.19

2.09

1.99

1.88

4.26

3.93

3.26

3.17

3.04

2.94

2.84

2.71

2.62

2.51

2.40

2.30

2.20

2.09

1.98

VLS threshold

voltage

V_VLSR

V_VLSF

V

1

^*1: Bit3~Bit0 of voltage level detection circuit 0 level register (VLS0LV).

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Measuring

circuit

Parameter

Symbol

I_VLS

Condition

Min.

Typ.

10

Max.

Unit

nA

VLS current

consumption

―

1

39/55

FEDL62Q2700-01

ML62Q2700 Group

Successive Approximation Type A/D Converter

(V_DD=2.1 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Parameter

Resolution

Symbol

n_AD

Condition

―

Min.

－

Typ.

－

Max.

12

Unit

bit

nominal value, V_DD≥ 2.7V, V_REF≥ 2.7V

nominal value, V_DD≥ 2.4V, V_REF≥ 2.4V

nominal value, V_DD≥ 1.8V, V_REF≥ 1.8V

f_ADCLK= 16MHz

32.768

1.375

－

16000

8000

1000

－

kHz

μs

Conversion clock

f_ADCLK

－

Conversion time

t_CONV

f_ADCLK= 32.768kHz

518.799

－

μs

V

A/D reference voltage

Overall error

V_REF

V_DD≥ V_REF

1.8

-6.5

-4

V_DD

+6.5

+4

－

4.5V ≤ V_REF≤ 5.5V

－

LSB

f_ADCLK= 16MHz

f_ADCLK= 8MHz

2.7V ≤ V_REF

2.4V ≤ V_REF

1.8V ≤ V_REF

2.7V ≤ V_REF

2.4V ≤ V_REF

1.8V ≤ V_REF

－

-6

－

+7

Integral non-linearity

error

INL_AD

DNL_AD

ZSE

f_ADCLK= 1MHz

-8

－

+8

f_ADCLK= 32.768kHz

f_ADCLK= 16MHz

f_ADCLK= 8MHz

-8

－

+8

-3

－

+3

-5

－

+5

Differential non-linearity

error

f_ADCLK= 1MHz

-7

－

+7

f_ADCLK= 32.768kHz

-7

－

+7

LSB

f_ADCLK= 16MHz

-6

－

+6

f_ADCLK= 8MHz

f_ADCLK= 1MHz

-8

－

+8

Zero-scale error

Full-scale error

-10

-6

－

+10

+6

f_ADCLK= 32.768kHz

f_ADCLK= 8MHz

－

f_ADCLK= 8MHz

-8

－

+8

FSE

f_ADCLK= 1MHz

-10

－

+10

f_ADCLK= 32.768kHz

－

VDD

VDDL

1.0μF

A

RI ≤ 1kΩ

0.1μF

-

1.0μF

AINx

+

Analog input

VSS

The current flows during the ADC sampling as it takes charging. Make the output impedance of the analog

signal source 1kΩ or smaller. Also, putting 0.1µF capacitor on the ADC input pin is recommended to reduce the

noise.

40/55

FEDL62Q2700-01

ML62Q2700 Group

Flash Memory

(V_SS= 0V)

Unit

Parameter

Symbol

T_OP

Condition

Data flash memory, At write/erase

Flash ROM, At write/erase

At write/erase

Range

-40 to +85

0 to +40

+1.8 to +5.5

10000

100

Operating temperature

Operating voltage

°C

V

V_DD

CEPD

CEPP

Data Flash

Maximum rewrite count

times

Program Flash

Block erasing

16K

―

Byte

Data Flash

all area

1K

Erasing unit

Program Flash

Sector erasing

―

Byte

ms

Data Flash

128

Block erasing /

Sector erasing

Erasing time (Max.)

Writing unit

50

Program Flash

Data Flash

4

Byte

1

―

Program Flash

80

40

15

Writing time (Max.)

μs

Data Flash

Data retention period

YDR

rewriting count 100 times

years

41/55

FEDL62Q2700-01

ML62Q2700 Group

LCD Driver

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105^oC, unless otherwise specified)

Condition

Range

Typ.

Measuring

circuit

Symbol

Parameter

Unit

LCN^*1

00H

02H

04H

06H

08H

0AH

0CH

0EH

10H

12H

14H

16H

18H

1AH

1CH

1EH

Min.

Max.

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

V_L1x 2

V_L1x 3

Ta=+25^oC

_{L1, L2, L3}=1.0μF

Typ.

-0.10

Typ.

+0.10

V_L1Voltage

V_L1

V

C

6

V_L2Voltage

V_L3Voltage

Bias

generation

circuit

V_L2

V_L3

V_L1x 1.8

V_L1x 2.7

―

V

Ta=+25^oC

_L1,C_L2,C_L3=1.0μF

C₁₂=1.0μF

C

t_BIAS

―

200

ms

start-up

time

^*1: Value in LCN4~LCN0 bits of bias control register (BIASCON)

42/55

FEDL62Q2700-01

ML62Q2700 Group

Measuring circuit

Measuring circuit 1

VDD

VDDL

C_L

XT0 XT1

Crystal resonator

VSS

C_V: 1.0μF

C_L: 1.0μF

C_DL: 12pF

C_GL: 12pF

(32.768kHz)

A

C_V

C_GL

C_DL

Measuring circuit 2

VIH

Measuring circuit 3

VIH

(*2)

V

(*1)

A

(*1)

VIL

VDD VDDL VSS

VDD

VSS

VDDL

Measuring circuit 4

(*2)

Measuring circuit 5

VIH

A

(*1)

VDD

VSS

VDDL

VIL

VDD

VSS

VDDL

43/55

FEDL62Q2700-01

ML62Q2700 Group

Measuring circuit 6

C1

C₁₂

C2

VL3

VDD VDDL

VL1 VL2

VSS

C_L1C_L2C_L3

(*1) Input logic circuit to determine the specified measuring conditions

(*2) Measured connecting specified pins

44/55

FEDL62Q2700-01

ML62Q2700 Group

PACKAGE DIMENSIONS

100pin TQFP Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin

number, package code and desired mounting conditions (reflow method, temperature and times).

45/55

FEDL62Q2700-01

ML62Q2700 Group

100pin QFP Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin

number, package code and desired mounting conditions (reflow method, temperature and times).

46/55

FEDL62Q2700-01

ML62Q2700 Group

80pin QFP Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin

number, package code and desired mounting conditions (reflow method, temperature and times).

47/55

FEDL62Q2700-01

ML62Q2700 Group

64pin TQFP Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin

number, package code and desired mounting conditions (reflow method, temperature and times).

48/55

FEDL62Q2700-01

ML62Q2700 Group

64pin QFP Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin

number, package code and desired mounting conditions (reflow method, temperature and times).

49/55

FEDL62Q2700-01

ML62Q2700 Group

52pin TQFP Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin

number, package code and desired mounting conditions (reflow method, temperature and times).

50/55

FEDL62Q2700-01

ML62Q2700 Group

48pin TQFP Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin

number, package code and desired mounting conditions (reflow method, temperature and times).

51/55

FEDL62Q2700-01

ML62Q2700 Group

48pin WQFN Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin

number, package code and desired mounting conditions (reflow method, temperature and times).

Note for the package with exposed die pad

The die pad is exposed on the bottom of WQFN package. Make the die pad electrically open when soldering onto the PCB.

52/55

FEDL62Q2700-01

ML62Q2700 Group

REVISION HISTORY

Page

Document

No.

Date

Feb. 17, 2023

Description

Current

Edition

FEDL62Q2700-01

-

1st Edition

53/55

FEDL62Q2700-01

ML62Q2700 Group

Notes for product usage

Notes on this page are applicable to the all LAPIS Technology microcontroller products.

For individual notes on each LAPIS Technology microcontroller product, refer to [Note]

in the chapters of each user's manual.

The individual notes of each user’s manual take priority over those contents in this page if they are different.

1. HANDLING OF UNUSED INPUT PINS

Fix the unused input pins to the power pin or GND to prevent to cause the device performing wrong operation or

increasing the current consumption due to noise, etc. If the handlings for the unused pins are described in the chapters,

follow the instruction.

2. STATE AT POWER ON

At the power on, the data in the internal registers and output of the ports are undefined until the power supply voltage

reaches to the recommended operating condition and "L" level is input to the reset pin.

On LAPIS Technology microcontroller products that have the power on reset function, the data in the internal registers

and output of the ports are undefined until the power on reset is generated.

Be careful to design the application system does not work incorrectly due to the undefined data of internal registers and

output of the ports.

3. ACCESS TO UNUSED MEMORY

If reading from unused address area or writing to unused address area of the memory, the operations are not guaranteed.

4. CHARACTERISTICS DIFFERENCE BETWEEN THE PRODUCT

Electrical characteristics, noise tolerance, noise radiation amount, and the other characteristics are different from each

microcontroller product.

When replacing from other product to LAPIS Technology microcontroller products, please evaluate enough the

apparatus/system which implemented LAPIS Technology microcontroller products.

5. USE ENVIRONMENT

When using LAPIS Technology microcontroller products in a high humidity environment and an environment where dew

condensation, take moisture-proof measures.

54/55

FEDL62Q2700-01

ML62Q2700 Group

Notes

1) The information contained herein is subject to change without notice.

2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals, application

notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating conditions, etc.) are within

the ranges specified. LAPIS Technology disclaims any and all liability for any malfunctions, failure or accident arising out of

or in connection with the use of LAPIS Technology Products outside of such usage conditions specified ranges, or without

observing precautions. Even if it is used within such usage conditions specified ranges, semiconductors can break down and

malfunction due to various factors. Therefore, in order to prevent personal injury, fire or the other damage from break down

or malfunction of LAPIS Technology Products, please take safety at your own risk measures such as complying with the

derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures.

You are responsible for evaluating the safety of the final products or systems manufactured by you.

3) Descriptions of circuits, software and other related information in this document are provided only to illustrate the standard

operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other

use of the circuits, software, and information in the design of your product or system. And the peripheral conditions must be

taken into account when designing circuits for mass production. LAPIS Technology disclaims any and all liability for any

losses and damages incurred by you or third parties arising from the use of these circuits, software, and other related

information.

4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Technology

or any third party with respect to LAPIS Technology Products or the information contained in this document (including but

not limited to, the Product data, drawings, charts, programs, algorithms, and application examples、etc.). Therefore LAPIS

Technology shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising

out of the use of such technical information.

5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer systems,

gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our Products in applications

requiring a high degree of reliability (as exemplified below), please be sure to contact a LAPIS Technology representative

and must obtain written agreement: transportation equipment (cars, ships, trains, etc.), primary communication equipment,

traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems,

etc. LAPIS Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising by

using the Product for purposes not intended by us. Do not use our Products in applications requiring extremely high reliability,

such as aerospace equipment, nuclear power control systems, and submarine repeaters, etc.

6) The Products specified in this document are not designed to be radiation tolerant.

7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this document. However,

LAPIS Technology does not warrant that such information is error-free and LAPIS Technology shall have no responsibility

for any damages arising from any inaccuracy or misprint of such information.

8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.

LAPIS Technology shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws

or regulations.

9) When providing our Products and technologies contained in this document to other countries, you must abide by the

procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export

Administration Regulations and the Foreign Exchange and Foreign Trade Act..

10) Please contact a ROHM sales office if you have any questions regarding the information contained in this document or

LAPIS Technology's Products.

11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Technology.

(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.

2-4-8 Shinyokohama, Kouhoku-ku,Yokohama 222-8575, Japan

https://www.lapis-tech.com/en/

55/55


型号：	ML62Q2747 (新产品)
厂家：	ROHM
描述：	ML62Q2700系列是内置16bit CPU nX-U16/100、并集成了程序存储器（Flash存储器）、数据存储器（RAM）、Date Flash（擦除单位128Byte，写入单位1Byte）、乘除法运算器、CRC运算器、时钟发生电路、定时器、通用端口、UART、同步串行端口、I2C总线（主/从）、电压电平检测功能（VLS）、高速逐次比较型12位A/D转换器、语音播放功能、安全功能（IEC60730/60335 Class B）、语音输出功能等丰富外围功能的高性能CMOS 16bit 微控制器。16Bit CPU nX-U16/100可通过流水线架构的并行处理实现一个时钟周期一个指令的高效指令执行。ML62Q2700系列具有片上调试功能，可在开发板上进行软件调试及软件改写。另外还具有ISP（In-System Programming）功能，可轻松实现在量产生产线上的Flash存储器写入。时钟生产线控制器微控制器存储转换器
文件：	总55页 (文件大小：2534K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ML62Q2747 (新产品) [ROHM]

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