ML630Q464 [ROHM]
ML630Q464/ML630Q466是内置32位CPU内核Cortex-M0+、并集成了128KB Flash存储器、16KB RAM、USB Full speed device、SSIO、UART、I2C、电源电压电平检测电路、RC振荡型A/D转换器、逐次比较型A/D 转换器、LCD驱动器等各种外围功能的高性能、低功耗32位微控制器。此外，还具有可通过软件进行写入的Data Flash存储区和通过软件改写程序区的功能。;
| 型号： | ML630Q464 |
| 厂家： | 
ROHM |
| 描述： | ML630Q464/ML630Q466是内置32位CPU内核Cortex-M0+、并集成了128KB Flash存储器、16KB RAM、USB Full speed device、SSIO、UART、I2C、电源电压电平检测电路、RC振荡型A/D转换器、逐次比较型A/D 转换器、LCD驱动器等各种外围功能的高性能、低功耗32位微控制器。此外，还具有可通过软件进行写入的Data Flash存储区和通过软件改写程序区的功能。 驱动 控制器 CD 微控制器 存储 驱动器 转换器 |
| 文件： | 总37页 (文件大小：2157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL630Q464-02
Issue Date: May. 13, 2021
ML630Q464/Q466
Ultra Low Power 32-bit Microcontroller
■GENERAL DESCRIPTION
This LSI is a high-performance low power 32-bit microcontroller. Equipped with a 32-bit CPU core ARM®Cortex®-M0+, it
implements a 128 KB flash memory* 16 KB RAM, rich peripheral circuits, such as USB Full speed device, synchronous serial
port, UART, I2C bus interface, supply voltage level detect circuit, RC oscillation type A/D converter, successive approximation
type A/D converter, and LCD driver. The Flash ROM* that is installed as program memory achieves low-voltage low-power
consumption operation (read operation) is most suitable for battery-driven applications.
*: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc. SuperFlash®
is a registered trademark of Silicon Storage Technology, Inc.
■FEATURES
• CPU
− 32-bit RISC CPU (CPU name: ARM®Cortex®-M0+)
− ARM®Thumb®/Thumb®-2 instruction supported
− Serial Wire Debug Port
− Minimum instruction execution time
30.5 µs (@32.768 kHz system clock)
41.7ns (@24 MHz system clock)
• Internal memory
− Re-writing the program memory area by software
− Number of segments
Flash memory
Product name
SRAM
Program area
Data area
ML630Q464
ML630Q466
64KB (16K × 32bit)
128KB (32K × 32bit)
2KB (0.5K × 32bit)
2KB (0.5K × 32bit)
8KB (2K × 32bit)
16KB (4K × 32bit)
• Interrupt controller (NVIC)
− 1 non-maskable interrupt source (Internal source: 1)
− 31 maskable interrupt sources (Internal sources: 30, External sources: 1)
− Priority level (4-level) can be set for each interrupt
• DMA controller (DMAC)
− 2 channels
− Enable to allocate multiple DMA transfer request sources for each channel.
− Channel priority: fixed mode/round robin mode
− DMA transfer mode: cycle steal mode/burst mode
− DMA request type: software requests/hardware requests
− Maximum transfer count: 65,536
− Data transfer size: 8 bits/16 bits/32 bits
− Transfer request source: SSIOF, UART, UARTF, I2CF, RC-ADC, SA-ADC
• Time base counter (TBC)
− Low-speed time base counter ×1 channel
• 1 kHz Timer
− 10 Hz / 1 Hz interrupt function
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FEDL630Q464-02
ML630Q464/Q466
• Timers (TMR)
− 8 bits × 8 channels
(Timer0-7: 16-bit x 4 configuration available by using Timer0-1 or Timer2-3, Timer4-5, Timer6-7)
− Selection of one shot timer mode is possible
− External clock can be selected as timer clock.
• Function Timers (FTM)
− 16-bit × 4 channels
− Equipped with the timer/capture/PWM functions using a 16-bit counter
− An event trigger (external pin input interrupt or timer interrupt request) can control start/stop/clear of the timer (however,
the minimum pulse width of pin input is timer clock 3φ)
− 1 to 64 dividing of LSCLK/OSCLK/HSCLK/external input selectable as timer clock
− Two types of PWM with the same period and different duties and complementary PWM with the dead time set can be
output.
• Real Time Clock (RTC)
− 1 channels (99 years calendar, alarm, revision of the clock)
• Watchdog timer (WDT)
− Non-maskable interrupt and reset
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s when LSCLK = 32.768 kHz)
• Synchronous serial port (SSIOF/SSIO)
− without FIFOs (SSIO) : 1 channel
− with 16-byte transmits and receives FIFOs (SSIOF) : 1 channel
− Master/slave selectable
− LSB first/MSB first selectable
− Clock polarity (data out at rising edge and data in at falling edge/data out at falling edge and data in at rising edge)
selectable
− 8-bit length/16-bit length selectable
− Initial clock level (High start/Low start) selectable
− supports slave-select signal (only SSIOF)
• UART (UARTF/UART)
− without FIFOs (UART) : 1channel
− with 16-byte transmits and receives FIFOs (UARTF) :1 channels
− Full duplex buffer system
− Communication speed: Settable within the range of 2400bps to 115200bps.
− Programmable interface (data length, parity, stop bits selectable)
• I2C bus interface (I2CF/I2C)
− without FIFOs(I2C) :1 channel
− with 16-byte transmits and receives FIFOs (I2CF) : 1 channels
− Master/slave function (only I2CF)
− Fast mode (400 kHz), standard mode (100 kHz)
• USB full-speed device
− Compliant with Universal Serial Bus (USB)
− Full speed (12 Mbps) 1 port.
− End points: 5 or 6
− Supports all data transfer types (control transfer, bulk transfer, interrupt transfer, isochronous transfer).
− Built-in SOF generation and CRC5/16 generation functions
− Access size to data transfer FIFOs: 8 bits/16 bits/32 bits
• General-purpose ports (PORT)
− Input/output port × 38 channels (including secondary or tertiary or quaternary or quinary functions).
(ML630Q464 and ML630Q466: including LCD com/seg ports ( each 20 ports ))
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FEDL630Q464-02
ML630Q464/Q466
• RC oscillation type A/D converter (RC-ADC)
− Time division × 2 channels
− Starting by trigger of Timer/FTM function.
− 24-bit counter
• Successive approximation type A/D converter (SA-ADC)
− Input × 12 channels
− 12-bit A/D converter
− Starting by trigger of Timer/FTM function.
− Capacitive touch sense function
• Analog Comparator (CMP)
− Input × 2ch
− Common mode input voltage:
0.2V to VDD－0.2V
− Input offset voltage: 30mV(max)
− Interrupt allow edge selection and sampling selection
• Voltage Level Supervisor (VLS)
− Threshold voltages: One of 64 levels
− Acuraccy: ±3%
− Interrupt or Reset generation are slectable
− Voltage measurement with voltage input pin or VDD pin
• Low Level Detector(LLD)
− Judgment Voltage: 1.8V±0.2V
− Can be used as low level detection reset.
• LCD driver
− Maximun 400 dots (50 segment x 8 common)
− 1/1 to 1/8 duty
− 1/2, 1/3 bias (built-in bias generation circuit)
− Frame frequency selecable
− Bias voltage multiplying clock selectable (5 types)
− Contrast adjustment (32 steps)
− 4 operating mode: LCD drive stop, LCD display, all LCDs on, all LCDs off
− Programmable display allocation function
• Random number generator (RANDOM)
− Generates 8-bit random numbers
• AES
− 128-bit Common key
− Supports key sizes of 128, 192, and 256 bits
− Supports ECB, CBC, and CTR modes
• Reset
− Reset by the RESET_N pin input
− Reset by power-on detection
− Reset by overflow of watchdog timer (WDT)
− Reset by threshold detection in Voltage Level Supervisor(VLS)
− Reset by low level detection in Low Level Detector(LLD)
− Reset by the low-speed crystal oscillation stop detection
− Reset by SYSRESETREQ of ARM®Cortex®-M0+ (software reset)
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FEDL630Q464-02
ML630Q464/Q466
• Clock
− Low-speed clock:
− Crystal oscillation (32.768 kHz)
− Built-in RC oscillation (32.768kHz)
− High-speed clock:
− PLL (24 MHz) generated from Crystal oscillation (32.768 kHz)
− Built-in RC oscillation (16MHz)
• Power management
− HALT mode: Instruction execution by CPU is suspended. All peripheral circuits can keep in operating states.
− HALT-H mode: Instruction execution by CPU is suspended. Stop of high-speed oscillation automatically. All peripheral
circuits can keep in operating states.
− DEEP-HALT mode: Instruction execution by CPU is suspended. Some peripheral circuits(Timer, LTBC etc.) can keep in
operating states.
− ULTRA-DEEP-HALT mode: Instruction execution by CPU is suspended. Some peripheral circuits(Timer, LTBC etc.) can
keep in operating states, at VDD>2.5V.
− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are
stopped.)
− Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8,1/16,1/32 of the
oscillation clock)
− Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals.
• Guaranteed operating range
− Operating temperature (ambient) : −40°C to +85°C
− Operating voltage: VDD = 1.8V to 3.6V
• Supply current (Typ)
− High-speed operation (24 MHz) : 250uA/MHz
− ULTRA-DEEP-HALT : 0.80uA
● Package
− 100-pin plastic TQFP
− Tray
ML630Q464-xxxTBZWAX
ML630Q466-xxxTBZWAX
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FEDL630Q464-02
ML630Q464/Q466
■BLOCK DIAGRAM
ML630Q464/Q466 Block Diagram
CPU (ARM®Cortex®-M0+)
SWC
SWD
DAP
NVIC
Cortex®-M0+
WIC
Data-bus
(AMBA AHB/APB)
Data-bus
(Single cycle IO)
INT
1
INT
2
SCK0
SIN0
SOUT0
SCKF0
SINF0
SSIO×1
LTBC
Program
Memory
SSIOF×1
INT
8
(Flash)
SOUTF0
Timer
SSF0
64K/128KB
INT
2
×8
RXD0
TXD0
RXDF0
TXDF0
UART×1
INT
4
TMOUT0-9
UARTF×1
Data Memory
(Flash)
Function
Timer ×4
TMOUTA-F
TMCKI0-7
INT
2
2KB
SDA1
SCL1
INT
1
I2C ×1
RTC
SDAF0
I2CF ×1
RAM
×1
SCLF0
8K/16KB
INT
1
INT
1
INT
2
DP
DM
PUCTL
1kHz Timer
USB
DMAC
×1
INT
1
INT
1
IN0
CS0
RS0
RT0
RCT0
RCM
IN1
CS1
RS1
RT1
Interrupt
WDT
Controller
INT
1
RC-ADC
INT
1
P00 to P05
P20 to P23
P30 to P37
P40 to P47
P50 to P57
AES
RND
GPIO
INT
1
P60 to P63
SA-ADC
VREF
INT
1
CMP0P
CMP0M
CMP1P
CMP1M
Analog
AIN0 to AIN11
INT
1
Comparator
×2
COM0 to COM7
SEG0 to SEG49
LCD
INT
1
Driver
VLS
VL1, VL2, VL3
C1, C2
LLD
LCD
RESET_N
XT0
XT1
32kCLKO0
RESET
OSC
BIAS
VDD
Power
VDDL
VSS
CH1, CH2
VHF
Figure 1. ML630Q464/Q466 Block Diagram
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FEDL630Q464-02
ML630Q464/Q466
■PIN CONFIGURATION
Figure 2. Pin Layout of ML630Q464/Q466
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FEDL630Q464-02
ML630Q464/Q466
■PIN LIST
Primary Function
Pin name
Secondary Function
Tertiary Function
Quaternary Function
Quinary Function
PIN
No.
.Reset
State
I/O
–
Pin name
I/O
pin name
I/O
pin name
I/O
–
pin name
I/O
–
14
68
79
65
81
–
–
VSS
VDD
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
80
70
90
–
–
–
VDDL
VHF
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
VREF
74
73
78
77
76
75
–
–
XT0
XT1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Pull-up
Input
Pull-up
Input
Pull-up
Input
Pull-down
Input
RESET_N
SWC
I
I
I/O
I
SWD
BRMP
P00/
EXI00/
AIN8
P01/
EXI01/
AIN9
Hi-Z
output
95
96
97
98
I/O
I/O
I/O
I/O
IN0
CS0
I
SOUT0
SIN0
SCK0
–
O
I
RXDF0
TXDF0
I
–
–
–
–
–
–
–
–
Hi-Z
output
O
O
O
O
O
O
P02/
Hi-Z
output
EXI02/
AIN10
P03/
EXI03/
AIN11
P04/
EXI04
P05/
EXI05
P20/
EXI20/
AIN4
P21/
EXI21/
AIN5
P22/
EXI22/
AIN6
P23/
EXI23/
AIN7
RCT0
RS0
I/O
–
TMOUT0
TMOUT1
Hi-Z
output
Hi-Z
output
Hi-Z
99
I/O
I/O
RT0
O
O
–
–
–
–
–
–
–
–
–
–
–
–
100
RCM
output
Hi-Z
output
91
92
93
94
I/O
I/O
I/O
I/O
IN1
CS1
RS1
RT1
I
SOUTF0
SINF0
O
I
–
–
–
–
–
–
–
–
–
–
–
Hi-Z
output
O
O
O
–
Hi-Z
output
SCKF0
SSF0
I/O
I/O
TMOUT2
TMOUT3
O
O
Hi-Z
output
P30/
Hi-Z
output
EXI30/
CMP0P
VLSin
P31/
EXI31/
CMP0M
P32/
EXI32/
CMP1P/
AIN2
82
83
84
I/O
I/O
I/O
SDAF0
SCLF0
RXDF0
I/O
I/O
I
SOUT0
SIN0
O
I
–
–
–
–
–
–
–
–
–
–
Hi-Z
output
Hi-Z
output
SCK0
I/O
TMOUT4
O
P33/
Hi-Z
output
EXI33/
CMP1M/
AIN3
P34/
EXI34/
AIN0
LED
P35/
EXI35/
AIN1
85
86
87
I/O
I/O
I/O
TXDF0
SDA1
SCL1
O
I/O
O
32kCLKO
SOUTF0
SINF0
O
O
I
TMOUT5
O
–
–
–
–
–
–
–
Hi-Z
output
–
–
Hi-Z
output
–
LED
P36/
Hi-Z
output
88
89
EXI36/
TMCKI4
P37/
EXI37/
TMCKI5
I/O
I/O
RXD0
TXD0
I
SCKF0
SSF0
I/O
I/O
TMOUT6
TMOUT7
O
O
–
–
–
–
Hi-Z
output
O
13 to
10
Low Level
Output
Hi-Z
output
Hi-Z
output
Hi-Z
output
COM0 to COM3
O
–
–
O
O
O
O
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
P60/
EXI60
P61/
EXI61
P62/
EXI62
P63/
EXI63
9
8
7
6
I/O
I/O
I/O
I/O
O
COM4
COM5
COM6
COM7
–
Hi-Z
output
Low Level
Output
15 to
48
SEG0 to SEG33
P40/
EXI40/
LED
Hi-Z
output
49
I/O
SDAF0
I/O
SOUT0
O
–
–
SEG34
O
7/37
FEDL630Q464-02
ML630Q464/Q466
Primary Function
Pin name
Secondary Function
Tertiary Function
Quaternary Function
Quinary Function
PIN
No.
.Reset
State
I/O
I/O
Pin name
SCLF0
I/O
pin name
SIN0
I/O
pin name
–
I/O
–
pin name
SEG35
I/O
O
P41/
EXI41/
LED
Hi-Z
output
50
51
52
I/O
I
I
P42/
Hi-Z
output
EXI42/
TMCKI0
P43/
EXI43/
TMCKI1
P44/
EXI44
P45/
EXI45
P46/
EXI46/
TMCKI2
P47/
EXI47/
TMCKI3
P50/
EXI50
P51/
EXI51
P52/
EXI52
I/O
I/O
RXDF0
TXDF0
SCK0
I/O
O
TMOUT8
TMOUT9
O
O
SEG36
SEG37
O
O
Hi-Z
output
O
32kCLKO
Hi-Z
output
Hi-Z
53
54
I/O
I/O
SDA1
SCL1
I/O
O
SOUTF0
SINF0
O
I
–
–
–
–
SEG38
SEG39
O
O
output
Hi-Z
output
55
56
I/O
I/O
RXD0
TXD0
I
SCKF0
SSF0
I/O
I/O
TMOUTA
TMOUTB
O
O
SEG40
SEG41
O
O
Hi-Z
output
O
Hi-Z
output
Hi-Z
output
Hi-Z
57
58
59
I/O
I/O
I/O
SDAF0
SCLF0
RXDF0
I/O
I/O
I
SOUT0
SIN0
O
I
–
–
–
–
SEG42
SEG43
SEG44
O
O
O
SCK0
I/O
TMOUTC
O
output
Hi-Z
output
P53/
EXI53
60
I/O
TXDF0
O
32kCLKO
O
TMOUTD
O
SEG45
O
Hi-Z
output
P54/
EXI54
61
62
63
I/O
I/O
I/O
SDA1
SCL1
RXD0
I/O
O
I
SOUTF0
SINF0
O
I
–
–
–
–
SEG46
SEG47
SEG48
O
O
O
Hi-Z
output
P55/
EXI55
P56/
EXI56/
TMCKI6
P57/
Hi-Z
output
SCKF0
I/O
TMOUTE
O
Hi-Z
output
64
EXI57/
TMCKI7
I/O
TXD0
O
SSF0
I/O
TMOUTF
O
SEG49
O
Hi-Z
output
Hi-Z
output
Low
output
66
67
69
DP
DM
I/O
I/O
O
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PUCTL
3
4
5
1
2
–
–
–
–
–
–
–
VL1
VL2
VL3
C1
C2
CH1
CH2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
71
72
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FEDL630Q464-02
ML630Q464/Q466
■PIN DESCRIPTION
In the table below indicates the functional pin description.
The pin name represents the function pin name of the primary function of each terminal, The pin mode represents the set of
mode register of Port Control.
(1st:primary function, 2nd:secondary function, 3rd: tertiary function, 4th: quaternary function, 5th:quinary function)
Pin mode
Pin name
System
RESET_N
I/O
I
Description
LSI pin name
RESET_N
Logic
L
Reset input pin. When this pin is set to a “L” level,
system reset mode is set and the internal section is
initialized. When this pin is set to a “H” level
subsequently, program execution starts. A pull-up
resistor is internally connected.
–
Remapping control input (for firmware update)
Based on the BRMP pin setting at the time of the reset
release, Bank0 is remapped.
BRMP
BRMP
I
–
H
Crystal connection pin for low-speed clock.
Capacitors CDL and CGL are connected across this pin
and VSS as required.
XT0
XT1
XT0
XT1
I
O
–
–
–
–
32kCLKO
O
2nd
Low-speed clock output pin
P33,P43,P53
General-purpose input/output port
P00-P05
P20-P23
P30-P37
P40-P47
P50-P57
P60-P63
I/O
I/O
I/O
I/O
I/O
I/O
P00-P05
P20-P23
P30-P37
P40-P47
P50-P57
P60-P63
1st
1st
1st
1st
1st
1st
–
–
–
–
–
–
General-purpose input/output port.
General-purpose input/output port.
General-purpose input/output port.
General-purpose input/output port.
General-purpose input/output port.
General-purpose input/output port.
External interrupt
1st
H/L
External maskable interrupt input pins. It is possible, for
each bit, to specify whether the interrupt is enabled and
select the interrupt edge by software.
EXI00-05
EXI20-23
EXI30-37
EXI40-47
EXI50-57
EXI60-63
I
P00-P05
P20-P23
P30-P37
P40-P47
P50-P57
P60-P63
LED
LED
UART
O
P34,P35,P40,P41
1st
–
N-channel open drain output pins to drive LED.
UART data output pin.
UART data input pin.
UARTF with FIFO data output pin.
UARTF with FIFO data input pin.
TXD0
RXD0
TXDF0
RXDF0
O
I
O
I
P37,P47,P57
P36,P46,P56
P01,P33,P43,P53
P00,P32,P42,P52
2nd
2nd
2nd
2nd
–
–
–
–
I2C bus interface
2nd
2nd
2nd
2nd
–
–
–
–
I2C1 data input/output pin. This pin has an NMOS open
drain output. When using this pin as a function of the
I2C, externally connect a pull-up resistor.
I2C1 clock output pin. This pin has an NMOS open
drain output. When using this pin as a function of the
I2C, externally connect a pull-up resistor.
I2CF0 data input/output pin. This pin has an NMOS
open drain output. When using this pin as a function of
the I2C, externally connect a pull-up resistor.
I2CF0 clock input/output pin. This pin has an NMOS
open drain output. When using this pin as a function of
the I2C, externally connect a pull-up resistor.
SDA1
I/O
P34,P44,P54
P35,P45,P55
P30,P40,P50
P31,P41,P51
SCL1
O
SDAF0
SCLF0
I/O
I/O
9/37
FEDL630Q464-02
ML630Q464/Q466
Pin mode
Pin name
I/O
Description
LSI pin name
Logic
Synchronous serial
3rd
3rd
3rd
3rd
–
–
–
–
Synchronous serial (SSIO) clock input/output pin.
Synchronous serial (SSIO) data input pin.
Synchronous serial (SSIO) data output pin.
Synchronous serial with FIFO (SSIOF) clock
input/output pin.
P02,P32,P42,P52
P01,P31,P41,P51
P00,P30,P40,P50
P22,P36,P46,P56
SCK0
SIN0
I/O
I
SOUT0
SCKF0
O
I/O
SINF0
SOUTF0
SSF0
I
O
I/O
3rd
3rd
3rd
–
–
Synchronous serial with FIFO (SSIOF) data input pin.
P21,P35,P45,P55
Synchronous serial with FIFO (SSIOF) data output pin. P20,P34,P44,P54
Synchronous serial with FIFO (SSIOF) select
input/output pin.
P23,P37,P47,P57
L
FTM
TMOUT0-9
TMOUTA-F
FTM output pin.
O
I
P02,P03,P22,P23
P32,P33,P36,P37
P42,P43,P46,P47
P52,P53,P56,P57
P42,P43,P46,P47
P36,P37,P56,P57
4th
–
–
1st
External clock input pin for FTM.
TMCKI0-7
RC oscillation type A/D converter
Oscillation input pin of Channel 0.
–
–
–
–
IN0
CS0
RS0
RT0
I
P00
P01
P03
P04
2nd
2nd
2nd
2nd
Reference capacitor connection pin of Channel 0.
Reference resistor connection pin of Channel 0.
O
O
O
Resistor sensor connection pin for measurement of
Channel 0.
Resistor/capacitor sensor connection pin of Channel 0
for measurement.
–
RCT0
O
P02
2nd
RCM
IN1
O
I
P05
P20
P21
P22
P23
2nd
2nd
2nd
2nd
2nd
RC oscillation monitor pin.
–
–
–
–
–
Oscillation input pin of Channel 1.
Reference capacitor connection pin of Channel 1.
Reference resistor connection pin of Channel 1.
CS1
RS1
RT1
O
O
O
Resistor sensor connection pin for measurement of
Channel 1.
Successive approximation type A/D converter
Reference power supply pin for successive
approximation type A/D converter.
Analog input for successive approximation type A/D
converter.
–
–
VREF
I
VREF
–
1st
(AIN0-3) P32-35,
(AIN4-7) P20-23,
(AIN8-11) P00-03
AIN0-11
I
Analog comparator
1st
1st
1st
1st
Comparator0 Non-inverted input pin.
Comparator0 Inverted input pin.
Comparator1 Non-inverted input pin.
Comparator1 Inverted input pin.
–
–
–
–
CMP0P
CMP0M
I
I
I
I
P30
P31
P32
P33
CMP1P
CMP1M
USB FS Device
USB dev D+ pin.
–
–
–
DP
DM
I/O
I/O
O
DP
DM
–
–
–
USB dev D- pin.
USB dev pull-up control
PUCTL
PUCTL
DEBUG Interface
Serial clock of Serial Wire Debug Port
Serial I/O data of Serial Wire Debug Port
–
–
SWC
SWD
I
SWC
SWD
–
–
I/O
10/37
FEDL630Q464-02
ML630Q464/Q466
Pin
mode
Pin name
I/O
Description
LSI pin name
Logic
Power supply
Negative power supply pin.
Positive power supply pin.
Positive power supply pin (internally generated) for
internal logic. Capacitors CL is connected between this
VSS
VDD
VDDL
–
–
–
VSS
VDD
VDDL
–
–
–
–
–
–
pin and VSS
.
Positive power supply pin (internally generated) for
built-in halver circuit. Capacitor CVH is connected
VHF
–
VHF
–
–
between this pin and VSS
.
Capacitor pins of built-in halver circuit
CH1 – CH2
LCD driver
COM0 –
COM3
–
–
–
–
–
CH1 – CH2
COM0 – COM3
P60-P63
–
–
–
–
–
–
–
Common pins of LCD driver
COM4 –
COM7
SEG0 –
SEG33
SEG34 –
SEG49
C1 – C2
2nd
Common pins of LCD driver
Segment pins of LCD driver
SEG0 – SEG33
–
P40-P47
P50-P57
C1 – C2
5th
Segment pins of LCD driver
Capacitor pins of built-in generation bias circuit
–
–
–
–
–
–
Reference voltage input pins of built-in bias generation
circuit
VL1 – VL3
VL1 – VL3
11/37
FEDL630Q464-02
ML630Q464/Q466
■TERMINATION OF UNUSED PINS
Table 1 shows methods of terminating the unused pins.
Table 1 Termination of Unused Pins
Pin
RESET_N
BRMP
Recommended pin termination
Connect to VDD
Connect to VSS
Connect a pull-up resistor.
SWC
Connect a pull-up resistor.
SWD
Connect to VDD
open
VREF
P00 to P05
P20 to P23
P30 to P37
P40 to P47
P50 to P57
P60 to P63
COM0 to COM3
SEG0 to SEG33
DP, DM, PUCTL
VL1, VL2, VL3
C1, C2
open
open
open
open
open
open
open
open
open
open
[Note]
For unused input ports or unused input/output ports, if the corresponding pins are configured as high-impedance
inputs and left open, the supply current may become excessively large. Therefore, it is recommended to configure
those pins as either inputs with a pull-down resistor/pull-up resistor or outputs.
12/37
FEDL630Q464-02
ML630Q464/Q466
■Electrical Characteristics
●ABSOLUTE MAXIMUM RATINGS
（VSS=0V）
Parameter
Symbol
Condition
Ta=25°C
Ta=25°C
Ta=25°C
Rating
Unit
V
Power supply voltage 1
Power supply voltage 2
Power supply voltage 3
VDD
VDDL
VL1-3
-0.3 to +4.6
-0.3 to +2.0
-0.3 to +6.0
V
V
Input voltage(P00-P05,
P20-P23,
P30-P35,
VIN
-0.3 to VDD+0.3
V
Ta=25°C
SWC, SWD, BRMP,
RESET_N, DP, DM)
Input voltage (5 V tolerant)
(P36, P37, P40-P47,
P50-P57, P60-P63)
VINT
-0.3 to +6.0
-0.3 to VDD+0.3
-0.3 to VL1-3+0.3
V
V
V
Ta=25°C
Ta=25°C
Ta=25°C
Output voltage 1
VOUT1
VOUT2
Output voltage 2
(COM0 to COM7
SEG0 to SEG49)
Output current 1
Output current 2
IOUT1
IOUT2
PD
-12 to +11
-12 to +20
0.9
mA
mA
W
Ta=25°C
Ta=25°C
Ta=25°C
–
Power dissipation
Storage temperature
TSTG
-55 to +150
°C
13/37
FEDL630Q464-02
ML630Q464/Q466
●RECOMMENDED OPERATING CONDITIONS
（VSS=0V）
Parameter
Symbol
TOP
Condition
–
Range
Unit
Operating temperature
(Ambience)
-40 to +85
°C
V
Operating voltage
Reference voltage
VDD
VREF
fOP
–
–
–
1.8 to 3.6
1.8 to VDD
V
LSCLK:32.768k
HSCLK:500k to 24M
Operating frequency
(CPU)
Low speed crystal
Hz
Hz
fXTL
–
32.768k
oscillation frequency
Low speed crystal
oscillation external
capacitor 1
Low speed crystal
oscillation external
capacitor 2
Low speed crystal *1
oscillation external
capacitor 3
CDL
CGL
CDL
6.8 to 12
6.8 to 12
12 to 16
Using VT-200-FL(from SII）
pF
pF
pF
Using DT-26(from Daishinku)
CGL
CDL
12 to 16
12 to 22
Using VT-200-F(from SII）
CGL
CL
12 to 22
VDDL external capacitor *2
ESR ≦500mΩ
2.2 ± 30%
µF
µF
VL1,2,3pin
external capacitor
C1-C2
external capacitor
CH1, CH2
external capacitor
VHF
external capacitor
Ca,b,c
C12
–
1.0 ± 30%
1.0 ± 30%
1.0 ± 30%
1.0 ± 30%
–
–
–
µF
µF
µF
CH12
CHF
*1 : Please use this crystal except DEEPHALT mode because this LSI may not be functioning at DEEPHALT mode with the crystal.
Please evaluate the matching when other crystal oscillator/ceramic oscillator is used.
*2：Please evaluate on user’s conditions, put on CL0( = 0.1uF) if necessary.
See the application note; “Precautions for MCU board design” for details, when designing MCU board.
14/37
FEDL630Q464-02
ML630Q464/Q466
●Operating Conditions of Flash Memory
（VSS= 0V）
Parameter
Symbol
Condition
Range
Unit
Data area : write/erase
-40 to +85
°C
°C
Operating temperature
(Ambience)
TOP
Program area : write/erase
Write/erase
0 to +40
1.8 to 3.6
10,000
100
VDD
CEPD
CEPP
V
Operating voltage
Write time
Data area (1,024B x 2)
times
times
Program area
Program area
8
2
1
Block erase
KB
Data area
Sector erase
–
Erase unit
KB
ms
–
Block erase/Sector erase
–
100
Erase time(Maximum)
Write unit
–
–
1 word (4 byte)
15/37
FEDL630Q464-02
ML630Q464/Q466
●AC characteristics (Oscillation)
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Typ.
Measuring
circuit
Parameter
Symbol
Condition
Unit
Max.
2
Min.
–
Low speed crystal
oscillation start time
TXTL
–
–
s
Typ
-1.5%
Typ
+1.5%
Ta=25°C
Ta=-40 to 85°C
Ta=25°C
32.768
32.768
16
Low speed built-in RC
fLCR
kHz
oscillation frequency*1*2*3
typ-5%
typ+5%
typ
-1%
typ
+1%
1
High speed build-in RC
oscillation frequency*1*2
fHCR
MHz
typ
-5%
typ
+5%
Ta=-40 to 85°C
fXTL=32.768kHz
–
16
typ
-0.25%
typ
+0.25%
PLL frequency
fPLL
24
MHz
Low speed crystal
oscillation stop
detection time
–
–
µs
TSTOP
600
*1 : Mean value of 1024 cycle.
*2 : Guarantee value at the time of the shipment.
*3 : Except DeepHALT mode and Ultra-DeepHALT mode.
16/37
FEDL630Q464-02
ML630Q464/Q466
●DC Characteristics (IDD)
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating*1
Measuring
circuit
Symbol
Parameter
Condition
Unit
Min.
–
Typ. Max.
Ta=25°C
0.70
–
2.5
28
CPU is Stopped
Low/High-speed oscillation is stopped
Power
consumption 1
IDD1
µA
–
–
Ta=-40 to 85°C
ULTRA-DEEP-HALT mode *3*4
(LBTC function)
Ta=25°C
0.80
–
2.5
20
Low-speed crystal oscillating
(32.768kHz)
High-speed oscillation is stopped.
IDD2-1
µA
Ta=-40 to 85°C
–
Power
consumption 2
2.5V≦VDD
DEEP-HALT mode *3*4
(LBTC function)
Ta=25°C
–
–
1.30.
–
3.0
28
Low-speed crystal oscillating
(32.768kHz)
IDD2-2
IDD3
µA
µA
Ta=-40 to 85°C
High-speed oscillation is stopped.
HALT mode *3*4
1
Ta=25°C
–
–
2.2
–
5.0
32
(LTBC function)
Low-speed crystal oscillating
(32.768kHz)
Power
consumption 3
Ta=-40 to 85°C
High speed oscillation is stopped.
CPU Low-speed *2*4
Low-speed crystal oscillating
High speed oscillation is stopped.
Ta=25°C
Ta=-40 to 85°C
Ta=25°C
–
–
–
–
–
–
9.0
–
14
45
Power
consumption 4
IDD4
IDD5
IDD6
µA
mA
mA
3.8
–
5.0
5.5
7.0
7.5
CPU High-speed(16MHz) *2*4
Power
consumption 5
High-speed Built-in RC oscillating
Ta=-40 to 85°C
Ta=25°C
6.0
–
CPU High-speed(24MHz) *2*4
High-speed PLL oscillating
Power
consumption 6
Ta=-40 to 85°C
*1：typ.rating is VDD=3.0V
*2：at CPU activity rate =100%（No HALT state）
*3 : using 32.768KHz crystal oscillator VT-200-FL (from SII)(CGL/CDL＝12pF)
using 32.768KHz crystal oscillator DT-26(from Daishinku)(CGL/CDL＝12pF）
*4 : CLKCON valid bits are “0”, RSTCON valid bits are “1”
17/37
FEDL630Q464-02
ML630Q464/Q466
●DC Characteristics (VLS)
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Measuring
circuit
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
VLSLV[5:0] = 00H*1
VLSLV[5:0] = 01H*1
VLSLV[5:0] = 02H*1
VLSLV[5:0] = 03H*1
VLSLV[5:0] = 04H*1
VLSLV[5:0] = 05H*1
VLSLV[5:0] = 06H*1
VLSLV[5:0] = 07H*1
VLSLV[5:0] = 08H*1
VLSLV[5:0] = 09H*1
VLSLV[5:0] = 0AH*1
VLSLV[5:0] = 0BH*1
VLSLV[5:0] = 0CH*1
VLSLV[5:0] = 0DH*1
VLSLV[5:0] = 0EH*1
VLSLV[5:0] = 0FH*1
VLSLV[5:0] = 10H*1
VLSLV[5:0] = 11H*1
VLSLV[5:0] = 12H*1
VLSLV[5:0] = 13H*1
VLSLV[5:0] = 14H*1
VLSLV[5:0] = 15H*1
VLSLV[5:0] = 16H*1
VLSLV[5:0] = 17H*1
VLSLV[5:0] = 18H
VLSLV[5:0] = 19H
VLSLV[5:0] = 1AH
VLSLV[5:0] = 1BH
VLSLV[5:0] = 1CH
VLSLV[5:0] = 1DH
VLSLV[5:0] = 1EH
VLSLV[5:0] = 1FH
VLSLV[5:0] = 20H
VLSLV[5:0] = 21H
VLSLV[5:0] = 22H
VLSLV[5:0] = 23H
VLSLV[5:0] = 24H
VLSLV[5:0] = 25H
VLSLV[5:0] = 26H
VLSLV[5:0] = 27H
VLSLV[5:0] = 28H
VLSLV[5:0] = 29H
VLSLV[5:0] = 2AH
VLSLV[5:0] = 2BH
VLSLV[5:0] = 2CH
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
1.875
1.900
1.925
1.950
1.975
2.000
2.050
2.100
2.150
2.200
2.250
2.300
2.350
2.400
2.450
2.500
2.550
2.600
VLS judge
voltage
(VDD=fall)
Typ.
-3%
Typ.
+3%
1
V
VVLS
18/37
FEDL630Q464-02
ML630Q464/Q466
2.650
2.700
2.750
2.800
2.850
2.900
2.950
3.000
3.050
3.100
3.150
3.200
3.250
3.300
3.350
3.400
3.450
3.500
3.550
VVLS
VLSLV[5:0] = 2DH
VLSLV[5:0] = 2EH
VLSLV[5:0] = 2FH
VLSLV[5:0] =30H
VLSLV[5:0] = 31H
VLSLV[5:0] = 32H
VLSLV[5:0] = 33H
VLSLV[5:0] = 34H
VLSLV[5:0] = 35H
VLSLV[5:0] = 36H
VLSLV[5:0] = 37H
VLSLV[5:0] = 38H
VLSLV[5:0] = 39H
VLSLV[5:0] = 3AH
VLSLV[5:0] = 3BH
VLSLV[5:0] = 3CH
VLSLV[5:0] = 3DH
VLSLV[5:0] = 3EH
VLSLV[5:0] = 3FH
Typ.
-3%
Typ.
+3%
V
1
VVLS Hysteresis
width
VVLS
X
VVLS
X
–
V
HVLS
X
(VDD=rise)
1.0%
2.7%
4.5%
VLSLV[3:0] are bits of the VLSCON register to change detection voltage level.
*1: Setable only at the time of select to VVLSP pin.
●DC characteristics (LLD)
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Typ.
Measuring
circuit
Parameter
Symbol
VLLR
Condition
–
Unit
V
Max.
2.00
Min.
1.60
LLD judge Voltage
1
1.80
●DC/AC characteristics (Analog comparator)
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Typ.
Measuring
circuit
Parameter
Symbol
Condition
Unit
Min.
0.2
Max.
VDD
-0.2
Common Input
voltage range
VCMPIN
VCMPOF
TCMP
–
–
–
–
V
1
Input offset voltage
–
-30
–
30
2
mV
µs
Comparator judge
time
CMPP- CMPM =40mV
19/37
FEDL630Q464-02
ML630Q464/Q466
●DC characteristics (LCD Driver)
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Typ.
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
1.10
1.12
1.14
1.16
1.18
1.20
1.22
1.24
1.26
1.28
1.30
1.32
1.34
1.36
1.38
1.40
1.42
1.44
1.46
1.48
1.50
1.52
1.54
1.56
Measuring
circuit
Parameter
Symbol
Condition
Unit
Min.
0.89
0.91
0.93
0.95
0.97
0.99
1.01
1.03
1.05
1.07
1.09
1.11
1.13
1.15
1.17
1.19
1.21
1.23
1.25
1.27
1.29
1.31
1.33
1.35
1.37
1.39
1.41
1.43
1.45
1.47
1.49
1.51
Max.
0.99
1.01
1.03
1.05
1.07
1.09
1.11
1.13
1.15
1.17
1.19
1.21
1.23
1.25
1.27
1.29
1.31
1.33
1.35
1.37
1.39
1.41
1.43
1.45
1.47
1.49
1.51
1.53
1.55
1.57
1.59
1.61
LCN[4:0] = 00H*2
LCN[4:0] = 01H*2
LCN[4:0] = 02H*2
LCN[4:0] = 03H*2
LCN[4:0] = 04H*2
LCN[4:0] = 05H*2
LCN[4:0] = 06H*2
LCN[4:0] = 07H*2
LCN[4:0] = 08H*2
LCN[4:0] = 09H*2
LCN[4:0] = 0AH*2
LCN[4:0] = 0BH*2
LCN[4:0] = 0CH*2
LCN[4:0] = 0DH*2
LCN[4:0] = 0EH*2
LCN[4:0] = 0FH*2
LCN[4:0] = 10H
LCN[4:0] = 11H
LCN[4:0] = 12H
LCN[4:0] = 13H
LCN[4:0] = 14H
LCN[4:0] = 15H
LCN[4:0] = 16H
LCN[4:0] = 17H
LCN[4:0] = 18H
LCN[4:0] = 19H
LCN[4:0] = 1AH
LCN[4:0] = 1BH
LCN[4:0] = 1CH
LCN[4:0] = 1DH
LCN[4:0] = 1EH
LCN[4:0] = 1FH
V
DD = 3.0V,
VL1 voltage
VL1
V
Tj = 25°C
1
VL1 temperature
deviation*1
VL1 voltage
dependency*1
%/°C
mV/V
∆VL1
∆VL1
VL2
VDD = 3.0V
–
–
−0.06
5
–
VDD = 1.8 to 3.6V
20
Typ.
−10%
Typ.
Typ.
+4%
Typ.
+4%
VL2 voltage
VL3 voltage
VL1×2
VDD = 3.0V, Tj = 25°C
1MΩ load (VL3−VSS
V
)
VL3
VL1×3
−10%
LCD bias voltage
generation time
TBIAS
–
–
–
600
ms
*1:VL1 can not exceed VDD level. The maximum VL1 becomes VDD level when the VL1 calculated by the temperature deviation
and voltage dependency is going to exceed the VDD level.
*2: 1/3 bias only.
20/37
FEDL630Q464-02
ML630Q464/Q466
●DC characteristics (VOHL, IOHL)
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Measuring
circuit
Parameter
Symbol
VOH1
Condition
Unit
Min.
Typ.
Max.
–
VDD
-0.5
Output voltage 1
( P00-P05, P20-P23,
P30-P37, P40-P47,
P50-P57,, P60-P63,
SWD,PUCTL)
IOH=-1.0mA
–
VOL1
VOL2
IOL=+0.5mA
–
–
–
–
–
–
0.4
0.6
0.4
Output voltage 2
( P34, P35,
P40, P41 )
2.7V ≤VDD ≤3.6V IOL=+5.0mA
(LED mode
is selected)
IOL=+2.0mA
Output voltage 3
(P30, P31, P34, P35,
P40, P41, P44, P45,
P50, P51, P54, P55 )
(I2C mode is
IOL3= +3mA (I2Cspec)
VOL3
VOL4
–
–
–
–
0.4
(VDD ≥2V)
selected)
Output voltage 4
( P30, P31, P34, P35,
P40, P41, P44, P45,
P50, P51, P54, P55 )
(I2C mode is
IOL4= +2mA(I2Cspec)
(VDD < 2V)
VDD
×0.2
selected)
VL3
-0.2
1/3bias, IOH5=-0.02mA,
VL1=1.2V
VOH5
VOM5
–
–
–
2
V
1/3bias, IOM5=+0.02mA,
VL1=1.2V
VL2
+0.2
–
Output voltage 5
(COM0～7)
(SEG00～49)
(LCD mode is
selected)
VL2
-0.2
1/3bias, IOM5S=-0.02mA,
VL1=1.2V
VOM5S
VOML5
VOML5S
VOL5
–
–
1/3bias, IOML5=+0.02mA,
VL1=1.2V
VL1
+0.2
–
–
VL1
-0.2
1/3bias, IOML5S=-0.02mA,
VL1=1.2V
–
–
0.2
―
1/3bias, IOL5=+0.02mA,
VL1=1.2V
–
–
VL3
-0.3
1/2bias, IOH5=-0.01mA,
VL1=1.4V
VOH5
―
―
―
―
―
―
VL2
+0.3
1/2bias, IOM5=+0.01mA,
VL1=1.4V
VOM5
―
Output voltage 5
(COM0～7)
(SEG00～49)
(LCD mode is
selected)
VL2
-0.3
1/2bias, IOM5S=-0.01mA,
VL1=1.4V
VOM5S
VOML5
VOML5S
VOL5
―
VL1
+0.3
1/2bias, IOML5=+0.01mA,
VL1=1.4V
―
VL1
-0.3
1/2bias, IOML5S=-0.01mA,
VL1=1.4V
―
1/2bias, IOL5=+0.01mA,
VL1=1.4V
―
0.3
21/37
FEDL630Q464-02
ML630Q464/Q466
Output leak 1
( P00-P05,
P20-P23,
P30-P37,
P40-P47,
VOH=VDD (at high impedance)
VOL=VSS (at high impedance)
–
–
–
+1
–
IOOH1
IOOL1
µA
3
P50-P57,
P60-P63,
-1
SWD,PUCTL )
22/37
FEDL630Q464-02
ML630Q464/Q466
●DC characteristics (IIHL)
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Measuring
circuit
Parameter
Symbol
Condition
Unit
Min.
–
Typ.
Max.
1
IIH1
IIL1
IIH3
IIL3
VIH1=VDD
VIL1=VSS
–
Input current 1
(RESET_N)
-900
1
-300
15
-20
200
-1
Input current 3
(P00-P05,
VIH3=VDD (at pull down)
VIL3=VSS (at pull up)
P20-P23,
-200
-15
P30-P37,
P40-P47,
P50-P57,
P60-P63,
VIH3=VDD
(at high impedance)
IIH3Z
IIL3Z
–
–
–
1
–
4
µA
VIL3=VSS
(at high impedance)
-1
SWC, SWD, BRMP)
Input current 4
(P36, P37,
P40-P47,
VIH4=5.0V
(at high impedance)
IIH4Z
–
–
1
P50-P57,
P60-P63)
*1：typ.rating is VDD=3.0V, Ta=25°C
●DC characteristics (VIHL)
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Measuring
circuit
Parameter
Symbol
VIH1
Condition
Unit
Min.
Typ.
Max.
VDD
0.7
×VDD
Input voltage 1
(RESET_N,
–
–
SWD, SWC,
BRMP,
P00-P05,
P20-P23,
P30-P37,
P40-P47,
P50-P57,
P60-P63 )
5
V
0.3
×VDD
VIL1
–
0
–
Input terminal
capacitance
(RESET_N,
SWD, SWC,
f=10kHz
Vrms=50mV
Ta=25°C
BRMP,
P00-P05,
P20-P23,
P30-P37,
P40-P47,
P50-P57,
P60-P63 )
–
CIN
–
–
10
pF
23/37
FEDL630Q464-02
ML630Q464/Q466
●DC characteristics (USB)
(VDD=3.0 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating*1
Measu
ring
circuit
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
Absolute value of the difference
between the DP and DM pins
Differential input sensitivity
VDI
VCM
VSE
0.2
0.8
0.8
-
-
-
-
V
V
V
Differential common mode range
Includes VDI range
2.5
2.0
Single end input threshold
voltage
-
15k W RL is connected
to GND
High level output voltage
Low level output voltage
VOH
VOL
ILO
2.8
-
-
-
-
V
V
1.5k W RL to 3.6 V
0 V < VIN < 3.3 V
Steady state
0.3
10
44
Hi-Z state input/output leakage
current
-10
28
uA
Ω
Driver output resistance
ZDRV
24/37
FEDL630Q464-02
ML630Q464/Q466
●MEASURING CIRCUITS
MEASURING CIRCUIT 1
CGL
XT0
XT1
32.768kHz
crystal
C2
C1
CDL
C12
VDD
VDDL
VL2 VL3
VSS
VL1
A
CV
CL
Cb Cc
Ca
CV
CL
Ca,Cb,Cc
C12
: 1µF
: 2.2µF
: 1µF
: 1µF
CGL
: 12pF
CDL
:12pF
32.768kHz crystal oscilation:
(DT-26 from Daishinku)
MEASURING CIRCUIT 2
(*2)
VIH
V
(*1)
VIL
VDD VDDL VL1 VL2 VL3
VSS
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
25/37
FEDL630Q464-02
ML630Q464/Q466
MEASURING CIRCUIT 3
(*2)
VIH
A
(*1)
VIL
VDD VDDL VL1 VL2 VL3
VSS
*1: Input logic circuit to determine the specified measuring conditions.
*2: Measured at the specified output pins.
MEASURING CIRCUIT 4
(*3)
A
VDD VDDL VL1 VL2 VL3
VSS
*3: Measured at the specified output pins.
MEASURING CIRCUIT 5
VIH
(*1)
VIL
VDD VDDL VL1 VL2 VL3
VSS
*1: Input logic circuit to determine the specified measuring conditions.
26/37
FEDL630Q464-02
ML630Q464/Q466
●AC characteristics (USB)
(VDD=3.0 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Typ.
Applied
pin
Parameter
Symbol
Condition
Unit
Min.
Max.
Rise time (*1)
Fall time (*1)
TR
TF
CL = 50 pF
CL = 50 pF
4
4
–
–
20
20
ns
ns
Output
voltage
signal
crossover
VCRS
CL = 50 pF
0.8
–
–
2.5
V
DP, DM
Average bit rate
(12Mbps ±0.25%)
Data rate
TDRATE
11.97
12.03
Mbps
* 1: TR and TF: Rise time and fall time between 10% and 90% of the pulse amplitude, respectively
27/37
FEDL630Q464-02
ML630Q464/Q466
●AC charctoristics (synchronous serial port)
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Typ.
Parameter
Symbol
Conditon
Unit
µs
Min.
10
Max.
–
High-speed oscillation
is not active
–
–
SCK input cycle
(slave mode)
tSCYC
tSCYC
tSW
High-speed oscillation is active
–
500*2
–
ns
SCK output cycle
(master mode)
–
4
SCK*1
–
–
–
s
High-speed oscillation
is not active
µs
SCK input pulse width
(slave mode)
High-speed oscillation is active
200
–
–
ns
SCK output pulse width
(master mode)
tSCYC
×0.4
tSCYC
×0.5
tSCYC
×0.6
tSW
tSD
tSD
–
–
–
s
SOUT output delay time
(slave mode)
–
–
–
–
180
80
ns
ns
SOUT output delay time
(master mode)
SIN input
Setup time
tSS
–
50
–
–
ns
(slave mode)
SIN input
Setup time
tSS
–
–
130
50
–
–
–
–
ns
(master mode)
SINinput
Hold time
tSH
Ns
*1 : The clock period which is selected by the below registers(min:250ns@ regularly, min:500ns@P02,P22 is used)
In case of SSIO : S0CK2-0 of serial port 0 mode register(SIO0MOD).
In case of SSIOF : SF0BR9-0 of SIOF0 port register(SF0BRR)
*2 : In case of SSIOF :Set the period of SYSCLK in half or less of the tSCYC in a period.
tSCYC
tSW
tSW
SCK0/SCKF0
("0" during transmission/reception)
SCK0/SCKF0
("1" during transmission/reception)
tSD
tSD
SOUT0/SOUTF0
SIN0/SINF0
tSS
tSH
28/37
FEDL630Q464-02
ML630Q464/Q466
●AC characteristics（I2C Bus interface : Standard mode 100kHz）
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Typ.
–
Parameter
Symbol
Condition
Unit
Min.
0
Max.
100
SCL clock frequency
fSCL
–
–
kHz
SCL hold time
(Start/restart condition)
tHD:STA
4.0
–
–
µs
SCL”L” level time
SCL”H” level time
tLOW
tHIGH
–
–
4.7
4.0
–
–
–
–
µs
µs
SCL setup time
(restart condition)
tSU:STA
tSU:DAT
tSU:STO
tBUF
–
–
–
–
4.7
0.25
4.0
–
–
–
–
–
–
–
–
µs
µs
µs
µs
SDA setup time
SDA setup time
(stop condition)
Bus-free time
4.7
●AC characteristics（I2C bus interface : fast mode 400kHz）
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rateing
Parameter
Symbol
Condition
Unit
Min.
0
Typ.
–
Max.
400
SCL clock frequency
fSCL
–
–
kHz
SCLhold time
(start/restart condition)
tHD:STA
0.6
–
–
µs
SCL”L” level time
SCL”H” level time
tLOW
tHIGH
–
–
1.3
0.6
–
–
–
–
µs
µs
SCL setup time
(restart condition)
tSU:STA
tSU:DAT
tSU:STO
tBUF
–
–
–
–
0.6
0.1
0.6
1.3
–
–
–
–
–
–
–
–
µs
µs
µs
µs
SDA setup time
SDA setup time
(stop condition)
Bus-free time
*1: Only at the time of SYSCLK=16MHz or 24MHz
Start
condition
Restart
condition
Stop
condition
SDA
SCL
tBUF
tSU:STO
tHD:STA
tLOW
tHIGH
tSU:STA tHD:STA
tSU:DAT
tHD:DAT
29/37
FEDL630Q464-02
ML630Q464/Q466
●AC characteristics (RC-ADC)
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40~+85°C, unless otherwise specified)
Rating
Typ.
Parameter
Symbol
Condition
unit
kΩ
kHz
kHz
kHz
–
Min.
1
Max.
400
RS0,RS1,RT0,
RT0-1,RT1
Resister for oscillation
–
–
528
59
Resister for oscillation
fOSC1_0
fOSC2_0
fOSC3_0
Kf1_0
Kf2_0
Kf3_0
–
–
–
–
=1kΩ
Oscillation freqency
VDD = 3.0V
Resister for oscillation
CVR=820pF
CS=560pF
=10kΩ
Resister for oscillation
–
5.9
8.94
1
–
=100kΩ
RT0, RT0-1, RT1=1kΩ
RT0, RT0-1, RT1=10kΩ
RT0, RT0-1, RT1=100kΩ
8.225
0.99
0.093
9.655
1.01
0.109
RS to RT oscillation
frequency ratio *1
VDD = 3.0V
–
CVR=820pF
CS=560pF
0.101
–
*1：Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same
conditions.
fOSCX
fOSCX
fOSCX
(RT0-CS0 oscillation)
(RT0-1-CS0 oscillation)
(RT1-CS1 oscillation)
Kfx =
fOSCX
fOSCX
fOSCX
,
,
(RS0-CS0 oscillation)
( x = 1, 2, 3 )
(RS0-CS0 oscillation)
(RS1-CS1 oscillation)
Measuring circuit
CVR0
CVR1
RT0, RT0-1, RT1: 1kΩ/10kΩ/100kΩ
RS0, RS1: 10kΩ
CS0, CT0, CS1: 560pF
CVR0, CVR1: 820pF
IN0 CS0 RCT0 RS0 RT0
IN1 CS1 RS1 RT1
RCM
VIH
Measure frequency
(fOSCX
)
(*1)
VIL
VDD
VDDL
VSS
CV
CL1 CL0
(*1) Input logic circuit to determine the specified measuring conditions.
【Note】
・Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and
IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1 and RS0/RS1. The coupling capacitance on the
wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise around the node.
・When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please shield the signal by VSS(GND).
・Please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. Wiring to reserved components
may affect to the A/D conversion operation by noise the components itself may have.
30/37
FEDL630Q464-02
ML630Q464/Q466
●AC characteristics (Low speed clock output)
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40~+85°C, unless otherwise specified)
Rating
Typ.
Parameter
Symbol
tclk
Condition
–
Unit
kHz
Min.
–
Max.
–
Clock output frequency
32.768
31/37
FEDL630Q464-02
ML630Q464/Q466
●Electrical Characteristics of SA-ADC
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40~+85°C, unless otherwise specified)
Rating
Typ.
Parameter
Resolution
Symbol
Condition
Unit
bit
Min.
Max.
n
–
–
12
–
–
2.7V ≤ VREF ≤ 3.6V
2.2V ≤ VREF < 2.7V
1.8V ≤ VREF < 2.2V
(using Low-speed clock)
2.7V ≤ VREF ≤ 3.6V
2.2V ≤ VREF < 2.7V
1.8V ≤ VREF < 2.2V
(using Low-speed clock)
−4
−6
+4
+6
–
Integral non-linearity error
INL
−10
–
+10
−3
−5
–
–
+3
+5
Differential non-linearity
error
DNL
−9
−6
–
–
–
–
–
+9
+6
LSB
2.2V ≤ VREF ≤ 3.6V
Zero-scale error
Full-scale error
VOFF
FSE
1.8V ≤ VREF < 2.2V
(using Low-speed clock)
−10
−6
+10
+6
2.2V ≤ VREF ≤ 3.6V
1.8V ≤ VREF < 2.2V
(using Low-speed clock)
−10
+10
Input impidance
RI
–
–
–
–
5k
Ω
Reference voltage
VREF
–
1.8
VDD
V
Using High-speed clock(max. 4MHz)
Using Low-speed clock
–
–
170
16
–
–
Conversion time
tCONV
clk
Measuring circuit
VDD
Reference
Voltage
VREF
1μF
A
RI ≤ 5kΩ
-
10μF
AIN
+
VSS
0.47μF
32/37
FEDL630Q464-02
ML630Q464/Q466
●Reset characteristics
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Measuring
circuit
Parameter
Symbol
PRST
Condition
Unit
Max.
–
Min.
200
Typ.
–
–
–
μs
Reset pulse width
Reset noise elimination
pulse width
–
–
–
–
0.3
10
PNRST
μs
1
Power-on reset activation
power rise time
–
TPOR
ms
0.9*VDD
VDD
0.3*VDD
PRST
0.3*VDD
0.3*VDD
PRST
RESET_N
External reset sequence
0.9*VDD
VDD
0.1*VDD
TPOR
Power on reset sequence
●Power-on and shutdown Procedures
In case of power-on or shutdown of VDD, the procedures and constraints are shown as following.
0.9*VDD
VDD
0.1*VDD
(VSS = 0)
30mV or less
TPOR
VDDL
(VSS = 0)
100mV or less
Power down/on and power on reset sequence
Note:
If VDDL level is 100mV or more over, reset the IC by RESET_N pin after power-on.
TPOR is the value when VDD slope is liner. If VDD slope is not liner in your system, use RESET_N or contact us.
33/37
FEDL630Q464-02
ML630Q464/Q466
■APPLICATION CIRCUIT EXAMPLE
3.3V
P00/IN0
VDD
CS0
RS0
P01/CS0
CVR0
CVR1
CV
P03/RS0
P04/RT0
RESET_N
RT0
RESET_N
VDDL
P02/RCT0
P05/RCM
P20/IN1
CL
CL0
CS1
RS1
P21/CS1
P22/RS1
P23/RT1
ML630Q464/
Q466
CH1
CH2
RT1
CH12
P30/SDAF0
P31/SCLF0
VHF
Vss
CVH
P32
XT0
XT1
(Output)
CGL
CDL
SDA
Vcc
WP
XL
SCL
I2C EEPROM
A0 A1 A2
32.768KHz
Xtal
Vss
SWC
SWD
VREF
P35
CAV
P34
/LED
VL3
C1 C2 VL1 VL2
/LED
Ca Cb Cc
C12
LED
CV
: 1uF*
CL
: 2.2uF
CL0
: open*
CGL,CDL
Ca~Cc
CH12
: 12 to 16pF*
: 1uF*
: 1uF*
C12
CVH
: 1uF*
: 1uF*
CAV
: 1uF*
: 560 pF
: Thermistor (103AT/Semitec)
: DT-26, Daishinku
RS0, RS1
CVR0, CVR1
: 10 KΩ
: 820 pF
CS0, CS1
RT0, RT1
XL
*: Make a decision the parameters after evaluating on user’s conditions when designing circuits for mass production.
34/37
FEDL630Q464-02
ML630Q464/Q466
■PACKAGE DIMENSIONS
●ML630Q464/Q466 Package Dimensions
LAPIS Technology Co.,Ltd.
Figure B-1 TQFP100
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number,
package code and desired mounting conditions(reflow method, temperature and times).
35/37
FEDL630Q464-02
ML630Q464/Q466
■REVISION HISTORY
Document No.
Date
Page
Description
Previous Current
Edition
Edition
FEDL630Q464-01
FEDL630Q464-02
Oct. 26. 2016
May. 13. 2021
-
-
Final Edition
Updated about RESET_N and BRMP pins
12
14
28
33
16
12
14
28
33
33
Added comment in recommended operating conditions.
Added comment
Corrected “Power-on and shutdown Procedures”
Changed placement of reset characteristics.
Added note.
*
*
Corrected typo
36/37
FEDL630Q464-02
ML630Q464/Q466
Notes
1) The information contained herein is subject to change without notice.
2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals, application
notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating conditions, etc.) are within
the ranges specified. LAPIS Technology disclaims any and all liability for any malfunctions, failure or accident arising out of
or in connection with the use of LAPIS Technology Products outside of such usage conditions specified ranges, or without
observing precautions. Even if it is used within such usage conditions specified ranges, semiconductors can break down and
malfunction due to various factors. Therefore, in order to prevent personal injury, fire or the other damage from break down or
malfunction of LAPIS Technology Products, please take safety at your own risk measures such as complying with the derating
characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures. You are
responsible for evaluating the safety of the final products or systems manufactured by you.
3) Descriptions of circuits, software and other related information in this document are provided only to illustrate the standard
operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other
use of the circuits, software, and information in the design of your product or system. And the peripheral conditions must be
taken into account when designing circuits for mass production. LAPIS Technology disclaims any and all liability for any
losses and damages incurred by you or third parties arising from the use of these circuits, software, and other related
information.
4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Technology
or any third party with respect to LAPIS Technology Products or the information contained in this document (including but
not limited to, the Product data, drawings, charts, programs, algorithms, and application examples、etc.). Therefore LAPIS
Technology shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out
of the use of such technical information.
5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer systems,
gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our Products in applications
requiring a high degree of reliability (as exemplified below), please be sure to contact a LAPIS Technology representative and
must obtain written agreement: transportation equipment (cars, ships, trains, etc.), primary communication equipment, traffic
lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems, etc.
LAPIS Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising by using
the Product for purposes not intended by us. Do not use our Products in applications requiring extremely high reliability, such
as aerospace equipment, nuclear power control systems, and submarine repeaters, etc.
6) The Products specified in this document are not designed to be radiation tolerant.
7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this document. However,
LAPIS Technology does not warrant that such information is error-free and LAPIS Technology shall have no responsibility
for any damages arising from any inaccuracy or misprint of such information.
8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.
LAPIS Technology shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws
or regulations.
9) When providing our Products and technologies contained in this document to other countries, you must abide by the
procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export
Administration Regulations and the Foreign Exchange and Foreign Trade Act..
10) Please contact a ROHM sales office if you have any questions regarding the information contained in this document or LAPIS
Technology's Products.
11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Technology.
(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.
Copyright 2020-2021 LAPIS Technology Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku,Yokohama 222-8575, Japan
https://www.lapis-tech.com/en/
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