ML7456N (新产品)_技术文档

FEDL7456N-03

Issue Date：Oct. 26, 2022

ML7456N

Sigfox Sub-GHz Microcontroller

■Overview

ML7456N is a Sigfox Sub-GHz Microcontroller, which integrates MCU and RF Transceiver in a single chip.

RF frequency corresponds to 315MHz - 920MHz. It applis to Sigfox, it is low consumption and implements long-range

wireless communication.

MCU equips with an 16-bit CPU nX-U16/100(A35 core) and integrated with program memory(Flash memory), data

memory(RAM), data Flash and rich peripheral functions such as the multiplier/divider, CRC generator, DMA controller, Clock

generator, Simplified RTC, Timer, General Purpose Ports, UART, Synchronous serial port, I²C bus interface unit(Master, Slave),

Buzzer, Voltage Level Supervisor(VLS), Successive approximation type A/D converter, D/A converter , Analog comparator,

Safety function(IEC60730/60335 Class B), and so on.

The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by pipeline architecture

parallel processing.

The built-in on-chip debug function enables debugging and programming the software. Also, ISP(In-System Programming)

function supports the Flash programming in production line.

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■Features

◆ Sigfox / IEEE802.15.4g , Sigfox RF chip (ML7414)(*1)

⚫

Supported standard



Sigfox Revision 2.E

ETSI EN 300 220(Europe)

EN 13757-4:2013(Wireless M-Bus)

RCR STD-30(Ⅲ and Ⅳ types)

ARIB STD-T67

ARIB STD-T108

⚫

RF frequency: 315MHz - 960MHz supported

Realized high resolution modulation by using fractional N type PLL direct modulation

Modulation formats: BPSK (TX only), 4GFSK/4GMSK, GFSK/GMSK, FSK/MSK (MSK indicates FSK at

modulation index = 0.5.)

⚫

Data transmission rate: 0.1 to 100 kbps

Data encoding/decoding by HW: NRZ, Manchester, 3 out of 6

Data whitening by HW

Programmable frequency channel filters

Programmable frequency deviation function

TX/RX data inverse function

36MHz oscillator circuits/TCXO (36MHz) direct input supported

Programmable oscillator's circuit pins load capacitance

Super-power-saving low speed RC oscillator circuit

Low speed clock adjustment function

Frequency fine tuning function (using fractional N type PLL)

Synchronous serial peripheral interface(SPI)

On-chip TX PAPower control function

TX power fine tuning function (±0.2 dB)

TX power automatic ramping control

External TX PA control function

RSSI indicator and threshold judgment function

High speed carrier checking function

AFC function (IF frequency automatic adjustment by Fractional N type PLL adjustment)

Antenna diversity function

Automatic wake-up, auto SLEEP function (32kHz clock direct inputor internal RC oscillator circuit selectable)

General purpose timer (2ch)

TEST PATTERN GENERATOR (PN9 ,CW, 01 PATTERN, ALL”1”, ALL”0” OUTPUT)

Packet mode function



Wireless M-BUS packet format (Format A/B)

General purpose packet format (Format C/D)

Max. 255-byte (Format A/B), 2047-byte (Format C/D) packet length

TX FIFO (64 byte), RX FIFO (64 byte)

RX Preamble pattern detection (Max.4 byte)

Automatic TX preamble length generation (Max.length 16383 byte)

SyncWord setting function (Max. 4byte × 2 type)

Program CRC function (CRC32/CRC16/CRC8 selectable, fully programmable polynomial)

Address check function (C-field/M-field/A-field in Wireless M-Bus can be detected)

* Proprietary packet format is possible depending on setting

FEC function (IEEE802.15.4g compliant)



*Please refer to “ML7414 Application Note Hardware details” about RF part in detail.

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◆ MCU 16 bit CPU nX-U16/100 A35 core chip(ML62Q1532)

⚫

CPU

・ 16-bit RISC CPU: nX-U16/100 (A35 core)

・ Instruction system: 16-bit length instructions

・ Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit

manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and

so on

・ Built-in On-chip debug function

・ Built-in ISP (In-System Programming) function

・ Minimum instruction execution time

Approximately 30.5 μs (at 32.768 kHz system clock)

Approximately 62.5ns/41.6ns (at 16 MHz/24MHz system clock)

⚫

Coprocessor for multiplication and division

・ Multiplication : 16bit × 16bit (operation time : 4 cycles)

・ Division

: 32bit ÷ 16bit (operation time : 8 cycles)

: 32bit ÷ 32bit (operation time : 16 cycles)

・ Multiply-accumulate (non-saturating)

・ Multiply-accumulate (saturating)

・ Signed or Unsigned is selectable

: 16bit × 16bit + 32bit (operation time : 4 cycles)

⚫

Internal memory

・ Program memory area 64Kbyte

・ Rewrite count: 100 cycles

・ Write unit: 32bit (4byte)

・ Erase unit: 16Kbyte/1Kbyte

・ Erase/Write temperature: 0 C to +40 C

・ Data Flash memory area 4Kbyte

Rewrite count 10,000 cycles

Write unit: 8bit (1byte)

Erase unit: all area/128byte

Erase/Write temperature: -40 C to +85 C

Back Ground Operation (CPU can work while erasing and rewriting)

This product uses Super Flash® technology licensed from Silicon Storage Technology,

Inc.

・ Data RAM area 8Kbyte

Rewrite unit: 8bit/16bit

Parity check function is available (interrupt / reset is generatable at Parity error)

⚫

Clock Generation Circuit

・ Low-speed clock (LSCLK)

Internal low-speed RC oscillation: Approximately 32.768 kHz

External low-speed clock input (ML62Q1500/ML62Q1800 and ML62Q1700 group only)

: Approximately 32.768 kHz

External low-speed crystal oscillation (ML62Q1500/ML62Q1800 and ML62Q1700 group only)

: 32.768 kHz crystal resonator is connectable.

3 selectable crystal oscillation mode (Tough, Normal, and Low current consumption)

-Tough mode: Largest oscillation allowance to make highest resistance against leakage between the pins

-Normal mode: Normal oscillation allowance and current consumption

-Low current consumption mode: Smallest oscillation allowance to make lower current consumption

・ High-speed clock (HSCLK)

PLL oscillation: 2 selectable oscillation frequency (24MHz and 16MHz) by code option

・ Watch Dog Timer (WDT): built-in independent clock for WDT (RC1K: Approximately 1kHz)

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⚫

Reset

・ Reset by reset input pin

・ Reset by Power-On Reset

・ Reset by WDT overflow

・ Reset by WDT invalid clear

・ Reset by RAM parity error

・ Reset by unused ROM area access (instruction access)

・ Reset by voltage level supervisor (VLS)

・ Software reset by BRK instruction (reset CPU only)

・ Reset the peripherals individually

・ Collective reset to the all control pins and peripheral circuits.

⚫

Power management

・ HALT mode: CPU stops executing instruction, peripheral circuits continue working

・ HALT-H mode: CPU stops executing instruction, high-speed clock oscillation stops and peripheral circuits

continue working with low-speed clock

・ STOP mode: CPU and peripheral circuits stops executing instruction, both high-speed oscillation and low-speed

oscillation stops.

・ STOP-D mode: CPU and peripheral circuits stops executing instruction, both high-speed oscillation and

low-speed oscillation stops. The internal logic voltage (V_DDL) goes down to reduce the current consumption

(RAM

data is retained).

・ Clock gear: High-speed system clock frequency can be changed (1/1, 1/2, 1/4, 1/8, 1/16 or 1/32 of HSCLK)

・ Block Control Function: Powers down the unused function blocks (reset the block or stop supplying the clock)

⚫

Interrupt controller

・ External interrupt ports : max. 6

・ Non-maskable interrupt source: 1 (Internal source: WDT)

・ Maskable interrupt sources: max. 51

・ Four step interrupt levels

Watchdog timer (WDT)

・ Selectable Operating clock : select RC1K or LSCLK by code option

・ Overflow period: 8selectable (7.8ms, 15.6ms, 31.3ms, 62.5ms, 125ms, 500ms, 2s and 8s)

・ Selectable window function (enable or disable): configurable clear enable period (50% or 75% of overflow

period)

・ Selectable WDT operation : select Enable or Disable by code option

・ Readable WDT counter : WDT counter monitor function

⚫

DMA (Direct Memory Access) controller

・ Channel : 2channels

・ Transfer unit: 8bit/16bit

・ Transfer count: 1 to 1024

・ Transfer cycle: 2 cycle transfer

・ Transfer address: Fixed addressing mode, inclement addressing mode , and decrement addressing mode

・ Transfer target: Special Function Register (SFR)/RAM → SFR/RAM (Transfer from/to Flash is not supported)

・ Transfer request: External pins, Serial communication unit, Successive approximation type A/D converter, 16bit

timer, and Functional timer

⚫

Low-speed Time base counter

・ Generate 8 frequency (128Hz to1Hz) internal pulse signals by dividing the Low-speed clock (LSCLK)

・ Selectable 3 interrupts from eight frequency internal pulse signals

・ 1Hz or 2Hz output from general purpose port

・ Built-in Frequency adjust function (Adjust range: Approximately -488ppm to +488ppm, adjust resolution:

Approximately 0.119ppm)

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⚫ Simplified RTC

・ Channel: 1 channel

・ Count by a unit for one second from "00 min. 00 sec" to "59 min. 59 sec"

・ Selectable Periodical interrupt request from four periods (0.5s, 1s, 30s or 60s)

・ Built-in minute and second writing error protraction function

⚫

Functional timer

・ Channel: Max. 6 channels (output 4 channels)

・ Built-in timer, capture, and PWM function by 16 bit counter

・ Continuous mode, One shot mode is available

・ Two types of PWM output with the same period and different duties, and complementary PWM output with the

dead time

・ Monitor input signal duty and the period by capture function

・ Generate periodical interrupts, duty interrupts, and interrupts coincided with set value.

・ Counter Start, Stop, Counter clear triggered by an external inputs or Timer

・ Generate Emergency stop and emergency stop interrupt triggered by an external input

・ Same start/stop among different channels of the functional timer

・ Selectable counter clock(external clock or divided by 1 to 128 of LSCLK or HSCLK) for each channels

⚫

16bit General timers

・ Channel: Max. 6 channels (output 2 channels)

・ 8 bits timer mode and 16-bit timer mode

(16bit x 1channel can be used as 8bit x 2channels)

・ Same start/stop among different channels of 16bit (8bit) timer

・ Timer output (toggled by overflow)

・ Selectable counter clock (external clock or divided by 1 to 128 of LSCLK or HSCLK) for each channels

Serial communication unit

・ Synchronous Serial Port (SSIO) mode or UART mode is selectable

・ Channel: Max. 2 channels

< Synchronous Serial Port mode >

・

Selectable from Master and Slave

Selectable from LSB first or MSB first

Selectable 8-bit length or 16-bit length

< UART mode>

・

Selectable from Full-duplex communication mode or Half-duplex communication mode

5 to 8 bit length, parity or no parity, odd parity or even parity, 1 stop bit or 2 stop bits

Selectable from Positive logic or Negative logic

Selectable from LSB first or MSB first

Configurable wide range communication speed

32.768kHz operation clock : 1 bit/s to 4,800 bit/s

24MHz operation clock : 600 bit/s to 3M bit/s

16MHz operation clock : 300 bit/s to 2M bit/s

Built-in baud rate generator

・

⚫

I²C bus unit (Master / Slave)

・ Selectable from Master mode or Slave mode

・ Channel: 1 channel

< Master function >

・

Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)

Handshake (Clock synchronization)

7bit address format (10bit address format is supported)

< Slave function >

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・

Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)

Clock stretch function

7bit address format

⚫

I²C bus Master

・ Channel: 1 channel

・ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)

・ Handshake (Clock synchronization)

・ 7bit address format (10bit address format is supported)

General-purpose ports (GPIO)

・ I/O port: Max. 15 (Including one pin for on-chip debug and pins for other shared functions)

・ Input port: Max. 2 (Including a shared function)

・ External interrupt port: Max. 6

・ LED driver port : Max. 12

・ Carrier frequency output function (for IR communication)

⚫

Successive approximation type A/D converter(SA-ADC)

・ Channel: Max. 5 channels

・ Resolution: 10bit

・ Conversion time: Min. 2.25μs/channel (When the conversion clock speed is 8MHz)

・ Reference voltages are selectable

(V_DDpin / Internal reference voltage(V_REFI= Approximately 1.55V) / External reference voltage (V_REFpin) )

・ Selected channel repeat conversion

・ Dedicated result register for each channel

・ Interrupt determining by upper limit or lower limit threshold of conversion result

⚫

Voltage Level Supervisor (VLS)

・ Accuracy: ±4%

・ Threshold voltage: 12 selectable (from 1.85V to 4.00V)

・ Functional Voltage level detection reset (VLS reset)

・ Functional Voltage level detection interrupt (VLS0 interrupt)

⚫

Analog comparator

・ Channel: Max. 2 channels

・ Selectable interrupt from the comparator output (rising edge or falling edge)

・ Comparable with external input and internal reference voltage (0.8V)

D/A converter

・ Channel: Max. 1 channel

・ Resolution: 8bit

・ Output impedance: 6k ohm (Typ.)

・ R-2R ladder type

⚫

Buzzer

・ 4 buzzer mode (Continuous sound, Single sound, Intermittent sound 1 and Intermittent sound 2)

・

frequencies (4.096kHz to 293Hz)

・ 15 step duty (1/16 to 15/16)

・ Selectable from positive logic buzzer output or negative logic buzzer output

CRC(Cyclic Redundancy Check) generator

・ Generation equation: X¹⁶+X¹²+X⁵+1

・ Selectable from LSB first or MSB first

・ Built-in Automatic program memory CRC calculation mode in HALT mode

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⚫

Safety Function (IEC60730/60335 Class B)

・ Automatic switching to the internal low-speed RC oscillation in case the low-speed crystal oscillation stopped

・ RAM/SFR guard

・ Automatic program memory CRC calculation

・ RAM parity error detection

・ ROM unused area access reset (instruction access)

・ Clock mutual monitoring

・ WDT counter monitoring

・ SA-ADC test

・ UART test

・ Synchronous serial I/O test

・ I²C bus test

・ GPIO test

◆

Operating Voltage

2.6V to 3.6V

◆ Operating temperature -40℃ to 85℃ (Guaranteed Operation)

-30℃ to 75℃ (Guaranteed RF characteristics)

◆ Current consumption

Sleep mode

3.45uA (RF=IDD_SLP1/MCU=IDD2-2)

44.7mA (RF=IDD_TX20/MCU=IDD5)

18.2mA (RF=IDD_RX/MCU=IDD5)

TX

RX

20mW

◆ Package

48 pin WQFN

Lead free, RoHS Compliant

(*1)Supported Standard and frequency differs from products

ML7456N-700AGDZ0ANL

Sigfox(RC3), ARIB STD-T108

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■Related Documents

Please refer to “ML7414 Application Note Hardware details” about RF part in details.

Please refer to “ML62Q1000 Series User’s Manual” about MCU part of ML61Q1532 in details. ML7456N uses a part of

pins of ML62Q1532. Prioritize this document information about the pin explanation, the number of equipped functions

which relates to the number of pins.

Replace pin names between this document and “ML62Q1000 User’s Manual” as following the table.

This document

ML62Q1000 Series User’s Manual

VDDIO_MCU

VDD

REG_CORE_MCU

VDDL

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■Description Convention

1) Numbers description

‘0xnn’ indicates hexadecimal. ‘0bnn’ indicates binary.

Example: 0x11= 17(decimal), 0b11= 3(decimal)

2) Registers description

Registers are described as follows.

[<register name>: B<Bank No> <register address>] register

Example: [RF_STATUS: B0 0x0B(3-0)]

Register name: RF_STATUS

Bank No: 0

Register address: 0x0B

3) Bit name description

Bit names are described as follows.

<bit name> ([<register name>: B<Bank No> <register address>(<bit location>)])

Example: SET_TRX([RF_STATUS: B0 0x0B(3-0)])

Register name: RF_STATUS

Bank No: 0

Register address: 0x0B

Bit: Bit3 to bit0

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■Block Diagram

●Whole/RF part

ML7456N TQFN48

MCU(ML62Q1532)

Data Flash

SRAM

CPU(uX-U16/100)

ProgramMemory

(FLASH)

GPIO

RF(ML7414)

deepsleep reset

control

IRC

GPIO

DIO

SPI

SubGHz

CH

Filter

LNA

ADC

DEMOD

PH

Y

PHY

Match

ing/

Trap

RSSI

Detector

Filter

PLL

Modulator

O SC

PA

VCO

Regulator

36MHz

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●MCU part

Block diagram of MCU part ML62Q1500/1800 group

CPU（nX-U16/100）

ECSR1～3

DSR/CSR

PC

EPSW1～3

ELR1～3

LR

Multiplier/Divider

(Coprocessor)

GREG

0 ～15

PSW

EA

Timing

Controller

ALU

SP

Program

Memory

（FLASH）

BUS

Controller

Instruction

Decoder

Instruction

Register

On-Chip

ICE

V_DD

V_SS

INT

SU0~1_SCLK*

SU0~1_SIN*

RAM

SU0~1_SOUT0*

Serial

Communication

V_DDL

V_REFO

SU0~1_RXD0*

SU0~1_TXD0*

SU0~1_RXD1*

SU0~1_TXD1*

Unit *¹

Power

Circuit

Data FLASH

RESET_N

TEST0*²

SYSTEM

FLASH

INT

Controller

I²C Bus

Unit

I2CU0_SDA*

I2CU0_SCL*

INT

Clock

Generation

Circuit

OUTLSCLK*

OUTHSCLK*

Interrupt

INT

I²C Bus

Master

I2CM0_SDA*

I2CM0_SCL*

Low-speed

RC

Oscillation

INT

WDT

VLS

TMH0~5OUT*

16-Bit

Timer

High-speed

PLL

Oscillation

INT

EXTRIG0～7

FTM0~3P*

FTM0~3N*

RC

Oscillation

(for WDT)

Functional

Timer

DMA

Controller

CRC

Generator

INT

Low Speed

Time Base

Counter

V_DD

V_SS

V_REF

TBCOUT1*

SA-ADC

AIN0 to AIN5/7*

BZ0P*

BZ0N*

Buzzer

CMP0P*

CMP0M*

Analog

Comparator

Safety

Function

INT

PX0~PX7

（X= 0~3)

GPIO

(External Interrupt)

D/A

Converter *³

DACOUT0*

Reset

EXI0~7

Function

*

: Indicates the shared function of general ports. For available pins, refer to the pin list and pin definitions.

*1 : Shared UART and Synchronous Serial Port.

*2 : Not available as the input port when connecting to the on-chip debug emulator.

*3 : Not available as the input port when connecting to the crystal resonator.

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■PIN Layout

48 pin WQFN

MMCCUU部p端art子’s pin

RF部端子

RF part’s pin

36

35

34

33

32

31

30

29

28

27

26

25

37

24

23

22

21

20

19

18

17

16

15

14

13

P62

LP

GPIO_RF2

GPIO_RF1

GPIO_RF0

SDI

38

39

40

41

42

43

44

45

46

47

48

VDD_CP

P63

IND1

SCEN

Reserved side PKG GND

裏面PKGꢀGND

GND_VCO

IND2

SCLK

(TOP View)

PO7

VB_EXT

VDD_VCO

XT0

PO6

PO4

SDO

XT1

EXT_CLK

VDDIO_RF

●

VDD_REG

1

2

3

4

5

6

7

8

9

10

11

12

Note: GND pad in the middle of the LSI is reverse side (name: reversed side GND).

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■PIN List

Table PIN List(1/2)

PIN Name

(Primary

Function)

Primary

Function

2^nd

function

3^rd

function

5^th

6^th

7^th

8^th

4^thfunction

communications

Pin No.

function function function function

Timers

Others communicationscommunications

Others

ADC

1

2

3

4

5

6

7

8

VBG

REG_OUT

-

VDDIO_MCU

REG_CORE_RF

XIN

REG_CORE_MCU

RESET_N *1

P00/TEST *2

9

P01

XOUT

P02

DACOUT0

-

TBCOUT0 TBCOUT1

-

10

11

12

13

14

15

16

-

EXI0

EXTRG0

SU0_RXD0

SU0_SIN

-

FTM0P OUTLSCLK CMP0M

FTM0N OUTHSCLK CMP0P

-

EXI1

EXTRG1

SU0_TXD0

SU0_SOUT

P03

SU0_TXD1

I2CU0_SDA

AIN11

VDDIO_RF

EXT_CLK

SDO

-

EXI2

EXTRG2

P04

SU0_SCLK

I2CU0_SCL

TMH0OUT

17

18

19

20

21

22

23

24

25

P06

P07

-

I2CM0_SDA

-

SU0_RXD1

SU0_RXD0

I2CM0_SCL

SCLK

-

SCEN

SDI

GPIO_RF0

GPIO_RF1

GPIO_RF2

GPIO_RF3

EXI3

EXTRG3

26

27

28

29

30

31

P17

P20

SU0_RXD1

SU0_TXD1

SU0_RXD0

-

FTM1P

TBCOUT0

BZ0P

AIN0

AIN1

AIN2

-

FTM1N TBCOUT1

FTM2P OUTLSCLK

BZ0N

EXI4

EXTRG4

SU1_RXD0

SU1_SIN

P21

-

PA_OUT

P22

-

SU1_TXD0

SU1_SOUT

SU1_TXD1

I2CM0_SDA

FTM2N OUTHSCLK

AIN3

-

REG_PA

-

EXI5

EXTRG5

V_REF

32

P23

SU1_SCLK

-

I2CM0_SCL

TMH2OUT

-

V_REFO

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Table PIN List(2/2)

Primary

Function

2^nd

function

3^rd

function

5^th

6^th

7^th

8^th

PIN Name

(Primary Function)

4^thfunction

communications

Pin No.

function function function function

Timers

Others communicationscommunications

Others

ADC

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

-

VDD_PA

AMON

-

LNA_P

VDD_RF

P62

-

FTM4N

CMP1P

LP

-

VDD_CP

P63

-

FTM4P

CMP1M

-

IND1

GND_VCO

IND2

VB_EXT

VDD_VCO

XT0

PI00

PI01

-

XT1

-

VDD_REG

*1 Connect RESET_N pin to VDD when On-chip debug function is not used.

*2 Connect P00/TEST0 pin to VDD when On-chip debug function is not used.

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■PIN Definitions

I/O Definition

Digital input

Digital output

Schmitt trigger input

Digital input/output

Analog input

Analog output 1

Analog output 2

Analog input/output

RF input

Symbols in reset state

Active Level

H level

L level

Open drain

Rising

Falling

I

O

IS

IO

IA

OA

OAH

IOA

IRF

ORF

VDDIO

VDDRF

GND

:

I

O

Hi-Z

:

Input state

H

L

OD

P

N

:

Output state

High impedance

RF output

I/O power supply

RF power supply

Ground

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●MCU Part

The following Table shows each function’s pin lists of ML7456N MCU part. “-“ indicates the VDD pin, "(I)" indicates the

input pin, “O” indicates the output pin and "(I/O)" indicates the input/output pin.

Function

Signal name Pin name

I/O

Description

Negative Power Supply

Logic

Reserved

-

Side GND

Positive Power Supply

-

V_{DDIO_MCU}

-

Connect a Capacitor Cv between V_{DDIO_MCU}and V_SS

Power supply pin for internal logic (internal regulator’s

output).Connect a Capacitor C_L（1μF）between this pin

and V_SS

Power

REG_COR

E_MCU

Input for testing, is used as on-chip debug interface

and ISP function. If this pin is used for on-chip debug,

this pin can not be used for general port. P00 is

initialized as pull-up input mode by the system reset.

Reference voltage output

Test

TEST0

V_REFO

P00

P23

I/O

-

－

Reset input.

Applying “L” level shifts the MCU in system reset

mode.

RESET_N

I

Applying “H” level shifts the CPU in program running

mode.

Negative

Used for on-chip debug interface and ISP function.

No pull-up resistor is installed.

System

XT0

XT1

I

-

Low speed crystal oscillation pins

Connect 32.768kHz crystal resonator and Connect

capacitors between the pin and V_SS.

XT1

O

P02

P21

P03

P22

OUTLSCLK

OUTHSCLK

Low-speed clock output.

High-speed clock output.

General purpose input.

Not available as general inputs when using the crystal

oscillator, because this pin is combined use with

Low-speed oscillator pin.

PI00,PI01

XT0,XT1

I

Positive

General purpose I/O port

- High-impedance

- Input with Pull-UP (initial value)

- Input without Pull-UP

P00

I/O

- CMOS output

Positive

General Purpose

Port

- N-channel open drain output

Not available to use as general port when using for

on-chip debug interface or ISP function, because this

pin is combined use with TEST0 pin.

General purpose I/O

- High-impedance (initial value)

- Input with Pull-UP

- Input without Pull-UP

P01 to P07 P01 to P07

P17 P17

P20 to P23 P20 to P23

I/O

Positive

- CMOS output

- N-channel open drain output

P62 to P63 P62 to P63

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Function

Signal name Pin name

I/O

Description

Logic

SU0_TXD0

P03

P02

P07

P17

P03

P20

P07

P17

P22

O

Serial communication unit0 UART0 data output

Positive

Serial communication unit0 Full-duplex data input

Serial communication unit0 UART0 data input

SU0_RXD0

I

Positive

Serial communication unit0 Full-duplex data output

Serial communication unit0 UART1 data output

SU0_TXD1

O

Serial

communication

unit

SU0_RXD1

SU1_TXD0

SU1_RXD0

I

O

I

Serial communication unit0 UART1 data input

(UART mode)

Serial communication unit1 UART0 data output

Serial communication unit1 Full-duplex data input

Serial communication unit1 UART0 data input

Serial communication unit1 Full-duplex data input

Serial communication unit1 UART0 data input

Positive

P21

P22

Positive

SU1_TXD1

O

Function

Signal name Pin name

I/O

Description

Serial communication unit0 Synchronous serial data

input

Serial communication unit0 Synchronous serial clock

I/O

Serial communication unit0 Synchronous serial data

output

Serial communication unit1 Synchronous serial data

input

Serial communication unit1 Synchronous serial clock

I/O

Serial communication unit1 Synchronous serial data

output

I²C Unit0 (Master and Salve) Data I/O

N-channel open drain

Connect a pull-up resistor externally

I²C Unit0 (Master and Salve) Clock I/O

N-channel open drain output

Connect a pull-up resistor externally

I²C Master0 Data I/O pin

N-channel open drain output

Connect a pull-up resistor externally

I²C Master0 Clock I/O

Logic

Positive

SU0_SIN

SU0_SCLK

SU0_SOUT

SU1_SIN

P02

P04

P03

P21

P23

P22

I

Positive

I/O

O

Serial

communication

unit

(Synchronous

Serial Port)

I

SU1_SCLK

SU1_SOUT

I/O

O

I2CU0_SDA

I2CU0_SCL

I2CM0_SDA

I2CM0_SCL

P03

P04

I/O

Positive

I²C Bus

P06

P22

P07

P23

N-channel open drain output

Connect a pull-up resistor externally

Function

Signal name Pin name

I/O

O

I

Description

Functional Timer 0 P Output

Functional Timer 0 N Output

Functional Timer 1 P Output

Functional Timer 1 N Output

Functional Timer 2 P Output

Functional Timer 2 N Output

Functional Timer 4 P Output

Functional Timer 4 N Output

Functional Timer Event Trigger Input

16 bit Timer 0 Output

Logic

Positive

Negative

Positive

Negative

Positive

Negative

Positive

FTM0P

FTM0N

P02

P03

P17

P20

P21

P22

P63

P62

P02

P03

P04

P17

P21

P23

P04

P23

P02

P03

P01

P17

P01

P17

FTM1P

FTM1N

FTM2P

FTM2N

FTM4P

FTM4N

Functional Timer

Negative

EXTRG0

EXTRG1

EXTRG2

EXTRG3

EXTRG4

EXTRG5

TMH0OUT

TMH2OUT

EXTRG0

EXTRG1

-

I

O

I

Positive

16 bit Timer 2 Output

16 bit Timer Event Trigger Input

16 bit timer

-

I

Positive

TBCOUT0

O

The virtual frequency adjustment output signal

Low-speed Time

Base Counter

Positive

TBCOUT1

BZ0P

O

Low speed time base counter output signal 1Hz/2Hz

Buzzer output (positive phase)

Buzzer

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Signal name Pin name

I/O

Description

External Interrupt 0 Input

External Interrupt 1 Input

Logic

Function

EXI0

EXI1

P02

P03

I

-

EXI2

EXI3

EXI4

EXI5

V_REF

P04

P17

P21

P23

I

-

External Interrupt 2 Input

External Interrupt 3 Input

External Interrupt 4 Input

External Interrupt 5 Input

-

External Interrupt

SA-ADC external reference voltage input

Successive

approximation

type

A/D converter

(SA-ADC)

AIN0

AIN1

AIN2

AIN3

P17

P20

P21

P22

I

SA-ADC channel 0 input

SA-ADC channel 1 input

SA-ADC channel 2 input

SA-ADC channel 3 input

-

AIN11

CMP0P

CMP0M

CMP1P

CMP1M

DACOUT0

P03

P02

P62

P63

P01

I

SA-ADC channel 11 input

-

Comparator input 0 (noninverting input)

Comparator input 0 (inverting input)

Comparator input 1 (noninverting input)

Comparator input 1 (inverting input)

D/A converter 0 output

Analog

comparator

D/A converter

O

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●RF Part

○RF and Analog Pins

Reset

Pin name

Active

Level

I/O

ORF

IOA

IA

Pin Function

State

PA_OUT

AMON

LNA_P

LP

O

-

RF antenna output

Test (*1)

Hi-Z

I

-

RF antenna input

Pin for loop filter

IOA

IND1

Inductor connection pin for VCO tank

Pin for smoothing capacitor for internal bias

IND2

IOA

VB_EXT

[Note]

*1 Used for checking analog functions at LAPIS Technology.

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○SPI Interface Pins

Reset

Pin name

Active

Level

I/O

O

Pin Function

SPI data output or DCLK output(*1)

State

H or L

or OD

SDO

Hi-Z

* OpenDrain output is selected in the reset state. When using SDO as

CMOS output, set SDO_OD([SPI/EXT_PA_CTRL: B0 0x53(7)]) to 0b0.

SCLK

SCEN

SDI

Hi-Z

IS

I

P or N SPI clock input

SPI chip enable

L

L: Enabled

H: Disabled

SPI data input

or DIO I/O(*1)

H or L

[Note]

*1 Please refer to “DIO function”

○Regulator Pins

Reset

State

Active

Level

Pin name

VBG

I/O

Pin Function

-

OAH

-

Pin for decoupling capacitor

Requlator1 output (typ. 1.5V)

Requlator2 output (typ. 1.5V)

REG_OUT

-

OAH

OA

REG_CORE_R

F

Power down control pin for regulator

REGPDIN

REG_PA

I

H

Fix to “L” for normal use. “H” is for deep sleep mode.

-

OAH

-

Regulator output for PA block

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PIN definitions (continued)

○Miscellaneous Pins

Reset

Pin name

Active

Level

I/O

Pin Function

State

XIN

N.C.(*2)

I

-

IA

-

P or N 36MHz crystal pin 1

-

* When using TCXO, this must be open.

36MHz crystal pin 2

(TCXO input)

XOUT

TCXO(*2)

-

OA

IO

P or N

Digital I/O (*3)

EXT_CLK

GPIO_RF0

GPIO_RF1

GPIO_RF2

GPIO_RF3

Hi-Z

-

Reset state: External PA control signal output

H or L

or

OD(*1)

H or L

or

OD(*1)

H or L

or

OD(*1)

H or L

or

Digital I/O (*4)

Hi-Z

IO

Reset state: Interrupt indication signal output

Digital I/O (*5)

Reset state: Clock output

Digital I/O (*6)

Reset state: Antenna diversity selection control signal

Digital I/O (*7)

Reset state: TX – RX selection signal output

OD(*1)

[Note]

*1 OD is open drain output.

*2 When using TCXO, set TCXO_EN = 0b1. Please make sure only one of the registers TCXO_EN and XTAL_EN is set

to 0b1.

*3 Refer to [EXTCLK_CTRL: B3 0x2C].

*4 Refer to [GPIO0_CTRL: B3 0x28].

*5 Refer to [GPIO1_CTRL: B3 0x29].

*6 Refer to [GPIO2_CTRL: B3 0x2A].

*7 Refer to [GPIO3_CTRL: B3 0x2B].

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PIN definitions (continued)

○Power Supply/GND Pins

Reset

State

Active

Level

Pin name

VDD_REG

VDDIO_RF

VDD_PA

VDD_RF

VDD_CP

GND

I/O

Pin Function

Power supply pin for Regulator

(Input voltage: 2.6 to 3.6 V)

-

VDDIO

VDDRF

GND

-

Power supply for digital I/O

(Input voltage: 2.6 to 3.6 V)

-

Power supply for PA block

(Input voltage: 2.6 to 3.6 V, depending on TX mode)

Power supply for RF blocks

(REG_OUT is connected, typ. 1.5 V)

Power supply for charge pump

(REG_OUT is connected, typ. 1.5 V)

GND for VCO

Power supply for VCO

VDD_VCO

VDDRF

(REG_OUT is connected, typ. 1.5 V)

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●Unused Pins Treatment

Unused pins treatment are as follows: The treatments that impair the basic operations of this LSI are not included.

Unused pins treatment

Pin Name

XIN

Recommended treatment

Open (with TCXO)

EXT_CLK

GPIO_RF0

GPIO_RF1

GPIO_RF2

GPIO_RF3

AMON

Open

GND

RESET_N

Connect to VDDIO_MCU

Connect to VDDIO_MCU with Pull-UP (Initial Value) that is

Input mode.

P00/TEST0

XT0/PI00, XT1/PI01 Set the pin to Open with HiZ (Initila Value) state.

P00

P01 to P07

P17

Set the pin to Open with HiZ (Initila Value) state.

P20 to P23

P62 to P63

[Note]

If unused input pins, input/output pins are set to input and are high-impedance state and leave open (Input mode without

Pull-UP or Input/Output mode), excess current could be drawn. Care must be taken that unused input pins and unused I/O

pins should not be left open.

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●Internal Pins

This product is configured woth RF and MCU parts. This chapter explains internal pins in the package.

The following table shows internal connections in the package.

Table. Internal Connection in the package

MCU part Internal Pins Name

RF part Internal Pins Name

P73

REGPDIN

P74

RESETN

The following table shows the internal pins in the package.

Table. Internal Pins in the package (MCU part)

Function

Signal Nmae

Pin Name

I/O

Description

Logic

General Input/Output

・HiZ (Initial Value)

P73

・Input with Pull-UP resister

・Input without Pull-UP resister

・CMOS output

General Purpose

Port

Positive

P74

・N-ch Open drain output

The following table shows the RF part’s internal pins in the package.

Table. Internal Pins in the package (RF part)

Pin Name

Input/Output Active Level

Reset State

I / -

Description

RF Hardware Reset Pin

L: Initialize, Stop

H: Operation

RESETN

Is

L

* If this pin is set to “L”, RF part is initialized. Set this pin to

“L” when RF is deepsleep state.

RF Regulator Power Down Control Pin

REGPDIN

I

H

I / -

Fix this pin to “L” when normal operation. Set this pin to “H”

when RF is deepsleep state.

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■Electrical Characteristics

●Absolute Maximum Ratings

Ta = -40 to +85 ˚C and GND = 0 V are the typical conditions if not defined specifically.

Item

Symbol

VDDIO

VDDIO_MCU

VDDRF

PRFI

Condition

-

Rating

Unit

V

I/O power supply

-0.3 to +4.6

RF power supply

RF input level

RF output voltage

-

-0.3 to +2.0

+10

-0.3 to 4.6

V

dBm

V

Antenna input in RX

VRFO

PA_OUT pin

Voltage on Analog Pins 1

Voltage on Analog Pins 2

VA

VAH

-

-0.3 to 2.0

-0.3 to 4.6

V

-0.3 to V_DDIO+0.3^*1

-0.3 toV_{DDIO_MCU}+0.3^*1

-0.3 to V_DDIO+0.3^*1

-0.3 to V_{DDIO_MCU}+0.3^*1

-8 to +8

Voltage on Digital input Pins

Voltage on Digital output Pins

VIN

V

-

VOUT

IDO

V

Digital output current (RF part)

Digital output current

(MCU part)

-

mA

IDO2

-15 to +15

Power dissipation

Pd

Ta= +25℃

1.2

W

Storage temperature

Tstg

-

-55 to +150

℃

*1: It needs to be less than 4.6V

*2: Minus sign shows current direction from internal side of LSI to pin.

The current absolute value is the maximum value.

Example: -1mA shows that the maximum 1mA current flows from internal side of LSI to pin.

[Note]

Absolute Maximum Ratings are the tolerance to protect the product’s physical quality, do not guarantee the normal

operaton.

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●Recommended Operating Conditions

Item

Symbol

Condition

VDDIO_RF pin

VDD_REG pin

VDD_PA pin

VDDIO_MCU pin

(*1)

Min.

2.6

Standard

3.3

Max.

3.6

Unit

Power Supply

VDDIO

V

Operating temperature

Digital input rise time

Digital input fall time

Digital output load

Ta

TIR

TIF

-

-40

-

+25

-

+85

20

℃

ns

pF

Digital input pins (*1)

All Digital Output pins

-

20

CDL

20

Master clock frequency

(XIN/XOUT pin)

FMCK1

-

36

-

MHz

Master clock accuracy (*2)

ACMCK1 FSK 時

-20

-

+20

80

ppm

ohm

X' tal equivalent series

resistance

ESR

-

－

DC cut

*TCXO opetions selected

TCXO input voltage

VTCXO

0.8

30k

-

1.5

25M

Vpp

Hz

Operating frequency(CPU)

f_OP

C_L

-

REG_CORE_MCU attached

capacity

-

1.0-30%

1.0

1.0+30%

uF

315

750

-

450

960

MHz

RF frequency

FRF

*1 In the pin description, I or Is are specified as the I/O.

*2 Indicating frequency deviation during TX-RX operation. In order to support various standards, please apply the

frequency accuracy for each standard to meet the requirements.

Specification

Required accuracy

ARIB STD T-108

±20 ppm

*Below typical values indicate typical center values. They are not guaranteed values with consideration given to a variety of

ICs.

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●MCU

○Power Consumption

o

(V_{DDIO_MCU}=2.6 to 3.6V， V_SS=0V， Ta=-40 to +85 C if not defined specifically.)

Standard

Typ.*³

Symbo

Item

Condition

Unit

μA

l

Min.

Max.

23

CPU is STOP-D state

All oscillators are stopped

CPU is STOP state

Power

Consumption 0

IDD0

―

0.8

Power

Consumption 1

IDD1

―

1.0

4.7

26

35

μA

All oscillators are stopped

Low RC oscillation*¹

Power

Consumption 2

IDD2-

1

CPU is HALT state

μA

PLL oscillation is stopped

Low oscillator*¹*⁴

Power

Consumption

2-2

IDD2-

2

CPU is HALT state

―

3.0

17

32

105

4.5

μA

PLL oscillation is stopped

CPU is operated with RC*¹*²

PLL oscillation is stopped

CPU is operated 16MHz *¹*²

When PLL 16MHz oscillation

Power

Consumption 3

IDD3

IDD4

Power

Consumption 4

3.3

mA

V

_{DDIO_MCU}=2.6 to 3.6V

CPU is operated with 24MHz*¹*²

Power

Consumption 5

IDD5

When PLL 24MHz oscillation

―

4.7

6.0

mA

V

_{DDIO_MCU}=2.6 to 3.6V

*¹：LTBC，WDT operating state，All controllable bits of Block Control Register（BCKCONn） and Block Reset

Control Register （BRECONn） are set to “1”.

*²：CPU is operated with Wait mode.

*³：V_{DDIO_MCU}=3.0V,Ta=+25 ^oC

^*4：Low current consumption mode，Noise removal filter is set to off.

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○Low Speed Crystal Oscillator Characteristics

(V_{DDIO_MCU}=2.6 to 3.6V， V_SS= 0V， Ta=-40 to +85 ^oC if not defined specifically.）

Standard

Typ.

Item

Symbol

f_XTL

Condition

Unit

kHz

s

Min.

-

Max.

-

Crystal Oscillator

Frequency*¹*²

Crystal Oscillator Starting

time

-

32.768

T_XTL

-

2

^*1：Oscillation frequency depends on oscllator circuit, crystal oscillator and circuit constant of capacitor with attached

crystal oscillator(CGL/CDL).

Matching evaluation on the implemented curcuit is neccesary because the circuit constant depends on crystal

oscillator.

Receive confirmation of oscillation characteristic from oscillator manifacture with marching evaluation.

^*2：There is a possibility that the expected oscilation characterictic is not guaranteed. It depends on material, writing

pattern of circuit board, writing, parasitic capacitance of crystal oscillator and pins.

Please take care of attached external circuit.

- Make the writing pattern of external circuit as short as possible.

- Make the writing pattern between capacitor of the attached crystal oscaillator and the crystal oscillator as short as

possible.

- Make the external circuit writing pattern and the writing pattern that large current flows not to cross or be close

each other.

- Make the external circuit writing pattern and the other signal’s writing pattern not to cross.

- Make the external capacitor of crystal oscillator to connect the GND whose current fluctuation and voltage

fluctuation as small as possible.

- There is a possibility that the expected oscillation characteristic is not guaranteed because of the environment of

moisture absorption of board, condensation of board surface. Resin sealed of circuit board and so on are

recommended.

Example of circuit diagram of Low-speed crystal oscillator

XT0

XT1

V_SS

Crystal Oscillator

（32.768kHz）

C_DL

C_GL

○External Clock Input Characteristics

(V_{DDIO_MCU}=2.6 to 3.6V， V_SS= 0V， Ta=-40 to +85 ^oC if not defined specifically.)

Standard

Typ.

Item

Symbol

f_EXCK

Condition

Unit

kHz

s

Min.

Max.

Typ.

-1.0%

Typ.

+1.0%

Input Frequency

Input Pulse Width

―

32.768

1/f_EXCK

x 0.4

1/f_EXCK

x 0.6

t_EXCKW

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○On-Chip Oscillator Characteristics

(V_{DDIO_MCU}=2.6 to 3.6V， V_SS=0V， Ta=-40 to +85 ^oC if not defined specifically.)

Standard

Sym

bol

Item

Condition

Unit

kHz

Min.

Typ.

Max.

Typ.

Ta=+25 ^oC，

32.768

Low speed RC Oscillator

Frequency1

V_{DDIO_MCU}=2.6 to 3.6V

Ta=-40 to +85 ^oC，

V_{DDIO_MCU}=2.6 to 3.6V

-2.0%

Typ.

+2.0%

Typ.

f_RCL1

without software correction

32.768

-3.5%

+3.5%

Low speed RC Oscillator

Frequency 2

Ta=-40 to +85 ^oC，

Typ.

f_RCL2

V_{DDIO_MCU}=2.6 to 3.6V

-2.0%

+2.0%

with software correction

PLL Oscillation Frequency 1

Internal low speed RC

Ta=-40 to +85 ^oC，

Typ.

f_PLL1

16/24

V_{DDIO_MCU}=2.6 to 3.6V

-2.5%

+2.5%

without software correction

PLL Oscillation Frequency 2

Internal Low speed RC

MHz

Ta=-40 to +85 ^oC，

Typ.

-1.0%

Typ.

+1.0%

f_PLL2

T_PLL

f_RC1K

16/24

V_{DDIO_MCU}=2.6 to 3.6V

with software correction

Ta=-40 to +85 ^oC，

PLL Oscillation Stable Time

-

2

ms

V_{DDIO_MCU}=2.6 to 3.6V

Low speed RC1K Oscillator

Frequency

Ta=-40 to +85 ^oC，

0.5

1

2.5

kHz

V_{DDIO_MCU}=2.6 to 3.6V

（Only for Watchdog timer）

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○Input,Output Pins Characteristics 1

(V_{DDIO_MCU}=2.6 to 3.6V， V_SS=0V， Ta=-40 to +85 ^oC if not defined specifically.)

Standard

Item

Symbol

VOH1

Condition

Unit

Min.

Typ.

-

Max.

-

“H”/”L” Level

Output Voltage 1

IOH1=-1mA

V_DD

-0.5

V

_{DDIO_MCU}≧2.6V

(P00)

(P01 to P07)

(P17)

IOL1=+1mA

VOL1

VOL2

-

0.5

(P20 to P23)

(P62 to P63)

V

_{DDIO_MCU}≧2.6V

V

“L” Level Output

IOL2=+8mA

Voltage 2

-

0.5

0.4

V_{DDIO_MCU}≧3.0V

(P01 to P07)

(P17)

When N-ch Open

drain output selected

IOL2=+3mA

(P20 to P23)

(P62 to P63)

V_{DDIO_MCU}≧2.6V

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○Input, Output Pins Characteristics

(V_{DDIO_MCU}=2.6 to 3.6V， V_SS=0V， Ta=-40 to +85 ^oC if not defined specifically.)

Standard

Item

Symbol

Condition

Unit

Min.

Typ.

Max.

-

“H” Level

Output Current

1 *⁶

-1 *³*⁵

-

V

_DD≧2.6V

IOH1

1 pin

“Sum of P00 to P07”

or

“H” Level

Output

total Current

*¹*⁴

-20 *⁵

-

“Sum of P17，P20 to P23，

P62 to P63”

IOH3

（When Duty≦50%）

Sum of all pins

-40 *⁵

V

_DD≧2.6V

（When Duty≦50%）

1 pin

“L” Level Output

Current 1 *⁶

IOL1

IOL2

-

1 *³

（When CMOS Output

selected）

1 pin

-

8 *³

3 *³

mA

V

_DD≧3.0V

_DD≧2.6V

“L” Level Output

Current 2 *⁶

（When N-ch Open drain

output selected）

“Sum of P00 to P07”

or

V

_DD≧3.0V

-

40

“Sum of P17，P20 to P23，

P62 to P63”

“L” Level Output

Total Current

*²*⁴

IOL3

（When N-ch Open drain

Output selected, Duty≦50%）

V

_DD≧2.6V

15

20

Sum of all pins（When N-ch

Open drain Output selected,

Duty≦50%）

Output Leak

(P00)

VOH=V_DD（When HiZ）

VOL=V_SS（When HiZ）

IOOH

IOOL

-

+1

-

(P01 to P07)

(P17)

μA

(P20 to P23)

(P62 to P63)

-1*⁵

*¹：This current value guarantees the device normal operation if it flows from V_{DDIO_MCU}pin to output pin.

*²：This current value guarantees the device normal operation if it flows from output pin to V_SSpin.

*³：Do not exceed the total output current.

*⁴：This is the output current when Duty≦50%.

On the condition of Duty＞50%, the output current is calculated as the following formula,

Total output current of pins＝IOL3 x 50/n （When Duty is n%）

＜Example of calculation＞

When IOL3=100mA，n=80%，

Total output current of pins＝ IOL3 x 50/80=62.5mA

The current that can be flowed to 1 pin is the same, and follows IOL1, IOL2.

It is impossible to flow the current more than Absolute Maximum Ratings.

*⁵：If current flows from internal side of LSI to pin, minus sign is written.

Absolute current value is the maximum value.

Example：-1mA means the maximum 1mA current flows from LSI pin.

*⁶： It is condition to satisfy VOH1,VOL1,VOL2.

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ML7456N

○Input, Output Pins Characteristics 3

(V_{DDIO_MCU}=2.6 to 3.6V， V_SS=0V， Ta=-40 to +85 ^oC if not defined specifically.)

Standard

Item

Symbol

Condition

Unit

Min.

-

-1^*1

-1500^*1

3.7

Typ.

Max.

IIH1

IIL1

VIH1=V_DD

-

1

Input Current1

(RESET_N)

VIL1=V_SS

-

-20^*1

80

1

μA

VIL2=V_SS（When Pull-UP）^*2

VIH2=V_DD（When HiZ）

VIL2=V_SS（When HiZ）

IIL2

-300^*1

V/IIL2

IIH2Z

IIL2Z

10

-

kΩ

Input Current 2

(P00/TEST0)

-

-1*¹

-

μA

VIL1=V_SS（When Pull-UP）^*2

VIH1=V_DD（When HiZ）

IIL3

-250^*1

-30^*1

-2^*1

Input Current 3

(P01-P07)

(P17)

V/IIL3

22

100

800

kΩ

IIH3Z

IIL3Z

-

1

-

(P20-P23)

(P62-P63)

-1^*1

VIL1=V_SS（When HiZ）

μA

IIH4

IIL4

VIH1=V_DD

VIL1=V_SS

-

1

-

Input Current 4

（PI00-PI01）

-1^*1

Input Voltage 1

（RESET_N）

(P01-P07)

(P17)

(P20-P23)

(P62-P63)

（PI00-PI01）

0.7

VIH1

VIL1

-

V_DD

xV_DD

0.3

0

V

5

xV_DD

0.7

VIH2

VIL2

-

V_DD

xV_DD

Input Voltage 2

（P00/TEST0）

0.25

xV_DD

0

Pin Capacitor

（RESET_N）

（P00/TEST0）

(P01-P07)

(P17)

(P20-P23)

(P62-P63)

（PI00-PI01）

f = 10kHz

Ta = +25^oC

CPIN

-

10

pF

-

*¹：If current flows from internal side of LSI to pin, minus sign is written.

Absolute current value is the maximum value.

Example：-1mA means the maximum 1mA current flows from LSI pin.

*²：Typ. value is a condition of V_{DDIO_MCU}=3.0V. Max. value is a condition of V_{DDIO_MCU}=2.6V, Min.value V_{DDIO_MCU}=3.6V.

32/218

FEDL7456N-03

ML7456N

○Synchronous Serial Port Characteristics

Slave Mode

(V_{DDIO_MCU}=2.6 to 3.6V， V_SS=0V， Ta=-40 to +85 ^oC if not defined specifically.）

Standard

Typ.

-

Item

Symbol

Condition

Unit

Min.

1*²

0.5*³

Max.

-

SCLK Input Cycle

t_SCYC

t_SW

μs

-

SCLK Input Pulse Width

100+

SOUT Output Delay Time

SIN Input Setup Time

SIN Input Hold Time

t_SD

t_SS

t_SH

-

ns

HSCLK*¹×3

-

HSCLK*¹×1

-

80+

-

HSCLK*¹×3

*¹：High speed clock frequency

*²：More than HSCLK×8 input cycle is neccesary.

*³：More than HSCLK×4 input cycle is neccesary.

t_SCYC

t_SW

0.7×V_DD

0.3×V_DD

SUn_SCLK*

t_SD

0.7×V_DD

0.3×V_DD

SUn_SOUT*

t_SS

t_SH

0.7×V_DD

0.3×V_DD

SUn_SIN*

*：Port’s 2^ndto 8^thfunctions.

n： 0 to 5

33/218

FEDL7456N-03

ML7456N

Master Mode

(V_{DDIO_MCU}=2.6 to 3.6V， V_SS=0V， Ta=-40 to +85 ^oC if not defined specifically.）

Standard

Typ.

Item

Symbol

Condition

Unit

Min.

Max.

SCLK Output Cycle

SCLK Output Pulse Width

SOUT Output Delay Time

t_SCYC

t_SW

t_SD

-

SCLK*¹

SCLK*¹×0.5

-

ns

SCLK*¹×0.4

-

SCLK*¹×0.6

100

-

SIN Input Setup Time

SIN Input Hold Time

t_SS

t_SH

120

80

ns

-

*¹：Clock frequency that is selected by bit 12-8(SnCK4-0) of Synchronous Serial Port n Mode Register(SIOnMOD).

(When V_{DDIO_MCU}≧2.6V：min250ns)

t_SCYC

t_SW

0.7×V_DD

0.3×V_DD

SUn_SCLK*

SUn_SOUT*

SUn_SIN*

t_SD

0.7×V_DD

0.3×V_DD

t_SS

t_SH

0.7×V_DD

0.3×V_DD

*：Port’s 2^nd– 8^thfunctions.

n：0 to 5

34/218

FEDL7456N-03

ML7456N

○I²C Bus Interface Characteristics

Standard Mode（100kbps）

(V_{DDIO_MCU}=2.6 to 3.6V， V_SS= 0V， Ta=-40 to +85 ^oC if not defined specifically.）

Standard

Typ.

Item

Symbol

f_SCL

Condition

Unit

kHz

μs

Min.

0

Max.

100

-

SCL Clock Frequency

SCL Hold Time

(Start/Restart Condition)

-

t_HD:STA

4.0

-

SCL“L” Level time

t_LOW

t_HIGH

4.7

4.0

μs

SCL“H” Level Time

SCL Setup Time

(Restart Condition)

SDA Hold Time

SDA Setup Time

(Stop Condition)

Bus Free Time

t_SU:STA

4.7

μs

t_HD:DAT

t_SU:DAT

-

0

0.25

-

μs

t_SU:STO

4.0

μs

t_BUF

-

4.7

-

μs

When it is used for I²C bus master, set I²C Master n Mode Register (I2MnMOD), I²C Bus 0 Mode Register (Master

side) (I2UM0MOD) to conform to the above standard.

Start

Restart

Stop

Condition

0.7×V_DD

0.3×V_DD

I2CUn_SDA

I2CMn_SDA

0.7×V_DD

0.3×V_DD

I2CUn_SCL

I2CMn_SCL

t

^SU:STOt_BUF

t_HD:STA

t_LOW

t_SU:STAt_HD:STA

t_SU:DATt_HD:DAT

t_HIGH

n：0 to 1

35/218

FEDL7456N-03

ML7456N

Fast Mode（400kbps）

(V_{DDIO_MCU}=2.6 to 3.6V， V_SS= 0V， Ta=-40 to +85 ^oC if not defined specifically.）

Standard

Typ.

Item

Symbol

f_SCL

Condition

Unit

kHz

μs

Min.

0

Max.

400

-

SCL Clock Frequency

-

SCL Hold Time

(Start/Restart Condition)

SCL“L” Level Time

t_HD:STA

0.6

-

t_LOW

t_HIGH

1.3

0.6

μs

SCL“H” Level Time

SCL Setup Time

(Restart Condition)

SDA Hold Time

SDA Setup Time

(Stop Condition)

Bus Free Time

t_SU:STA

0.6

μs

t_HD:DAT

t_SU:DAT

-

0

0.1

-

μs

t_SU:STO

0.6

μs

t_BUF

-

1.3

-

μs

When it is used for I²C bus master, set I²C Master n Mode Register (I2MnMOD), I²C Bus 0 Mode Register (Master

side) (I2UM0MOD) to conform to the above standard.

Start

Restart

Stop

Condition

0.7×V_DD

0.3×V_DD

I2CUn_SDA

I2CMn_SDA

0.7×V_DD

0.3×V_DD

I2CUn_SCL

I2CMn_SCL

t

^SU:STOt_BUF

t_HD:STA

t_LOW

t_SU:STAt_HD:STA

t_SU:DATt_HD:DAT

t_HIGH

n：0 to 1

36/218

FEDL7456N-03

ML7456N

1Mbps Mode

(V_{DDIO_MCU}= 2.7 to 3.6V， V_SS= 0V， Ta=-40 to +85 ^oC if not defined specifically.）

Standard

Typ.

Item

Symbol

Condition

Unit

Min.

0

Max.

1000

-

SCL Clock Frequency

SCL Hold Time

(Start/Restart Condition)

f_SCL

-

kHz

t_HD:STA

0.26

μs

-

SCL“L” Level Time

t_LOW

t_HIGH

0.5

0.26

μs

SCL“H” Level Time

SCL Setup Time

(Restart Condition)

SDA Hold Time

SDA Setup Time

(Stop Condition)

Bus Free Time

t_SU:STA

0.26

μs

t_HD:DAT

t_SU:DAT

-

0

0.1

-

μs

t_SU:STO

t_BUF

0.26

0.5

μs

-

When it is used for I²C bus master, set I²C Master n Mode Register (I2MnMOD), I²C Bus 0 Mode Register (Master

side) (I2UM0MOD) to conform to the above standard.

Start

Restart

Stop

Condition

0.7×V_DD

0.3×V_DD

I2CU0_SDA

I2CMn_SDA

0.7×V_DD

0.3×V_DD

I2CU0_SCL

I2CMn_SCL

t

^SU:STOt_BUF

t_HD:STA

t_LOW

t_SU:STAt_HD:STA

t_SU:DATt_HD:DAT

t_HIGH

n：0 to 1

37/218

FEDL7456N-03

ML7456N

○ Reset Characteristics

(V_{DDIO_MCU}=2.6 to 3.6V， V_SS=0V， Ta=-40 to +85 ^oC if not defined specifically.）

Standard

Item

Symbol

Condition

-

Unit

ms

Min.

2

Typ.

-

Max.

-

Reset Enable Time

P_RST

t_SP00

P00“H” Level Setup Time

P00“H”Level Hold Time^*1

-

1

-

ms

*1

t_HP00

^*1：It is the regulation without ISP mode. When ISP mode is used, refer to the timing of ISP mode of User’s Manual

“25.4 In-System Programing Function”.

VIH1

VIL1

RESET_N

*2

P_RST

VIH2

“H” Level or L” Level

“H” Level Input

t_SP00t_HP00

^*2：When Power on reset, the time is counted after V_{DDIO_MCU}=2.6V.

P00/TEST0

[Note]



If the pulse that is shorter than Reset Enable Time (PRST) is inputted into Reset pin, unexpected operation will

be caused. Do not input short pulse than Reset Enable Time.

38/218

FEDL7456N-03

ML7456N

○Power Slope, Power-on Reset Characteristics

(V_SS=0V， Ta=-40 to +85 ^oC if not defined specifically.）

Standard

Item

Symbol

Condition

Unit

Min.

-

Typ.

Max.

60

Power Rising Slope

Power Falling Slope

S_VR

S_VF

-

V/ms

V

-

2

V_PORR

V_PORF

When Power-on Rising

When Power-on Falling

1.47

1.33

1.57

1.49

-

1.80

1.58

-

Power-on Reset Judgement

Voltage

V

Power-on Reset Minimum

Pulse Width

P_POR

V_INIT

-

200

1.8

μs

Power-on Initial Voltage

CPU Operation Start time

When Power-on

-

V

(Time between releasing

Reset and CPU Operation

Start)

t_CPUI

-

11

16

ms

-

When Power Voltage is changed

S_VR

When Power-on again

S_VF

S_VR

V_{DDIO_MCU}

V_INIT

V_PORR

V_PORF

0V

P_POR

When Power-off

t_CPUI

When Power-on

[Note]



If short pulse that is shorter than Power-on Reset response time is inputted into, there is a possibility that LSI is

not reset and operated incorrectly. Prevent low power voltage by Bypass capacitors or reset by Reset input pin.

Start High speed clock after V_{DDIO_MCU}voltage becomes within the operating voltage.



39/218

FEDL7456N-03

ML7456N

○VLS Characteristics

(V_{DDIO_MCU}=2.6 to 3.6V， V_SS=0V， Ta=-40 to +85 ^oC if not defined specifically.）

Condition

Power Voltage

Standard

Typ.

4.06

4.00

3.76

3.70

3.11

3.05

3.01

2.95

2.91

2.85

2.81

2.75

2.71

2.65

2.61

2.55

2.51

2.45

2.11

2.05

2.01

1.95

1.91

1.85

Item

Symbol

Unit

VLS0LV^*1

00H

Min.

3.86

3.84

3.57

3.55

2.94

2.92

2.85

2.83

2.75

2.73

2.66

2.64

2.56

2.54

2.46

2.44

2.37

2.35

1.98

1.96

1.89

1.87

1.79

1.77

Max.

4.26

4.16

3.95

3.85

3.28

3.18

3.17

3.07

2.97

2.96

2.86

2.76

2.66

2.65

2.55

2.24

2.14

2.13

2.03

1.93

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

V_VLSR

V_VLSF

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

VLS Judgement

Voltage^*2

V

VLS Current

Consumption

I_VLS

-

50

-

nA

^*1： Bit3 to 0 of Voltage Level Supervisor Function 0 Level Register (VLS0LV)

^*2： Setting VLS0LV=0CH - 0FH of VLS Judgement Voltage is inhibited.

○Analog Comparator Characteristics

(V_{DDIO_MCU}=2.6 to 3.6V， V_SS=0V， Ta=-40 to +85 ^oC if not defined specifically.）

Standard

Item

Symbol

Condition

Unit

Min.

0.1

Typ.

Max.

V_{DDIO_}

MCU

Comparator

In-Phase Input

Voltage Range

V_CMR

V_CMOF

V_CMREF

-

V

mV

V

-1.5

Comparator Input

Offset

Ta=+25 ^oC，V_{DDIO_MCU}=3.3V

-

5

-

Comparator

Reference

Voltage

-

0.75

0.8

0.85

40/218

FEDL7456N-03

ML7456N

○Successive Approximation Type A/D Converter

(V_{DDIO_MCU}=2.6 to 3.6V， V_SS= 0V， Ta=-40 to +85 ^oC if not defined specifically.)

Standard

Item

Symbol

n_AD

Condition

Unit

Bit

Min.

-

-4

Typ.

-

Max.

10

4

Resolution

-

2.7V≦SA-ADC Ref Voltage ^*1≦3.6V

2.2V≦SA-ADC Ref Voltage ^*1＜2.7V

1.8V≦SA-ADC Ref Voltage ^*1＜2.2V

SA-ADC Ref Voltage = Internal Ref

-6

-

6

Integral

Nonlinearity

INL_AD

-10

10

-15

-

15

Voltage（V_REFI

）

2.7V≦SA-ADC Ref Voltage ^*1≦3.6V

2.2V≦SA-ADC Ref Voltage ^*1＜2.7V

1.8V≦SA-ADC Ref Voltage ^*1＜2.2V

SA-ADC Ref Voltage =Internal Ref

-3

-5

-9

-

3

5

9

LSB

Differencial

Nonlinearity

DNL_AD

-14

-

14

Voltage（V_REFI

RI≦1kΩ

-

）

Zero Scale Error

Full Scale Error

ZSE

FSE

V_REF

-6

-

6

A/D Reference Voltage

1.8

V_DD

V

Internal Reference

Voltage

V_REFI

-

1.5

1.55

1.6

2.2V≦V_DD≦3.6V

1.8V≦V_DD≦3.6V

4.5

18

-

427

Conversion Time

t_CONV

μs

*¹：It is the case that V_{DDIO_MCU}，P23/V_REFare selected as SA-ADC Reference Voltage.

Current flows to charge in capacitors during SA-ADC sampling. Set the output impedance of analog input resource to less

than 1 kΩ for getting enougth sampling result. It is recommended to implement about 0.1μF capacitor to reduce noise.

V_DD

V_DDL

1.0μF

A

RI≦1kΩ

0.1μF

AINx

-

1.0μF

+

Analog Input

V_SS

41/218

FEDL7456N-03

ML7456N

○D/A Converter Characteristics

(V_{DDIO_MCU}=2.6 to 3.6V， V_SS= 0V， Ta=-40 to +85 ^oC if not defined specifically.)

Standard

Typ.

Item

Symbol

Condition

Unit

Min.

-

10

Max.

8

-

Resolution

Conversion Frequency

Integral

n_DA

tc

-

Bit

μs

INL_DA

RL=4MΩ

-2

2

Nonlinearity

Differential

Nonlinearity

LSB

-

DNL_DA

Ro

RL=4MΩ

-1

3

1

9

Output Impedance

-

6

kΩ

○Reference Voltage Output Characteristics

(V_{DDIO_MCU}=2.6 to 3.6V， V_SS= 0V， Ta=-40 to +85 ^oC if not defined specifically.)

Standard

Item

Symbol

Condition

Unit

Min.

-

Typ.

1.55

-

Max.

-

500

Output Voltage Value

Output Impedance

V_REFO

R_VREFO

-

V

kΩ

○Flash Memory Operation Condition

（V_SS= 0V）

Item

Symbol

Ta

Condition

Data Area：Program/Erase

Program Area：Program/Erase

Program/Erase

Standard

-40 to +85

0 to +40

2.6 to 3.6

10000

100

Unit

Operation Temperature

(surroundings)

^oC

V

Operation Voltage

V_{DDIO_MCU}

CEPD

Data Area

Programming cycle

Erasing Unit

times

CEPP

Program Area

Block Erase

16K

-

B

Data Area

All Areas

1K

Program Area

Sector Erase

Data Area

128

-

Block Erase/

Sector Erase

Program Area

50

ms

B

Erasing Time(Max)

Programming Unit

-

4

Data Area

Program Area

Data Area

-

1

-

80

40

15

Programming Time(Max)

Data Retention Years

μs

YDR

Year

42/218

FEDL7456N-03

ML7456N

●RF

○Power Consumption

Values are under the condition of the master clock frequency = 36 MHz (Typ.).

Item

Symbol

Condition

Deep Sleep mode

(Not retaining Registers, all function

halt)

Min.

-

Typ. (*2)

0.1

Max (*3)

Unit

µA

14

IDD_DSLP

(0.24)

33

IDD_SLP1

IDD_IDLE

-

µA

Sleep mode 1 (*4)

0.45

1.0

(2.3)

Power

Consumption (*1)

1.2

16

mA

Idle state (*5)

IDD_RX

RX state (*6) (*7)

mA

-

13.5

40

IDD_TX20

TX state (20 mW) (*5) (*7) (*8)

49

IDD_XTAL Crystal oscillator circuit (*7)

0.3

0.4

*1 Power consumption is sum of current consumption of all power supply pins.

*2 Typical value is a center value under the condition of VDDIO = 3.3 V, 25 ˚C.

*3 Value in parentheses indicates the maximum (reference) value at normal temperature.

*4 The definition of each sleep state is shown in the following table.

State

Register

Retain

FIFO

RC Osc. circuit state

OFF

Low clock timer

-

Sleep mode 1

Retain RXFIFO only

Sleep mode 2

Retain

ON

*5 Indicates a current value under the following LSI conditions: FSK mode, 100 kbps, frequency 920 MHz, TCXO used,

LOW_RATE_EN([CLK_SET2:B0 0x03(0)]) = 0b1.

*6 Indicates a current value under following LSI conditions: Sigfox mode, frequency:920MHz, TCXO used.

*7 When using crystal oscillator, the operating current of crystal oscillator circuit is added to the power consumption except for the sleep and

deep sleep modes.

*8 It is the current of CW mode.

43/218

FEDL7456N-03

ML7456N

○DC Characteristics

Values are under the condition of the master clock frequency = 36 MHz (Typ.).

Item

Symbol

Condition

Min.

Standard

Max.

Unit

V

Voltage input high

VIH1

Digital input Pin

－

VDDIO x 0.75

VDDIO

Voltage input low

VIL1

VT+

Digital input pin

0

－

V

VDDIO x 0.18

Schmitt trigger

RESETN、SDI、SCLK、SCEN、

EXT_CLK、REGPDIN、GPIO1 pins

high-level decision

threshold value

Schmitt trigger

－

1.2

VDDIO x 0.75

RESETN、SDI、SCLK、SCEN、

EXT_CLK、REGPDIN、GPIO1pins

low-level

decision

VT-

0.8

－

V

VDDIO x 0.18

threshold value

IIH1

Digital input pin

-1

－

1

µA

Input leakage current

IIL1

IOZH

IOZL

VOH

VOL

Digital input pin

IOH=-4mA

－

µA

V

Tri-state

output

leakage

current

Voltage output high

Voltage output low

VDDIO x 0.78

0

VDDIO

0.3

IOL=4mA

V

REG_CORE pin

all states except SLEEP state

MAIN_REG

1.4

1.5

1.6

V

Regulator

output voltage

REG_CORE pin

Sleep state

SUB_REG

CIN

1.2

－

1.5

6

1.65

－

V

Input pin

pF

COUT

CRFIO

CAI

Output pin

9

－

Input capacitance

RF I/O pin

Analog input pin

9

－

9

－

44/218

FEDL7456N-03

ML7456N

○RF Characteristics

The measurement point is at antenna end specified in the recommended circuits.

[TX characteristics]

Values are under the condition of the master clock frequency = 36 MHz (Typ.).

920MHz Band

Standard

(*1)

Item

Condition

Min.

Max.

17

Unit

dBm

TX Power

Spurious emission level

20mW(13dBm) setting

13dBm, with LC trap circuit, 2^ndto 5^thHarmonics

9

-

13

-

-30

(*1) Typical value is a center value under the condition of VDDIO = 3.3 V, 25 ˚C.

45/218

FEDL7456N-03

ML7456N

[RX characteristics]

Values are under the condition of the master clock frequency = 36 MHz (Typ.).

920MHz Band

Item

Condition

Min.

Standard

Max.

Unit

－

-103

-94

100kbps mode

BER<1% GFSK, 50kHz

deviation

Ta= -30 to +75℃

Ta= 15 to 30℃

dBm

Sensitivity (min)

－

-103

37

-96

400kHz spacing, Ta=25℃, 100kbps mode

Adjacent channel interference (*1)

RX Blocking (*1)

20

－

dB

Undesired wave: CW

2MHz offset, Ta=25℃, 100kbps mode

10MHz offset, Ta=25℃, 100kbps mode

－

52

62

－

dB

Minimum energy detection level RFmin in RSSI characteristics diagram (*2)

－

-105

-96

dBm

(ED value)

100kbps, Channel filter band = 200kHz setting

Dynamic range in RSSI characteristics diagram

(*2)

energy detection range

Spurious emission

55

65

－

dB

－

-54

dBm

*1. The measurement conditions on the interference-related characteristics are as follows.

Using the desired input level as [Level achieving BER = 1 % (= reference sensitivity) + 3 dB], the level achieving BER =

1 % is searched by varying the undesired wave level and defined as U/D [dB] = (Undesired wave level) - (Level achieving

BER = 1 %).

*2. The following diagram shows the RSSI characteristics.

Measured

Calculated

ED

EDmax

EDmin

No Input

-100

Dynamic Range

-80

RFmin

-30

RF Input Level

RFmax

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○RC Oscillator Circuit Characteristics

ML7456N has 32 kHz clock generation function for timer. For details, please refer to “LSI state transition control/SLEEP

setting” section.

Item

Symbol

Condition

Min.

Standard

Max.

Unit

After trimming

RCOSC oscillation frequency

FRCOSC

27

38

kHz

32

RCOSC stable time

TRCOSC

－

100

ms

○SPI Interface Characteristics

Item

Symbol

Condition

Min.

0.032

45

Standard

Max.

16

Unit

MHz

%

SCLK clock frequency

SPI clock input duty ratio

SCEN input setup time

SCEN input hold time

SCLK high pulse width

SCLK low pulse width

SDI input setup time

SDI input hold time

FSCLK

DSCLK

2

50

55

-

TSCENSU

TSCENH

TSCLKH

TSCLKL

TSDISU

TSDIH

30

-

ns

-

30

ns

Load

capacitance

CL=20pF

-

31

ns

31

ns

5

ns

15

ns

SCEN negate period

SDO output delay time

TSCENNI

200

0

ns

-

TSDODLY

25

ns

[Note]

All timing measurement conditions are V_DDIO* 20 % level and V_DDIO* 80 % level.

SCEN

TSCENH

FSCLK

TSCENSU

TSCLKL

TSCLKH

SCLK

SDI

TSDISU

TSDIH

MSB IN

BITS6-1

LSB IN

TSDODLY

MSB OUT

LSB OUT

SDO

TSCENNI

SCEN

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○TX/RX Data Interface Characteristics

Item

DIO input setup time

DIO input hold time

DIO output hold time

Symbol

Condition

Min.

1

Standard

Max.

Unit

µs

-

TDISU

-

TDIH

0

ns

-

TDOH

20

ns

Negative

clock

frequency

deviation

Positive

clock

frequency

deviation

DCLK frequency accuracy (*1)

(TX)

FDCLK_TX

kHz

Load capacitance

CL=20pF

-

DCLK frequency accuracy (*2)

(RX)

FDCLK_RX

DDCLK_TX

-30

45

+30

55

%

DCLK output duty ratio

(TX)

DCLK output duty ratio

(RX)

DDCLK_RX

30

70

%

*1 If there is no decimal point generated in the TX data rate setting calculation (see [TX_RATE_H: B1 0x02]), the maximum and

minimum values of TX DCLK frequency become the master clock frequency deviation.

*2 Max.and min.of RX DCLK frequency indicates jitter amount of recovered clock from RX signal upon synchronization established.

[Note]

All timing measurement conditions are VDDIO * 20 % level and VDDIO * 80 % level.

FDCLK_TX/ FDCLK_RX

DCLK

TDISU

TDIH

DIO(Input)

VALID

TDOH

DIO(Output)

VALID

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○Clock Output Characteristics

ML7456N has clock output function. DMON_SET([MON_CTRL: B3 0x27(3-0)]) and [GPIO*_CTRL: B0 0x28-0x2A] are

used for control. Upon reset, clock is output through GPIO1 pin.

Item

Symbol

Condition

Load

Min.

Standard

3

Max.

Unit

Clock output frequency

FCLKOUT

0.0088

36(*2)

MHz

12MHz

33

47

-

67

53

%

capacitance

CL=20pF

Clock output duty ratio (*1)

DCLKOUT

Other than

above

50

*1 Duty cycle is High:Low = 1:2 , only when 8MHz is used. [CLK_OUT: B0 0x03].

*2 Indicates the frequency with the setting of LOW_RATE_EN([CLK_SET2: B3 0x01(0)] = 0b0.

[Note]

All timing measurement conditions are VDDIO * 20 % level and VDDIO * 80 % level.

FCLKOUT

GPIO*

○Reset Characteristics (Internal Pins)

Item

Symbol

Condition

Min.

0.5

Standard

Max.

Unit

ms

RESETN release delay time

(power on period)

All power pins

After Power On

TRDL1

-

RESETN pulse period

(start-up from VDDIO=0V)

TRPW1

0.5

-

ms

RESETN pulse period 2 (*1)

TRPW2

TRDL2

0.5

1

-

ms

µs

(start-up from VDDIO≠0V)

RESETN input delay time

After VDDIO>1.8V

[Note]

All timing measurement conditions are V_DDIO* 20 % level and V_DDIO* 80 % level.

1.8V

VDD Level

GND Level

VDDIO

Below 1.8V

TRDL2

TRPW1

TRPW2

TRDL1

RESETN

(*1) When starting from VDDIO ≠ 0 V, a pulse must be sent to RESETN after VDDIO exceeds 1.8 V.

(*2) RESETN is a internal pin. MCU (Software) need to control the above timing.

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○Deep Sleep Mode Characteristics

Item

Symbol

Condition

VDDIO=”H”

Min.

0

Standard

Max.

Unit

µs

REGPDIN rising edge delay time

TRPFD

-

REGPDIN assert time

TRPASS

TREFD

VDDIO=”H”

0.3

0.5

-

ms

RESETN input delay time

[Note]

All timing measurement conditions are VDDIO * 20 % level and VDDIO * 80 % level.

VDD Level

GND Level

VDDIO

TRPFD

TREFD

RESETN(*1)

REGPDIN(*1)

TRPASS

(*1) REGPDIN, RESETN is a internal pin in PKG. MCU (Software) need to control the above timing.

○Power-on Characteristics

Item

Symbol

Condition

Power on state

Min.

Standard

Max.

Unit

ms

Power-on time difference

TPWON

-

5

(all power pins)

[Note]

All timing measurement conditions are VDDIO * 20 % level and VDDIO * 80 % level.

TPWON

VDD Level

GND Level

80%

20%

VDD

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■Functional Description

■MCU

●CPU and Memory Space

ML62Q1532 has LAPIS Technology's original 16-bit CPU nX-U16/100 (A35 core), the multiplier/divider in the

coprocessor, flash memory in the program memory space, and RAM and data flash in the data memory space. In addition,

it has the built-in remap function that remaps a 4 Kbyte area in the program memory space.

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●Reset Function

ML7456N has a function to reset the CPU, peripheral circuits and other hardware due to the causes described in Table

3-1. This chapter describes the system reset mode, reset input pin reset and power-on reset (POR). See reference chapters

in Table 3-1 for other causes of resets. See Table 3-2 for the availability of resets for each cause.

Table 3-1 Reference for Details of Causes of Resets

Reference

Cause

(ML62Q1000 Series User’s Manual)

Reset input pin reset (pin reset)

This chapter

Power-On Reset (POR)

This chapter

Watchdog timer (WDT) overflow reset

Watchdog timer (WDT) invalid clear reset

Voltage Level Supervisor reset (VLS0 reset)

RAM parity error reset

Chapter 10 Watchdog Timer

Chapter 22 Voltage Level Supervisor

Chapter 29 Safety Function

Unused ROM area access reset

CPU reset by BRK instruction execution (when ELEVEL is 2 or higher)

"nX-U16/100 Core Instruction

Manual"

Individual reset to the peripheral circuits(Block reset)

Chapter 4 Power Management

One-time reset to the all peripheral circuits and port controller (SOFTR reset)

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○Features

Each reset can uniquely be managed depending on its cause as this function contains following features to identify the

cause in an early stage.

•

Reset status register (RSTAT) to indicate the cause of the reset

Reset status register (SRSTAT) to indicate the cause of the safety function reset

In addition, it has the INITE flag function to detect abnormal start-up of the LSI.

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○Configuration

Figure 3-1 shows the configuration of the reset generation circuit.

RESET_N

Reset signal to the CPU, peripheral

circuits, and other circuits

Power-on reset

WDT overflow reset

WDT invalid clear reset

BRK instruction reset

RAM parity error reset

Reset signal to the CPU

Unused ROM area

access reset

Reset signal to peripheral circuits

INITE flag

BRECON0 to 3

SOFTRCON

SRSTAT

RSTAT

Data bus

RSTAT

: Reset status register

SRSTAT

BRECON 0 to 3

SOFTRCON

: Safety function reset status register

: Block reset control register 0 to 3

: Software reset control register

Hardware(Other circuits): Power supply and oscillation circuits, start control part, etc.

Figure 3-1 Configuration of Reset Generation Circuit

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○List of Pins

Pin name

RESET_N

I/O

I

Function

Reset input pin

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●Power Management

ML62Q1532 has four power management modes to save the current consumption.

•

HALT mode

HALT-H mode

：Stop the CPU and peripherals continue to work.

：Stop the CPU, peripherals continue to work with low-speed clock only,

forcely stop high-speed clock and forcely start the high-speed clock after releasing the mode.

：Stop the CPU, peripheral circuits, low-speed clock and high-speed clock.

STOP mode

STOP-D mode

Internal logic voltage(REG_CORE_MCU) is minimized to lower the current consumption.

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○Features

•

Stop code acceptor qualifies for entering STOP mode and STOP-D mode

Data of RAM and SFR are retained even in the STOP-D mode

Clock supply is control-able peripheral by peripheral to reduce the current consumption, by block clock control

registers

•

Reset is control-able peripheral by peripheral by block reset control registers

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○Configuration

Figure 4-1 shows the transition diagram of the operating state.

The bit symbols in the figure are assigned to the standby control register (SBYCON).

Reset released

Power on

System reset

Mode

Program run

Mode

Reset

HLT=1

HLTH=1

Interrupt

STP=1

STPD=1

Interrupt

HALT Mode

HALT-H Mode

STOP Mode

STOP-D Mode

Figure 4-1 Operating State Transition Diagram

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●Interrupt

ML62Q1532 has the non-maskable interrupt, maskable interrupts and the software interrupt (SWI).

For details of each interrupt, see the corresponding Chapters.

See Chapter 29 "Safety Function" for the MCU status interrupt.

See "Table 1-4 Main Function List" for ML62Q1300 group, "Table 1-5 Main Function List" for

ML62Q1500/ML62Q1800 group and "Table 1-6 Main Function List" for ML62Q1700 group in the Chapter 1 to confirm

the presence/absence of function in each product.

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○Features

•

Master Interrupt Enable (MIE) flag enables or disables collectively the all maskable interrupts. For more details

about MIE, see "nX-U16/100 Core Instruction Manual".

•

Each maskable interrupt has the enable flag in the register IE0 to IE7.

The occurrence of interrupt request is confirmable by checking the request flag in IRQ registers.

The occurrence of interrupt is maskable by setting each request flag by the software in IRQ registers.

Four interrupt levels are available for each maskable interrupt.

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●Clock Generation Circuit

The clock generation circuit generates following kinds of clock and supplied them to the CPU or the peripheral circuits.

Table 6-1 Clocks generated by the clock generation circuit

Clock Name

Low-speed clock

Simplified RTC clock

High-speed clock

Symbol

LSCLK

RTCCLK

HSCLK

Description

Low speed clock for peripherals (32.768kHz)

Low speed clock for the simplified RTC (32.768kHz)

High speed clock for peripherals (Max. 24MHz)

CPU operating clock (32.768kHz or Max. 24MHz):

The maximum frequency depends on the CPU operation mode(See

Table 6-2)

CPUCLK

CPU clock

SYSTEMCLK

System control clock:

System clock

The frequency is the same as CPU clock.

Low speed output from a general port (32.768kHz)

High speed output from a general port (Max. 12MHz)

Clock for the watch dog timer (Approx 1kHz)

Low-speed output clock

High-speed output clock

WDT clock

OUTLSCLK

OUTHSCLK

WDTCLK

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○Features

•

Low-speed clock generation circuit

–

Low-speed RC oscillation circuit

Adjustable to ±1% by using the frequency adjustment function (V_{DDIO_MCU}≥ 2.6V)

A crystal resonator is connectable*¹

In case the low-speed crystal oscillation stopped, the clock is automatically switched to the low-speed RC

oscillation (clock backup function).*¹

–

A low-speed external clock is available to input to XT1 pin*¹

The crystal oscillation clock and the low-speed external clock each is continuously supplied during the reset

input pin reset.*¹

•

Simplified RTC clock

Operating by the low-speed clock

High-speed oscillation circuit

–

PLL oscillation mode (16 MHz or 24 MHz is choosable for the PLL reference frequency by the code option)

High-speed clock wake-up time is choosable

•

WDT clock

–

RC1K oscillation circuit

The RC1K clock or the 1.024 kHz divided from the LSCLK is choosable by the code option.

Table 6-2 shows relation of CPU operation mode and PLL oscillation reference frequency.

The CPU operation mode and the PLL oscillation reference frequency are choosable by the code option. See Chapter

26 "Code Option" for more details.

Table 6-2 CPU operation mode and PLL oscillation reference frequency

Maximum operating frequency

PLL oscillation

SYSTEMCLK

reference frequency

HSCLK

Wait mode

No wait mode

24MHz

16MHz

24MHz

6MHz

24MHz

16MHz

8MHz

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○Configuration

Figure 6-1 shows the configuration of the clock generation circuit.

Table 6-3 shows the list of operation clocks for each function.

Code option

Approx.1kHz

RC1K

oscillation

Low-speed

crystal

Approx.1.024kHz

WDTCLK

Divider

Low-speed

oscillation

circuit

oscillation/

External clock

1

*

CBUINT*¹

RTCCLK*¹

XT0 *¹

XT1 *¹

Approx.32.768kHz

LSCLK

LS RC

OUTLSCLK

SYSTEMCLK

CPUCLK

High-speed

oscillation

circuit

Divider

1/1 - 1/32

Divider

1/1 - 1/32

OUTHSCLK

HSCLK

Code option

16M/24MHz

FHWUPT

LRCADJ

FHCKMOD

FCON

Data bus

FHCKMOD : High-speed clock mode register

FCON

: Frequency control register

FHWUPT

LRCADJ

CBUINT*

: High-speed clock wake-up time setting register

: Low-speed RC oscillation frequency adjustment register

: Clock backup interrupt register

^*1：Available except for ML62Q1300 group

Figure 6-1Configuration of Clock Generation Circuit

[Note]

After the power-on or the system reset, LSCLK (32.768 kHz) is initially chosen as SYSTEMCLK.



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Table 6-3 Operating clock list in each function

System clock

or

Low-spee

d clock

LSCLK

Simplified RTC

clock

High speed

clock

WDT clock

WDTCLK

CPU clock

SYSTEMCLK/

CPUCLK

Function

RTCCLK

HSCLK

CPU

RAM

●

－

●

－

Watchdog timer

－

External interrupt control

Low speed time base counter

16-bit timer

●*¹

●

●*¹

－

●

Functional timer

Serial communication unit

I²C bus unit

●

I²C bus master

－

●

Buzzer

●

－

SA type A/D converter

D/A converter

●

－

●*¹

－

●*¹

Analog comparator

Voltage Level

Supervisor(VLS）

●*¹

－

●*¹

－

Simplified RTC

●

－

●

－

●

－

DMA controller

CRC calculator

Flash (BGO operation)

●: The clock is supplied -: The clock is Not supplied

*¹: The clock is supplied for start control or sampling

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○List of Pins

The output pins of the high-speed/low-speed clocks are assigned to the shared function of general purpose ports.

For details of pin assignment and the shared function of general purpose ports, see the list of pins.

Pin Name

OUTLSCLK

OUTHSCLK

XT0

I/O

O

Function

Low-speed clock output

High-speed clock output

O

Low-speed crystal resonator connect pin

I

Low-speed crystal resonator connect pin / Low-speed external clock input pin

XT1

O/I

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●Low Speed Time Base Counter

The low speed time base counter enables following functions.

•

Generate periodical interrupt requests

Output periodical pulse signals to the general ports

Adjust the frequency of simplified RTC clock

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○Features

•

Generate eight frequency (128Hz, 64Hz, 32Hz, 16Hz, 8Hz, 4Hz, 2Hz and 1Hz) of pulse signals by dividing the

low-speed clock (LSCLK)

•

Three interrupt requests can be chosen among eight periodical interrupt requests

The 1Hz or 2Hz signal can be output from general ports

An interrupt request (LTB0INT) can be used for a trigger event source of the Successive Approximation type A-D

Converter.

•

The clock frequency adjust function

- Allows to adjust in a range approx.-488ppm to +488ppm with the resolution approx.0.119ppm.

- Two confirmation methods with the low-speed clock or high-speed clock.

The 1Hz or 2Hz signal is used for the simplified RTC clock

•

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○Configuration

Figure 7-2 shows the configuration of the low speed time base counter on ML7456N.

(LCD; Frequency correction confirmation

test mode）

T128HZ

T64HZ

T32HZ

T16HZ

T8HZ

LTB2INT

LTB1INT

T4HZ

T2HZ

T1HZ

LTB0INT

(SA-ADC)

(Buzzer)

LSCLK

(Clock generation Circuit)

Counter

TBCOUT0

(General port)

Internal rest signal

(Reset function)

LTCO

TFRQ

HSCLK

Virtual

frequency

adjustment

(Clock generation Circuital)

RTCCLK

(Clock generation Circuit)

Clock generation

for simplified RTC

T4HZR

T2HZR

T1HZR

(Simplified RTC,

LCD)

Power-on reset

(Reset function)

LTBADJ

TBCOUT1

(General port)

LTCO

Data bus

LTBADJ

：

Low speed time base counter frequency adjustment register

Time base counter output signals

T1HZ to T128HZ

LTB2INT

Low speed time base counter 2 interrupt request

Low speed time base counter 1 interrupt request

Low speed time base counter 0 interrupt request

Simplified RTC time base counter output signals

LTB1INT

LTB0INT

T1HZR to T4HZR

Figure 7-2 Configuration of Low Speed Time Base Counter

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○List of Pins

The output pins of the low speed time base counter are assigned to the shared function of genral purpose ports.

Signal name

TBCOUT0

TBCOUT1

I/O

O

Function

The virtual frequency adjustment output signal or the low speed time base counter

output signal

O

Hz/2Hz clock for the Simplified RTC

Table 7-1 shows the list of the general purpose ports and the register setting.

Table 7-1 Low speed time base counter function port and the register setting

Setting

Register

Pin Name

Shared Port

Setting Value

P01 6^thfunction P0MOD1 0101_XXXX^*1

P17 6^thfunction P1MOD7 0101_XXXX^*1

P01 7^thfunction P0MOD1 0110_XXXX^*1

P20 6^thfunction P2MOD0 0101_XXXX^*1

TBCOUT0

TBCOUT1

*1: XXXX determines the port output condition

XXXX

0010

1010

1111

Port output condition

CMOS output

Nch open drain (without pull-up)

Nch open drain (with pull-up)

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●16-Bit Timer

The 16-bit timer enables following functions.

•

Generate periodical interrupts in an arbitrary period

Generate one shot interrupts in an arbitrary period

Output pulse signals with an arbitrary frequency to the general ports

Output one shot pulse signals to the general ports

Count up the rising edges of the external input signal

ML62Q1532 equips 6 channels (n=0 to 6)16-bit timers.

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○Features

•

Two timer modes and two operation modes are available

Timer mode

Operation mode

Repeat mode

One shot mode

Repeat mode

One shot mode

Description

Count-able to the max. 0xffff

Repeat the specified operation until stop by the

software.

Count-able to the max. 0xffff

Run the specified operation once and stop it.

Count-able to the max. 0xff

Repeat the specified operation until stop by the

software.

Count-able to the max. 0xff

Run the specified operation once and stop it.

16-bit timer mode

8-bit timer mode

•

One channel of 16-bit timer is configurable as two channels of 8-bit timer

LSCLK or HSCLK can be chosen for the timer clock

A timer clock, a divided time clock or an external input can be chosen for the count clock.

A timer interrupt request is generated when the value of the timer counter register value coincides with that of the

16-bit timer n data register

•

A port output is reversed when the value of the timer counter register value coincides with that of the 16-bit timer n

data register

The initial value of the port can be chosen by a register.

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○Configuration

Figure 8-1 shows configuration of the 16-bit timer and Figure 8-2 shows configuration of the 8-bit timer

SYSTEMCLK

LSCLK

HSCLK

Timer clock

Interrupt

control

TMnINT

THnCS

Timer control

TMHnMOD

TMHnTRG

TMHnOUT

TMHSTR/TMHSTP

TMHSTAT

Count clock

Port output

control

Division

Circuit

THnDIV2-0

THnEX

TMHnD

Compare

TMHnC

Rising edge

detection

TMHnTRG

External

interrupt

function

EXTRG0

EXTRG1

THnEXS

Figure 8-1 Configuration of the timer in 16-bit timer mode

SYSTEMCLK

LSCLK

Timer clock

Interrupt

HSCLK

control

TMHnIS

TMHnIC

TMnINT

THnCS

Timer control

TMHnMOD

TMHSTR/TMHSTP

TMHSTAT

Count clock

Division

Circuit

TMHnOUT

Port output

control

THnDIV2-0

THnEX

Rising edge

detection

TMHnDH

TMHnDL

Compare

TMHnCL

Compare

External

interrupt

function

EXTRG0

EXTRG1

TMHnCH

THnEXS

Figure 8-2 Configuration of the timer in 8-bit timer mode

: 16-bit timer n interrupt request TMHnTRG : 16-bit timer n trigger

TMnINT

EXTRG0

EXTRG1

: EXI0 pin input (come through the noise filter of the external interrupt function)

: EXI1 pin input (come through the noise filter of the external interrupt function)

TMHnD

: 16-bit timer n data register

TMHnC

: 16-bit timer n counter register

TMHnDH

TMHnDL

: 16-bit timer n data register upper 8 bit

: 16-bit timer n data register lower 8 bit

TMHnCH

TMHnCL

: 16-bit timer n counter register upper 8 bit

: 16-bit timer n counter register lower 8 bit

[Note]



When the 16-bit timer is used as two channels of 8-bit timer, the same clock settings and interrupts are

applied.

In the 8-bit timer mode, the TMHnOUT outputs the comparison result of the upper side ("TMHnDH" and

"TMHnCH").

Choose the 16-bit timer mode when using the 16-bit timer DMA request or SA-ADC trigger.

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○List of Pin

The I/O pins of the 16-bit timer are assigned to the shared function of the general ports.

Pin name

EXTRG0

EXTRG1

I/O

Description

I

External trigger input 0

External trigger input 1

16-bit timer channel n output

TMHnOUT

O

When used in an 8-bit timer, only the upper 8-bit timer can output the signal.

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●Functional Timer

The Functional timer enables following functions in four operation modes (TIMER/CAPTURE/PWM1/PWM2).

ML62Q1532 equips 6 channels (n=0 to 5) Functional Timers.

TIMER mode:

In this mode, the Functional Timer generates pulse signals, levels of which are reversed in sync with the counter start and

the counter overflow. Also, it generates the interrupt when the counter overflows.

Counter Overflow

Cycle

Counter Start

Counter

Positive phase

Negative phase

Interrupt

CAPTURE mode:

In this mode, the Functional Timer stores the value of counter into FTnEA register at the rising edge of a trigger event,

into FTnEB register at the falling edge of a trigger event.

Counter Clear

y

z

b

a

Counter

Trigger Event

Counter Start & Stop

FTnEA

Start

Stop

Start

Stop

z

b

a

y

FTnEB

(n=0 to 7)

PWM1 mode:

In this mode, the Functional Timer generates two types of PWM waveform that have the same cycle and the start

timing.

The setting value of FTnEA register makes the duty of the positive phase output and the setting value of FTnEB

register makes the duty of the negative phase output.

Cycle

Duty (FTnEA)

Duty (FTnEB)

Counter

Positive phase

Negative phase

PWM2 mode:

In this mode, the Functional Timer generates the complimentary PWM waveform of which the positive phase output

and the negative phase output works exclusively. The setting of FTnEA register makes the duty of the positive phase

output. Also, a dead time can be configured by setting FTnDT register.

Cycle

Duty (FTnEA）

Counter

Dead time

Positive phase

Negative phase

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○Features

•

The Timer/Capture/PWM functions using the 16-bit counter

The count clock can apply the LSCLK/HSCLK divided by 1 to 128 and the external clock input

The timer output signal can be switched (Positive logic or Negative logic)

Generate a cyclic interrupt, a duty interrupt and a coincident interrupt with the setting value

One-shot mode

Start/stop/clear the timer by an external trigger input or a timer interrupt request(event triggers)

Emergency stop and emergency stop interrupt by an external trigger input

Two types of PWM output with the same cycle and different duties, and complementary PWM output with the dead

time

•

Input signal duty/cycle measurement by the capture function

Chosen interrupt source can be notified

DMA request signal can be used

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○Configuration

Figure 9-1 shows the configuration of the FTM circuit.

EXTRG0 or EXTRG4 can

be chosen

Emergency

stop control

FTMnTRG

(FTM)

FTMnTRG

(FTM)

TMH0TRG toTMH7TRG

(16bit timer)

Functional Timer n

DMA request (DMAC)

Trigger

Control

FTMnINT (Interrupt)

Noise

Filter

CMP0TRG

(Analog comparator)

Compar

ator

EXTRG0 to EXTRG7

(External Interrupt)

FTM0P

(General port)

FTnC

count clock

FTMnP pin

FTMnN pin

Division

Circuit

Output

Control

LSCLK

HSCLK

(Clock generation circuit)

FTnEA

FTnEB

FTnD

Division

Circuit

FTnMOD

FTnP

timer clock

8/16

Data bus

FTnEA

FTnEB

FTnDT

FTnP

FTnC

FTnMOD

: FTMn event A register

: FTMn event B register

: FTMn dead time register

: FTMn cycle register

: FTMn counter register

: FTMn mode register

FTMnTRG

: Functional Timer n trigger

EXTRG0 to EXTRG 7

CMP0TRG

: External trigger n / external clock

: Analog comparator 0 trigger

TMH0TRG to TMH7TRG : 16-bit Timer n trigger

(n=0 to 7)

Figure 9-1 Configuration of the Functional Timer

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○List of Pins

The I/O pins of the Functional timer are assigned to the shared function of the general ports.

Pin name

EXTRG0 to

EXTRG7

FTMnP

I/O

I

Description

External trigger 0 to 7 / External clock 0 to 7

O

Functional timer channel n output P

Functional timer channel n output N

FTMnN

（n=0 to 7）

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●Watchdog Timer

The watchdog timer (WDT) is equipped with the following functions and can detect the runaway state of program or the

undefined state of the CPU by generating an interrupt or reset when an abnormality occurs.

•

If the counter is not cleared for more than a certain time period in program operation and overflows, the WDT

interrupt is generated in the first overflow and the WDT reset in the second overflow (if the window function is

disabled).

•

If the counter is not cleared for more than a certain time period in program operation and overflow occurs, the WDT

reset is generated in the first overflow (if the window function is enabled).

If the counter is cleared in the unexpected time period, the WDT invalid clear reset is generated (if the window

function is enabled).

The window function refers to the function through which "the time period during which WDT counter clear is enabled"

= "the time period during which the window is opened" and

"the time period in which WDT counter clear is disabled" = "the time period in which the window is closed" can be set.

Count Clear Control

Mode Control

Overflow

(Interrupt/Reset)，

Invalid Clear Reset

Program operation

(clear processing)

Watchdog Timer

Counter

Interrupt, Reset

CPU Clock

Clear

CPU

WDT Clock

(WDTCLK)

WDT Counter Value

Overflow

Frequency

(T_WOV

)

Time

0

WDT Clear

WDT Reset

generated

WDT Interrupt

generated

(Second overflow)

(First overflow)

Figure10-1 Watchdog Timer Overview (With the Window Function Disabled)

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○Features

•

Eight types of overflow periods can be chosen (7.8 ms, 15.6 ms, 31.3 ms, 62.5 ms, 125 ms, 500 ms, 2 s, or 8 s)

Two types of use are available:

・Window function disabled mode

The WDT counter can always be cleared. The WDT interrupt is generated when the first counter overflow occurs,

and the WDT reset is generated when the second counter overflow occurs.

・Window function enabled mode

The periods during which WDT counter clear is enabled and disabled respectively can be set. The WDT reset is

generated when the first counter overflow occurs, and the WDT invalid clear reset is generated when the counter

is cleared in the period during which WDT counter clear is disabled.

Table 10-1 Watchdog Timer Operation Modes

Overflow

Mode

WDT invalid clear reset

First

Second

Window function disabled

mode

Window function disabled

mode

Interrupt

Reset

Window function enabled

mode

Window function enabled

mode

Reset

-

•

The following items can be chosen by the code option. See the Chapter 26 "Code Option" for details of the code

option.

・Enabling/disabling the WDT timer operation

・Operation clock of the WDT counter (32 dividing of low-speed clock LSCLK, WDTCLK RC1K oscillation)

[Note]



WDT is the function used to monitor the CPU runaway. Its function as an ordinary timer is not

guaranteed.

The watchdog timer is undetectable to all the abnormal operations. Even if the CPU loses control, the

watchdog timer is undetectable to the abnormality in the operation state in which the WDT counter is

cleared. It is recommended that the WDT counter is cleared at one place in the main loop of the program

as a fail-safe.



WDT can be operated based on the clock independent of the system clock by using RC1K oscillation for

the WDTCLK, resulting in further improvement of safety. However, it is recommended to choose LSCLK

if high accuracy of the frequency is required, since the RC1K oscillation is less accurate than the

LSCLK.

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○Configuration

The following diagram shows the configuration of the watchdog timer.

Clock Generation Circuit

WDTNMCK (Code Option)

RC1K

WDT Overflow

WDTCLK

1/32

LSCLK

WDT Counter

WDT Interrupt (WDTINT)

(Interrupt)

(32 dividing)

Reset

Interrupt

Control

WDTClear

Control

WDTMD

(Code Option)

WDT Overflow Reset

WDT Invalid Clear Reset

(Reset function)

STOP/STOP-D

Mode Control

Clear Period

Control

Data Bus

WDTMOD

WDTCON

WDTSTA

WDTMC

WDTCON

WDTMOD

WDTMC

: Watchdog timer control register

: Watchdog timer mode register

: Watchdog timer counter register

: Watchdog timer status register

WDTSTA

Figure 10-2 Configuration of Watchdog Timer

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●Serial Communication Unit

ML62Q1532 has two types of the serial communication function.

 8-bit/16-bit synchronous serial port (SSIO)

 Asynchronous serial interface UART (Universal Asynchronous Receiver Transmitter)

ML62Q1532 equips 2 channels Serial Communication Units.

○Features

Two serial communication modes are available. Table 11-2 shows features of the serial communication.

Table 11-2 Features of the Serial Communication

Serial Communication mode

Operation mode

Features

・ Max. 2ch (Both SSIO and UART are unavailable to use in

the same channel)

・ Master mode / Slave mode

・ MSB first / LSB first

・ 8bit / 16bit data length

・8-bit mode

・16-bit mode

Synchronous Serial I/O Port

(SSIO)

・ Self-test function using the master and slave modes.

For the self-test functions, see "Safety Function."

・ 5-bit/6-bit/7-bit/8-bit data length

・ Odd parity/even parity/0 parity/1 parity/and no parity

・ One stop bit/Two stop bits

・ Positive logic/negative logic for communication logic

・ MSB first / LSB first

・ Wide range of communication speed

・Half-duplex

communication

mode

・Full-duplex

communication

mode

- 1bps to 4,800bps (Clock frequency is 32.768kHz)

- 600bps to 3Mbps (Clock frequency is 24MHz)

- 300bps to 2Mbps(Clock frequency is 16MHz)

・ Built-in baud rate generator for each channel

・ Parity error flag, overrun error flag, framing error flag,

transmission buffer status flag, reception buffer status flag

・ Self-test function using transmission and reception

For the self-test functions, see "Safety Function."

UART mode

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○Configuration

Figure 11-1 shows configuration of the serial communication unit.

SUn_SCLK

SUn_RXD0/1

SUn_SIN

Shift register

8/16bits (SSIO)

5/6/7/8bits (UART)

SUn_TXD0/1

SUn_SOUT

Clock

Dividing

Circuit

SUn_SCLK

Baud rate

generator

LSCLK

HSCLK

Receive register

SUnRC

Transmit register

SUnTR

SIUn0INT

UAn0BRT, UAn1BRT

UAn0MOD, UAn1MOD

SIOnMOD

(For SSIO,UART)

SIUn1INT

Controller for

Communication mode

(SSIO/UART)

Data format

Communication operation

(For UART)

SIUnSIO_TXREQ

SIUnSIO_RXREQ

SUnCON

SUnMOD

SIUnUART_TXREQ

SUnDLYL

SIUnUART_RXREQ

(For DMA request)

UAn0STAT,

UAn1STAT

SDnBUF

SIOnSTAT

n=0 to 1

Data bus

Figure 11-1 Configuration of the Serial Communication Unit

SDnBUF

SUnMOD

: Serial communication unit n transmission/reception buffer

: Serial communication unit n mode register

SUnCON

: Serial communication unit n control register

SUnDLYL

SIOnMOD

: Serial communication unit n transmission interval setting register

: Synchronous serial port n mode register

SIOnSTAT

: Synchronous serial port n status register

UAn0MOD, UAn1MOD

UAn0BRT, UAn1BRT

UAn0STAT, UAn1STAT

SIUn0INT

: UARTn0 mode register, UARTn1 mode register

: UARTn0 baud rate register, UARTn1 baud rate register

: UARTn0 status register, UARTn1 status register

: Serial communication unit n0 Interrupt

SIUn1INT

: Serial communication unit n1 Interrupt

SIUnSIO_TXREQ

SIUnSIO_RXREQ

SIUnUART_TXREQ

SIUnUART_RXREQ

: Serial communication unit n SSIO transmission DMA request

: Serial communication unit n SSIO reception DMA request

: Serial communication unit n UART transmission DMA request

: Serial communication unit n UART reception DMA request

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○List of Pins

The I/O pins of the serial communication unit are assigned to the shared function of the general ports.

Pin name

SUn_RXD0

SUn_RXD1

SUn_TXD0

SUn_TXD1

SUn_SCLK

SUn_SOUT

SUn_SIN

I/O

I

Description

Full-duplex data input UART0 data input of serial communication unit n

UART1 data input of serial communication unit n

I

O

I/O

O

I

UART0 data output of serial communication unit n

Full-duplex data output UART1 data output of serial communication unit n

SSIO synchronous clock input/output of serial communication unit n

SSIO transmission data output of serial communication unit n

SSIO reception data input of serial communication unit n

(n=0 to 1)

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Table 11-3 (1) and (2) show the list of the general ports used for the serial communication unit and the register settings of

the ports.

Table 11-3(1) Ports used for the serial communication unit and the register settings (UART)

Setting

register

Pin name

Shared port

Setting value

SU0_TXD0

SU0_RXD0

P03

2^ndFunc.

P0MOD3

P0MOD2

P0MOD7

P1MOD7

P0MOD3

P2MOD0

P0MOD7

P1MOD7

P2MOD2

P2MOD1

P2MOD2

0001_XXXX^*2

0001_XXXX^*1

0010_XXXX^*1

0010_XXXX^*2

0001_XXXX^*2

0001_XXXX^*1

0001_XXXX^*2

0001_XXXX^*1

0010_XXXX^*2

P02

P07

P17

P03

P20

P07

P17

P22

P21

P22

3^rdFunc.

0

3^rdFunc.

SU0_TXD1

SU0_RXD1

2^ndFunc.

SU1_TXD0

SU1_RXD0

SU1_TXD1

1

3^rdFunc.

*1: “XXXX” determines the condition of the port input

XXXX

0001

0101

Condition of the port input

Input (without Pull-UP)

Input (with Pull-UP)

*2: “XXXX” determines the condition of the port input

XXXX

0010

1010

1111

Condition of the port output

CMOS output

Nch open drain output (without Pull-UP)

Nch open drain output (with Pull-UP)

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Table 11-3(2) Ports used in the serial communication unit and the register settings (SSIO)

Setting

register

Pin name

Shared port

Setting value

SU0_SIN

P02 2^ndFunc.

P0MOD2

P0MOD4

P0MOD3

P2MOD1

P2MOD3

P2MOD2

0001_XXXX^*1

0001_XXXX^*3

0001_XXXX^*2

0001_XXXX^*1

0001_XXXX^*3

0001_XXXX^*2

0

1

SU0_SCLK P04 2^ndFunc.

SU0_SOUT P03 2^ndFunc.

SU1_SIN

P21 2^ndFunc.

SU1_SCLK P23 2^ndFunc.

SU1_SOUT P22 2^ndFunc.

*1: “XXXX” determines the condition of the port input

XXXX

0001

0101

Condition of the port

Input (without Pull-UP)

Input (with Pull-UP)

*2: “XXXX” determines the condition of the port output

XXXX

0010

1010

1111

Condition of the port

CMOS output

Nch open drain output (without Pull-UP)

Nch open drain output (with Pull-UP)

*3: “XXXX” determines the condition of the port input/output

XXXX

0010

0001

Condition of the port

CMOS output (SSIO master mode)

Input (SSIO slave mode)

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○Combination of SSIO port

SUn_SIN, SUn_SOUT and SUn_SCLK are assigned to multiple general ports.

Be sure to use the ports in following combinations.

Port

SUn_SIN*

SUn_SOUT*

SUn_SCLK*

1

2

0

1

P02

P21

P03

P22

P04

P23

^*：n= Channel Number.

○Combination of UART port

The pin assignment depends on the communication mode. See Table 11-4 in section 11.2.1 of [ML62Q1000 Series

User’s Manual] for details of the pin assignment.

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●I²C Bus Unit

ML62Q1532 has one channel of I²C bus unit that supports both master and slave function.

Either of master or slave can be chosen to use and both functions of master and slave are unworkable at the same time.

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○Features

Table 12-2 shows the features of I²C bus unit.

Table 12-2 Features of I²C bus unit

Function

Operation mode

Master function

Features

・ Communication speed: Standard mode (100 kbps), fast mode

(400 kbps), and original standard 1 Mbps mode (1Mbps)

・ Support clock stretch function for the Slave

・ 7-bit address format (only the master function supports 10-bit

address format)

・ Self-test function by reading transmitted data onto the I²C bus

(Safety function)

I²C bus unit

・ Communication speed: Standard mode (100 kbps), fast mode

(400 kbps), and original standard 1 Mbps mode (1Mbps)

・ Clock stretch function

Slave function

・ 7-bit address format

・ Wake-up from STOP mode by matching slave address

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○Configuration

Figure 12-1 shows the configuration diagram of the I²C bus unit circuit.

Master

I2UM0RD, I2UM0STR

SCL

I2CU0_SCL pin

I2CU0_SDA pin

SDA

Controller

Clock

Generation

Circuit

HSCLK

LSCLK

Shift register

I²C

Controller

I2CU0INT

I2UM0SA I2UM0TD

I2UM0CON

I2U0MSS

Data bus

Slave

I2US0RD, I2US0STR

SCL

SDA

Controller

Shift register

I²C

Controller

Comparator

I2US0SA I2US0TD

I2US0CON

I2US0MD

Data bus

Figure 12-1 Configuration of I²C Bus Unit

Serial Clock

I2CU0_SCL:

I2CU0_SDA:

I2U0MSS:

Serial Data

I²C bus unit n mode register

I2UM0RD：

I2UM0SA：

I2UM0TD：

I2UM0CON：

I2UM0STR：

I²C bus 0 receive register (master)

I²C bus 0 slave address register (master)

I²C bus 0 transmit data register (master)

I²C bus 0 control register (master)

I²C bus 0 status register (master)

I²C bus 0 receive register (slave)

I2US0RD

：

I2US0SA：

I2US0TD：

I2US0CON：

I2US0MD：

I2US0STR：

I²C bus 0 slave address register (slave)

I²C bus 0 transmit data register (slave)

I²C bus 0 control register (slave)

I²C bus 0 mode register (slave)

I²C bus 0 status register (slave)

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○List of Pins

The I/O pins of the I²C bus unit are assigned to the shared function of the general ports.

Pin name

I2CU0_SDA

I2CU0_SCL

I/O

Description

I²C bus unit 0 data I/O pin

I²C bus unit 0 clock I/O pin

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○Pin Setting

I2CU0_SDA pin and I2CU0_SCL pin are assigned to multiple general ports.

Be sure to use the ports in following combinations.

Pin name

I2CU0_SDA

I2CU0_SCL

Combination 1

P03

P04

In addition to the mode setting of the shared function, choose "Enable Input, Enable Output, Nch open drain output and

without pull-up" by setting following data to the port n mode register m (PnMODm).

Table 12-3 I²C bus unit general port combinations

PnMODm

P03

P0MOD3

1

0x3B

[Note]



Use external pull-up resistors for SDA pin and SCL pin referring to the I²C bus specification. The internal

pull-up resistors unsatisfy the I²C bus specification. See the data sheet for each product for the value of

internal pull-up resistors.



If powering off this LSI in the slave mode, it disables communications of other devices on the I²C bus.

Keep this LSI powered on when it works as a slave mode until the master device is powered off.

When using the master function, do not connect multiple master devices on the I²C bus.

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●I²C Bus Master

ML62Q1532 has two channels of I²C bus master that support only the master function on the I²C bus specification.

This unit has the function of the I²C bus unit, described in Chapter 12, not containing the slave function and the low-speed

clock (LSCLK) operation.

○Features

Table 13-2 shows the features of I²C bus master.

Table 13-2 Features of I2C bus master

Function

Operation mode

Features

・ Communication speed: Standard mode (100 kbps), fast

mode (400 kbps), and original standard 1 Mbps mode

(1Mbps)

・ Support clock stretch function for the Slave

・ 7-bit address format (only the master function supports

10-bit address format)

I²C bus master

Master mode

・ Self-test function by reading transmitted data onto the I2C

bus (Safety function)

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○Configuration

Figure 13-1 shows the configuration diagram of the I²C bus master circuit.

I2CMn_SCL pin

I2MnRD，I2MnSTAT

SCL

SDA

Controller

Clock

Generation

Circuit

I2CMn_SDA pin

I2CMnINT

Shift register

HSCLK

I²C

Controller

I2MnCON

I2MnMOD

I2MnSA

I2MnTD

Data bus

n=0,1

Figure 13-1 Configuration of I²C Bus Master

Serial Clock

I2CMn_SCL:

I2CMn_SDA:

I2MnRD:

I2MnSA:

I2MnTD:

I2MnCON:

I2MnMOD:

I2MnSTAT:

Serial Data

I²C master n receive register

I²C master n slave address register

I²C master n transmit data register

I²C master n control register

I²C master n mode register

I²C master n status register

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○List of Pins

The I/O pins of the I²C bus master are assigned to the shared function of the general ports.

Pin name

I2CMn_SDA

I2CMn_SCL

I/O

Function

I²C bus master n data I/O pin

I²C bus master n clock I/O pin

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○Pin Setting

I2CMn_SDA pin and I2CMn_SCL pin are assigned to multiple general ports.

Be sure to use the ports in following combinations.

Pin name

I2CM0_SDA

I2CM0_SCL

Combination 1

P06

Combination 2

P22

P07

P23

In addition to the mode setting of the shared function, choose "Enable Input, Enable Output, Nch open drain output and

without pull-up" by setting following data to the port n mode register m (PnMODm).

Table 13-3 I²C bus master general port combinations

PnMODm

P06

P07

P22

P23

P0MOD6

P0MOD7

P2MOD2

P2MOD3

1

2

0x3B

[Note]



Use external pull-up resistors for SDA pin and SCL pin referring to the I²C bus specification. The internal

pull-up resistors unsatisfy the I²C bus specification. See the data sheet for each product for the value of

internal pull-up resistors.

Do not connect multiple master devices on the I²C bus.

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●DMA Controller

ML62Q1532 has two channels of the Direct Memory Access Controller (DMAC), which enables to transfer data between

SFR of peripheral circuits and the built-in RAM without the CPU operation.

Table 14-1 in the section 14.3.6 "DMA Transfer Target Block" of “ML62Q1000 Series User’s Manual” shows available

peripheral blocks to use as the DMA transfer source or destination.

Data transfer control,

Bus control, Trigger control and

Interrupt control

Settings

CPU

DMAC

Data bus

Serial

Communication

Unit

RAM

16-bit Timer

Other SFRs

SFR (Special Function Register)

Figure 14-1 DMA Controller Overview

[Note]

Do not use the DMA controller and the Coprocessor (Hardware multiplier/divider) simultaneously.

•

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○Features

•

Transfer unit

Transfer count

Transfer cycle

: 8bit/16bit

: 1 to 1024 time

: 2 cycle (CPU operation has priority if the access is competed)

Transfer address : Fixed address / Increment address / Decrement address

Transfer target : SFR/RAM → SFR/RAM (Transfer from/to Flash is not supported)

Transfer request : Serial communication DMA request, SA-ADC DMA request, 16bit timer DMA request,

Functional timer DMA request, External DMA request and the software DMA request

Transfer priority : Channel 0 > Channel 1 (Channel 0 has higher priority)

•

Interrupt

: The DMA Controller interrupt occurs when the all transfers are completed.

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○Configuration

Figure 14-2 shows the configuration of the DMA Control circuit.

A/D converter DMA request

Serial communication unit

DMA request

16bit timer DMA request

Functional timer DMA request

External DMA request

Channel priority control

Interrupt control

DMACINT

DMA transfer/bus control

Count decrement

DCnSTRG

signal

Address

increment signal

DMA transfer

enable DCEN

Transfer source/

destination address control

DCnSA, DCnDA

Transfer

count

DCnTN

Transfer mode

DCnMOD

Read

Data

Data bus

DCnMOD

DCnTN

: DMA channel n transfer mode register

: DMA channel n transfer count register

DCnSA

DCnDA

DCEN

: DMA channel n transfer source address register

: DMA channel n transfer destination address register

: DMA transfer enable register

DCnSTRG

: DMA channel n software request

(n = 0,1)

Figure 14-2 Configuration of DMA Controller Circuit

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●Buzzer

The buzzer circuit generates a base signal in combination of 8 frequencies and 15 duties and outputs the signal in four

modes.

Intermittent sound 1 mode:

Arbitrary period

Buzzer output waveform

BZ0P, BZ0N pin

Beep Beep Beep Beep Beep Beep Beep Beep Beep Beep

Arbitrary period

Intermittent sound 2 mode:

Buzzer output waveform

BZ0P, BZ0N pin

Beep Beep Beep Beep, Beep Beep Beep Beep

0.125 to 0.25sec

Single sound mode:

Buzzer output waveform

BZ0P, BZ0N pin

Beep

Continuous sound:

Arbitrary period

Beep

Arbitrary period

Beep

Buzzer output waveform

BZ0P, BZ0N pin

Figure 15-1 Buzzer output image

The buzzer circuit outputs a positive phase pulse (BZ0P) and negative phase pulse (BZ0N).

Also, for details of the clock used in the buzzer block (T8HZ, T1HZ), see "Low Speed Time Base Counter".

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○Features

•

Four types of buzzer mode (Intermittent sound 1, Intermittent sound 2, Single sound and Continuous sound)

Eight types of frequency (4.096 kHz to 293 Hz)

15 duties (1/16 to 15/16 = 6.25% to 93.75%)

Only seven duties (1/8 to 7/8 = 12.5% to 87.5%) are available when the buzzer frequency is 4.096 kHz.

The initial level (positive logic or negative logic) of the buzzer output pins can be chosen

•

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○Configuration

Figure 15-2 shows the configuration of the buzzer circuit.

T8HZ

T1HZ

LSCLK

BZ0P pin

BZ0N pin

Duty

generation

circuit

Buzzer output

mode choice

circuit

Buzzer frequency

generation circuit

Control circuit

BZ0CON

Frequency choice Duty choice

BZ0MOD

mode choice

Data bus

BZ0CON

BZ0MOD

: Buzzer 0 control register

: Buzzer 0 mode register

Figure 15-2 Configuration of Buzzer

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○List of Pins

The output pins of the buzzer signal are assigned to the shared function of the general port.

Pin name

BZ0P

I/O

O

Function

Buzzer output (positive phase)

Buzzer output (negative phase)

BZ0N

O

Table 15-1 shows the list of the general ports used for the buzzer output and the register settings of the ports.

Table 15-1 Ports used for the buzzer and the register settings

Pin name

BZ0P

Shared port

7^thFunc.

Setting register

P1MOD7

Setting value

0110_XXXX

P17

P20

BZ0N

P2MOD0

"XXXX" determines the condition of the port output

XXXX

0010

1010

1111

Condition of the port output

CMOS output

Nch open drain output (without the pull-up)

Nch open drain output (with the pull-up)

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●Simplified RTC

ML62Q1532 has the simplified RTC (RTC: Real Time Clock).

The simplified RTC counts up from 00 minutes 00 seconds to 59 minutes 59 seconds in the unit of one second and also

generates an interrupt request periodically.

For the interrupt enable/request flags, etc. described in this chapter, refer to Chapter "Interrupts".

○Features

•

A desired periodical interrupt request can be chosen from among four types (0.5, 1, 30 and 60 seconds).

A function to prevent erroneous writing to the simplified RTC minute/second counter included.

The simplified RTC minute/second counter continues counting operation even when a reset (other than power-on

reset) is generated.

•

Counting operation is continued all the time, except when operating in the STOP/STOP-D mode.

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○Configuration

Figure 16-1 shows the configuration of simplified RTC.

Data bus

SRTCCON

SRTCACP

Write enable signal

Periodical interrupt request

control

RTCINT

(Simplified RTC interrupt

request)

30 sec 60 sec

0.5 sec 1 sec

T1HZR/T2HZR

SRTCMAS

(Simplified RTC clock)

Figure 16-1 Simplified RTC Configuration

: Simplified RTC acceptor

: Simplified RTC minute/second counter

SRTCMIN (minute counter), SRTCSEC (second counter)

: Simplified RTC control register

SRTCACP

SRTCMAS

SRTCCON

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●General Purpose Port

The general purpose port is used as an input port or an output port.

The input and output are switchable on each pin. A general input port or output port shares a number of functions. See

"List of Pins" or "Description of Pins"for more detail.

Two general input ports are shared with the crystal resonator connection pins.

The number of general ports is dependent of each product. See Table 17-1 "List of Pins".

○Features

•

Input or output can be chosen in each pin

Pull-up resistor can be chosen in each pin

CMOS output or N-channel open drain output is can be chosen in each pin

Direct driving LEDs is supported when the N-channel open drain output is chosen

Carrier frequency output function

Port output level test function

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○Configuration

Figure 17-1 shows the configuration of the general purpose port.

V_DD

Pull-up

Controller

Data bus

PnMOD01

PnMOD23

PnMOD45

PnMOD67

PnPMD

PnPSL

V_DD

PnDI, PnDO

Output

Pn0 to Pn7

Controller

Output in a shared function

PnIE

V_SS

Input in a shared function

Analog signal

(AINx, V_REF, V_REFO, CMP0M, CMP0P,

CMP1M, CMP1P, DACOUT0 to 1)

LCD output (COM0 to 7, SEG0 to 64)

TMH0OUT (Carrier Frequency),

FTM0P (Carrier Frequency Input)

PnDI

PnDO

: Port n data register(bit 7 to 0)

: Port n data register(bit 15 to 8)

: Port n mode register 01

: Port n mode register 23

: Port n mode register 45

: Port n mode register 67

: Port n pulse mode register

: Port n pulse selection register

PnMOD01

PnMOD23

PnMOD45

PnMOD67

PnPMD

PnPSL

Figure 17-1 Configuration of General Purpose I/O port n

図 17-2 に汎用入力ポートの構成を示します。

Crystal oscillation clock

PXTMOD01

PI01

Crystal

Oscillation

Circuit

Data bus

PI00

PXT0DI

PXT1DI

PXT0DI

PXT1DI

: PORTXT data input register(bit 0)

: PORTXT data input register(bit 1)

PXTMOD01 : PORTXT mode register01

Figure 17-2 Configuration of General Purpose Input Port

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○List of Pins

Table 17-1 List of Pins

Primary

Name

Function

General purpose Input/

Crystal Oscillator Input

PI00

General purpose Input/

PI01 Crystal Oscillator Input/

External Clock Input

General purpose

Input/Output

P00

General purpose

P01

Input/Output /

DACOUT0

General purpose

Input/Output /EXI0

General purpose

Input/Output /EXI1

General purpose

Input/Output /EXI2

General purpose

Input/Output

General purpose

Input/Output

General purpose

Input/Output

General purpose

Input/Output /EXI3

General purpose

Input/Output

General purpose

Input/Output /EXI4

General purpose

Input/Output

General purpose

Input/Output /EXI5

General purpose

Input/Output

General purpose

Input/Output

P02

P03

P04

P05

P06

P07

P17

P20

P21

P22

P23

P62

P63

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●External Interrupt Function

The external interrupt function generates interrupts by signals input to the general ports.

The interrupt channel has each dedicated interrupt vector.

The number of general ports with the external interrupt function is dependent of each product. See Table 18-1 " Ports used

for the external interrupt and the register settings".

○Features

•

Maskable 6 interrupts

Available to choose the interrupt mode: interrupt disabled mode, falling-edge interrupt mode, rising-edge interrupt

mode or both-edge interrupt mode

•

Available to choose "with sampling" or "without sampling" for the input signal (the sampling clock is LSCLK or

HSCLK)

○Configuration

Figure 18-1 shows the configuration of the external interrupt function (EXI0 to EXI7)

EXI0INT DMA request

EXI1INT DMA request

EXI2INT DMA request

EXI3INT DMA request

EXI4INT DMA request

EXI5INT DMA request

EXI6INT DMA request

EXI7INT DMA request

P02/EXI0/EXTRG0

P03/EXI1/EXTRG1

P04/EXI2/EXTRG2

P17/EXI3/EXTRG3

P21/EXI4/EXTRG4

P23/EXI5/EXTRG5

P26/EXI6/EXTRG6

P27/EXI7/EXTRG7

Sampling

Controller

Interrupt

Controller

Trigger for 16-bit Timer /

Functional Timer

Sampling

Clock Control

HSCLK

EICON0

EIMOD0

Data bus

EICON0

EIMOD0

：External interrupt control register 0

：External interrupt mode register 0

Figure 18-1 Configuration of External Interrupt Function

[Note]

ML7456N does not equips P26/EXI6/EXTRG6 and P27/EXI7/EXTRG7.

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○List of Pins

External interrupt is assigned to the primary function of the general port.

Pin name

EXI0

I/O

Function

I

External Interrupt Input 0

External Interrupt Input 1

External Interrupt Input 2

External Interrupt Input 3

External Interrupt Input 4

External Interrupt Input 5

EXI1

EXI2

EXI3

EXI4

EXI5

Table 18-1 shows the list of the general ports used for the external interrupt and the register settings of the ports.

Table 18-1 Ports used for the external interrupt and the register settings

name

Setting

register

Shared port

Setting value

Primary

Function

EXI0

EXI1

EXI2

EXI3

EXI4

EXI5

P02

P0MOD2

P0MOD3

P0MOD4

P1MOD7

P2MOD1

P2MOD3

0000_0X01^*1

Primary

Function

P03

P04

P17

P21

P23

Primary

Function

Primary

Function

Primary

Function

Primary

Function

^*1："X" of “01X1” determines the condition of the port input

X

0

1

Condition of the port input

Input (without an internal pull-up resistor)

Input (with an internal pull-up resistor)

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●CRC Calculator

ML7456N has the CRC (Cyclic Redundancy Check) generator that performs CRC calculation and generates the CRC

data used for error detection in serial communications.

Also, the CRC generator has automatic CRC calculation mode to check data in program memory, available in HALT

mode or HALT-H mode.

CRC calculator

Arithmetic

input data

Generator polynomial: X¹⁶+X¹²+X⁵+1

Manual CRC

calculation mode

CPU

Calculation Result

Arithmetic

For error detection in

data communications

Arithmetic

result

Register

control,

Mode

control

Address setting

register

Automatic CRC

calculation mode

Memory address

Program

memory

For data error

detection in program

memory

Data input register

Arithmetic

input data

(For self-test)

Figure 19-1 CRC generator overview

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○Features

•

Manual CRC calculation mode

Generates CRC data from data set in CRC calculation register by the software

Calculation unit is 8bit

•

Automatic CRC calculation mode

Automatic CRC calculation by the hardware to check data in program memory in HALT or HALT-H mode and

generates CRC data

Calculation unit is 32bit. The interrupt occurs when the arithmetic operation is completed

•

Generator polynomial: X¹⁶+X¹²+X⁵+1

MSB first or LSB first selectable

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○Configuration

Figure 19-2 shows the configuration of the CRC generator.

Interrupt request of the Automatic CRC calculation completion

(MCU status interrupt)

HALT/HALT-H mode

Match

Arithmetic

circuit

Comparator

Arithmetic

Control

Program

Memory

CRCSSEG

CRCSAD

CRCESEG

CRCEAD

CRCMOD

CRCDATA

CRCRES

Data bus

CRCMOD

CRCDATA

CRCRES

: CRC Calculation Mode Register

: CRC Calculation Data Register

: CRC Calculation Result Register

CRCSSEG : Automatic CRC Calculation Start Segment Setting Register

CRCESEG : Automatic CRC Calculation End Segment Setting Register

CRCSAD

CRCEAD

: Automatic CRC Calculation Start Address Setting Register

: Automatic CRC Calculation End Address Setting Register

Figure 19-2 Configuration of CRC Generator

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●Analog Comparator

The Analog Comparator enables to use following functions.

 Compare voltages input to the two pins

 Compare a voltage input to the one pin with the internal reference voltage (Approx. 0.8V)

ML7456N equips 2 channels analog comparator.

○Features

•

Comparable with external 2 voltage inputs.

Comparable with external voltage input and internal reference voltage (approx. 0.8V).

Three types of interrupt timing generated by the voltage comparison are available.

-

Rising edge of the comparison result

Falling edge of the comparison result

Rising edge and Falling edge of the comparison result

•

The sampling with a clock is optional for the comparison result

-

HSCLK

LSCLK

1/2 HSCLK to 1/64 HSCLK

1/2 LSCLK to 1/64 HSCLK

•

Last comparison result CMPnD(n=0,1) is retained when the analog comparator is stopped

The analog comparator result output can be used as a trigger event source for the Functional Timer.

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○Configuration

Figure 20-1 shows the configuration of the analog comparator (n=0 to 1).

CMP0TRG

Analog

CMPnP pin

CMPnM pin

+

-

Interrupt

Control

Sampling

Control

CMPnINT

CMPnD

Latch

CMPnVREF

Frequency

Division

Circuit

HSCLK

LSCLK

0.8V

Reference

Voltage

CMPnCON

CMPnMOD

Data bus

Generation

Circuit

CMPnCON : Comparator n control register

CMPnMOD : Comparator n mode register

CMPnD

CMPnINT

: Analog Comparator n result

: Analog Comparator n Interrupt

CMPnVREF : Reference voltage select setting

CMP0TRG : Analog Comparator 0 output. Trigger event source for the Functional Timer.

Figure 20-1 Configuration of Analog Comparator

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○List of Pins

The I/O pins of the Analog Comparator are assigned to the shared function of the general ports (n=0 to 1).

Pin name

CMPnP

CMPnM

I/O

Function

Analog comparator n non-inverting input

Analog comparator n inverting input

I

Table 20-2 shows the list of the general ports used for the Analog Comparator and the register settings of the ports.

Table 20-2 Ports used in the Analog Comparator and the register settings

Setting

Register

Pin name

Shared port

Setting value

CMP0P

CMP0M

CMP1P

CMP1M

P03 7^thFunc. P0MOD3

P02 7^thFunc. P0MOD2

P62 7^thFunc. P6MOD2

P63 7^thFunc. P6MOD3

0110_0000

[Note]



When using the analog comparator, write "0" to the target PnmIE bit and PnmOE bit of port n mode

registers (n=0 to 9, A, B，m=0 to 7) to set the general port to Hi-impedance, otherwise a shoot-through

current may flow.

An influence of the noise is reducible by preventing the switching of neighboring pins when the

comparator enables.

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●D/A Converter

ML62Q1532 has one channel 8-bit resolution D/A converter that converts digital input signals to analog signals.

○Features

•

8-bit resolution

R-2R ladder method

Analog output voltage (DACOUT0/DACOUT1)

- Output voltage: V_{DDIO_MCU}x（Setting value in the SFR）/256

- Output impedance: 6kΩ (Typ.)

○Configuration

Figure 21-1 shows the configuration of the D/A converter.

D/A Converter 0

D/A Converter 1

DACCODE1[7:0]

DACCODE[7:0]

R-2R

Ladder

R-2R

Ladder

DACOUT0

DACOUT1

DAEN

DACCON

DAEN1

DACCON1

DACCODE1

DACCODE

Data Bus

DACCON

: D/A converter 0 control register

DACCODE : D/A converter 0 code register

DACCON1 : D/A converter 1 control register

DACCODE1 : D/A converter 1 code register

Figure 21-1 Configuration of D/A Converter Circuit

[Note]

ML7456N equips only D/A converter 0.

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○List of Pins

The I/O pins of the D/A converter are assigned to the shared function of the general ports.

Pin name

I/O

O

Function

DACOUT0

D/A converter 0 output

Table 21-2 shows the list of the general ports used for the D/A converter and the register settings of the ports.

Table 21-2 Ports used in the D/A converter and the register settings

Setting

Register

Channel no. Pin name

Shared port

Setting value

0000_0000

Primary

Func.

0

DACOUT0 P01

P0MOD1

[Note]



When using the D/A converter, write "0" to the target PnmIE bit and PnmOE bit of port n mode registers

(n=0 to 9, A, B，m=0 to 7) to set the general port to Hi-impedance (input and output disabled), othewise a

shoot-through current may flow.

An infuluence of the noise is reduceable by preventing the switching of neighboring pins while the D/A conveter is

operating.

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●Voltage Level Supervisor

ML62Q1532 has the Voltage Level Supervisor (VLS0) that detects whether the voltage level of V_DDis lower or higher

than the specified threshold voltage.

○Features

•

Accuracy: ±4 %

Threshold voltage: Selectable from 12 values (1.85 to 4.00 V)

Operation mode: Supervisor mode (continuous detection) or single mode (one detection)

Mode

Description

Detect the voltage level of V_{VDD_MCU}only once.

Single mode 1

The interrupt occurs after detecting the voltage of V_DD, indicates the

detection has been completed.

Detect the voltage level of V_{VDD_MCU}only once.

Single mode 2

The interrupt occurs after detecting the voltage of V_DDis lower than the

threshold voltage, indicates the MCU is in the low voltage condition.

Detect continuously the voltage level of V_{VDD_MCU}, suitable for always

detecting the low voltage level of V_{VDD_MCU}and generating the interrupt

or reset. The interrupt or reset occurs according to the setting in the

VLS0MOD register.

Supervisor mode

The VLS0 reset function is available by choosing the supervisor mode.

•

Voltage level supervisor reset (VLS0 reset)

Voltage level supervisor interrupt (VLS0 interrupt)

Initialized by the power-on reset (POR) or pin reset

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○Configuration

The voltage level supervisor (VLS0) consists of a comparator, a sampling control circuit, and a voltage level detection

control circuit. Figure 22-1 shows the configuration of the VLS0.

LSCLK

HSCLK

Comparator

Comparison

Result

Voltage level

Detection

V_DD

VLS0F

VLS0 interrupt

VLS0 reset

Sampling

Controller

Threshold

voltage

Control

Circuit

Threshold

voltage

selector

VLS0CON

VLS0MOD

VLS0LV

VLS0SMP

Data bus

VLS0CON

: Voltage level supervisor 0 control register

VLS0MOD : Voltage level supervisor 0 mode register

VLS0LV

: Voltage level supervisor 0 level register

VLS0SMP

: Voltage level supervisor 0 sampling register

Figure 22-1 Configuration of Voltage Level Supervisor

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●Successive Approximation Type A/D Converter

ML62Q1532 has the Successive Approximation type A/D Converter (SA-ADC), converts an analog input level to a digital

value.

The number of A/D Converter channels is dependent of the product specification.

ML7456N equips 5 channels (n=0,1,2,3,11)

○Features

•

Resolution

Conversion time

Number of input channel

: 10bit

: Min. 2.25μs/channel (conversion clock is 8MHz)

: Max. 5ch

Reference voltage: Voltage input from the VDD pin, Internal reference voltage(approx.1.55V) or External reference

voltage(VREF pin)

•

Sampling time can be chosen

Consecutive scan conversion function for target channels

Consecutive scan conversion with a specific interval time

One conversion result register for each channel

Upper /Lower limit is configurable for the conversion result, generates an interrupt

A built-in temperature sensor usable for the low-speed RC oscillation adjustment

A/D converter self-test function (full scale, zero scale, internal reference voltage)

Following triggers is available to start the A/D conversion

- 16-bit Timer 0 trigger (TMH0TRG)

- 16-bit Timer 1 trigger (TMH1TRG)

- Functional Timer 0 trigger (FTM0TRG)

- Functional Timer 1 trigger (FTM1TRG)

- Low-speed Time Base Counter interrupt (LTB0INT)

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○Configuration

Figure 23-1 shows the configuration of SA-ADC.

V_DD

V_SS

Successive

approximation

type A/D

V_REF

Selector

convertor

SADR

SADRn

SADINT

1.55V

SADLMOD

SADUPL

SADLOL

SADULS0/1

AIN0

to

AIN15

Reference

voltage

Regulator

Selector

SADTMOD

VREFCON

HSCLK

LSCLK

TMH0TRG

TMH1TRG

FTM0TRG

FTM1TRG

LTB0INT

SADCON, SADEN0/1

SADMOD, SADSTM

SADTRG

Data bus

SADCON

SADEN0/1

SADMOD

SADSTM

SADR

: SA-ADC control register

: SA-ADC enable register 0, 1

: SA-ADC mode register

: SA-ADC scan conversion interval setting register

: SA-ADC result register

SADRn

: SA-ADC result register n (n = 0 to 16)

: SA-ADC upper/lower limit mode register

: SA-ADC upper limit setting register

: SA-ADC lower limit setting register

: SA-ADC upper/lower limit status register n (n=0,1)

: Reference voltage control register

: SA-ADC trigger register

: SA-ADC test mode register

: SA-ADC interrupt request, SA-ADC DMA request

: 16-bit Timer 0, 1 interrupt

SADLMOD

SADUPL

SADLOL

SADULSn

VREFCON

SADTRG

SADTMOD

SADINT

TMH0TRG, TMH1TRG

FTM0TRG, FTM1TRG

LTB0INT

: Functional Timer 0, 1 interrupt

: Low speed time base counter 0 interrupt request

Figure 23-1 Configuration of successive approximation type A/D Converter

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○List of Pins

The I/O pins of the Successive Approximation type A/D converter are assigned to the shared function of the general ports.

Pin name

V_{DDIO_MCU}

V_SS

I/O

Description

Positive power supply for SA-ADC

-

I

Negative power supply for SA-ADC

Reference power supply for SA-ADC

SA-ADC channel 0 analog input

SA-ADC channel 1 analog input

SA-ADC channel 2 analog input

SA-ADC channel 3 analog input

SA-ADC channel 11 analog input

V_REF

AIN0

AIN1

AIN2

AIN3

AIN11

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●Regulator

ML62Q1532 incorporates the regulator.

Figure 24-1 shows the general scheme of the regulator.

The regulator generates a constant internal logic voltage (REG_CORE_MCU) independent of the variation of V_{DDIO_MCU}

(2.6 V to 3.6 V) using an amplifier for the low power consumption. The REG_CORE_MCU generated by the regulator is

supplied to peripheral circuits such as the internal logic circuit, flash memory, RAM, and oscillation circuit.

In order to stabilize the REG_CORE_MCU, connect the REG_CORE_MCU pin to V_SSvia a capacitor (1 μF).

V_DD=2.6 V to 3.6 V

+

-

Reference voltage

V_DDL=1.1V or 1.55 V

C_L=1 μF

Figure 24-1 General Scheme of Regulator

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○Features

Mode

REG_CORE_MCU voltage

STOP mode

1.55 V

HALT mode

HALT-H mode

Program run mode

STOP-D mode

1.1 V

(content of RAM and SFR can be retained)

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○Configuration

Figure 24-2 shows the configuration of the internal power supply.

V_DD=2.6 V to 3.6 V

V_DD

Regulator

C_V

V_DDL=1.55 V

REG_CORE_MCU

C_L=1 μF

Logic

circuit

Flash

memory

Oscillation

circuit

GPIO

RAM

V_SS

Figure 24-2 Internal Power Supply Configuration

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○List of Pins

In order to stabilize REG_CORE_MCU, connect the REG_CORE_MCU pin to V_SSvia a capacitor (1 μF).

Pin name

REG_CORE_MCU

V_REFO

I/O

Function

Internal logic power supply (Internal generated)

Reference voltage output

-

[Note]



In order to improve the noise resistance, place the inter-power supply bypass capacitor (C_V) and the

internal logic voltage (REG_CORE_MCU) capacitor (C_L: 1 μF) in the vicinity of LSI on the user board

using the shortest possible wiring without passing through via holes.



The internal logic voltage (REG_CORE_MCU) is unavailable to use for an external device voltage.

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●Flash Memory

ML62Q1532 has the flash memory in the program memory space and data flash area. For details of the program

memory space and data flash area, see Chapter 2 "CPU and Memory Space" of “ML62Q1000 Series User’s Manual”.

The flash memory is programmable by following three ways.

•

The ways of programming the flash memory

Reference Chapter

(ML62Q1000 Series

User’s Manual)

Programming method

Tool/Register/Communication

Programming by the on-chip On-chip debug emulator or other

debug function programmers

Self-Programming by using the Special Function

programming the flash memory

flash Chapter 28 "On chip

Debug function"

for Section 25.3

Registers(SFRs)

special function register(SFR)

Programming by the ISP

"Self-programming"

UART communication with an external device

3^rdParty Flash programmers (*1)

Section 25.4

"ISP function"

(In-System

function

Programming)

*1: Contact the 3^rdparty manufacturers for details about the Flash programmer.

The specification of the program memory space and data flash of ML7456N is following.

•

Program memory space and Data flash area Overview

Program memory space

Data flash area

Product Name

Size

Address

Size

Address

4K Byte

（128 Byte x 32

Sector）

0x0:0000 to

0x0:FFFF

0x1F:0000 to

0x1F:0FFF

ML7456N(ML62Q1532)

64K Byte

•

Program memory space and Data flash area Overview

Item

Program memory space

All area

Data flash area

All area

Chip erase(ISP only)

Block erase

Sector erase

Programming

Max. 50ms

Block erase

Sector erase

Max. 80μs

16K Byte

1K Byte

All area

128 Byte

Erasing and

programming unit

4 Byte （32bit）

1 Byte （8bit）

Max. 50ms

Erasing and

programming time

Max. 80μs

100 times

0^oC to +40^oC

-

Max. 40μs

10,000 回

-40^oC to +85^oC

Yes

Programming cycle

Erasing and programming temperature

Background operation(BGO) function

Erasing and programming completion Interrupt

No

Yes

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○List of Pins

Programming by the ISP function uses the following pins.

Signal name

RESET_N

I/O

I

Function

Input signal for entering the ISP mode

Input signal for entering the ISP mode and data

input/output data in the single wired UART communication

TEST0

I/O

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●Code Option

The code option is used to choose the CPU operating mode, PLL reference frequency, watchdog timer operation clock,

etc. depending on values written in the code option area of the program memory space.

The hardware automatically refers to data in the code option area when the microcontroller starts up due to one of system

resets described below to set each function.

•

Power-on reset

Voltage Level Supervisor reset

RESET_N pin reset

Watchdog timer (WDT) overflow reset

Watchdog timer (WDT) invalid clear reset

RAM parity error reset

Unused ROM area access reset

Code option setting circuit

CPU operation mode

0H

No-wait mode

PLL=16MHz

WDT clock

Others

WDT=Low-speed

RC oscillation

Program

code area

Peripheral

circuits,

and etc.

control circuits

Code option area

64 bytes

Updated at power-on reset,

or any other system reset

The code option area can be erased or programmed through the on-chip debug function, self-rewrite function of flash

memory, or ISP function.

Figure 26-1 Code Option Overview

○Function List



Enabling or disabling the unused ROM area access reset

Enabling or disabling the remapping function

Watchdog timer operation clock (low-speed oscillation LSCLK/WDT oscillation)

Enabling or disabling the watchdog timer operation

PLL reference frequency (16 MHz or 24 MHz)

CPU operation mode (wait mode or no-wait mode)

The software remap or hardware remap is selectable for the remap function

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●On-Chip Debug Function

This function is used by connecting the host PC and LSI through the on-chip debug emulator (hereafter referred to as

"On-chip emulator").

On-board debugging or programming is available by using the program development environment software (debugger)

installed on the host PC.

○Features

•

The following debug functions are provided using the debugger by connecting LSI and On-chip emulator

− Emulation

- Real time emulation

- Single step emulation

− Break

- Hardware break point break (four points)

- RAM data matching break

- Sequential break

- Trace overflow break

- Stack overflow/underflow break

- Unused ROM area access break

- RAM parity error break

− Trace

- Branch trace

− Real time watch

− CPU resource display/change

- Program memory reference/disassembly

- RAM and SFR display/change

- Register display/change in the CPU

− Program download

- Program download/read/erase to/from flash memory

- Data write/read/erase to/from data flash

− Peripheral circuit operation continue/stop control during break

Target peripheral circuits

- External interrupt

- Low-speed time base counter

- 16-bit timer

- Functional timer

- Serial communication unit (synchronous serial port/UART)

- I²C bus master

- I²C bus unit (master/slave)

- DMA controller

- Buzzer

- Analog module

(Analog comparator, successive approximation type A/D converter, voltage level supervisor (VLS))

•

The following program download function is provided using the flash multi-writer by connecting LSI and On-chip

emulator.

- Program download

- Erasing/Programming the program memory space

- Erasing/Programming the data flash memory area

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○Configuration

When using the on-chip debug function, two methods are available for power supply to LSI as described below:

- Use the 3.3 VOUT power supply (+3.3 V/100 mA) of On-chip emulator

- Use the power supply of the target system (V_{DDIO_MCU}=2.6 V to 3.6 V)

・

Using 3.3 VOUT Power Supply (+3.3 V/100 mA) of On-chip Emulator

Figure 28-1 shows a connection example when using the 3.3 VOUT power supply (+3.3 V/100 mA) of On-chip emulator.

On-chip emulator

Interface connector

Target system

Power supply circuit

LSI

1

VTref

V_{DDIO_MCU}

*1

10kΩ

5

RST_OUT/SCK

RESET_N

7

SDATA

P00/TEST0

13

3.3VOUT

V_SS

C_V=1µF

2,4,6,8,10,12

3,9,11,14

V_SS

NC

*1) Normal operation (reset IC, V_{DDIO_MCU}, etc.)

Figure 28-1 Connection Example When Using On-chip Emulator 3.3 VOUT Power Supply

・

Using Power Supply of Target System (V_{DDIO_MCU}=2.6 V to 3.6 V)

Figure 28-2 shows a connection example when using the power supply (V_{DDIO_MCU}=2.6 V to 3.6 V) of the target system.

On-chip emulator

Interface connector

Target system

LSI

Power supply circuit

1

VTref

V_{DDIO_MCU}

*1

10kΩ

5

RST_OUT/SCK

SDATA

RESET_N

7

P00/TEST0

13

3.3VOUT

V_SS

C_V=1µF

2,4,6,8,10,12

3,9,11,14

V_SS

NC

*1) Normal operation (reset IC, V_{DDIO_MCU}, etc.)

Figure 28-2 Connection Example When Using Target System Power Supply

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○List of Pins

The following pins are used for the on-chip debug function.

Signal name

RESET_N

I/O

I

Function

Reset input

On-chip debug function signal input/output

P00/TEST0

I/O

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●Safety Function

ML62Q1532 has the safety functions to make a safe stop in case a failure is detected by executing the self-diagnosis

software, available to support IEC60730/60335 Class B.

○Features

•

Safety Functions on the LSI

Function Name

Description

Control by SFR

Available

RAM guard

SFR guard

Protect from the miss-writing to the specified RAM area

Protect from the miss-writing to the specified SFR

Available

Successive approximation

type A/D converter test

Successive approximation type AD converter test function

Available

-

RAM parity error check and generates a reset on error (enable/disable reset

by SFR, with reset status flag and parity error flag)

RAM parity error detection

ROM unused area access Make a reset in case the CPU executes an instruction in the unused area

reset

(enable/disable reset by the code option, with reset status flag)

Monitor to check whether the oscillation of the high-speed and low-speed

clocks are normal

Clock mutual monitoring

Available

CRC calculation

Detect data error in the flash memory or data error in communications

Make the UART self-test

Available

UART self-test function

SSIO self-test function

I²C self-test function

WDT counter read

Make the SSIO self-test

Make the I²C self-test function

WDT counter read function

Port output level self-test

function

General port self-test function

Available

Clock backup function and Switch automatically to the low-speed RC oscillation in case the low-speed

the self-test

crystal oscillation stopped

Control interrupts generated by RAM parity error, automatic CRC calculation

completion, and data flash erase/program completion.

MCU status interrupt

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■RF

●Host Interface

○Serial Peripheral Interface (SPI)

This LSI has a serial peripheral interface (hereafter referred to as SPI). This LSI has a SPI, which supports slave mode. Host

MCU can read/write to the RF part registers and on-chip FIFO using MCU clock. Single access mode and burst access mode

are also supported.

[Single access mode timing chart]

In write operation, data will be stored into internal register at rising edge of clock which is capturing D0 data. During write

operation, if SCEN is set to “H”, the control section will be reset. After the internal clock is stabilized, the data will be

written into the register in synchronization with the internal clock.

[Write]

SCLK

SCEN

A

6

A

0

D

7

D

0

SDI

"1"

W

Write data field

Address field

(Register write timing)

Before clock stable

After clock stable

D7-0

[Read]

SCLK

SCEN

A

6

A

0

SDI

Address field

R

D

SDO

0

7

Read data field

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[Burst access mode timing chart]

By maintaining SCEN line as “L”, Burst access mode will be active. By setting SCEN line to “H”, exiting from the burst

access mode. During burst access mode, address will be automatically incremented. When SCEN line becomes “H” before

Clock for D0 is input, data transaction will be aborted.

[Note]

If access destination is [WR_TX_FIFO: B0 0x7C] or [RD_FIFO: B0 0x7F] register, address will not be incremented,

allowing continuous access to the FIFO.

[Write]

SCEN

A

6

A

0

D

7

D

0

SDI

"1"

W

Write data field

Address field

(Register write timing)

Before clock stable

After clock stable

D7-0

Up to 0.45µs

[Read]

SCLK

SCEN

A

6

A

0

"0"

R

SDI

Address field

D

7

D

0

SDO

Read data field

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●LSI State Control

The LSI state can be changed by setting registers below.

State transition command

TX_ON

Registers setting

SET_TRX ([RF_STATUS: B0 0x0B(3-0)]) = 0x9

SET_TRX ([RF_STATUS: B0 0x0B(3-0)]) = 0x6

SET_TRX ([RF_STATUS: B0 0x0B(3-0)]) = 0x8

SET_TRX ([RF_STATUS: B0 0x0B(3-0)]) = 0x3

SLEEP_EN([SLEEP/WU_SET: B0 0x2D(0)]) = 0b1

RX_ON

TRX_OFF

Force_TRX_OFF

SLEEP

VCO_CAL

VCO_CAL_START([VCO_CAL_START: B0 0x6F(0)])= 0b1

The LSI state can be changed autonomously (please refer to the following table.) If one of the following conditions is met, state

is changed automatically according to the following table.

Function

Automatic TXON after FIFO write completion

Automatic TXON during FIFO write

RF state setting after packet transmission

completion

RF state setting after packet reception completion

Automatic RXON/TXON by Wake-up timer

function

Register

AUTO_TX_EN([RF_STATUS_CTRL: B0 0x0A(4)])

FAST_TX_EN([RF_STATUS_CTRL: B0 0x0A(5)])

TXDONE_MODE([RF_STATUS_CTRL: B0 0x0A(1-0)])

RXDONE_MODE([RF_STATUS_CTRL: B0 0x0A(3-2)])

[SLEEP/WU_SET:B0 0x2D]

Automatic VCO calibration after recovering from

SLEEP

Automatic SLEEP by Timer

Automatic SLEEP by high speed carrier checking

mode

AUTO_VCOCAL_EN([VCO_CAL_START: B0 0x6F(4)])

[SLEEP/WU_SET: B0 0x2D]

FAST_DET_MODE_EN ([CCA_CTRL:B0 0x39(3)])

Automatic TX_ON by high speed carrier checking

mode

CCADONE_MODE([ED_CTRL:B0 0x41(6)])

Force_TRX_OFF after PLL unlock detection

during TX

PLL_LD_EN([PLL_LOCK_DETECT: B1 0x0B(7)])

Each LSI state transition control follows the state diagram shown below.

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○LSI State Transition Diagram

TRX_OFF

Force_TRX_OFF

SLEEP

TRX_OFF

Force_TRX_OFF

SLEEP

TRASMIT

RECEIVE

Force_TRX_OFF

SLEEP

Force_TRX_OFF

SLEEP

TX completion

(TRX_OFF)

Start reception

RX completion

(TRX_OFF)

(SyncWord detection)

Start transmission

TRX_OFF

Force_TRX_OFF

SLEEP

TRX_OFF

Force_TRX_OFF

SLEEP

TRX_OFF

Force_TRX_OFF

SLEEP

TX_ON

RX_ON

TX_ON

RX_ON

VCO_CAL

SLEEP

TRX_OFF

Force_TRX_OFF

SLEEP

RX_ON

TX_ON/RX_ON

TX_ON

RX_ON

Start VCO_CAL

TRX_OFF

IDLE

PLLWAIT

TRX_OFF/Force_TRX_OFF/

VCO calibration completion/

DEEP

Exit from SLEEP

SLEEP

DEEP

SLEEP

Exit form

VCO_CAL completion

Start VCO_CAL

SLEEP

DEEP

SLEEP

VCOCAL

Exit from

SLEEP

DEEP

Exit from SLEEP

[STATE]

DEEP SLEEP

SLEEP

TRX_OFF/IDLE

PLL_WAIT

TX_ON

TRANSMIT

RX_ON

RECEIVE

VCO_CAL

: DEEP sleep

: Sleep

: Idle (TX-RX stand-by)

: PLL stand-by

: TX ready (TX data waiting)

: TX operation

: RX stand-by (RX data waiting)

: RX operation

: VCO calibration

State transition

instruction

Pins control

Normal sequence

(state transition)

State of ML7456N

RF part Self

State of command

reception from

controlled state

transition state

higher layer state

LSI state diagram

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○SLEEP Setting

DEEP_Sleep mode: Powers for all blocks except IO pins are turned off.

Sleep mode: Main regulator and 36MHz oscillation circuits are turned off. But sub-regulator is turned-on.

The following registers can be programmed to control SLEEP state.

Function

Register

Power control

Wake-up setting

Wake-up timer clock source setting

Internal RC oscillator circuit control

PDN_EN([SLEEP/WU_SET: B0 0x2D(1)])

WAKEUP_EN([SLEEP/WU_SET: B0 0x2D(4)])

WUT_CLK_SOURCE([SLEEP/WU_SET: B0 0x2D(2)]）

RC32K_EN ([CLK_SET2: B0 0x03(3)])

Setting method and internal state for DEEP_SLEEP and various SLEEP modes are as follows:

SLEEP

Setting method

mode

DEEP

SLEEP

RESETN pin=”L”

REGPDIN pin=”H”

[SLEEP/WU_SET: B0 0x2D(5-0)]

= 0b00_0111

OFF

ON

OFF

SLEEP1

[CLK_SET2: B0 0x03(3)] = 0b0

[SLEEP/WU_SET: B0 0x2D(5-0)]

= 0b11_0111

OFF

ON

OFF

ON

OFF

SLEEP2

[CLK_SET2: B0 0x03(3)] = 0b1

Contents of registers are not kept during DEEP_SLEEP. Contents of registers are kept during SLEEP1 and SLEEP2. However,

in SLEEP1 and SLEEP2, contents of TX FIFO are not kept, because power to FIFO is turned off.

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○Notes to Set RF State

This LSI is able to change the RF state transition autonomously (without RF state transition commands by register

settings), by issuing RF state transition commands from LSI . (please refer to ”LSI state transition instruction”). If

both timing of operation (autonomous state and state change from MCU command) overlapped, unintentional RF

state may occur. Timing of autonomous state RF change is described in the following table. Care must be taken not

to overlap the conditions.

RF state change

(before =>after)

TRX_OFF/RX_ON =>

TX_ON

RF state transition timing

(not from Host MCU command)

After TX data reception completion interrupt

occurs, {[TX_RATE_H/L: B1 0x02/03)] setting

value

Function

Recommended process

Automatic TX

Perform a write access to

[RF_STATUS:B0 0x0B] after

RF state transition completion

interrupt occurs or GET_TRX

([RF_STATUS:B0 0x0B(7-4)])

has changed to the expected

state.

* 2 / 36} [µs] period

FAST_TX mode

After FIFO write access amount exceeds trigger

level + 1, {[RX_RATE1_H/L:B1 0x04/05]

setting value

* 5 / 36} [µs] period

After TX completion

RF status setting

After TX completion interrupt occurs,

{[TX_RATE_H/L:B1 0x02/03] setting value

* 2 / 36} [µs] period

TX_ON => TRX_OFF

TX_ON => RX_ON

TX_ON => SLEEP

RX_ON => TRX_OFF

RX_ON => TX_ON

RX_ON => SLEEP

SLEEP => TX_ON

After RX completion

RF status setting

After data RX completion interrupt occurs,

{[RX_RATE1_H/L:B1 0x04/05] setting value

* 2 / 36} [µs] period

Wake-up timer

After wake-up timer completion, low speed

wake-up timer clock cycle duration

SLEEP => RX_ON

SLEEP => VCO_CAL

=> TX_ON

After wake-up timer completion interrupt

(INT[6]: group1),

After a VCO calibration

completion interrupt occurs,

perform an access to

[RF_STATUS:B0 0x0B] and

BANK2.

before VCO calibration completion interrupt

(INT[1] group1).

SLEEP => VCO_CAL

=> RX_ON

Continuous operation

timer

After continuous operation timer completion, low

speed wake-up timer clock cycle duration

Perform a write access to

[RF_STATUS:B0 0x0B] after

RF state transition completion

interrupt occurs or GET_TRX

([RF_STATUS:B0 0x0B(7-4)])

has changed to the expected

state.

TX_ON => SLEEP

RX_ON => SLEEP

High speed carrier

checking

After CCA completion interrupt, 6.3 [µs] period.

RX_ON => TX_ON

PLL unlock detection

After PLL unlock detection interrupt (INT[2]

group1), 24 [µs] (*1) period.

24 µs (*1) after the interrupt

occurs, perform a write access to

[RF_STATUS:B0 0x0B].

TX_ON => TRX_OFF

(*1) Depends on the ramp down time setting.

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●Packet Handling Function

○Packet Format

ML7456N RF part supports Wireless M-Bus frame Format A/B, and Format C/D which is non Wireless M-Bus universal

format. The following packet handling are supported in FIFO mode or DIO mode

• Preamble and SyncWord automatic insertion (TX)

• Preamble and SyncWord automatic detection (RX)

• Preamble and SyncWord automatic deletion (RX)

• CRC data insertion

--- Common to DIO/FIFO mode

--- FIFO mode only

• CRC check and error notification

--- Common to DIO/FIFO mode

Packet format registers are as follows:

Function

Register

Packet format setting

PKT_FORMAT([PKT_CTRL1: B0 0x04(1-0)])

RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)])

DAT_LF_EN([PKT_CTRL1: B0 0x04(4)])

RX extended link layer mode disable

Data area bit order setting

Length area bit order setting

Extended link layer mode setting

LEN_LF_EN([PKT_CTRL1: B0 0x04(5)])

EXT_PKT_MODE([PKT_CTRL1: B0 0x04(7-6)])

EXT_PKT_MODE2([DATA_SET2: B0 0x08(7-6)])

LENGTH_MODE([PKT_CTRL2: B0 0x05(1-0)])

Length field setting

Packet formats supported by ML7456N RF part are as follows.

(1) Format A (Wireless M-Bus)

To use Format A, set PKT_FORMAT([PKT_CTRL1: B0 0x04(1-0)]) = 0b00. B0 0x04(1-0)]) = 0b00

Format A consists of 1^stBlock, 2^ndBlock and Optional Block(s). Each block has 2 bytes of CRC. “L-field” (1st byte of 1^st

Block ) indicates packet Length, which indicates the total byte count of data subsequent to C-field of the 1^stBlock excluding

CRC and Postamble. In addition, the 2^ndBlock or Optional Block subsequent to the 1^stBlock is added according to the

Length.

The following [] indicates register address [bank #, address].

Manchester/3-out-of-6 applicable

[B0 0x07]

CRC applicable

2nd Block

CRC applicable

Opt Block

MSB

LSB

Length

1st Block

Sync

Word

Preamble

Postamble

L

C

M

A

CRC

field

CRC

field

CI

field

Data

field

Data

field

field field field field field

0/2-8

bit

1

byte

Max. 15

byte

2

byte

Max. 16

byte

2

byte

n*2

or more

10/18/

32bit

1

2

6

2

byte byte byte byte byte

[B0 0x07]

[B0 0x42]

[B0 0x43]

[B0 0x08]

[B1 0x25-2E]

(*2)

[B0 0x44]

(*3)

(*4)

[B0 0x05]

TX: automatic insertion

RX: automatic

[B0 0x7A-7E]

detection, deletion

*1: Each mode of Wireless M-Bus has different minimum value of n.

*2: Indicates TX FIFO data storage area upon TX.

*3: Indicates RX FIFO data storage area upon RX.

*4: Indicates DCLK/DIO output area at RXDIO_CTRL [DIO_SET: B0 0x0C(7-6)])=0b10)

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Extended Link Layer Format

If “CI-field” (1st byte of 2^ndBlock ) is set to 0x8C/0x8D/0x8E/0x8F, Extended Link Layer Format is applied and the packet

format is extended as follows.

(a) CI-field = 0x8C

If using the extended format upon TX, set EXT_PKT_MODE[PKT_CTRL1: B0 0x04(7-6)]) = 0b01 and

EXT_PKT_MODE2([DATA_SET2: B0 0x08(7-6)]) = 0b00. If RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)]) = 0b0 is

set for RX, whether or not the RX packets are extended packet format is judged automatically and the RX process is carried

out.

Manchester/3-out-of-6 applicable

[B0 0x07]

CRC applicable

Opt Block

MSB

LSB

1st Block

(*1)

Extended

Length

Block

2nd Block

Sync

Word

Preamble

Postamble

CI

field

C-CRC

field

L

CI

CC ACC

CRC

field

CRC

field

Data

field

Data

field

field field field

0/2-8

bit

n*2

or more

1

byte

Max. 12

byte

2

byte

Max. 16

byte

2

byte

10/18/

32bit

1

11

1

byte byte byte byte byte

(*2)

[B0 0x08]

[B1 0x25-2E]

[B0 0x07]

[B0 0x42]

[B0 0x43]

[B0 0x44]

(*3)

(*4)

[B0 0x05]

[B0 0x7A-7E]

TX: automatic insertion

RX: automatic

detection, deletion

*1: 1st Block is identical to normal Format A.

*2: Indicates TX FIFO data storage area upon TX.

*3: Indicates RX FIFO data storage area upon RX.

*4: Indicates DCLK/DIO output area at RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)]) = 0b10.

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(b) CI-field = 0x8D

If using the extended format upon TX, set EXT_PKT_MODE[PKT_CTRL1: B0 0x04(7-6)]) = 0b10 and

EXT_PKT_MODE2([DATA_SET2: B0 0x08(7-6)]) = 0b00. If RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)]) = 0b0 is set

for RX, whether or not the RX packets are extended packet format is judged automatically and the RX process is carried out.

Manchester/3-out-of-6 applicable

[B0 0x07]

CRC applicable

2nd Block

CRC applicable

Opt Block

MSB

LSB

1st Block

(*1)

Extended Block

Length

Sync

Word

Postamble

Preamble

SN CRC

field field

CI

C-CRC

field

CRC

field

CRC

field

L

CI

CC ACC

Data

field

field field field

0/2-8

bit

2

byte

n*2

or more

4

byte

1

byte

Max. 15

byte

2

byte

Max. 16

byte

2

byte

10/18/

32bit

1

11

1

byte byte byte byte byte

[B0 0x08]

[B1 0x25-2E]

(*2)

[B0 0x44]

[B0 0x07]

[B0 0x42]

[B0 0x43]

(*3)

(*4)

[B0 0x05]

[B0 0x7A-7E]

TX: automatic insertion

RX: automatic

detection, deletion

*1: 1^stBlock is identical to normal Format A..

*2: Indicates TX FIFO data storage area upon TX.

*3: Indicates RX FIFO data storage area upon RX.

*4: Indicates DCLK/DIO output area at RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)]) = 0b10.

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(c) CI-field = 0x8E

If using the extended format upon TX, set EXT_PKT_MODE[PKT_CTRL1: B0 0x04(7-6)]) = 0b00 and

EXT_PKT_MODE2([DATA_SET2: B0 0x08(7-6)]) = 0b01. If RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)]) = 0b0 is set

for RX, whether or not the RX packets are extended packet format is judged automatically and the RX process is carried out.

Manchester/3-out-of-6 applicable

[B0 0x07]

CRC applicable

Opt Block

MSB

LSB

1st Block

(*1)

Extended

Length

Block

2nd Block

Sync

Word

Preamble

Postamble

CC/ACC/M CI

2/A2 field field

C-CRC

field

L

CI

field

CRC

field

CRC

field

Data

field

Data

field

0/2-8

bit

n*2

or more

10

byte

1

byte

Max. 4

byte

2

byte

Max. 16

byte

2

byte

10/18/

32bit

1

11

1

byte byte byte

(*2)

[B0 0x08]

[B1 0x25-2E]

[B0 0x07]

[B0 0x42]

[B0 0x43]

[B0 0x44]

(*3)

(*4)

[B0 0x05]

[B0 0x7A-7E]

TX: automatic insertion

RX: automatic

detection, deletion

*1: 1st Block is identical to normal Format A.

*2: Indicates TX FIFO data storage area upon TX.

*3: Indicates RX FIFO data storage area upon RX.

*4: Indicates DCLK/DIO output area at RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)]) = 0b10.

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(d) CI-field = 0x8F

If using the extended format upon TX, set EXT_PKT_MODE[PKT_CTRL1: B0 0x04(7-6)]) = 0b00 and

EXT_PKT_MODE2([DATA_SET2: B0 0x08(7-6)]) = 0b10. If RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)]) = 0b0 is set

for RX, whether or not the RX packets are extended packet format is judged automatically and the RX process is carried out.

Manchester/3-out-of-6 applicable

[B0 0x07]

CRC applicable

2nd Block

CRC applicable

Opt Block

MSB

LSB

1st Block

(*1)

Extended Block

Length

Sync

Word

Postamble

Preamble

CC/ACC/M2/A2/ CRC

CI

C-CRC

field

CRC

field

CRC

field

L

CI

field

Data

field

SN field

field

0/2-8

bit

2

byte

n*2

or more

1

byte

Max. 15

byte

2

byte

Max. 16

byte

2

byte

10/18/

32bit

1

11

1

14

byte

byte byte byte

[B0 0x08]

[B1 0x25-2E]

(*2)

[B0 0x44]

[B0 0x07]

[B0 0x42]

[B0 0x43]

(*3)

(*4)

[B0 0x05]

[B0 0x7A-7E]

TX: automatic insertion

RX: automatic

detection, deletion

*1: 1^stBlock is identical to normal Format A..

*2: Indicates TX FIFO data storage area upon TX.

*3: Indicates RX FIFO data storage area upon RX.

*4: Indicates DCLK/DIO output area at RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)]) = 0b10.

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(2) Format B (Wireless M-Bus)

To use Format B, set PKT_FORMAT([PKT_CTRL1: B0 0x04(1-0)]) = 0b01.

Format B consists of 1st Block, 2nd Block or Optional Block. Each block after 2nd Block has 2 bytes of CRC. “L-field” (1st

byte of 1^stBlock) indicates packet Length, which indicates the total byte count of data from C-field to final CRC data of the 1^st

Block. In addition, the 2^ndBlock or Optional Block subsequent to the 1^stBlock is added according to the Length.

The following [] indicates register address [bank #, address].

Manchester/3-out-of-6 applicable

[B0 0x07]

CRC applicable

Length

CRC applicable

Opt Block

MSB

LSB

2nd Block

1st Block

Sync

Word

Preamble

Postamble

A

field

L

C

M

CRC

field

CRC

field

CI

field

Data

field

Data

field

field field field

0/2-8

bit

n*2

or more (*1)

6

byte

1

byte

Max. 115

byte

2

byte

Max. 126

byte

2

byte

10/18/

32bit

1

2

byte byte byte

[B0 0x07]

[B0 0x42]

[B0 0x43]

[B0 0x08]

[B1 0x25-2E]

(*2)

[B0 0x44]

(*3)

(*4)

TX: automatic insertion

RX: automatic

detection, deletion

[B0 0x05]

[B0 0x7A-7E]

*1: Each mode of Wireless M-Bus has different minimum value of n.

*2: Indicates TX FIFO data storage area upon TX.

*3: Indicates RX FIFO data storage area upon RX.

*4: Indicates DCLK/DIO output area at RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)]) = 0b10.

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Extended Link Layer Format

If “CI-field” (1st byte of 2^ndBlock ) is set to 0x8C/0x8D/0x8E/0x8F, Extended Link Layer Format is applied and the packet

format is extended as follows.

(a) CI-field = 0x8C

If using the extended format upon TX, set EXT_PKT_MODE[PKT_CTRL1: B0 0x04(7-6)]) = 0b01 and

EXT_PKT_MODE2([DATA_SET2: B0 0x08(7-6)]) = 0b00. If RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)]) = 0b0 is

set for RX, whether or not the RX packets are extended packet format is judged automatically and the RX process is carried

out.

Manchester/3-out-of-6 applicable

[B0 0x07]

CRC applicable

MSB

LSB

1st Block

(*1)

Extended

Length

2nd Block

Opt Block

Block

Sync

Word

Preamble

Postamble

C-A

field

L

CI

CC ACC

CRC

field

CRC

field

CI

field

Data

field

Data

field

field field field

n*2

or more

2 to 8

bit

1

byte

Max. 112

byte

2

byte

Max. 126

byte

2

byte

10/18/

32bit

1

9

1

byte byte byte byte byte

(*2)

[B0 0x08]

[B1 0x25-2E]

[B0 0x07]

[B0 0x42]

[B0 0x43]

[B0 0x44]

(*3)

(*4)

TX: automatic insertion

RX: automatic

detection, deletion

[B0 0x05]

[B0 0x7A-7E]

*1: 1^stBlock is identical to normal Format B..

*2: Indicates TX FIFO data storage area upon TX.

*3: Indicates RX FIFO data storage area upon RX.

*4: Indicates DCLK/DIO output area at RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)]) = 0b10.

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(b) CI-field = 0x8D

If using the extended format upon TX, set EXT_PKT_MODE[PKT_CTRL1: B0 0x04(7-6)]) = 0b10 and

EXT_PKT_MODE2([DATA_SET2: B0 0x08(7-6)]) = 0b00. If RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)]) = 0b0 is

set for RX, whether or not the RX packets are extended packet format is judged automatically and the RX process is carried

out.

Manchester/3-out-of-6 applicable

[B0 0x07]

CRC applicable

2nd Block

CRC applicable

Opt Block

MSB

LSB

1st Block

(*1)

Extended

Length

Block

CC ACC

Sync

Word

Postamble

Preamble

SN CRC CI

field field field

C-A

field

CRC

L

CI

field field field

Data

field

Data

field

2

byte

n*2

or more

4

byte

1

byte

Max. 106

byte

2

byte

Max. 126

byte

2

byte

2 to 8

bit

10/18/

32bit

1

9

1

byte byte byte byte byte

(*2)

[B0 0x44]

[B0 0x07]

[B0 0x42]

[B0 0x43]

[B0 0x08]

[B1 0x25-2E]

(*3)

(*4)

TX: automatic insertion

RX: automatic

detection, deletion

[B0 0x05]

[B0 0x7A-7E]

*1: 1^stBlock is identical to normal Format B.

*2: Indicates TX FIFO data storage area upon TX.

*3: Indicates RX FIFO data storage area upon RX.

*4: Indicates DCLK/DIO output area at RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)]) = 0b10.

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(c) CI-field = 0x8E

If using the extended format upon TX, set EXT_PKT_MODE[PKT_CTRL1: B0 0x04(7-6)]) = 0b00 and

EXT_PKT_MODE2([DATA_SET2: B0 0x08(7-6)]) = 0b01. If RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)]) = 0b0 is

set for RX, whether or not the RX packets are extended packet format is judged automatically and the RX process is carried

out.

Manchester/3-out-of-6 applicable

[B0 0x07]

CRC applicable

Opt Block

MSB

LSB

1st Block

(*1)

Extended

Length

2nd Block

Block

Sync

Word

Preamble

Postamble

CC/ACC/M

2/A2 field

C-A

field

L

CI

field

CRC

field

CRC

field

CI

field

Data

field

Data

field

n*2

or more

10

byte

2 to 8

bit

1

byte

Max. 104

byte

2

byte

Max. 126

byte

2

byte

10/18/

32bit

1

9

1

byte byte byte

(*2)

[B0 0x08]

[B1 0x25-2E]

[B0 0x07]

[B0 0x42]

[B0 0x43]

[B0 0x44]

(*3)

(*4)

TX: automatic insertion

RX: automatic

detection, deletion

[B0 0x05]

[B0 0x7A-7E]

*1: 1^stBlock is identical to normal Format B..

*2: Indicates TX FIFO data storage area upon TX.

*3: Indicates RX FIFO data storage area upon RX.

*4: Indicates DCLK/DIO output area at RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)]) = 0b10.

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(d) CI-field = 0x8F

If using the extended format upon TX, set EXT_PKT_MODE[PKT_CTRL1: B0 0x04(7-6)]) = 0b00 and

EXT_PKT_MODE2([DATA_SET2: B0 0x08(7-6)]) = 0b10. If RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)]) = 0b0 is

set for RX, whether or not the RX packets are extended packet format is judged automatically and the RX process is carried

out.

Manchester/3-out-of-6 applicable

[B0 0x07]

CRC applicable

Opt Block

MSB

LSB

1st Block

(*1)

Extended

Length

2nd Block

Block

Sync

Word

Postamble

Preamble

CC/ACC/M2/A2/ CRC CI

C-A

field

CRC

field

CRC

field

L

CI

field

Data

field

Data

field

SN field

field field

field

2

1

byte

n*2

or more

2 to 8

bit

Max. 98

byte

2

byte

Max. 126

byte

2

byte

10/18/

32bit

1

9

1

14

byte

byte byte byte

(*2)

[B0 0x44]

[B0 0x07]

[B0 0x42]

[B0 0x43]

[B0 0x08]

[B1 0x25-2E]

(*3)

(*4)

TX: automatic insertion

RX: automatic

detection, deletion

[B0 0x05]

[B0 0x7A-7E]

*1: 1^stBlock is identical to normal Format B..

*2: Indicates TX FIFO data storage area upon TX.

*3: Indicates RX FIFO data storage area upon RX.

*4: Indicates DCLK/DIO output area at RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)]) = 0b10.

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(3) Format C (non-Wireless M-Bus, general purpose format)

To use Format C, set PKT_FORMAT([PKT_CTRL1: B0 0x04(1-0)]) = 0b10.

Format C consists of 1^stBlock only, which has 2 bytes of CRC. “L-field” (first one or two bytes of 1^stBlock) indicates packet

Length, which indicates the total byte count from Data-field to final CRC data. Data Whitening function is supported.

The following [] indicates register address [bank #, address].

[B0 0x07]

[B0 0x08]

Manchester/3-out-of-6 applicable

Whitening applicable

CRC applicable

1st Block

MSB

LSB

Length

Sync

Word

Preamble

Postamble

L

field

CRC

field

Data

field

0/2-8

bit

Max. 2047

byte

0/1/2/4

byte

n*2

or more (*1)

1/2

byte

Max.

32bit

(*2)

[B0 0x07]

[B0 0x42]

[B0 0x43]

[B0 0x05]

[B0 0x08]

[B1 0x25-2E]

[B0 0x44]

(*3)

(*4)

TX: automatic insertion

RX: automatic

detection, deletion

[B0 0x05]

[B0 0x7A/7B, 7D/7E]

*1: Preamble length (n) is can be set to arbitrary value.

*2: Indicates TX FIFO data storage area upon TX.

*3: Indicates RX FIFO data storage area upon RX.

*4: Indicates DCLK/DIO output area at RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)]) = 0b10.

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(4) Format D (non-Wireless M-Bus, general purpose format)

To use Format D, set PKT_FORMAT([PKT_CTRL1: B0 0x04(1-0)]) = 0b11. B0 0x04(1-0)]) = 0b11.

Format D consists of 1^stBlock only, which starts with Data field followed by CRC-field (selectable from 0/1/2 bytes). “L-field”

indicates the total byte count from Data-field to final CRC data and is set by [TX_PKT_LENGTH: B0 0x7A/0x7B] or

[RX_PKT_LENGTH: B0 0x7D/0x7E].

The following [] indicates register address [bank #, address].

[B0 0x07]

[B0 0x08]

Manchester/3-out-of-6 applicable

Whitening applicable

CRC applicable

MSB

LSB

Length

1st Block

Sync

Word

Preamble

Postamble

CRC

field

Data

field

0/2-8

bit

Max. 2047

byte

0/1/2/4

byte

n*2

or more

Max.

32bit

[B0 0x07]

[B0 0x42]

[B0 0x43]

[B0 0x08]

[B1 0x25-2E]

(*2)

(*3)

[B0 0x05]

[B0 0x44]

TX: automatic insertion

RX: automatic

(*4)

detection, deletion

*1: Preamble length (n) is can be set to arbitrary value.

*2: Indicates TX FIFO data storage area upon TX.

*3: Indicates RX FIFO data storage area upon RX.

*4: Indicates DCLK/DIO output area at RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)]) = 0b10.

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○CRC Function

ML7456N RF part has CRC32,CRC16 and CRC8 function. CRC is calculated and appended to TX data. CRC is checked for

RX data. The following modes are used for automatic CRC function. In addition, they can be set using the registers shown in

the following table.

• FIFO mode --- RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)]) = 0b00

• DIO mode

--- RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)]) = 0b11

Function

Register

TX CRC setting

TX_CRC_EN([PKT_CTRL2: B0 0x05(2)])

RX CRC setting

RX_CRC_EN([PKT_CTRL2: B0 0x05(3)])

CRC_LEN([PKT_CTRL2: B0 0x05(5-4)])

CRC_COMP_OFF([PKT_CTRL2: B0 0x05(6)])

[CRC_POLY3/2/1/0: B1 0x16/17/18/19]

[CRC_ERR_H/M/L: B0 0x13/14/15]

CRC length setting

CRC complement value OFF setting

CRC polynomial setting

CRC error status

CRC length setting 2 enable

CRC length setting 2

CRC_LEN2_EN([CRC_ERR_H: B0 0x13(7)])

CRC_LEN2([CRC_ERR_H: B0 0x13(6-5)])

Any CRC polynomials for CRC32/CRC16/CRC8 can be specified. Reset value is as follows:

CRC16 polynomial = x¹⁶+ x¹³+ x¹²+ x¹¹+ x¹⁰+ x⁸+ x⁶+ x⁵+ x²+ 1 (reset value)

* CRC result data can be inverted by CRC complement value OFF setting.

CRC data will be generated by the following circuits. By programming [CRC_POLY3/2/1/0] registers, any CRC polynomials

can be supported. Generated CRC will be transferred from the left most bit (S15). If the CRC function is used for data shorter

than CRC length (3-byte data of CRC32 only), data 0s will be added before performing CRC calculation. CRC check result is

indicated in [CRC_ERR_H/M/L] registers. Unlike Format C, Format A/B can include multiple CRC-fields in one packet. For

multiple CRC-fields, the CRC check result closest to L-field will be indicated in CRC_ERR[0] ([CRC_ERR_L:B0 0x15(0)]).

Subsequent bit will be indicated in CRC_ERR from MSB in sequence.

CRC_POLY

[14]

CRC_POLY

[2]

CRC_POLY

[0]

CRC_POLY

[1]

CRC_POLY

[13]

Input

data

S15

S14

S3

S2

S1

S0

※

：Exclusive OR

Example: CRC generation circuits

General polynomial can be programmed by below [CRC_POLY3/2/1/0] register setting. CRC length can be set by CRC_LEN.

[CRC_POLY3/2/1/0]

CRC polynomial

(B1 0x16)

0x00

(B1 0x17)

0x00

(B1 0x18) (B1 0x19)

CRC8

CRC16

x⁸+ x²+ x + 1

0x00

0x08

0x40

0x1E

0x03

0x10

0x02

0xB2

x¹⁶+ x¹²+ x⁵+ 1

0x00

x¹⁶+ x¹⁵+ x²+ 1

x¹⁶+ x¹³+ x¹²+ x¹¹+ x¹⁰+ x⁸+ x⁶+ x⁵+ x²+ 1

x³²+ x²⁶+ x²³+ x²²+ x¹⁶+ x¹²+ x¹¹+ x¹⁰+ x⁸+ x⁷+ x⁵

+ x⁴+ x²+ x + 1

CRC32

0x02

0x60

0x8E

0xDB

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In addition, for ML7456N RF part, CRC length for CRC calculation and CRC length for appending to packets (upon TX) or

checking (upon RX) can be set individually. To do this, use CRC_LEN2_EN, CRC_LEN2, and CRC_LEN for setting.

CRC length for

appending or checking

CRC

CRC length for

calculating CRC

CRC_LEN2_EN

(B0 0x13)

CRC_LEN2

(B0 0x13)

CRC_LEN

(B0 0x05)

CRC8

CRC16

CRC8

CRC16

CRC32

0

1

0

1

0

-

0b00

0b01

0b00

0b01

0b10

0b01

-

0b10

-

CRC16

CRC32

However, when different CRC lengths are set for calculating CRC and for appending to packets (upon TX) or checking (upon

RX), "CRC length for calculating CRC" must be longer than or equal to "CRC length for appending to packets (upon TX) or

checking (upon RX)."

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○Data Whitening Function

ML7456N RF part supports the Data Whitening function. In packet format A/B, data succeeding C-field is the target area for

Whitening. In packet format C, data succeeding Data-field is the target area for Whitening. Data generated by the following

9-bit pseudo random noise sequence (PN9) generation circuit will be XORed with TX data (encoded in 3-out-of-6 coding)

before transmission and transmitted. Initialization value of the PN9 generation circuit shift register can be set by

[WHT_INIT_H/L: B1 0x64/65] registers. PN9 polynomial can be set to any polynomial by [WHT_CFG: B1 0x66]. B1 0x66],

any polynomial can be programmed.

･ Data Whitening setting enable

･ Data Whitening initialization value

･ Whitening polynomial

: WHT_SET ([DATA_SET2: B0 0x08(0)])

: [WHT_INIT_H/L: B1 0x64/65]

: [WHT_CFG: B1 0x66]

When [WHT_CFG: B1 0x66(0)] is set to 0b1, the polynomial setting function feeds back the shift register S1 output to XOR. In

a similar way, when [WHT_CFG: B1 0x66(1)] is set to 0b1, it feeds back the shift register S2 output to XOR, and [WHT_CFG:

B1 0x66(7-2)] also has a similar function. Two or more bits can be also set to 0b1. Therefore any type of PN9 polynomial can

be programmed.

Whitening

data

S8

S7

S6

S5

S4

S3

S2

S1

S0

*

: Exclusive OR

Whitening data generation circuits

(Polynomial: x⁹+ x⁵+ 1)

The relation ship between General PN9 polynomial and [WHT_CFG] settings are as follows.

PN9 polynomial

x⁹+ x⁴+ 1

[WHT_CFG: B1 0x66]

0x08

0x10

x⁹+ x⁵+ 1

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○SyncWord Detection function

This LSI supports automatic SyncWord recognition function. By having two sets of SyncWord pattern storage area, it is

possible to detect two different packet format (Format A/B) which are defined by Wireless M-Bus. (For details, please refer

to Wireless M-BUS standard) Receiving packet format is indicated by SW_DET_RSLT([STM_STATE:B0 0x77(5)]). In

addition, when Two SyncWords waiting setting is set for Format C/D, it is possible to wait for two SyncWords. but detected

result is not indicated.

1）TX

SyncWord pattern defined by SYNCWORD_SEL ([DATA_SET2: B0 0x08(4)]) will be selected. SyncWord length for TX

is defined by SYNC_WORD_LEN ([SYNC_WORD_LEN: B1 0x25(5-0)]). Data of each SyncWord pattern of the defined

SyncWord length will be transmitted from higher bit.

SYNCWORD_SEL

0

TX SyncWord pattern

SYNCWORD1_SET[31:0]

([SYNCWORD1_SET3/2/1/0: B1 0x27/28/29/2A])

SYNCWORD2_SET[31:0]

1

([SYNCWORD2_SET3/2/1/0: B1 0x2B/2C/2D/2E])

Example) SyncWord pattern and SyncWord length

If the following registers are programmed, 18 bits of SYNCWORD1_SET [17:0] will be transmitted from higher bit

sequentially.

[SYNC_WORD_LEN: B1 0x25]=0x12

SyncWord pattern defined by SYNCWORD_SEL ([DATA_SET2: B0 0x08(4)]) will be selected. B0 0x08(4)]) = 0b0

If the following registers are programmed, 24 bits of SYNCWORD2_SET [23:0] will be transmitted from higher bit

sequentially.

[SYNC_WORD_LEN: B1 0x25]=0x18

SyncWord pattern defined by SYNCWORD_SEL ([DATA_SET2: B0 0x08(4)]) will be selected. B0 0x08(4)]) = 0b1

2）RX

By setting SYNCWORD_SEL and 2SW_DET_EN ([DATA_SET2: B0 0x08(5)]), one pattern waiting or two patterns waiting

can be selected as shown in the following table. Packet format automatic detection is valid only when 2SW_DET_EN = 0b1

and Format A/B is selected. Packet format automatic detection result for two patterns waiting is indicated in

SW_DET_RSLT[STM_STATE: B0 0x77(5)]. B0 0x77(5)].

Automatic

SyncWord

2SW_DET_ SYNCWORD_

SyncWord pattern during

sync detection

packet

format

Data process after SyncWord

detection

operation

EN

SEL

detection

Waiting for

1 pattern

0

1

SYNCWORD_SET1[31:0]

SYNCWORD_SET2[31:0]

No

Process according to each Format setting

Waiting for

1 pattern

Process according to each Format setting

[Format A or Format B setting]

If matched with SYNCWORD1_SET,

process as Format A. If matched with

SYNCWORD2_SET, process as Format B.

SYNCWORD_SET1[31:0]

SYNCWORD_SET2[31:0]

Waiting for

2 patterns

1

-

Supported

[Format C setting]

Process as Format C

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Length of SyncWord pattern referred to at detection can be defined by SYNC_WORD_LEN ([SYNC_WORD_LEN: B1

0x25(5-0)]). In this case, SyncWord pattern of the SyncWord length from the lowest bit of SYNCWORD1_SET or

SYNCWORD2_SET will be the reference pattern.

Example) SyncWord length

If the following registers are set, 18 bits of SYNCWORD1_SET[17:0] or SYNCWORD2_SET[17:0] will be the

reference pattern for the SyncWord detection. Higher bits (bit31-18) are not checked.

[SYNC_WORD_LEN: B1 0x25]=0x12

[SYNC_WORD_EN: B1 0x26]=0x0F

32bit SyncWord pattern can be controlled by enabling/disabling by each 8bit, when receiving SyncWord. The following table

describes enable/disable control and SyncWord pattern. However, note that when the SyncWord length setting is outside the

range of bits for enable/disable control, the expected SyncWord detection is unavailable.

[SYNC_WORD_EN]

Register

SYNCWORD*_SET

SyncWord detection operation

[31:24]

[23:16]

[15:8]

[7:0]

(B1 0x26)

Prohibited

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Only [7:0] are valid.

Upon [7:0] detection, SyncWord detection.

Only [15:8] are valid.

Upon [7:0] detection, SyncWord detection.

Only [15:0] are valid.

Upon [7:0] detection, SyncWord detection.

Only [23:16] are valid.

Upon [7:0] detection, SyncWord detection.

Only [23:16] and [7:0] are valid.

Upon [7:0] detection, SyncWord detection.

Only [23:8] are valid.

D.C.(*1)

ON

D.C.

ON

D.C.

ON

D.C.

ON

D.C.

ON

D.C.

ON

Upon [7:0] detection, SyncWord detection.

Only [23:0] are valid.

Upon [7:0] detection, SyncWord detection.

Only [31:24] are valid.

ON

D.C.

Upon [7:0] detection, SyncWord detection.

Only [31:24] and [7:0] are valid.

Upon [7:0] detection, SyncWord detection.

Only [31:24] and [15:8] are valid.

Upon [7:0] detection, SyncWord detection.

Only [31:24] and [15:0] are valid.

Upon [7:0] detection, SyncWord detection.

[31:16] are valid.

Upon [7:0] detection, SyncWord detection.

Only [31:16] and [7:0] are valid.

Upon [7:0] detection, SyncWord detection.

[31:8] are valid.

ON

D.C.

ON

D.C.

ON

D.C.

ON

D.C.

ON

D.C.

ON

D.C.

ON

Upon [7:0] detection, SyncWord detection.

Whole [31:0] are valid.

Upon [7:0] detection, SyncWord detection.

ON

*1: D.C. stands for Don' t Care.

*2: Preamble pattern connecting with SyncWord can be added to the SyncWord detection conditions in addition to SyncWord

pattern. To include preamble pattern, set RXPR_LEN([SYNC_CONDITION1: B0 0x45(5:0)]).

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○Field Check Function

ML7456N RF part has a function for comparing the 9 bytes following C-field (Format A/B) or 9 bytes following Data-field

(Format C) in a receiving packet and notifying through an interrupt when matching or not matching (field check function).

Field check can be possible with the following register setting. The Field check function is enabled only in FIFO mode for

discriminating L-field (RXDIO_CTRL[DIO_SET: B0 0x0C(7-6)] = 0b00) and data output mode 2 of DIO mode

(RXDIO_CTRL[DIO_SET: B0 0x0C(7-6)]=0b11).

Function

RX data process setting when Field check

unmatched

Register

[C_CHECK_CTRL: B0 0x1B(7)]

Field check interrupt setting

C-field detection enable setting

M-field detection enable setting

A-field detection enable setting

C-field code setting

[C_CHECK_CTRL: B0 0x1B(6)]

[C_CHECK_CTRL: B0 0x1B(4-0)]

[M_CHECK_CTRL: B0 0x1C(3-0)]

[A_CHECK_CTRL: B0 0x1D(5-0)]

[C_FIELD_CODE1: B0 0x1E]

[C_FIELD_CODE2: B0 0x1F]

[C_FIELD_CODE3: B0 0x20]

[C_FIELD_CODE4: B0 0x21]

[C_FIELD_CODE5: B0 0x22]

[M_FIELD_CODE1: B0 0x23]

[M_FIELD_CODE2: B0 0x24]

[M_FIELD_CODE3: B0 0x25]

[M_FIELD_CODE4: B0 0x26]

[A_FIELD_CODE1: B0 0x27]

[A_FIELD_CODE2: B0 0x28]

[A_FIELD_CODE3: B0 0x29]

[A_FIELD_CODE4: B0 0x2A]

[A_FIELD_CODE5: B0 0x2B]

[A_FIELD_CODE6: B0 0x2C]

M-field code setting

A-field code setting

The following describes the relation between each comparison code and incoming RX data.

[Format A/B(Wireless M-Bus)]

Field check can be controlled by setting disabled/enabled for each comparison code (1byte). If all specified Field data

(C-field/M-field/A-field) are matched, Field checking matching will be notified. However, if C-field data and

C_FIELD_CODE5 are matched, even if other Field data (M-field/A-field) are not matched, Field check result will be notified

as ”match”.

LSB

MSB

1st Block

Sync

Word

Preamble

Data

field

L

field

CRC

field

1

n*2

or more

10/18/

32bit

1-2

byte byte

1

0/2

bytes

byte byte byte byte byte byte byte byte

A1

A2

A3

A4

A5

A6

C1 M1

C2 M2

C3

M3

M4

C1: [C_FIELD_CODE1: B0 0x1E]

C2: [C_FIELD_CODE 2: B0 0x1F]

C3: [C_FIELD_CODE 3: B0 0x20]

C4: [C_FIELD_CODE 4: B0 0x21]

C5: [C_FIELD_CODE 5: B0 0x22]

A1. [A_FIELD_CODE1: B0 0x27]

A2. [A_FIELD_CODE2: B0 0x28]

A3. [A_FIELD_CODE3: B0 0x29]

A4. [A_FIELD_CODE4: B0 0x2A]

A5. [A_FIELD_CODE5: B0 0x2B]

A6. [A_FIELD_CODE6: B0 0x2C]

C4

C5

M1. [M_FIELD_CODE 1: B0 0x23]

M2. [M_FIELD_CODE 2: B0 0x24]

M3. [M_FIELD_CODE 3: B0 0x25]

M4. [M_FIELD_CODE 4: B0 0x26]

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Check field

C-field

Comparison code

C_FIELD_CODE1 or C_FIELD_CODE2 or

C_FIELD_CODE3 or C_FIELD_CODE4 or

C_FIELD_CODE5

Conditions for match

Matches when one of the five comparison codes

matches.

M-field 1st byte

M-field 2nd byte

A-field

M_FIELD_CODE1 or

M_FIELD_CODE2

M_FIELD_CODE3 or

M_FIELD_CODE4

Matches when one of the two comparison codes

matches.

Matches when one of the two comparison codes

matches.

A_FIELD_CODE1/2/3/4/5/6

Matches when the comparison code matches.

[Format C]

Field check can be controlled by setting disabled/enabled for each comparison code (1byte). If all the Data-field data satisfy the

matching conditions shown in the following table, the Field check result will be notified as matching. However, if the 1st byte

of Data-field matches with C_FIELD_CODE5, the Field check result will be notified as matching even when other Field data

(from 2nd byte to 9th byte of Data-field) do not match.

LSB

MSB

1st Block

Sync

Word

Preamble

Data

field

L

field

･･･

1

n*2

or more

10/18/

32bit

1-2

byte byte

1

byte byte byte byte byte byte byte byte

A1

A2

A3

A4

A5

A6

C1 M1

C2 M2

C3

M3

M4

C1: [C_FIELD_CODE1: B0 0x1E]

C2: [C_FIELD_CODE 2: B0 0x1F]

C3: [C_FIELD_CODE 3: B0 0x20]

C4: [C_FIELD_CODE 4: B0 0x21]

C5: [C_FIELD_CODE 5: B0 0x22]

A1. [A_FIELD_CODE1: B0 0x27]

A2. [A_FIELD_CODE2: B0 0x28]

A3. [A_FIELD_CODE3: B0 0x29]

A4. [A_FIELD_CODE4: B0 0x2A]

A5. [A_FIELD_CODE5: B0 0x2B]

A6. [A_FIELD_CODE6: B0 0x2C]

C4

C5

M1. [M_FIELD_CODE 1: B0 0x23]

M2. [M_FIELD_CODE 2: B0 0x24]

M3. [M_FIELD_CODE 3: B0 0x25]

M4. [M_FIELD_CODE 4: B0 0x26]

Check field

Comparison code

Conditions for match

Data-field 1st byte

C_FIELD_CODE1 or C_FIELD_CODE2 or

C_FIELD_CODE3 or C_FIELD_CODE4 or

C_FIELD_CODE5

Matches when one of the five comparison codes

matches.

Data-field 2nd byte

Data-field 3rd byte

M_FIELD_CODE1 or

M_FIELD_CODE2

M_FIELD_CODE3 or

M_FIELD_CODE4

Matches when one of the two comparison codes

matches.

Matches when one of the two comparison codes

matches.

Data-field 4th byte

Data-field 5th byte

Data-field 6th byte

Data-field 7th byte

Data-field 8th byte

Data-field 9th byte

A_FIELD_CODE1

A_FIELD_CODE2

A_FIELD_CODE3

A_FIELD_CODE4

A_FIELD_CODE5

A_FIELD_CODE6

Matches when the comparison code matches.

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[Format D]

Field check can be controlled by setting disabled/enabled for each comparison code (1byte). If all the Data-field data satisfy the

matching conditions shown in the following table, the Field check result will be notified as matching. However, if the 1st byte

of Data-field matches with C_FIELD_CODE5, the Field check result will be notified as matching even when other Field data

(from 2nd byte to 9th byte of Data-field) do not match.

LSB

MSB

1st Block

Sync

Word

Preamble

Data

field

･･･

1

n*2

or more

10/18/

32bit

1

byte

byte byte byte byte byte byte byte byte

A1

A2

A3

A4

A5

A6

C1 M1

C2 M2

C3

M3

M4

A1. [A_FIELD_CODE1: B0 0x27]

A2. [A_FIELD_CODE2: B0 0x28]

A3. [A_FIELD_CODE3: B0 0x29]

A4. [A_FIELD_CODE4: B0 0x2A]

A5. [A_FIELD_CODE5: B0 0x2B]

A6. [A_FIELD_CODE6: B0 0x2C]

C4

C5

C1: [C_FIELD_CODE1: B0 0x1E]

C2: [C_FIELD_CODE 2: B0 0x1F]

C3: [C_FIELD_CODE 3: B0 0x20]

C4: [C_FIELD_CODE 4: B0 0x21]

C5: [C_FIELD_CODE 5: B0 0x22]

M1. [M_FIELD_CODE 1: B0 0x23]

M2. [M_FIELD_CODE 2: B0 0x24]

M3. [M_FIELD_CODE 3: B0 0x25]

M4. [M_FIELD_CODE 4: B0 0x26]

Check field

Comparison code

Conditions for match

Data-field 1st byte

C_FIELD_CODE1 or C_FIELD_CODE2 or

C_FIELD_CODE3 or C_FIELD_CODE4 or

C_FIELD_CODE5

Matches when one of the five comparison codes

matches.

Data-field 2nd byte

Data-field 3rd byte

M_FIELD_CODE1 or

M_FIELD_CODE2

M_FIELD_CODE3 or

M_FIELD_CODE4

Matches when one of the two comparison codes

matches.

Matches when one of the two comparison codes

matches.

Data-field 4th byte

Data-field 5th byte

Data-field 6th byte

Data-field 7th byte

Data-field 8th byte

Data-field 9th byte

A_FIELD_CODE1

A_FIELD_CODE2

A_FIELD_CODE3

A_FIELD_CODE4

A_FIELD_CODE5

A_FIELD_CODE6

Matches when the comparison code matches.

●Packet processing as a result of Field checking

By setting CA_RXD_CLR ([C_CHECK_CTRL: B0 0x1B(7)]) = 0b1, if the result of Field check is unmatched, the data packet

will be aborted and the state will become the next packet reception waiting state.

●Storing number of unmatched packets

Unmatched packets can be counted up to 2047 packets and results are indicated in [ADDR_CHK_CTR_H: B1 0x62] and

[ADDR_CHK_CTR_L: B1 0x63]. This count value can be cleared by STATE_CLR4([STATE_CLR: B0 0x16(4)]).

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○FIFO Control Function

ML7456N RF part has on-chip TX_FIFO(64Byte) and RX_FIFO(64Byte). As TX/RX_FIFO do not support multiple packets,

packet should be processed one by one. If RX FIFO keeps RX packet and next RX packet is received, RX FIFO will be

overwritten. It applies to TX FIFO as well.

When receiving, RX data is stored in FIFO (byte by byte) and the host MCU will read RX data through SPI. When transmitting,

host MCU write TX data to TX_FIFO through SPI and transmitting through RF.

Writing or reading to/from FIFO is through SPI with burst access. The data is written to [WR_TX_FIFO: B0 0x7C] register on

TX, read from [RD_FIFO: B0 0x7F] register on RX. Continuous access to the FIFO increments internal FIFO counter

automatically and data is saved or output. If FIFO access is suspended during write or read operation, address will be kept until

the packet process is completed. Therefore, when resuming FIFO access, next data will be resumed from the suspended address.

FIFO control register are as follows:

Function

Register

TX FIFO Full level setting

[TXFIFO_THRH: B0 0x17]

[TXFIFO_THRL: B0 0x18]

[RXFIFO_THRH: B0 0x19]

[RXFIFO_THRL: B0 0x1A]

[FIFO_SET: B0 0x78]

TX FIFO Empty level setting

RX FIFO Full level setting

RX FIFO Empty level setting

FIFO readout setting

RX FIFO data usage status indication

TX packet Length setting

RX packet Length setting

TX FIFO

[RX_FIFO_LAST: B0 0x79]

[TX_PKT_LEN_H/L: B0 0x7A/7B]

[RX_PKT_LEN_H/L: B0 0x7D/7E]

[WR_TX_FIFO: B0 0x7C]

FIFO read

[RD_FIFO: B0 0x7F]

TX – RX procedure using FIFO are as follows:

[TX]

(a) TX L-filed value is set to [TX_PKT_LEN_H: B0 0x7A], [TX_PKT_LEN_L: B0 0x7B]. If Length is 1 byte,

[TX_PKT_LEN_L] register will be transmitted.

Length setting can be set by LENGTH_MODE([PKT_CTRL: B0 0x05(1-0)]).

(b) TX data is written to FIFO.

[Note]

1. If TX data write sequence is aborted during transmission, [STATE_CLR: B0 0x16] (TX FIFO clear) must be issued.

Otherwise data pointer which manages data in the LSI keeps the status, preventing the proper FIFO process of the next

packet.

For example, when an interrupt notification of TX FIFO access error ([INT_SOURCE_GRP3: B0 0x0F(4)]) is received,

the TX data write sequence may be aborted. This interrupt can be generated when FIFO overrun (for example, data is

written to TX FIFO when there is no available space in it) or underrun (for example, a transmission is attempted when

FIFO is empty) occurs.

2. If the next writing sequence is performed when one packet data is stored, FIFO is overwritten.

3. Depending on the packet format, TX data Length value is different.

Format A: Data length excluding the Length and CRC areas is set as the Length value.

Format B: Data length excluding the Length area is set as the Length value.

Format C: Data length excluding the Length area is set as the Length value.

Format D: Data length from Data-field to CRC-field is set as the Length value.

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[RX]

(1) Format A/B/C

(a) Read the L-field value (Length) from [RX_PKT_LEN_H: B0 0x7D], [RX_PKT_LEN_L: B0 0x7E].

(b) Read RX data from FIFO.

When reading from RX FIFO, set FIFO_R_SEL([FIFO_SET: B0 0x78(0)]) = 0b0. B0 0x78(0)]) to 0b0. If

FIFO_R_SEL=0b1 , TX_FIFO will be selected.

Data usage value of RX FIFO is indicated by [RX_FIFO_LAST: B0 0x79] register.

(2) Format D

(a) Set the data length (Length value) to [RX_PKT_LEN_H: B0 0x7D], [RX_PKT_LEN_L: B0 0x7E].

(b) Read RX data from FIFO.

When reading from RX FIFO, set FIFO_R_SEL([FIFO_SET: B0 0x78(0)]) = 0b0. B0 0x78(0)]) to 0b0. If

FIFO_R_SEL=0b1 , TX_FIFO will be selected.

Data usage value of RX FIFO is indicated by [RX_FIFO_LAST: B0 0x79] register.

[Note]

1. If reading RX data is terminated before reading all data, RX FIFO clear ([STATE_CLR: B0 0x16]) must be issued.

Otherwise data pointer which manages data in the LSI keeps the status, preventing the proper FIFO process of the next

packet.

2. If 1 packet data is kept in the RX_FIFO, next RX data will be overwritten. Read all the necessary RX data before

receiving the next packet. Incidentally, to detect the next packet being received even though all the data has not been

read, the SyncWord detection interrupt (INT[13](INT_SOURCE_GRP2: B0 0x0E(5))) can be used.

3. Control FIFO so that FIFO overrun and underrun do not occur.

There are following methods for controlling FIFO so that FIFO overrun and underrun do not occur.

(a) Read RX FIFO usage ([RX_FIFO_LAST: B0 0x79]) and read that amount of data from FIFO.

(b) Set the Full level of RX FIFO ([RXFIFO_THRH: B0 0x19]), and after a FIFO-Full interrupt

(INT[5](INT_SOURCE_GRP1: B0 0x0D(5))) is generated, read data from FIFO up to the amount equivalent to

the Full level of RX FIFO.

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IF TX/RX packet is larger than FIFO size, FIFO access can be controlled easily by FIFO-Full trigger or FIFO-Empty trigger.

(1) TX FIFO usage notification function

This function is to notice TX_FIFO usage to the MCU using interrupt (SINTN). If the TX FIFO usage (un-transmitted data)

exceeds the threshold (FULL level) set by [TXFIFO_THRH: B0 0x17], an interrupt will occur to notify about it. Also, if

ML7456N RF part transmits data and the TX FIFO usage decreases under the threshold (EMPTY level) set by

[TXFIFO_THRL: B0 0x18], an interrupt will occur to notify about it. Interrupt signal (SINTN) can be output from GPIO* or

EXT_CLK pin. For output settings, refer to [GPIO0_CTRL: B0 0x4E], [GPIO1_CTRL: B0 0x4F], [GPIO2_CTRL: B0

0x50], [GPIO3_CTRL: B0 0x51], [EXTCLK_CTRL: B0 0x52].

[FIFO usage]

SINTN signal

0x3F

Notify with an

Clear interrupt

interrupt when the

amount of written

data exceeds the

FULL level.

TX data amount

FULL level

(Example 0x2E)

Notify with an

interrupt when TX

data usage

decreases under the

EMPTY level.

FULL level

0x2E

0x0F

EMPTY level

(Example 0x0F)

EMPTY level

Time

TX start timing by

FAST_TX trigger

TX_FIFO usage transition

0x00

[Note]

1. Do not set the notification levels of [TXFIFO_THRH] and [TXFIFO_THRL] to the same value.

Set them as satisfying the condition [TXFIFO_THRH] > [TXFIFO_THRL].

2. The Full detection state in LSI is cleared at Full trigger ([TXFIFO_THRH])>FIFO usage, allowing the next Full trigger

to be detected. Note that the above clear condition may be met during FIFO write, and the Full trigger may be detected,

depending on the timing of reading TX data (PHY) and FIFO write through SPI. To avoid such a case, disable the trigger

level setting after the Full trigger is detected, and enable it again after the FIFO write is completed.

3. The Empty detection state of the inside of the LSI is cleared when the FIFO usage becomes larger than or equal to the

Empty trigger ([TXFIFO_THRL]). After that, the next Empty trigger can be detected. Note that the above clear condition

may be met during FIFO write, and the Empty trigger may be detected, depending on the timing of reading TX data

(PHY) and FIFO write through SPI. To avoid such a case, make the trigger level setting disabled after the Empty trigger

is detected, and make it enabled again after the FIFO write is completed.

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(2) RX FIFO usage notification function

This function is to notify TX FIFO unread data amount (FIFO usage amount) by using interrupt (SINTN) to the MCU. When

the RX FIFO usage (un-read) exceeds the threshold set by [RXFIFO_THRH: B0 0x19] (FULL level), an interrupt will occur

to notify about it. Also, after MCU reads RX data and un-read data amount of RX FIFO (FIFO usage) decreases under the

threshold set by [RXFIFO_THRL: B0 0x1A] (EMPTY level), an interrupt will occur to notify about it. Interrupt signal

(SINTN) can be output from GPIO* or EXT_CLK pin. For output settings, refer to [GPIO0_CTRL: B0 0x4E],

[GPIO1_CTRL: B0 0x4F], [GPIO2_CTRL: B0 0x50], [GPIO3_CTRL: B0 0x51], [EXTCLK_CTRL: B0 0x52].

[FIFO usage]

SINTN signal

0x3F

Notify with an

Clear interrupt

interrupt when the

RX data amount

exceeds the FULL

level.

RX data amount

FULL level

(Example 0x3E)

Notify with an

interrupt when the

data usage after

data reading

decreases under

the EMPTY level.

Trigger level LH

Trigger level HL

0x3E

0x0F

EMPTY level

(Example 0x0F)

Time

RX FIFO usage transition

0x00

[Note]

1. Do not set the notification levels of [RXFIFO_THRH] and [RXFIFO_THRL] to the same value.

Set them as satisfying the condition [RXFIFO_THRH] > [RXFIFO_THRL].

2. The internal Full detection state is cleared at Full trigger ([RXFIFO_THRH])>FIFO usage, allowing the next Full trigger

to be detected. Note that the above clear condition may be met during FIFO read, and the Full trigger may be detected,

depending on the timing of writing RX data (PHY) and FIFO read through SPI. To avoid such a case, make the trigger

level setting disabled after the Full trigger is detected, and make it enabled again after the FIFO read is completed.

3. The internal Empty detection state is cleared when the FIFO usage becomes larger than or equal to the Empty trigger

([RXFIFO_THRL]). After that, the next Empty trigger can be detected. Note that the above clear condition may be met

during FIFO read, and the Empty trigger may be detected, depending on the timing of writing RX data (PHY) and FIFO

read through SPI. To avoid such a case, make the trigger level setting disabled after the Empty trigger is detected, and

make it enabled again after the FIFO read is completed.

4. This function is valid during data receiving. FIFO-Empty interrupt does not occur after RX completion.

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○DIO Function

Using GPIO0-3, EXT_CLK or SDI/SDO pins, TX/RX data can be input/output. Output pins are controlled by [GPIO*_CTRL:

B0 0x4E/0x4F/0x50/0x51], [EXTCLK_CTRL: B0 0x52], and [SPI/EXT_PA_CTRL: B0 0x53]. Data format for TX/RX are as

follows:

TX --- TX data (NRZ or Manchester/3-out-of-6coding) will be input.

RX --- pre-decoded RX data or decoded RX data will be output. (Selectable by [DIO_SET: B0 0x0C])

DIO function registers are as follows:

Function

DIO RX data output start setting

DIO RX completion setting

TX DIO mode setting

Register

[DIO_SET: B0 0x0C(0)]

[DIO_SET: B0 0x0C(2)]

[DIO_SET: B0 0x0C(5-4)]

[DIO_SET: B0 0x0C(7-6)]

RX DIO mode setting

(1) In case of using GPIO*, EXT_CLK pins

If GPIO0-3 pins are used for input/output of TX/RX data, DCLK/DIO should be controlled as follow. (below DIO/DCLK

vertical line part indicate output or input period)

[TX]

(a) Continuous input mode

Set TXDIO_CTRL([DIO_SET: B0 0x0C(5-4)]) to 0b01.

After TX_ON, the TX clock is output. At falling edge of the TX clock, TX data is input from the DIO pin. TX data must be

encoded data.

TX_ON

TX data

Preamble

SyncWord

Data-field

DIO(GPIO0-3,EXT_CLK)

DCLK(GPIO0-3,EXT_CLK)

TRX_OFF command

TX_ON command

* For details of timing, please refer to the “TX” in the “Timing Chart”.

(b) Data input mode

Set TXDIO_CTRL([DIO_SET: B0 0x0C(5-4)]) to 0b10.

After TX_ON, the TX clock is output from data input timing after SyncWord. At falling edge of the TX clock, TX data is

input from the DIO pin. TX data must be encoded data. Preamble and SyncWords generated automatically according to the

registers setting.

TX_ON

TX data

Preamble

SyncWord

Data-field

DIO(GPIO0-3,EXT_CLK)

DCLK(GPIO0-3,EXT_CLK)

TX_ON command

TRX_OFF command

Preamble can be set by PB_PAT([DATA_SET1: B0 0x07(7)], TXPR_LEN([TXPR_LEN_H/L: B0 0x42/43]). Also, SyncWord

can be set by SYNCWORD_SEL([DATA_SET2: B0 0x08(4)]), SYNCWORD_LEN([SYNC_WORD_LEN: B1 0x25]),

SYNC_WORD_EN*([SYNC_WORD_EN: B1 0x26), SYNCWORD1_SET([SYNCWORD1_SET3/2/1/0: B1 0x27/28/29/2A])

and SYNCWORD2_SET([SYNCWORD2_SET3/2/1/0: B1 0x2B/2C/2D/2E]).

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[RX]

(a) Continuous output mode

When RXDIO_CTRL([DIO_SET: B0 0x0C(7-6)]) = 0b01

After RX_ON, the RX clock is output continuously. RX data (demodulated data) is output from the DIO output pin at falling

edge of the RX clock. RX data is not buffered in FIFO.

RX_ON

RX data

Preamble

SyncWord

Data-field

DIO(GPIO0-3,EXT_CLK)

DCLK(GPIO0-3,EXT_CLK)

RX_ON command

TRX_OFF command

(b) Data output mode 1

Set RXDIO_CTRL([DIO_SET: B0 0x0C(7-6)]) to 0b10.

After SyncWord detection, RX data is buffered in RX FIFO. RX data buffering will continue until RX sync signal (SYNC)

becomes “L”. By RX data output setting DIO_START([DIO_SET: B0 0x0C(0)]), the buffered RX data will be output from

the first byte through the DIO interface (DIO/DCLK) (RX data is output at falling edge of the RX clock). However, when

RX data output setting is done after 64-byte time, data will be overwritten from the first byte. If all buffered data is output

until SYNC becomes “L”, RX completion interrupt (INT[8] group 2) will be generated. After RX completion, ready to

receive next packet.

RX_ON

RX data

Preamble

SyncWord

Data-field

RX sync signal

Buffering to FIFO

DIO(GPIO0-3,EXT_CLK)

DCLK(GPIO0-3,EXT_CLK)

DIO_START command

RX_ON command

TRX_OFF command

[Note]

1. RX data buffering in RX_FIFO is byte by byte access. DIO_START should be issued after 1 byte access time upon

SyncWord detection.

2. This mode does not process L-field. Field checking function is not supported.

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With this setting, when DIO_START is issued before SyncWord detection, data is not buffered in FIFO and RX data/clock is

output after SyncWord detection. In order to complete RX before SYNC becomes L, set DIO RX completion setting

(DIO_RX_COMPLETE([DIO_SET: B0 0x0C(2)])). After DIO_RX_COMPLETE setting, ready to receive the next packet.

RX_ON

RX data

Preamble

SyncWord

Data-field

RX sync signal

Buffering to FIFO

DIO(GPIO0-3,EXT_CLK)

DCLK(GPIO0-3,EXT_CLK)

DIO_START command

DIO_RX_COMPL

ETE command

RX_ON command

TRX_OFF command

(c) Data output mode 2

Set RXDIO_CTRL([DIO_SET: B0 0x0C(7-6)]) to 0b11.

Only Data-field of RX data is buffered in FIFO. RX data of the amount of Length indicated by L-field is buffered in FIFO.

By the RX data output setting (DIO_START([DIO_SET: B0 0x0C(0)])), buffered RX data is output from the first byte

through the DIO interface (DIO/DCLK). However, when RX data output setting is done after 64-byte time, data will be

overwritten from the first byte. If all data indicated by L-field is output, RX completion interrupt (INT[8] group2) will be

generated. After RX completion, ready to receive next packet. Received Length information is indicated in

[RX_PKT_LEN_H/L: B0 0x7D/7E]. This mode supports field check function.

RX_ON

RX data

Preamble

SyncWord

L-field

Data-field

DIO(GPIO0-3,EXT_CLK)

DCLK(GPIO0-3,EXT_CLK)

DIO_START

command

RX_ON command

TRX_OFF command

[Note]

1. RX data buffering in RX_FIFO is byte by byte access. DIO_START should be issued after elapsed time from SyncWord

detection to L-field length + over 1byte access time.

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(2) In case of using SDI/SDO pin (sharing with SPI interface)

When the SPI interface (SDI/SDO) is used to input/output TX/RX data, DCLK/DIO are controlled as follows. (below

DIO/DCLK vertical line part indicate output or input period) For the operation of LSI about each DIO mode, please refer to the

previous chapter “(1) In case of using GPIO*, EXT_CLK pins”.

[TX]

(a) Continuous input mode

Set TXDIO_CTRL([DIO_SET: B0 0x0C(5-4)]) to 0b01.

After a TX_ON command is issued ([RF_STATUS: B0 0x0B(3-0)] = 0x9), TX clock is output from the SDO pin while

SCEN is H. Input TX data from the SDI pin. After TRX_OFF([RF_STATUS: B0 0x0B(3-0)] = 0x8) command is issued,

input/output of TX data/clock will be disabled. In addition, even during DCLK output, if SCEN becomes L, the TX clock

output will stop (SPI access has priority).

TX_ON

TX data

Preamble

SyncWord

Data-field

SCEN

DIO(SDI)

DCLK(SDO)

TX_ON command

TRX_OFF command

(b) Data input mode

Set TXDIO_CTRL([DIO_SET: B0 0x0C(5-4)]) to 0b10.

After a TX_ON command is issued ([RF_STATUS: B0 0x0B(3-0)] = 0x9), TX clock is output from the SDO pin while

SCEN is H. Input TX data from the SDI pin. After TRX_OFF is issued (SET_TRX[3:0] ([RF_STATUS: B0

0x0B(3-0)])=0x8), TX data/clock input/output are invalid. In addition, even during TX clock output, if SCEN becomes L,

the TX clock output will stop (SPI access has priority).

TXON

Preamble

SyncWord

Data-field

TX data

SCEN

DIO(SDI)

DCLK(SDO)

TX_ON command

TRX_OFF command

[Note]

If SPI access is attempted during packet transmission, SPI access has a higher priority while the TX operation is continuing,

thus TX data error can be expected. Do not attempt access SPI before TX completion.

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[RX]

(a) Continuous output mode

When RXDIO_CTRL([DIO_SET: B0 0x0C(7-6)]) = 0b01

After RX_ON command is issued (([RF_STATUS: B0 0x0B(3-0)] = 0x6), RX clock is output from the SDO pin and RX

data is output from the SDI pin while SCEN is H. After TRX_OFF issuing, DCLK/DIO output will stop. In addition, even

during RX data/clock output, if SCEN becomes L, the RX data/clock output will stop (SPI access has priority).

RX_ON

TX data

Preamble

SyncWord

Data-field

SCEN

DIO(SDI)

DCLK(SDO)

RX_ON command

TRX_OFF command

[Note]

During packet reception, if SPI access is attempted by the host, RX data error can be expected. At this time, reception data is not

output causing missing bits, so do not conduct SPI access until reception is completed.

(b) Data output mode 1 or data output mode 2

Set RXDIO_CTRL([DIO_SET: B0 0x0C(7-6)]) to 0b10/11.

After RX_ON command is issued ([RF_STATUS: B0 0x0B(3-0)] = 0x6), RX clock is output from the SDO pin and RX data

is output from the SDI pin while SCEN is H. After TRX_OFF issuing, DCLK/DIO output will stop. In addition, even during

RX data/clock output, if SCEN becomes L, the RX data/clock output will stop (SPI access has priority).

RX_ON

TX data

Preamble

SyncWord

Data-field

SCEN

DIO(SDI)

DCLK(SDO)

RX_ON command

DIO_START

command

DIO_RX_COMPL

ETE command

TRX_OFF

command

[Note]

During packet reception, if SPI access is attempted by the host, RX data error can be expected. At this time, reception data is not

output causing missing bits, so do not conduct SPI access until reception is completed.

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(3) DCLK output method

The DCLK output method depends on the DIO mode setting.

(a) Data output mode 2 (RXDIO_CTRL([DIO_SET: 0x0C(7-6)]) = 0b11)

In this mode, decoded data is output. The DCLK output section in an output interval varies depending on the encoding

method. DCLK output section is as follows.

DCLK

Clock output (8 cycle)

1 cycle=1/data rate[bps]

Output interval

NRZ : 8 cycle

Manchester : 16 cycle

3 out of 6 : 12 cycle

(b) Mode other than (a) (RX continuous output mode/data output mode 1, TX continuous input mode/data input mode)

In this mode, undecoded data is input or output. DCLK is output continuously. It does not depend on the encoding method.

TX continuous input mode or RX continuous mode

DCLK

1 cycle=1/data rate[bps]

(*) The number of cycle per 1 byte

NRZ : 8 cycle

Manchester : 16 cycles

3 out of 6 : 12 cycle

TX Data input mode / RX Data output mode 1

DCLK

1 cycle=1/data rate[bps]

TX: SyncWord final 2 bits TX timing

(*) The number of cycle per 1 byte

NRZ : 8 cycle

RX: DIO_START command

Manchester : 16 cycles

3 out of 6 : 12 cycle

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○FEC (Forward Error Correction) Function

This LSI is equipped with FEC and interleaver complying with IEEE802.15.4g.

FEC registers are as follows:

Function

Register

FEC_EN([FEC_CTRL: B6 0x02(0)])

FEC_SCHEME([FEC_CTRL: B6 0x02(1)])

INTLV_EN([FEC_CTRL: B6 0x02(2)])

FEC setting

FEC scheme setting

Interleave setting

[Note]

1. To use the FEC function, use it with the following settings.

(a) Set TX data encoding mode setting (TX_DEC_SCHEME([DATA_SET1: B0 0x07(1-0)])) and RX data encoding

mode setting (RX_DEC_SCHEME([DATA_SET1: B0 0x07(3-2)])) to NRZ.

(b)Use Format C (PKT_FORMAT([PKT_CTRL1: B0 0x04(1-0)]) = 0b10) as the packet format.

(c) Set the Length field length setting to 2-byte mode (LENGTH_MODE([PKT_CTRL2: B0 0x05(1-0)]) = 0b01).

2. When receiving data undergone Whitening, enable the Whitening setting (WHT_SET([DATA_SET2: B0 0x08(0)]) =

0b1) before receiving.

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●Timer Function

○Wake-up Timer

ML7456N RF part has automatic wake-up function using wake-up timer. The following operations are possible by using

wake-up timer.

•

Upon timer completion, automatically wake-up from SLEEP state. Operation after wake-up can be selected from state

changes to RX_ON state and TX_ON state by WAKEUP_MODE([SLEEP/WU_SET: B0 0x2D(6)]).

By setting WUT_1SHOT_MODE[SLEEP/WU_SET] B0 0x2D(7)]), repetitive wake-up operations (interval operation) or

a single operation (one-shot operation) can be selected.

•

In interval operation, if RX_ON /TX_ON state is caused by wake-up timer, continuous operation timer is in operation..

After moving to the RX_ON state by the wake-up timer, when the continuous operation timer is completed, move to the

SLEEP state automatically. However, if SyncWord is detected before timer completion, RX_ON state will be maintained.

In this case, ML7406 does not go back to the SLEEP state automatically. SLEEP setting (SLEEP_EN ([SLEEP/WU_SET:

B0 0x2D(0)]) = 0b1) is necessary to go back to the SLEEP state. However if RXDONE_

MODE[1:0]([RF_STATUS_CTRL:B0 0x0A(3-2)]) =0b11, after RX completion, move to SLEEP state automatically.

The timing to determine whether or not to continue RX after continuous operation timer completion is selectable from

SyncWord detection, Field check detection, and synchronization detection by RCV_CONT_SEL([M_CHECK_CTRL: B0

0x1C(5:4)]).

•

After moving to the TX_ON state by the wake-up timer, automatic return to the SLEEP state is not made even when the

continuous operation timer is completed. To enter the SLEEP state after the completion of TX operation, configure the

SLEEP setting (SLEEP_EN ([SLEEP/WU_SET: B0 0x2D(0)])=0b1).

•

After wake-up by combining with high speed carrier checking mode, CCA is automatically performed, if IDLE is detected,

able to move to SLEEP state immediately. For details, please refer to the “(3) high speed carrier detection mode”.

By setting WUT_CLK_SOURCE ([SLEEP/WU_SET:B0 0x2D(2)]), the clock source for wake-up timer can be selected

from EXT_CLK pin or on-chip RC OSC circuit.

Wake-up interval, wake-up timer interval and continuous operation timer can be calculated in the following formula.

Wake-up interval [s] = Wake-up timer interval [s] + Continuous operation timer [s]

Wake-up timer interval [s] = Wake-up timer clock cycle *

Division setting ([WUT_CLK_SET: B0 0x2E(3-0)]) *

(Wake-up timer interval setting ([WUT_INTERVAL_H/L: B0 0x2F/0x30]) + 1)

Continuous operation timer [s] = Wake-up timer clock cycle *

Division setting ([WUT_CLK_SET: B0 0x2E(7-4)]) *

(Continuous operation timer operating time setting ([WU_DURATION: B0 0x31]) – 1)

[Note]

1. When set to move to TX_ON after wake-up, if the continuous operation timer is completed during TX, it is judged as

TX in progress and TX continues. After TX is completed, RF state transition is performed according to

TXDONE_MODE([RF_STATUS_CTRL: B0 0x0A(1-0)]) setting.

2. WUDT_CLK_SET ([WUT_CLK_SET: B0 0x2E(7-4)]) and WUT_CLK_SET ([WUT_CLK_SET: B0 0x2E(3-0)]) of

dividing setting can be set independently. When using the continuous operation timer, set the same setting to

WUDT_CLK_SET and WUT_CLK_SET.

3. The minimum setting for wake-up timer setting interval ([WUT_INTERVAL_H/L: B0 0x2F/0x30]) is 0x02. The

minimum setting for continuous operation timer operating time setting ([WU_DURATION: B0 0x31]) is 0x01. Note

that continuous operation timer operating time setting should be set so that the timer completion is occurred after a

notification of a clock stabilization completion interrupt (INT[0]([INT_SOURCE_GRP1: B0 0x0D(0)])) caused by

wake-up.

4. Since SyncWord detection is not conducted during reception of DIO mode set to RXDIO_CTRL([DIO_SET: B0

0x0C(7-6)]) = 0b01, after continuous operation timer is completed, the state moves to the SLEEP state forcibly. Note

that the SyncWord detection is not issued when in DIO mode with RXDIO_CTRL([DIO_SET: B0 0x0C(7-6)])=0b01.

Therefore, when continuous operation timer completed, forcibly move to SLEEP state.

5. ML7456N RF part automatically moves to the SLEEP state by timer operation, and if the SLEEP state transition and a

SPI access occurs at the same time, the SPI access will become invalid. Please take some measure so that SLEEP state

transition and SPI access do not happen at the same time.

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(1) Interval operation

(a) RX

After wake-up, RX_ON state. If continuous operation timer completed before SyncWord detection, automatically return to

SLEEP state. If SyncWord detected, continue RX_ON. After RX completion, continue operation defined by

RXDONE_MODE[1:0] ([RF_STATUS_CTRL: B0 0x0A(3-2)]). In addition, the state can be moved to the SLEEP state by

setting SLEEP_EN(SLLEP/WU_SET:B0 0x2D(0)] = 0b1.

When [SLEEPWU_SET: B0 0x2D(6-4)] = 0b011 is set

Wake-up timer operation period

[WUT_INTERVAL_H/L: B0 0x2F/0x30]

Continuous operation timer range

[WU_DURATION: B0 0x31]

Wake-up timer

Continuous

operation timer

RXON

TXON

SLEEP

RXON

SLEEP

RXON

SLEEP

RXON

SLEEP

SLEEP RXON

RXON

LSI State

Wake up operation

enable setting

After Wake-up timer

completion , move to

RX_ON state

SyncWord detection

before continuous

operation timer

completion

After RX completion

move to the SLEEP

state by a SLEEP

command

Move to the SLEEP

state due to continuous

operation timer

completion

(b) TX

After wake-up, TX_ON state. After TX completion, operate according to TXDONE_MODE[1:0] ([RF_STATUS_CTRL: B0

0x0A(1-0)]). Even when the continuous operation timer is completed, a return to the SLEEP state is not made. Therefore, set

SLEEP_EN(SLLEP/WU_SET:B0 0x2D(0)] = 0b1 after completion of TX operation to enter the SLEEP state.

When [SLEEPWU_SET: B0 0x2D(6-4)] = 0b111 is set

Wake-up timer operation period

Continuous operation timer range

[WU_DURATION: B0 0x31]

[WUT_INTERVAL_H/L: B0 0x2F/0x30)

Wake-up timer

Continuous

operation timer

RXON

TXON

SLEEP

TXON

IDLE

SLEEP

LSI State

Wake-up operation

enable setting

TX data

Write TX data

to TX FIFO

TX completion

and move to IDLE

state.

Move to the SLEEP

state by a SLEEP

command

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(2) One-shot operation

(a) RX

After wake-up timer completion, move to RX_ON state. And continue RX_ON state. Move to SLEEP state by SLEEP

command. Since wake-up timer setting interval ([WUT_INTERVAL_H/L: B0 0x2F/0x30]) is maintained, after a SLEEP

command is issued, the one-shot operation will restart. Clear the wake-up interrupt ([INT_SOURCE_GRP1: B0 0x0D(6)])

before moving to the SLEEP state. If RX completed during RX_ON, continue operation defined by RXDONE_ MODE[1:0]

([RF_STATUS_ CTRL: B0 0x0A(3-2)]) . Same manner in TX_ON state.

When [SLEEP/WU_SET: B0 0x2D(7-4)] = 0b1001 is set

Wake-up timer operation period

[WUT_INTERVAL_H/L: B0 0x2F/0x30]

Wake-up timer

Continuous

operation timer

RXON

TXON

RXON

SLEEP

RXON

SLEEP

LSI State

RX_ON is maintained

if SLEEP command is

not issued

Wake-up operation

enable setting

Move to the SLEEP

state by a SLEEP

command

Wake-up timer

completion and move

to RXON state

(3) Combination with high speed carrier detection

(a) Interval operation

After wake-up timer completion, move to RX_ON state. And perform CCA to check carrier. If no carrier is detected,

automatically move to SLEEP state. If carrier detected, maintaining RX_ON state and perform SyncWord detection. If

continuous operation timer completed before SyncWord detection, automatically move to SLEEP state. And If SyncWord

detected, continue RX_ON state state.

[SLEEP/WU_SET: B0 0x2D(7-4)]=0b0011

When FAST_DET_MODE_EN([CCA_CTRL: B0 0x39(3)]) = 0b1 is set

Wake-up timer operation period

[WUT_INTERVAL_H/L: B0 0x2F/0x30]

Continuous operation timer range

[WU_DURATION: B0 0x28]

Wake-up timer

Continuous

operation timer

RXON

TXON

SLEEP

RXON

Wake-up operation

enable setting

RXON

SLEEP

RXON

SLEEP

SLEEP RXON

RXON

LSI State

After RX completion,

move to the SLEEP

state by a SLEEP

command

No carrier is detected

by carrier check, so

move to the SLEEP

state

Move to the SLEEP

state due to continuous

operation timer completion

SyncWord detection

before continuous

operation timer

completion

Carrier is detected by

carrier check, so

continue RXON

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(b) One-shot operation

After wake-up timer completion, move to RX_ON state. And perform CCA to check carrier. If no carrier is detected,

automatically move to SLEEP state. In case of no carrier detection, if periodic waking up at wake-up timer interval is necessary,

clear the wake-up interrupt ([INT_SOURCE_GRP1: B0 0x0D(6)]) before moving to the SLEEP state. If carrier is detected,

continue RX state. Able to go back to SLEEP by setting SLEEP parameters.

When [SLEEPWU_SET: B0 0x2D(7-4)]=0b1001

When FAST_DET_MODE_EN([CCA_CTRL: B0 0x39(3)]) = 0b1 is set

Wake-up timer operation period

[WUT_INTERVAL_H/L: B0 0x2F/0x30]

Wake-up timer

Continuous

operation timer

RXON

TXON

RXON

SLEEP

RXON

SLEEP

RXON

SLEEP

LSI State

Wake-up operation

enable setting

Move to the SLEEP

state by a SLEEP

command

No carrier is detected

by carrier check, so

move to the SLEEP

state

No carrier is detected

by carrier check, so

move to the SLEEP

state

Clear wake-up interrupt

○General Purpose Timer

This LSI has general purpose timer. 2 channels of timer are able to function independently. Clock sources, timer setting can be

programmed independently. This timer uses 1-shot operation. When timer is completed, General purpose timer 1 interrupt

(INT[22] group3) or General purpose timer 2 interrupt (INT[23] group3) will be generated.

General timer interval can be programmed as the following formula.

General purpose timer interval [sec] = general purpose timer clock cycle *

Division setting ([GT_CLK_SET: B0 0x33]) *

After general purpose timer interval setting ([GT1_TIMER: B0 0x35]) B0 0x34] or

[GT2_TIMER: B0 0x35])

By setting GT2/1_CLK_SOURCE [GT_SET: B0 0x32(5,1)], the clock source for general purpose timer is selectable from

wake-up timer clock and 2 MHz.

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●Frequency Setting Function

○Channel Frequency Setting

Maximum 256 channel frequencies can be set (CH#0 to CH#255). The setting of TX/RX frequencies can be performed by the

following registers.

Frequency

CH#0 frequency

Register

[TXFREQ_I: B1 0x1B]、[TXFREQ_FH: B1 0x1C]、[TXFREQ_FM: B1 0x1D] and

[TXFREQ_FL: B1 0x1E]

[RXFREQ_I: B1 0x1F]、[RXFREQ_FH: B1 0x20]、[RXFREQ_FM: B1 0x21] and

[RXFREQ_FL: B1 0x22]

TX

RX

Channel spacing

Channel setting

[CH_SPACE_H: B1 0x23] and [CH_SPACE_L: B1 0x24]

[CH_SET: B0 0x09]

[PLL_DIV_SET: B1 0x1A]

PLL dividing setting

[Channel frequency setting]

Using above registers, channel frequency is defined as following formula.

Channel frequency = CH#0 frequency + Channel spacing * Channel setting

[Channel frequency allocation image]

iii) Channel setting

ii) Channel space setting

(setting Nth channel)

Channel No. →

0

1

2

3

・・・

n

・・・ 255

Frequency

i) CH#0 frequency setting

Set the PLL dividing setting according to the RF frequency (for each frequency band) as shown below.

PLL dividing setting

[PLL_DIV_SET: B1 0x1A]

315 to 510 MHz band

900 MHz band

0x02

0x00

(divided by 2)

(divided by 1)

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[Note]

(1) The channel frequency to be selected must meet the following conditions. If the following conditions cannot be met, please

change channel #0 frequency or use other channels. If this formula cannot be met, expected frequency is not functional or

PLL may not be locked.

F_MCK1: Master clock frequency

N_div= 1,2

(F_MCK1*n + 1 MHz) / N_div≤ Used channel frequency ≤ (F_MCK1* (n + 1) - 1 MHz) / N_div

* n = integer

Concept diagram

Unusable Frequency

Usable frequency

(a)

Frequency

(FMCK1×n )/N_div

(FMCK1×(n+1))/N_div

(Example of calculating Range (a) shown above)

For 1 division mode (N_div = 1), master clock 36 MHz, n = 25

(36 MHz x 25 + 1) MHz ≤ Channel frequency to be used ≤ (36 MHz x (25 + 1) - 1)

=> 901 MHz ≤ Channel frequency to be used ≤ 935 MHz

(2) CH#0 frequency and channel interval settings may have error. Therefore, channel frequency has frequency error indicated by

the following formula.

Channel frequency error [Hz] = CH#0 frequency error [Hz] + Channel interval setting error [Hz] * Channel setting

When changing “channel frequency” by setting “channel setting” without “CH#0 frequency” change, the “channel frequency

error” will become larger than by setting both “CH#0 frequency” and “channel setting”. If the “channel frequency error”

becomes larger, please change “CH#0 frequency”.

(3) If the 26-bit channel frequency ( = CH#0 frequency + Channel spacing x Channel setting) setting value (integer and decimal

parts, refer to “Channel #0 frequency setting”) exceeds the maximum value 0x3FF_FFFF, the expected channel frequency is

not achieved. Take this maximum value into account when deciding the channel #0 frequency, channel interval, and channel

setting.

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(1) Channel #0 frequency setting

TX frequency can be set by [TXFREQ_I: B1 0x1B], [TXFREQ_FH: B1 0x1C], [TXFREQ_FM: B1 0x1D] and

[TXFREQ_FL: B1 0x1E], and RX frequency can be set by [RXFREQ_I: B1 0x1F], [RXFREQ_FH: B1 0x20],

[RXFREQ_FM: B1 0x21] and [RXFREQ_FL: B1 0x22].

Refer to “Channel Frequency Setting” for N_div.

Channel #0 frequency setting value can be calculated using the following formula.

f_rf

I =

(Integer part)

f_ref/ N_div













f_rf

F =

− I 2²⁰(Integer part)





f / N

ref

div

Where

f_rf

: Channel #0 frequency

f_ref

: PLL reference frequency ( = master clock frequency: F_MCK1

)

I

F

N_div

: Integer part of frequency setting

: Fractional part of frequency setting

: Division setting (1 or 2)

I

(hex) is set to [TXFREQ_I: B1 0x1B] and [RXFREQ_I: B1 0x1F]. Also,

For TX, set [TXFREQ_FH: B1 0x1C], [TXFREQ_FM: B1 0x1D] and [TXFREQ_FL: B1 0x1E] in this order from MSB.

For RX, set [RXFREQ_FH: B1 0x20], [RXFREQ_FM: B1 0x21] and [RXFREQ_FL: B1 0x22] in this order from MSB.

F

(hex) is set to the following registers.

Frequency error f_erris calculated as follows :

F

2²⁰











f_err= I +

( f / N_div) − f_rf



ref

[Example] When setting TX CH#0 frequency f_rfto 920 MHz (master clock 36 MHz, Ndiv = 1), following calculations

are performed.

920MHz

I =

(Integer part) =25(0x19)

(36MHz /1)









920MHz

F =

− 25  2²⁰

(Integer part)=582542(0x8E38E)





(36MHz /1)

[TXFREQ_I: B1 0x1B] =

[TXFREQ _FH: B1 0x1C] =

[TXFREQ _FM: B1 0x1D] =

[TXFREQ _FL: B1 0x1E] =

0x19

0x08

0xE3

0x8E

Frequency error f_erris calculated as follows:

582542

2²⁰









f_err= 25 +

 (36MHz /1) − 920MHz = 0Hz





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(2) Channel space setting

Channel space can be set by [CH_SPACE_H: B1 0x23] and [CH_SPACE_L: B1 0x24]. Convert the channel space

calculated by the following formula into hexadecimal value and set it to [CH_SPACE_H: B1 0x23] and [CH_SPACE_L: B1

0x24] in this order from MSB.

Channel space is from the center frequency of given channel to adjacent channel center frequency.

Refer to “Channel Frequency Setting” for N_div.

The setting values of [CH_SPACE_H: B1 0x23] and [CH_SPACE_L: B1 0x24] are obtained by the following formula.











_div



f_sp

CH _ SPACE =

2²⁰(Integer part)





f / N

ref

Where,

CH _ SPACE :Channel space setting

f_sp:Channel space [MHz]

f_ref

:

PLL reference frequency ( = master clock frequency: F_MCK1

)

_div: Division setting (1 or 2)

N

[Example] When setting channel space to 400 kHz (master clock 36 MHz, Ndiv = 1), following calculation is performed.

0.4MHz













CH _ SPACE =

 2²⁰(Integer part) = 11650(0x2D82)

36MHz /1

[CH_SPACE_H: B1 0x23] = 0x2D

[CH_SPACE_L: B1 0x24] = 0x82

○IF Frequency Setting

IF frequency is set by [IF_FREQ: B0 0x61]. See the following table for the IF frequency for each IF frequency setting value.

These can be set separately for the normal receiving mode and during CCA.

IF_FREQ([IF_FREQ: B0 0x61(2-0)]

IF frequency (*1)

IF_FREQ_CCA([IF_FREQ: B0 0x61(6-4)]

0b000

0b001

0b010

0b011

0b100

0b101

0b110

0b111

225kHz

150kHz

Prohibited

112.5kHz

Prohibited

75kHz

180kHz

0kHz

(*1) These IF frequency values are for a master clock of 36MHz. When using another frequency as master clock, the IF frequency varies

depending on the amount of frequency change from 36 MHz.

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●Modulation Function

○ FSK Modulation

To use FSK modulation, set MOD_TYPE([MOD_CTRL: B6 0x01(1-0)]) = 0b00.

(1) GFSK modulation setting

To use GFSK mode, GFSK_EN([DATA_SET1: B0 0x07(4)])=0b1 should be set. In GFSK modulation, frequency

deviation can be set by [GFSK_DEV_H: B1 0x30] and [GFSK_DEV_L: B1 0x31] registers, and the filter coefficient of

Gaussian filter can be set by [FSK_DEV0_H/ GFIL0: B1 0x32] to [FSK_DEV3_H: B1 0x38] registers. 2FSK/4FSK can

be selected by FSK_SEL[DATA_SET2: B0 0x08(5)].

Refer to “Channel Frequency Setting” for N_div.

(a) GFSK frequency deviation setting

F_DEV value can be calculated as the following formula:











_div



f_dev

F _ DEV =

2²⁰(Integer part)





f / N

ref

Where,

f_dev

f_ref

:

Frequency deviation [Hz]

PLL reference frequency ( = master clock frequency: F_MCK1

)

_div: Division setting (1 or 2)

N

In 4GFSK mode, the value of maximum frequency deviation should be specified.

[Example] When setting frequency deviation to 50 kHz, the setting value for the case of f_REF= 36 MHz and N_div= 1 is

calculated as follows.

F_DEV = {0.05 MHz ÷ (36 MHz/1)} x 2²⁰(integer value) = 1456 (0x05B0)

Here, [GFSK_FDEV_H/L: B1 0x30/31] should be set as below:

[GFSK_DEV_H: B1 0x30] = 0x05

[GFSK_DEV_L: B1 0x31] = 0xB0

(b) Gaussian filter setting

GFSK mode can be set by GFSK_EN([DATA_SET1: B0 0x07(4)])=0b1.

The BT value of the Gaussian filter can be set by the following registers.

Here is the relationship between the BT value and the register setting.

BT value

Register

0.5

1.0

[FSK_DEV0_H/GFIL0: B1 0x32]

[FSK_DEV0_L/GFIL1: B1 0x33]

[FSK_DEV1_H/GFIL2: B1 0x34]

[FSK_DEV1_L/GFIL3: B1 0x35]

[FSK_DEV2_H/GFIL4: B1 0x36]

[FSK_DEV2_L/GFIL5: B1 0x37]

[FSK_DEV3_H/GFIL6: B1 0x38]

0x24

0xD6

0x19

0x29

0x3A

0x48

0x4C

0x00

0x02

0x0C

0x31

0x74

0x9A

[Note]

GFSK filter coefficient setting register and FSK frequency deviation setting register are common. In GFSK mode, filter

coefficient applies to this register. In FSK mode, frequency deviation applies to this register.

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(2) FSK modulation setting

FSK mode can be set by GFSK_EN([DATA_SET1: B0 0x07(4)])=0b0. Also, fine frequency deviation can be set by

[FSK_DEV0_H/GFIL0: B1 0x32] - [FSK_DEV4_L: B1 0x3B]. By adjusting the setting value of [FSK_TIM_ADJ4: B1

0x3C] - [FSK_TIM_ADJ0: B1 0x40], FSK timing can be fine tuned. 2FSK/4FSK can be selected by

FSK_SEL[DATA_SET2: B0 0x08(5)].

[2FSK]

v

iv

iii

(d)(c)(b)(a)

(a)(b)(c) (d) (e)

ii

i

(e) (d) (c)(b)(a)

(a)(b)(c) (d) (e)

i

ii

iii

iv

v

1 output

(When B0 0x07(6) = 0b0)

0 output

(When B0 0x07(6) = 0b0)

Frequency deviation setting

Time setting

Symbol

i

Register name

Address

Function

Symbol

(a)

Register name

Address

Function

FSK_FDEV0_H/GFIL0

FSK_FDEV0_L/GFIL1

FSK_FDEV1_H/GFIL2

FSK_FDEV1_L/GFIL3

FSK_FDEV2_H/GFIL4

FSK_FDEV2_L/GFIL5

FSK_FDEV3_H/GFIL6

FSK_FDEV3_L

B1 0x32/33

FSK_TIM_ADJ4

B1 0x3C

ii

iii

iv

v

(b)

(c)

(d)

(e)

B1 0x34/35

B1 0x36/37

B1 0x38/39

B1 0x3A/3B

FSK_TIM_ADJ3

FSK_TIM_ADJ2

FSK_TIM_ADJ1

FSK_TIM_ADJ0

B1 0x3D

B1 0x3E

B1 0x3F

B1 0x40

Modulation

timing

4 MHz/12 MHz

counter value

(*1)

Frequency

deviation

approx. 34

(Hz)

FSK_FDEV4_H

FSK_FDEV4_L

(*1) Modulation timing resolution can be switched by FSK_CLK_SET ([FSK_CTRL: B1 0x2F(0)]).

[Note]

GFSK filter coefficient setting register and FSK frequency deviation setting register are common. In GFSK mode, filter

coefficient applies to this register. In FSK mode, frequency deviation applies to this register.

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[4FSK]

(a)(b)(c)(d) (e) (d)(c)(b)(a)

4th freq. dev.

3rd freq. dev.

2nd freq. dev.

1st freq. dev.

v

iv

iii

ii

i

Carrier freq.

10 output (*1)

00 output (*1)

01 output (*1)

11 output (*1)

(*1) The mapping of the data (00/101/0/11) for each frequency deviation (1st to 4th) can be changed by [4FSK_DATA_MAP:

B1 0x40].

(*2) If the frequency is changed by 2 levels such as from 1st to 3rd frequency deviation, the amount of the frequency change is 2

times as much as i to v. If the frequency is changed by 3 levels such as from 1st to 4th frequency deviation, the amount of

the frequency change is 3 times as much as i to v.

The table below indicates the frequency deviation setting. The parameter of calculation formula is the register bit name.

Frequency deviation setting

Symbol

Formula

Address

Function

i

ii

iii

iv

v

FSK_FDEV4 - FSK_FDEV3

FSK_FDEV4 - FSK_FDEV2

FSK_FDEV4 - FSK_FDEV1

FSK_FDEV4 - FSK_FDEV0

FSK_FDEV4

B1 0x3A/3B, B1 0x38/39

B1 0x3A/3B, B1 0x36/37

B1 0x3A/3B, B1 0x34/35

B1 0x3A/3B, B1 0x32/33

B1 0x3A/3B

Frequency deviation

approx. 34 (Hz)

Time setting

Symbol

(a)

Register name

FSK_TIM_ADJ4

FSK_TIM_ADJ3

FSK_TIM_ADJ2

FSK_TIM_ADJ1

FSK_TIM_ADJ0

Address

B1 0x3C

B1 0x3D

B1 0x3E

B1 0x3F

B1 0x40

Function

Modulation timing

4 MHz/12 MHz counter

(b)

(c)

(d)

(e)

value

(*1)

(*1) Modulation timing resolution can be switched by FSK_CLK_SET ([FSK_CTRL: B1 0x2F(0)]).

[Note]

GFSK filter coefficient setting register and FSK frequency deviation setting register are common. In GFSK mode, filter

coefficient applies to this register. In FSK mode, frequency deviation applies to this register.

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○BPSK Modulation

This LSI is equipped with the following two methods for BPSK modulation.

･ Phase switching method

Switch the phase of carrier signal between 0 and 180 ° according to TX data.

･ Frequency control method

Control the frequency of carrier signal according to TX data to switch the phase.

Phase switching and

amplitude control are

performed at a data

changing point.

BPSK modulation waveform (PA output image)

Modulation is performed through phase switching and PA (amplitude) control.

The following registers need to be set for BPSK method/PA control setting. For the setting value, use the value specified in

“Initialization Table”.

BPSK method

Bit name

Address

Phase

switching

✓ (0b01)

✓ (0b0)

✓ (0b1)

-

Phase

switching

✓ (0b01)

✓ (0b1)

✓

MOD_TYPE[1:0]

BPSK_PLL_CTRL

GFSK_EN

[MOD_CTRL: B6 0x01(1-0)]

[BPSK_PLL_CTRL: B0 0x7B(0)]

[DATA_SET1: B0 0x07(4)]

[BPSK_PLL_CTRL: B6 0x7B(1)]

[BPSK_P_START_H/L: B6

0x7C(2-0)/7D(7-0)]

BPSK_P_CLKEL

✓

BPSK_P_START[10:0]

BPSK_P_HOLD[11:0]

-

[BPSK_P_HOLD_H/L: B6

0x7E(3-0)/7F(7-0)]

BPSK_STEP_EN

BPSK_STEP_SEL

BPSK_CLK_SEL

[BPSK_STEP_CTRL:B10 0x01(4)]

[BPSK_STEP_CTRL:B10 0x01(5)]

[BPSK_STEP_CTRL:B10 0x01(6)]

[BPSK_STEP_CTRL:B10 0x01(0)]

✓ (0b1)

✓

BPSK_CLK_SET[8:0]

[BPSK_STEP_CLK_SET:B10

0x02(7-0)]

[BPSK_STEP_SET0:B10 0x04(3-0)]

[BPSK_STEP_SET0:B10 0x04(7-4)]

…

✓

STEP0[3:0]-STEP119[3:0]

[BPSK_STEP_SET59:B10 0x3F(3-0)]

[BPSK_STEP_SET59:B10 0x3F(7-4)]

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To suppress harmonics generated at the time of phase/frequency switching, TX power control is performed by PA before

and after phase/frequency switching. The PA controls shown in the following table are available for the above two methods:

(a) Common PA power down/up setting

(b) Individual PA power down/up setting

(a) Common PA power down/up setting (BPSK_STEP_SEL([BPSK_STEP_CTLR: B10 0x01(5)]) = 0b1)

Power/cord

S118(0 in diagram)

Time

(b) Individual PA power down/up setting (BPSK_STEP_SEL([BPSK_STEP_CTLR: B10 0x01(5)]) = 0b0)

Power/cord

S58(in diagram)

S61,60(in diagram)

Time

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PA control related registers in BPSK modulation are as follows:

Symbol

Bit name

Address

Function

Remarks

S0

S1

STEP0[3:0]

STEP1[3:0]

STEP2[3:0]

STEP3[3:0]

STEP4[3:0]

STEP5[3:0]

STEP6[3:0]

STEP7[3:0]

STEP8[3:0]

STEP9[3:0]

STEP10[3:0]

STEP11[3:0]

STEP12[3:0]

STEP13[3:0]

STEP14[3:0]

STEP15[3:0]

STEP16[3:0]

STEP17[3:0]

STEP18[3:0]

STEP19[3:0]

STEP20[3:0]

STEP21[3:0]

STEP22[3:0]

STEP23[3:0]

STEP24[3:0]

STEP25[3:0]

STEP26[3:0]

STEP27[3:0]

STEP28[3:0]

STEP29[3:0]

STEP30[3:0]

STEP31[3:0]

STEP32[3:0]

STEP33[3:0]

STEP34[3:0]

STEP35[3:0]

STEP36[3:0]

STEP37[3:0]

STEP38[3:0]

STEP39[3:0]

STEP40[3:0]

STEP41[3:0]

STEP42[3:0]

STEP43[3:0]

STEP44[3:0]

STEP45[3:0]

STEP46[3:0]

STEP47[3:0]

STEP48[3:0]

STEP49[3:0]

STEP50[3:0]

STEP51[3:0]

STEP52[3:0]

STEP53[3:0]

[B10 0x04(3-0)]

[B10 0x04(7-4)]

[B10 0x05(3-0)]

[B10 0x05(7-4)]

[B10 0x06(3-0)]

[B10 0x06(7-4)]

[B10 0x07(3-0)]

[B10 0x07(7-4)]

[B10 0x08(3-0)]

[B10 0x08(7-4)]

[B10 0x09(3-0)]

[B10 0x09(7-4)]

[B10 0x0A(3-0)]

[B10 0x0A(7-4)]

[B10 0x0B(3-0)]

[B10 0x0B(7-4)]

[B10 0x0C(3-0)]

[B10 0x0C(7-4)]

[B10 0x0D(3-0)]

[B10 0x0D(7-4)]

[B10 0x0E(3-0)]

[B10 0x0E(7-4)]

[B10 0x0F(3-0)]

[B10 0x0F(7-4)]

[B10 0x10(3-0)]

[B10 0x10(7-4)]

[B10 0x11(3-0)]

[B10 0x11(7-4)]

[B10 0x12(3-0)]

[B10 0x12(7-4)]

[B10 0x13(3-0)]

[B10 0x13(7-4)]

[B10 0x14(3-0)]

[B10 0x14(7-4)]

[B10 0x15(3-0)]

[B10 0x15(7-4)]

[B10 0x16(3-0)]

[B10 0x16(7-4)]

[B10 0x17(3-0)]

[B10 0x17(7-4)]

[B10 0x18(3-0)]

[B10 0x18(7-4)]

[B10 0x19(3-0)]

[B10 0x19(7-4)]

[B10 0x1A(3-0)]

[B10 0x1A(7-4)]

[B10 0x1B(3-0)]

[B10 0x1B(7-4)]

[B10 0x1C(3-0)]

[B10 0x1C(7-4)]

[B10 0x1D(3-0)]

[B10 0x1D(7-4)]

[B10 0x1E(3-0)]

[B10 0x1E(7-4)]

BPSK step control 0

BPSK step control 1

BPSK step control 2

BPSK step control 3

BPSK step control 4

BPSK step control 5

BPSK step control 6

BPSK step control 7

BPSK step control 8

BPSK step control 9

BPSK step control 10

BPSK step control 11

BPSK step control 12

BPSK step control 13

BPSK step control 14

BPSK step control 15

BPSK step control 16

BPSK step control 17

BPSK step control 18

BPSK step control 19

BPSK step control 20

BPSK step control 21

BPSK step control 22

BPSK step control 23

BPSK step control 24

BPSK step control 25

BPSK step control 26

BPSK step control 27

BPSK step control 28

BPSK step control 29

BPSK step control 30

BPSK step control 31

BPSK step control 32

BPSK step control 33

BPSK step control 34

BPSK step control 35

BPSK step control 36

BPSK step control 37

BPSK step control 38

BPSK step control 39

BPSK step control 40

BPSK step control 41

BPSK step control 42

BPSK step control 43

BPSK step control 44

BPSK step control 45

BPSK step control 46

BPSK step control 47

BPSK step control 48

BPSK step control 49

BPSK step control 50

BPSK step control 51

BPSK step control 52

BPSK step control 53

S2

S3

S4

S5

S6

S7

S8

S9

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

S24

S25

S26

S27

S28

S29

S30

S31

S32

S33

S34

S35

S36

S37

S38

S39

S40

S41

S42

S43

S44

S45

S46

S47

S48

S49

S50

S51

S52

S53

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PA control register list (continued)

Symbol

Bit name

Address

Function

Remarks

S54

S55

S56

S57

S58

S59

S60

S61

S62

S63

S64

S65

S66

S67

S68

S69

S70

S71

S72

S73

S74

S75

S76

S77

S78

S79

S80

S81

S82

S83

S84

S85

S86

S87

S88

S89

S90

S91

S92

S93

S94

S95

S96

S97

S98

S99

S100

S101

S102

S103

S104

S105

S106

STEP54[3:0]

STEP55[3:0]

STEP56[3:0]

STEP57[3:0]

STEP58[3:0]

STEP59[3:0]

STEP60[3:0]

STEP61[3:0]

STEP62[3:0]

STEP63[3:0]

STEP64[3:0]

STEP65[3:0]

STEP66[3:0]

STEP67[3:0]

STEP68[3:0]

STEP69[3:0]

STEP70[3:0]

STEP71[3:0]

STEP72[3:0]

STEP73[3:0]

STEP74[3:0]

STEP75[3:0]

STEP76[3:0]

STEP77[3:0]

STEP78[3:0]

STEP79[3:0]

STEP80[3:0]

STEP81[3:0]

STEP82[3:0]

STEP83[3:0]

STEP84[3:0]

STEP85[3:0]

STEP86[3:0]

STEP87[3:0]

STEP88[3:0]

STEP89[3:0]

STEP90[3:0]

STEP91[3:0]

STEP92[3:0]

STEP93[3:0]

STEP94[3:0]

STEP95[3:0]

STEP96[3:0]

STEP97[3:0]

STEP98[3:0]

STEP99[3:0]

STEP100[3:0]

STEP101[3:0]

STEP102[3:0]

STEP103[3:0]

STEP104[3:0]

STEP105[3:0]

STEP106[3:0]

[B10 0x1F(3-0)]

[B10 0x1F(7-4)]

[B10 0x20(3-0)]

[B10 0x20(7-4)]

[B10 0x21(3-0)]

[B10 0x21(7-4)]

[B10 0x22(3-0)]

[B10 0x22(7-4)]

[B10 0x23(3-0)]

[B10 0x23(7-4)]

[B10 0x24(3-0)]

[B10 0x24(7-4)]

[B10 0x25(3-0)]

[B10 0x25(7-4)]

[B10 0x26(3-0)]

[B10 0x26(7-4)]

[B10 0x27(3-0)]

[B10 0x27(7-4)]

[B10 0x28(3-0)]

[B10 0x28(7-4)]

[B10 0x29(3-0)]

[B10 0x29(7-4)]

[B10 0x2A(3-0)]

[B10 0x2A(7-4)]

[B10 0x2B(3-0)]

[B10 0x2B(7-4)]

[B10 0x2C(3-0)]

[B10 0x2C(7-4)]

[B10 0x2D(3-0)]

[B10 0x2D(7-4)]

[B10 0x2E(3-0)]

[B10 0x2E(7-4)]

[B10 0x2F(3-0)]

[B10 0x2F(7-4)]

[B10 0x30(3-0)]

[B10 0x30(7-4)]

[B10 0x31(3-0)]

[B10 0x31(7-4)]

[B10 0x32(3-0)]

[B10 0x32(7-4)]

[B10 0x33(3-0)]

[B10 0x33(7-4)]

[B10 0x34(3-0)]

[B10 0x34(7-4)]

[B10 0x35(3-0)]

[B10 0x35(7-4)]

[B10 0x36(3-0)]

[B10 0x36(7-4)]

[B10 0x37(3-0)]

[B10 0x37(7-4)]

[B10 0x38(3-0)]

[B10 0x38(7-4)]

[B10 0x39(3-0)]

BPSK step control 54

BPSK step control 55

BPSK step control 56

BPSK step control 57

BPSK step control 58

BPSK step control 59

BPSK step control 60

BPSK step control 61

BPSK step control 62

BPSK step control 63

BPSK step control 64

BPSK step control 65

BPSK step control 66

BPSK step control 67

BPSK step control 68

BPSK step control 69

BPSK step control 70

BPSK step control 71

BPSK step control 72

BPSK step control 73

BPSK step control 74

BPSK step control 75

BPSK step control 76

BPSK step control 77

BPSK step control 78

BPSK step control 79

BPSK step control 80

BPSK step control 81

BPSK step control 82

BPSK step control 83

BPSK step control 84

BPSK step control 85

BPSK step control 86

BPSK step control 87

BPSK step control 88

BPSK step control 89

BPSK step control 90

BPSK step control 91

BPSK step control 92

BPSK step control 93

BPSK step control 94

BPSK step control 95

BPSK step control 96

BPSK step control 97

BPSK step control 98

BPSK step control 99

BPSK step control 100

BPSK step control 101

BPSK step control 102

BPSK step control 103

BPSK step control 104

BPSK step control 105

BPSK step control 106

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PA control register list (continued)

Symbol

Bit name

Address

Function

Remarks

S107

S108

S109

S110

S111

S112

S113

S114

S115

S116

S117

S118

S119

STEP107[3:0]

STEP108[3:0]

STEP109[3:0]

STEP110[3:0]

STEP111[3:0]

STEP112[3:0]

STEP113[3:0]

STEP114[3:0]

STEP115[3:0]

STEP116[3:0]

STEP117[3:0]

STEP118[3:0]

STEP119[3:0]

[B10 0x39(7-4)]

[B10 0x3A(3-0)]

[B10 0x3A(7-4)]

[B10 0x3B(3-0)]

[B10 0x3B(7-4)]

[B10 0x3C(3-0)]

[B10 0x3C(7-4)]

[B10 0x3D(3-0)]

[B10 0x3D(7-4)]

[B10 0x3E(3-0)]

[B10 0x3E(7-4)]

[B10 0x3F(3-0)]

[B10 0x3F(7-4)]

BPSK step control 107

BPSK step control 108

BPSK step control 109

BPSK step control 110

BPSK step control 111

BPSK step control 112

BPSK step control 113

BPSK step control 114

BPSK step control 115

BPSK step control 116

BPSK step control 117

BPSK step control 118

BPSK step control 119

Step control clock cycle T =

Clock cycle for step control

x Step control clock

Step control clock selection setting

0: Master clock frequency / 2 (18 MHz)

1: Master clock frequency / 4 (9 MHz)

BPSK_STEP_CLK_SEL

[B10 0x01(5)]

selection setting

T

L

[B0 0x02(0),

B0 0x03(7-0)]

Step control clock cycle setting

CLK_SET[8:0]

[B0 0x67(0),

B0 68(7:0)]

PA regulator output voltage adjustment

setting

PA_REG_ADJ[8:0]

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●RX Related Function

○AFC Function

This LSI part supports AFC function in RX. Frequency deviation (max±20ppm) between remote device and local device can be

compensated by this function. Using this function, stable RX sensitivity and interference blocking performance can be achieved.

This function can be enabled by setting AFC_EN([AFC/GC_CTRL: B1 0x15(7)])=0b1. Note that the AFC function used to

compensate local signals does not work when the spread spectrum function is used.

○Energy Detection Value (ED value) Acquisition Function

This LSI supports the function to indicate the received signal strength indicator (RSSI) as the energy detection value (ED value).

ED value acquisition can be enabled by setting ED_CALC_EN ([ED_CTRL: B0 0x41(7)])=0b1. As soon as a transition is made

to RX_ON state, acquisition of ED value starts automatically.

While in RX_ON state, the ED value is constantly updated. ED value is not RSSI value at given timing, but average values. A

number of average times can be specified by ED_AVG([ED_CTRL: B0 0x41(2-0)]). During diversity operation, this can be set

by 2DIV_ED_AVG([2DIV_MODE: B1 0x48(2-0)]). As soon as ED value is acquired for the number of average processing,

ED_DONE([ED_CTRL: B0 0x41(4)]) is set to “1” and ED_VALUE([ED_RSLT: B0 0x3A]) will be updated.

ED_DONE bit will be cleared if one of the following conditions is met.

(a) Antenna is switched.

(b) Gain is switched.

(c) Once stopping ED value acquisition and then resume it.

Timing from ED value starting point to ED value acquisition is calculated as below formula.

ED value average time = Average interval (16μs) * ED value number of average times

The timing example is as follows:

[Condition]

ED_AVG[2:0]=0b011 (ED value 8 times average) [ED_CTRL: B0 0x41(2-0)]

ED value calculation

execution flag

(Internal signal)

Average interval (16 μs)

RSSI value

(Internal signal)

RSSI1 RSSI2 RSSI3 RSSI4 RSSI5

RSSI6 RSSI7 RSSI8

RSSI9

Compensation

and averaging

ED

1-8

ED

2-9

ED

3-10

ED_VALUE

[ED_RSLT: B0 0x3A]

INVALID

Constantly update by

moving average

ED value averaging period (16 µs x 8 = 128 µs)

ED_DONE

([ED_CTRL:B0 0x41(4)])

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○Programmable Channel Filter Bandwidth Function

Channel filter bandwidth can be set by CHFIL_BW_ADJ([CHFIL_BW: B0 0x54(6-0)]), CHFIL_WIDE_SET([CHFIL_BW:

B0 0x54(7)]) and CHFIL_BW_OPTION([CHFIL_BW_OPTION: B0 0x6B]). The relationship between the setting value and

the channel filter bandwidth is expressed by the following formula.

Channel filter bandwidth [Hz] = {Master clock frequency [Hz] * (CHFIL_WIDE_SET + 1)} / {CHFIL_BW_ADJ * 180} *

Magnification setting (CHFIL_BW_OPTION)

See the following table for the channel filter bandwidth for each setting value. Channel filter bandwidth can be set separately

for the normal receiving mode and during CCA. For the channel filter bandwidth during CCA, the setting values of

CHFIL_BW_ADJ_CCA([CHFIL_BW_CCA: B0 0x6A(6-0)]) and CHFIL_WIDE_SET_CCA([CHFIL_BW_CCA: B0

0x6A(7)]) will be applied.

(1) For the case of CHFIL_WIDE_SET = 0b0 and CHFIL_BW_OPTION = 0b000

Channel filter bandwidth

[kHz]

CHFIL_BW_ADJ

[dec]

CHFIL_BW_ADJ

Channel filter bandwidth

[dec]

0

1

2

3

4

[kHz]

12.5

11.8

11.1

10.5

10

Prohibited

200

16

17

18

19

20

100

66.7

50

5

40

21

9.5

6

7

8

33.3

28.6

25

22

23

24

9.1

8.7

8.3

9

22.2

20

25

26

27

28

・・・

126

127

8

7.7

7.4

7.1

・・・

1.59

1.57

10

11

12

13

14

15

18.2

16.7

15.4

14.3

13.3

(2) For the case of CHFIL_WIDE_SET = 0b1 and CHFIL_BW_OPTION = 0b000

Channel filter bandwidth

[kHz]

CHFIL_BW_ADJ

[dec]

CHFIL_BW_ADJ

Channel filter bandwidth

[dec]

[kHz]

0

1

2

3

Prohibited

400

200

133.3

100

16

17

18

19

20

25

23.5

22.2

21.1

20

4

5

80

21

19

6

7

8

9

10

11

12

13

66.7

57.1

50

44.4

40

36.4

33.3

30.8

22

23

24

25

26

27

28

・・・

126

127

18.2

17.4

16.7

16

15.4

14.8

14.3

・・・

3.18

3.14

14

15

28.6

26.7

The channel filter bandwidth needs to be optimized according to the data rate and the maximum frequency deviation.

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○Diversity Function

This LSI supports two antenna diversity function.

While in 2DIV_EN([2DIV_CTRL: B0 0x48(0)])=0b1 setting, as soon as RX_ON is set, the diversity mode will start. When

diversity mode is started, and upon RX data detection, each ED value will be acquired by switching two antennas. And then

antenna with higher ED value will be selected automatically. As diversity uses preamble data for ED value acquisition, longer

preamble length is desirable. If preamble is too short, accurate ED values may not be obtained.

The timing diagrams are shown below.

RX packet

Sync

Word

Length

Data

Preamble

RX_ON

ANT_SW

Synchronization

detected

Fixed to the

ANT with the

higher ED

Update ANT RSLT and ED values

([2DIV_RSLT: B0 0x49(1-0)])

ANT1/ANT2 search is repeated until the

first Bit-Synchronization detection. ANT

search periods at this time are determined

by SEARCH_TIME1([2DIV_SEARCH1:

B1 0x49(6-0)]).

After Bit-Synchronization detection, search

is performed by using another ANT different

from the one used in the last search. ANT

search period is determined by

Diversity search completion interrupt

notification

([INT_SOURCE_GRP2: B0 0x0E(2)])

SEARCH_TIME2([2DIV_SEARCH2: B1

0x4A(6-0)])

ED value obtained by Diversity ([ANT1_ED: B0 0x4A] or [ANT2_ED: B0 0x4B]) and Diversity antenna result ([2DIV_RSLT:

B0 0x49(1-0)]) are updated and overwritten when SyncWord is detected.

The number of detection performed during the ED value calculation is specified by 2DIV_ED_AVG([2DIV_MODE: B1

0x48(2:0)]).

Time resolution of search times ([SEARCH_TIME1] and [SEARCH_TIME2]) can be specified by

SEARCH_TIME_SET([2DIV_SEARCH1: B1 0x49(7)]).

When Diversity search completion interrupt INT[10] ([INT__SOURCE_GRP2: B0 0x0E(2)]) is cleared, the ED value obtained

by Diversity ([ANT1_ED: B0 0x4A]) or [ANT2_ED: B0 0x4B]) and Diversity antenna result ([2DIV_RSLT: B0 0x49(1-0)])

are cleared to zero.

[Note]

When an incorrect diversity completion is caused by erroneous detection, ML7456N RF part re-executes antenna search

automatically. However, when a desired wave is received during the period from the completion of diversity search caused by

erroneous detection to the determination of erroneous detection, the obtained ED value ([ANT1_ED: B0 0x4A]) or [ANT2_ED:

B0 0x4B]) shows a low ED value different from the input level of desired wave.

The occurrence of this event can be checked by reading out the ED value, which is displayed by [ED_RSLT: B0 0x41], after the

occurrence of SyncWord detection interrupt of desired wave INT[13] ([INT_SOURCE_GRP2: B0 0x0E(5)]).

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(1) Antenna switching function

Using [2DIV_CTRL: B0 0x48], [ANT_CTRL: B0 0x4C] and [EXT_PA_CTRL: B0 0x53], TX-RX signal selection

(TRX_SW), antenna switching signal (ANT_SW), and external PA control signal (DCNT) can be controlled.

Two types of antenna switches (SPDT switch/DPDT switch) can be controlled by [2DIV_CTRL: B0 0x48(3-1)] and

[ANT_CTRL: B0 0x4C]). The relationship between the output status of ANT_SW and TRX_SW pins during each antenna

switch control and [2DIV_CTRL: B0 0x48(2-1)] is indicated below.

(a) When DPDT switch is used

Set 2PORT_SW([2DIV_CTRL: B0 0x48(1)]) = 0b1 and ANT_CTRL1([2DIV_CTRL: B0 0x48(5)]) = 0b0. ANT_SW and

TRX_SW are output as follows during IDLE, TX, and RX states

(default setting): INV_TRX_SW([2DIV_CTRL: B0 0x48(2)])=0b1, polarities of ANT_SW and TRX_SW are reversed.

INV_TRX_SW([2DIV_CTRL: INV_TRX_SW([2DIV_CTRL:

B0 0x48(2)])=0

(default setting)

B0 0x48(2)])=1

(reversed polarity)

TX/RX state

Description

ANT_SW

TRX_SW

ANT_SW

TRX_SW

Idle

TX

RX

H

L

H

L

H

L

Idle state

TX state

This is the initial state when Diversity disable

is set to 0b0 ([2DIV_CTRL: B0

H

L

H

0x48(0)]=0b0) and at the start of Diversity

when Diversity is enabled ([2DIV_CTRL: B0

0x48(0)]=0b1).

If diversity enable is set ([2DIV_CTRL: B0

0x48(0)]=0b1), (ANT_SW=H, TRX_SW=L)

and (ANT_SW=L, TRX_SW=H) are

switched alternately during search. When the

diversity is complete, it is fixed to either

state.

L/H

H/L

L/H

(b) When SPDT switch is used

2PORT_SW([2DIV_CTRL: B0 0x48(1)])=0b0. ANT_SW and TRX_SW are output as follows during IDLE, TX, and RX states

(default setting): INV_TRX_SW([2DIV_CTRL: B0 0x48(2)])=0b1, polarity of TRX_SW is reversed

INV_TRX_SW([2DIV_CTRL: INV_TRX_SW([2DIV_CTRL:

B0 0x48(2)])=0

(default setting)

B0 0x48(2)])=1

(reversed polarity)

TX/RX state

Description

ANT_SW

TRX_SW

ANT_SW

TRX_SW

Idle

TX

RX

L

H

L

H

L

Idle state

TX state

This is the initial state when Diversity disable

is set to 0b0 ([2DIV_CTRL: B0

L

H

0x48(0)]=0b0) and at the start of Diversity

when Diversity is enabled ([2DIV_CTRL: B0

0x48(0)]=0b1).

If diversity enable is set ([2DIV_CTRL: B0

0x48(0)]=0b1), (ANT_SW=H, TRX_SW=L)

and (ANT_SW=L, TRX_SW=H) are

switched alternately during search. When the

diversity is complete, it is fixed to either state.

H/L

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By setting INV_ANT_SW([2DIV_CTRL: B0 0x48(3)])=0b1 and ANT_CTRL1([2DIV_CTRL: B0 0x48(5)])=0b1 to the above

default setting, the polarity of ANT_SW pin will be reversed.

INV_ANT_SW([2DIV_CTRL:

B0 0x48(3)])=0

B0 0x48(3)])=1

ANT_CTRL1([2DIV_CTRL:

B0 0x48(5)])=1

ANT_CTRL1([2DIV_CTRL:

B0 0x48(5)])=0

TX/RX

state

Description

(default setting)

ANT_SW

TRX_SW

ANT_SW

TRX_SW

Idle

TX

RX

L

H

L

H

Idle state

TX state

This is the initial state when Diversity

disable is set to 0b0 ([2DIV_CTRL: B0

0x48(0)]=0b0) and at the start of Diversity

when Diversity is enabled ([2DIV_CTRL:

B0 0x48(0)]=0b1).

If diversity enable is set ([2DIV_CTRL: B0

0x48(0)]=0b1), (ANT_SW=H,

TRX_SW=L) and (ANT_SW=L,

TRX_SW=H) are switched alternately

during search. When the diversity is

complete, it is fixed to either state.

L

H

L

H/L

L/H

(2) Antenna switch forced setting

By using [ANT_CTRL: B0 0x4C] register, ANT_SW pin output status can be set forcibly.

TX: By setting TX_ANT_EN([ANT_CTRL: B0 0x4C(0)])=0b1, the setting value of TX_ANT([ANT_CTRL: B0 0x4C(1)]) will

be output.

RX: By setting RX_ANT_EN([ANT_CTRL: B0 0x4C(4)])=0b1, the setting value of RX_ANT([ANT_CTRL: B0 0x4C(5)])

will be output.

However, when output is defined forcibly by [GPIO*_CTRL: B0 0x4E - 0x51] registers, [GPIO*_CTRL:B0 0x4E - 0x51]

register settings have higher priority.

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Antenna switching control signals can also be used as follows.

[Example 1] Using one DPDT switch

2PORT_SW([2DIV_CTRL: B0 0x48(1)]) to 0b1.

LSI

DPDT#1

LNA_P pin

PA_OUT(#20)

TRX_SW output pin (GPIOx)

ANT_SW output pin (GPIOx)

(*) By allocating one more GPIO to an external PA, it becomes possible to control both DPDT SW and the external PA.

(*) External circuits between LNA_P/PA_OUT pin and antenna switch (DPDT#1) are omitted in this example.

[Example 2] Using two SPDT switches

2PORT_SW([2DIV_CTRL: B0 0x48(1)]) to 0b0.

LSI

SPDT#2

SPDT#1

LNA_P pin

PA_OUT pin

TRX_SW output pin (GPIOx)

ANT_SW output pin (GPIOx)

(*) By allocating one more GPIO to an external PA, it becomes possible to control both DPDT SW and the external PA.

(*) External circuits between LNA_P/PA_OUT pin and antenna switch (SPDT#2) are omitted in this example.

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○CCA (Clear Channel Assessment) Function

This LSI supports CCA function. CCA is a function that receives frequency channels and makes a judgment whether the

specified frequency channel is busy or idle. This LSI supports Normal mode, Continuous mode and IDLE detection mode.

These modes can be set as follows:

[CCA mode setting]

[CCA_CTRL: B0 0x39]

Bit4 (CCA_EN)

Bit5 (CCA_CPU_EN)

Bit6 (CCA_IDLE_EN)

Normal mode

Continuous mode

IDLE detection

mode

0b1

0b0

0b1

0b0

0b1

(1) Normal mode

Normal mode determines IDLE or BUSY. When CCA_EN(CCA_CTRL: B0 0x39(4)]) = 0b1, CCA_CPU_EN(CCA_CTRL:

B0 0x39(5)]) = 0b0, and CCA_IDLE_EN(CCA_CTRL: B0 0x39(6)]) = 0b0, CCA (normal mode) is executed by RX_ON.

CCA judgment is based on the comparison of the average ED value displayed by the [ED_RSLT: B0 0x3A] register with the

CCA threshold set by the [CCA_LVL: B0 0x37] register. If the average ED value displayed by [ED_RSLT: B0 0x3A]

exceeds the CCA threshold, it is determined as BUSY, and CCA_RSLT[1:0] ([CCA_CTRL: B0 0x39(1-0)]) is set to 0b01.

If the average ED value continues to be smaller than the CCA threshold for the IDLE detection period set by

IDLE_WAIT[9:0] of [IDLE_WAIT_L: B0 0x3C] and [IDLE_WAIT_H: B0 0x3B])], it is determined as IDLE, and

CCA_RSLT[1:0] is set to 0b00. For the detailed operation of IDLE_WAIT[9:0], please refer to “IDLE detection for long

time period”.

If “BUSY” or “IDLE” state is detected, CCA completion interrupt (INT[18] of group 3) is generated, and CCA_EN bit is

cleared to 0b0 automatically.

Upon clearing CCA completion interrupt, CCA_RSLT[1:0] is reset to 0b00. Therefore, CCA_RSLT[1:0] should be read

before clearing CCA completion interrupt.

If the ED value exceeds the value set by [CCA_IGNORE_LVL: B0 0x36], IDLE determination is not performed as long as

the target ED value is included in the averaging target range. At this time, if the average ED value is larger than [CCA_LVL:

B0 0x37], it is determined as BUSY, and CCA is completed. However, if the average ED value is smaller than [CCA_LVL:

B0 0x37], IDLE determination is not performed, and 0b11 is displayed in CCA_RSLT[1:0] ([CCA_CTRL: B0 0x39(1-0)]).

In this case, CCA continues until BUSY determination is made or IDLE determination is made after the target ED value is

excluded from the averaging target range. For the detailed operation for the case where the ED value exceeds

[CCA_IGNORE_LVL: B0 0x36], please refer to “IDLE determination exclusion under strong signal input”.

Time from CCA command issue to CCA completion is in the formula below.

[IDLE detection]

CCA execution time = (ED value average times + IDLE_WAIT setting) x Average interval (16 us)

[BUSY detection]

CCA execution time = ED value average times x Average interval (16 us)

* The above formulas do not take the IDLE detection exclusion by [CCA_IGNORE_LVL: B0 0x36] into account. Set

[CCA_IGNORE_LVL: B0 0x36] in a way so that the relationship of [CCA_IGNORE_LVL:B0 0x36] >= [CCA_LVL: B0

0x37] is maintained. B0 0x36], please refer to ”IDLE determination exclusion under strong signal input”.

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The following is timing chart for normal mode.

[Condition]

ED_AVG[2:0]=0b011 (ED value 8 times average) [ED_CTRL: B0 0x41(2-0)]

IDLE_WAIT[9:0]=0b00_0000_0000 (IDLE detection time 0 μs) [IDLE_WAIT_L: B0 0x3C], [IDLE_WAIT_H: B0 0x3B(1-0)]

[IDLE detection case]

CCA_EN

[CCA_CTRL: B0 0x39(4)]

Average

interval (16 μs)

ED value average period (16 µs*8 =128 µs)

ED value

(Internal signal)

ED1

ED2

ED3

ED5

ED0

ED6

ED7

Averaging

Average ED value

Select ED value displayed in

[ED_RSLT: B0 0x3A]

ED

(0-7)

< CCA_LVL

B0 0x37

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

0b00 (IDLE)

0b10 (determination on-going)

IDLE_WAIT[9:0]

should be set, for

IDLE detection for

longer period.

INT[18]

[INT_SOURCE_GRP3: B0 0x0F(2)]

CCA execution period (Min.128 µs)

[BUSY result case]

CCA_EN

[CCA_CTRL: B0 0x39(4)]

Average

interval

ED value average period (16 µs*8 =128 µs)

ED1 ED2 ED3 ED5

ED value

(internal signal)

ED0

ED6

ED7

Averaging

Average ED value

ED

(0-7)

Select ED value displayed in

[ED_RSLT: B0 0x3A]

> CCA_LVL

B0 0x37

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

0b01 (BUSY)

0b10 (determination on-going)

IDLE_WAIT[9:0]

should be set, for

IDLE detection for

longer period.

INT[18]

[INT_SOURCE_GRP3: B0 0x0F(2)]

CCA execution period (Min.128 µs)

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(2) Continuous mode

Continuous mode continues CCA until terminated by the host CPU. When CCA_EN(CCA_CTRL: B0 0x39(4)]) = 0b1,

CCA_CPU_EN(CCA_CTRL: B0 0x39(5)]) = 0b1, and CCA_IDLE_EN(CCA_CTRL: B0 0x39(6)]) = 0b0, CCA

(continuous mode) is executed by RX_ON.

As with the normal mode, CCA judgment is based on the comparison of the average ED value displayed by the [ED_RSLT:

B0 0x3A] register with the CCA threshold set by the [CCA_LVL: B0 0x37] register. If the average ED value displayed by

ED_VALUE ([ED_RSLT:B0 0x3A]) exceeds the CCA threshold, it is determined as “BUSY, and CCA_RSLT[1:0] is set to

0b01. If the average ED value continues to be smaller than the CCA threshold for the IDLE detection period set by

IDLE_WAIT[9:0] of [IDLE_WAIT_L:B0 0x3C] and [IDLE_WAIT_H: B0 0x3B(1-0)], it is determined as IDLE, and

CCA_RSLT[1:0] is set to 0b00. For the detailed operation of IDLE_WAIT[9:0], please refer to “IDLE detection for long

time period”.

If the ED value exceeds the value set by [CCA_IGNORE_LVL: B0 0x36], IDLE determination is not performed as long as

the target ED value is included in the averaging target range. At this time, if the average ED value is larger than [CCA_LVL:

B0 0x37], it is determined as BUSY, and CCA_RSLT[1:0] is set to 0b01. However, if the average ED value is smaller than

[CCA_LVL: B0 0x37], IDLE determination is not performed, and CCA_RSLT[1:0] is set to 0b11. For the detailed operation

for the case where the ED value exceeds [CCA_IGNORE_LVL: B0 0x36], please refer to “IDLE determination exclusion

under strong signal input”.

The continuous mode does not stop the operation even when BUSY or IDLE is detected. CCA operation continues until 0b1

is set to CCA_STOP ([CCA_CTRL: B0 0x39(7)]). The result is updated every time the ED value is acquired. At this time,

CCA completion interrupt INT[18]([INT_SOURCE_GRP2:B0 0x0F(2)]) will not be generated.

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The following is timing chart for continuous mode.

[Condition]

ED_AVG[2:0]=0b011 (ED value 8 times average) [ED_CTRL: B0 0x41(2-0)]

IDLE_WAIT[9:0]=0b00_0000_0000 (IDLE detection time 0 μs) [IDLE_WAIT_L: B0 0x3C], [IDLE_WAIT_H: B0 0x3B(1-0)]

[BUSY to IDLE transition, terminated with CCA_STOP]

After CCA_STOP is issued, CCA_EN

and CCA_CPU_EN are cleared, and

CCA_STOP bit is automatically cleared.

CCA_EN

[CCA_CTRL: B0 0x39(4)]

CCA_STOP

[CCA_CTRL:B0 0x39]

Average interval

(16 μs)

ED value average period (128 µs)

ED value

(internal signal)

ED0

ED7

ED8

ED28

ED50

...

Averaging

Average ED value

Select ED value displayed in

[ED_RSLT: B0 0x3A]

ED

(1-8)

ED

(21-28)

ED

(43-50)

ED

(0-7)

INVALID

...

> CCA_LVL

B0 0x37

< CCA_LVLB0

0x37

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

0b10 (determination

on-going)

0b00 (IDLE)

0b01 (BUSY)

IDLE_WAIT[9:0]

should be set, for

IDLE detection for

longer period.

INT[18]

Interrupt not generated

[INT_SOURCE_GRP3: B0 0x0F(2)]

ED_DONE

[ED_CTRL: B0 0x41(4)]

When the ED value is acquired eight time,

ED_DONE=1. (8 times averaging setting)

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(3) IDLE detection mode

IDLE detection mode continues CCA until IDLE detection. When CCA_EN(CCA_CTRL: B0 0x39(4)])=0b1,

CCA_CPU_EN(CCA_CTRL: B0 0x39(5)])=0b0, and CCA_IDLE_EN(CCA_CTRL: B0 0x39(6)])=0b1 are set, CCA (IDLE

detection mode) is executed by RX_ON.

As with the normal mode, CCA judgment is based on the comparison of the average ED value displayed by the [ED_RSLT:

B0 0x3A] register with the CCA threshold set by the [CCA_LVL: B0 0x37] register. If the average ED value exceeds the

CCA threshold, it is determined as BUSY, and CCA_RSLT[1:0] ([CCA_CTRL: B0 0x39(1-0)]) is set to 0b01. If the average

ED value continues to be smaller than the CCA threshold for the IDLE detection period set by IDLE_WAIT[9:0] of

[IDLE_WAIT_L] and [IDLE_WAIT_H]: B0 0x3B,0x3C], it is determined as “IDLE”, and CCA_RSLT[1:0] is set to 0b00.

For the detailed operation of IDLE_WAIT[9:0], please refer to “IDLE detection for long time period”.

In IDLE detection mode, CCA completion interrupt INT[18]([INT_SOURCE_GRP3: B0 0x0F(2)]) is generated only when

IDLE is detected. B0 0x0F(2)]) is generated. Also, when CCA is executed by CCA_EN setting, CCA_EN(CCA_CTRL: B0

0x39(4)]) and CCA_IDLE_EN(CCA_CTRL: B0 0x39(6)]) are cleared to 0b0 automatically.

In IDLE detection mode, CCA completion interrupt INT[18]([INT_SOURCE_GRP3: B0 0x0F(2)]) is not generated while

BUSY is detected, and continues to detect IDLE. When CCA completion interrupt INT[18]([INT_SOURCE_GRP3: B0

0x0F(2)]) is cleared, CCA_RSLT[1:0]([CCA_CTRL: B0 0x39(1-0)]) is reset to 0b00. Therefore, CCA_RSLT[1:0] should be

read before CCA completion interrupt INT[18]([INT_SOURCE_GRP3: B0 0x0F(2)]) is cleared.

If the ED value exceeds [CCA_IGNORE_LVL: B0 0x36], IDLE determination is not performed as long as the target ED

value is included in the averaging target range. IDLE determination is not performed also when the average ED value is

smaller than [CCA_LVL: B0 0x37]. In this case, 0b11 is displayed in CCA_RSLT[1:0], and CCA is continued until IDLE

determination is made after the target ED value is excluded from the averaging target range. For the detailed operation for

the case where the ED value exceeds [CCA_IGNORE_LVL: B0 0x36], please refer to “IDLE determination exclusion under

strong signal input”.

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The following is the timing diagram of IDLE detection.

[Upon BUSY detection, continue CCA and IDLE detection case]

[Condition]

ED_AVG[2:0]=0b011 (ED value 8 times average) [ED_CTRL: B0 0x41(2-0)]

IDLE_WAIT[9:0]=0b00_0000_0000 (IDLE detection time 0 μs) [IDLE_WAIT_L: B0 0x3C], [IDLE_WAIT_H: B0 0x3B(1-0)]

After IDLE detection, CCA will be

completed,

CCA_IDLE_EN is cleared at the same time.

CCA_EN

[CCA_CTRL: B0 0x39(4)]

Average interval

(16 μs)

ED value average period

IDLE detection period

ED value

(internal signal)

ED0

ED7

ED8

ED28

...

ED27

ED29

...

Averaging

Average ED value

Select ED value displayed in

[ED_RSLT: B0 0x3A]

ED

(20-27)

ED

(22-29)

ED

(21-28)

ED

(0-7)

ED

(1-8)

INVALID

...

> CCA_LVL

B0 0x37

< CCA_LVL

B0 0x37

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

0b10 (determination

on-going)

0b00 (IDLE)

0b01 (BUSY)

Interrupt is not generated

by BUSY

INT[18]

[INT_SOURCE_GRP3: B0 0x0F(2)]

IDLE_WAIT[9:0]

should be set, for

IDLE detection for

longer period.

CCA execution period (Min.128 μs + IDLE detection time)

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(4) IDLE determination exclusion under strong signal input

If acquired ED value exceeds the value set by [CCA_IGNORE_LVL: B0 0x36], IDLE determination is not performed as

long as the given ED value is included in the averaging target range. If the average ED value including this strong ED value

displayed by [ED_RSLT: B0 0x39] exceeds the CCA threshold set by [CCA_LVL: B0 0x37], it is determined as “carrier

detected (BUSY)”, and CCA_RSLT[1:0] ([CCA_CTRL: B0 0x39(1-0)]) is set to 0b01. Also, if this average ED value is

equal to or smaller than the CCA threshold, it is determined as “CCA evaluation on-going (ED value excluded from CCA

judgment acquired)”, and CCA_RSLT[1:0] is set to 0b11.

Even if the moving average of the ED value is equal to or smaller than [CCA_LVL: B0 0x37], IDLE determination is not

made when the ED value to be moving-averaged contains a value larger than [CCA_IGNORE_LVL: B0 0x36]. In this case,

CCA_RSLT[1:0] indicates 0b11 (on-going), and CCA operation continues until IDLE or BUSY is determined (until IDLE is

determined in the IDLE detection mode, or CCA_STOP([CCA_CTRL: B0 0x39(7)]) is issued in the continuous mode).

If the moving average of the ED value exceeds [CCA_LVL: B0 0x37], BUSY is determined immediately regardless of the

comparison result of [CCA_IGNORE_LVL: B0 0x36].

[Note]

CCA completion interrupt is notified of only when CCA result is judged as IDLE or BUSY. Therefore, if data whose ED

value exceeds CCA_IGNORE_LVL is input intermittently, neither “IDLE” or “BUSY” can be determined and CCA may

continues.

[ED value acquisition under strong signal input]

ED value > CCA_IGNORE_LVL

[CCA_IGNORE_LVL

: B0 0x36]

[CCA_LVL: B0 0x37]

ED value

Averaging target includes ED value

[Time 1]

[Time 2]

[Time 3]

Shift register

(ED value 8 times

average)

exceeding CCA_IGNORE_LVL. In

this case, IDLE is not determined.

However, if averaging value

exceeds CCA threshold, “BUSY” is

determined.

[Time 8]

[Time 9]

ED value, which includes

CCA_IGNORE_LVL, is

out of averaging target. In

this case, “IDLE” can be

determined.

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The following is the timing diagram when ED value under strong signal input was acquired.

[During IDLE_WAIT counting, detected strong signal input. After the given signal is out of averaging target, IDLE detection

case]

[Condition]

CCA mode

Normal mode

ED_AVG[2:0]=0b011 (ED value 8 times average)

IDLE_WAIT[9:0]=0b00_0000_0111 (IDLE detection time 112 μs)

[ED_CTRL: B0 0x41(2-0)]

[IDLE_WAIT_L: B0 0x3C], [IDLE_WAIT_H: B0

0x3B(1-0)]

ED value > CCA_IGNORE_LVL

ED value < CCA_IGNORE_LVL

ED value

(internal signal)

ED13 ED14 ED15

ED7

ED8

ED21 ED22

ED29

...

When average ED value > CCA_LVL

Average ED value < CCA_LVL

“BUSY” is determined immediately

Average ED value

Select ED value

displayed in

ED

(0-7)

ED

(1-8)

ED

(8-15)

ED

(22-29)

INVALID

...

(6-13) (7-14)

(14-21) (15-22)

Resumed counting because

strong signal input went out of

averaging target.

[ED_RSLT: B0 0x3A]

ED value > CCA_IGNORE_LVL

detection and reset

CCA_PROG[9:0]

[CCA_PROG_L/H:

B0x3E,B0x3D]

0x0007

...

0x0006 0x0000

...

0x0001

CCA _RSLT is maintained

until IDLE/BUSY

detected.

Due to strong signal input in the average target,

Average < CCA_LEVEL does not indicate

IDLE.

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

0b10 (determination on-going)

0b11 (determination on-going)

0b00 (IDLE)

CCA_RSLT[1:0]=0b11 does not generate interrupt.

INT[18]

[INT_SOURCE_GRP3: B0 0x0F(2)]

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(5) IDLE detection for long time period

To perform CCA IDLE detection for a long time, it can be set by IDLE_WAIT [9:0] of [IDLE_WAIT_L:B0 0x3C] and

[IDLE_WAIT_H: B0 0x3B(1-0)].

Using IDLE_WAIT [9:0] of [IDLE_WAIT_L:B0 0x3C] and [IDLE_WAIT_H: B0 0x3B(1-0)], it is possible to detect IDLE

longer than the average period (128 µs for eight times of averaging process with 16 µs average interval). This function

counts how many times the state where the moving average of ED value becomes equal to or smaller than [CCA_LVL: B0

0x37] is continued, and it makes IDLE determination when the count reaches or exceeds IDLE_WAIT [9:0]. Even when this

function is used, when the moving average of ED value exceeds [CCA_LVL: B0 0x37], BUSY is determined immediately

without waiting for the duration of time set by IDLE_WAIT [9:0].

The following timing diagram is IDLE detection setting IDLE_WAIT[9:0].

[ED value 8 times average IDLE detection case]

[Condition]

CCA mode

Normal mode

ED_AVG[2:0]=0b011 (ED value 8 times average)

[ED_CTRL: B0 0x41(2-0)]

IDLE_WAIT[9:0] = 0b00_0000_0011 (IDLE detection time 48 μs) [IDLE_WAIT_L: B0 0x3C], [IDLE_WAIT_H: B0

0x3B(1-0)]

CCA_EN

[CCA_CTRL: B0 0x39(4)]

Average interval

(16 μs)

ED value average period (128 µs)

IDLE determination time (48 µs)

ED value

(Internal signal)

ED1

ED2

ED7

ED8

ED9

ED10 ED11

...

Averaging

Average ED value

Select ED value displayed in

[ED_RSLT: B0 0x3A]

ED

(2-9)

ED

(1-8)

INVALID

(3-10) (4-11)

< CCA_LVL

B0 0x37

IDLE_WAIT[9:0]

[IDLE_WAIT_H/L:B0

0x3B/3C]

0x000

0x001 0x002 0x003

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

0b00 (IDLE)

0b10 (determination on-going)

IDLE_WAIT start

INT[18]

[INT_SOURCE_GRP3: B0 0x0F(2)]

CCA execution period (Min.128 µs+48 µs = 176 µs)

When average ED value <

CCA_LVL continues for three

times of average interval period

(48 µs), then IDLE is

determined.

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[ED value single average IDLE detection case]

[Condition]

CCA mode

Normal mode

ED_AVG[2:0]=0b000 (ED value 1 times average)

IDLE_WAIT[9:0] = 0b00_0000_1110 (IDLE detection time 224 μs)

[ED_CTRL: B0 0x41(2-0)]

[IDLE_WAIT_L: B0 0x3C], [IDLE_WAIT_H: B0

0x3B(1-0)]

CCA_EN

[CCA_CTRL: B0 0x39(4)]

Average interval

(16 μs)

IDLE detection period (224 µs)

ED value

(Internal signal)

ED0

ED14

ED1

ED2

ED3

ED13

...

Do not average

Average ED value

Select ED value displayed in

[ED_RSLT: B0 0x3A]

ED

(12)

ED

(13)

ED

(14)

ED

(0)

ED

(1)

ED

(2)

INVALID

...

If IDLE_WAIT = 0x000,

IDLE detection here.

< CCA_LVL

IDLE_WAIT[9:0]

[IDLE_WAIT_L]B0 0x3C

[IDLE_WAIT_H]B0 0x3B

0x000

0x001 0x002

...

0x00C 0x00D 0x00E

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

0b00 (IDLE)

0b10 (determination on-going)

INT[18]

[INT_SOURCE_GRP3: B0 0x0F(2)]

CCA execution period (Min.16 µs + 224 µs = 240 µs)

Because average ED value <

CCA_LVL continued for the

duration of 14 times of the

average interval period,

IDLE is determined.

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(6) CCA operation during diversity

(a) CCA operation during diversity search

During diversity search, if CCA command is issued, diversity search will be terminated and CCA will start.

Upon CCA starting, antenna is fixed to the reset value (*1), and is maintained until the next diversity search is conducted.

However, if antenna specification function ([ANT_CTRL: B0 0x4C(5-4)]) is enabled, it is fixed to the antenna which was

specified by the register function. After CCA completion, diversity search will be resumed.

*1: The setting is described in the upper most section of “RX” of each table in “Function Description Diversity Function

ANT_SW/TRX_SW Setting”.

If RX_ANT_EN = 0b1, switch to the antenna

specified by RX_ANT.

If RX_ANT_EN=0b0. ANT1 is default antenna.

After CCA completion, diversity search is resumed.

ANT_SW

CCA_EN

[CCA_CTRL: B0 0x39(4)]

CCA_DONE

[INT_SOURCE_GRP3: B0 0x0F(2)]

Diversity Search

CCA

Diversity Search

[Note]

During CCA operation, RX operation is performed at the same time. Even if CCA completion interrupt is not generated,

SyncWord detection interrupt ([INT_SOURCE_GRP2: B0 0x0E(5)]), FIFO-Full trigger interrupt ([INT_SOURCE_GRP1: B0

0x0D(5)]), RX completion interrupt ([INT_SOURCE_GRP3: B0 0x0E(0)]), and CRC detection error interrupt

([INT_SOURCE_GRP3: B0 0x0E(1)]) may be generated.

For details of diversity function, please refer to “Diversity Function”.

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(b) Operation when CCA is executed before RX_ON during diversity ON

If diversity ON setting and CCA operation setting are enabled before RX_ON state, CCA will start without the diversity search

operation after RX_ON state transition. After CCA completion, diversity search will be performed.

If RX_ANT_EN = 0b1, switch to the antenna

specified by RX_ANT.

If RX_ANT_EN=0b0. ANT1 is default antenna.

After CCA completion, diversity search is performed.

RX_ON

ANT_SW

2DIV_DONE

[2DIV_RSLT: B0 0x49(7)]

CCA_EN

[CCA_CTRL: B0 0x39(4)]

CCA

Diversity Search

CCA_DONE

INT[18][INT_SOURCE_GRP3: B0 0x0F(2)]

(7) CCA threshold setting

CCA threshold value, defined by [CCA_LVL: B0 0x37] register, should be set by considering the desired input level (ED

value), variations (IC components variation, temperature fluctuation), and other losses (antenna, matching circuits, etc.).

Relationship between input level and ED value are described in the following formula.

[2.4 k/4.8 kbps]

ED value = 255/80 * (120 + Input level [dBm] - Variation - Other loss)

In order to validate whether CCA threshold is optimized or not, CCA should be executed to confirm the level changing from

IDLE to BUSY, every time input level is changed.

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●TX Related Function

○Ramp Control Function

Ramp control function reduces the spurious emissions at the time of transmission startup and stop time.

Ramp control can be performed by the following registers.

Setting

Ramp control counter increment setting

Ramp control reference clock cycle setting

Ramp-up time setting

Register

RAMP_INC([RAMP_CTRL1: B3 0x41(1-0)])

RAMP_CLK_STEP([RAMP_CTRL1: B3 0x41(2)])

RAMP_CLK_SET_R([RAMP_CTRL2: B3 0x42])

RAMP_CLK_SET_F([RAMP_CTRL3: B3 0x43])

Ramp-down time setting

Ramp-up time and ramp-down time can be calculated by the following formulas.

Ramp-up time [s] = Ramp control reference clock cycle setting (RAMP_CLK_STEP([RAMP_CTRL1: B3

0x41(2)])) *

Ramp-up time setting (RAMP_CLK_SET_R[6:0]([RAMP_CTRL2: B3 0x42(6-0)]))} *

Maximum amplitude setting (PA_REG_ADJ[8:0]([PA_REG_ADJ_H: B0 0x67(0), PA_REG_ADJ_L: B0

0x68(7-0)])) /

Ramp control counter increment setting (RAMP_INC[1:0]([RAMP_CTRL1: B3 0x41(1-0)]))

Ramp-down time [s] = Ramp control reference clock cycle setting (RAMP_CLK_STEP([RAMP_CTRL1: B3 0x41(2)])) *

Ramp-down time setting (RAMP_CLK_SET_F[6:0]([RAMP_CTRL3: B3 0x43(6-0)]))} *

Maximum amplitude setting (PA_REG_ADJ[8:0]([PA_REG_ADJ_H: B0 0x67(0), PA_REG_ADJ_L:B0 0x68(7-0)])) /

Ramp control counter increment setting (RAMP_INC[1:0]([RAMP_CTRL1: B3 0x41(1-0)]))

RF signal

Transmitter

power

[PA_REG_ADJ: B0

0x67/68]

Min

Time

Ramp-up time

Ramp-down time

In the reset, maximum setting or Sigfox setting state (PA output power + 13 dBm), the ramp-up and -down times (example) will

be as follows:

Reset state

(min.)

Sigfox

setting

Maximum

setting

Setting register

RAMP_INC[1:0] ([RAMP_CTRL1: B3 0x41(1-0)])

RAMP_CLK_STEP ([RAMP_CTRL1: B3 0x41(2)])

RAMP_CLK_SET_R[6:0] ([RAMP_CTRL2: B3

0x42(6-0)])

RAMP_CLK_SET_F[6:0] ([RAMP_CTRL3: B3

0x43(6-0)])

0x0

0x1

0x0

0x1

0x01

0x3F

0x7F

PA_REG_ADJ[8:0]([PA_REG_ADJ_H: B0 0x67(0),

PA_REG_ADJ_L:B0 0x68(7-0)])

0x0E4

17.7us

0x0E4

Ramp-up/down time

17.8ms

25.7ms

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●Other Functions

○Data Rate Setting Function

(1) Data rate change setting

ML7456N RF part supports various TX/RX data rate setting defined by the following registers.

TX ... [TX_RATE_H: B1 0x02] and [TX_RATE_L: B1 0x03]

RX ... [RX_RATE1_H: B1 0x04], [RX_RATE1_L: B1 0x05] and [RX_RATE2: B1 0x06]

TX/RX data rate can be defined in the following formula.

[TX]

TX data rate [bps] = round (Master clock frequency [Hz] / 10/ [TX_RATE])

The following table shows the recommended value for each data rate. By setting TX_DRATE([DRATE_SET: B0 0x06(3-0)],

following register setting values are automatically set to [TX_RATE_H: B1 0x02] and [TX_RATE_L: B1 0x03].

[TX_RATE_H][ TX_RATE_L]

Data rate deviation

TX data rate [kbps]

setting value (decimal)

[%] *1

0.00

-0.27

0.00

-0.12

0.00

1.2

2.4

4.8

3000

1500

750

375

360

188

240

110

72

9.6

10.0

19.2

15.0

32.768

50

100

36

*1 Data rate deviation is assumption that frequency deviation of master clock is 0ppm.

If the data rate deviation becomes large by using the transmission data rate calculated by the formula above, the data rate

deviation can be reduced by using [TX_RATE2_H: B1 0x7C] and [TX_RATE2_L: B1 0x7D].

TX_RATE2[13:0] = round [[ {1/data rate (bps)} –

{1 / (Master clock frequency (Hz) / TX_RATE[11:0]) x 9}] /

{1 / Master clock frequency (Hz)}]

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[RX]

RX data rate [bps] = round ({Master clock frequency [Hz] / N} / {[RX_RATE1] * [RX_RATE2])})

* When N=1(LOW_RATE_EN=0b0)

When N=2(LOW_RATE_EN=0b1)

The following table shows the recommended value for each data rate (when LOW_RATE_EN([CLK_SET2: B0 0x03(0)])=0b1

is set). By setting RX_DRATE([DRATE_SET: B0 0x06(7-4)]), following register setting values are automatically set to

[RX_RATE1_H: B1 0x04], [RX_RATE1_L: B1 0x05], and [RX_RATE2: B1 0x06].

[RX_RATE1_H][RX_RATE1_L]

[RX_RATE2]

setting value (decimal)

RX data rate [kbps]

setting value (decimal)

1.2

2.4

4.8

120

60

30

15

8

12

9

5

125

120

117

100

110

90

9.6

10.0

19.2

15.0

20

32.768

40

5

50

100

3

2

120

90

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[Note]

1. When LOW_RATE_EN([CLK_SET2: B0 0x03(0)])=0b0 is set, the RX data rate should be calculated by the formula above.

It should be noted that when LOW_RATE_EN=0b0 is set, even if TX/RX data rate setting register ([DRATE_SET: B0

0x06]) is set, the optimum values are not set to [RX_RATE1_H: B1 0x04], [RX_RATE1_L: B1 0x05], and [RX_RATE2: B1

0x06] automatically.

(2) Other register settings associate with data rate change

When the data rate is changed, registers should be changed according to the Initialization table.

[Note]

1. Please change data rate setting in TRX_OFF state.

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○Interrupt Generation Function

This LSI supports interrupt generation function. When interrupt occurs, interrupt notification signal (SINTN) becomes “L” to

notify interrupt to the host MCU. Interrupt events are categorized into three groups: [INT_SOURCE_GRP1: B0 0x0D], and

[INT_SOURCE_GRP2: B0 0x0E], and [INT_SOURCE_GRP3: B0 0x0F]. Each interrupt event can be masked by

[INT_EN_GRP1: B0 0x10], and [INT_EN_GRP2: B0 0x11], and [INT_EN_GRP3: B0 0x12]. Interrupt signal (SINTN) can be

output from GPIO* or EXT_CLK pin. For output settings, refer to [GPIO1_CTRL: B0 0x4E], [GPIO1_CTRL: B0 0x4F],

[GPIO2_CTRL: B0 0x50], [GPIO3_CTRL: B0 0x51] and [EXTCLK_CTRL: B0 0x52].

[Note]

If any single unmasked interrupt event occurs, SINTN maintains Low.

(1) Interrupt events table

Each interrupt event is described below table.

Register

Interrupt name

INT[0]

Function

Clock stabilization completion interrupt

VCO calibration completion interrupt or

Fuse access completion interrupt or

IQ adjustment completion interrupt

PLL unlock interrupt/

INT[1]

INT[2]

Out of VCO adjusting voltage range detected interrupt

RF state transition completion interrupt

FIFO-Empty interrupt

INT_SOURCE_GRP1

INT[3]

INT[4]

INT[5]

FIFO-Full interrupt

INT[6]

INT[7]

INT[8]

Wake-up timer completion interrupt

Clock calibration completion interrupt

RX completion interrupt

INT[9]

CRC error interrupt

INT[10]

INT[11]

INT[12]

INT[13]

INT[14]

INT[15]

INT[16]

INT[17]

INT[18]

INT[19]

INT[20]

INT[21]

INT[22]

INT[23]

Diversity search completion interrupt

RX Length error interrupt

Reserved

SyncWord detection interrupt

Field checking interrupt

Sync error interrupt

TX completion interrupt

TX Data request accept completion interrupt

CCA completion interrupt

TX Length error interrupt

TX FIFO access error interrupt

Reserved

INT_SOURCE_GRP2

INT_SOURCE_GRP3

General purpose timer 1 interrupt

General purpose timer 2 interrupt

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(2) Interrupt generation timing

In each interrupt generation, timing from reference point to interrupt generation (notification) is described in the following table.

Timeout procedure for interrupt notification waiting is also described below.

[Note]

(1) The following table shows values at 100 kbps. For any symbol rate, replace the value described as symbol time with the

symbol period in the following table.

(2) The following table uses the following format for TX/RX data.

10 byte

Preamble

2 byte

SyncWord

1 byte

Length

24 byte

User data

2 byte

CRC

(3) Even when an interrupt notification is set to OFF, ML7456N RF part internally holds the interrupt. When the interrupt

notification setting is then changed from OFF to ON without clearing the interrupt, it will be notified. When the interrupt

occurs, it is recommended that interrupt should be cleared after turning off the interrupt notification.

Timing from reference point to interrupt generation

Interrupt notification

Reference point

or interrupt generation timing

INT[0]

Clock

stabilization crystal

completion

In case of

RESETN release

(upon power-up)

Exit from SLEEP

(recovered from

SLEEP)

300 to 500 µs

oscillator

circuits

TCXO

used

TCXO_EN setting 10 to 500 µs

(upon power-up)

Exit from SLEEP

(recovered from

SLEEP)

10 to 500 µs

INT[1]

INT[2]

VCO calibration

completed

VCO calibration

start

9ms

-

(TX) during TX after PA_ON

(RX) during RX after RX enable.

(TX) PA_ON rise

PLL unlock detection

Out of VCO adjusting

voltage range detected

RF state transition

completion

-

(RX) RX enable rise

INT[3]

TX_ON command (IDLE) 143 μs

(RX) 24 μs

RX_ON command (At IDLE) 118μs

(TX) 25μs

TRX_OFF

command

Force_TRX_OFF

command

(TX) 24μs

(RX) 5 μs

(TX) 24μs

(RX) 5 μs

INT[4]

INT[5]

FIFO-EMPTY

TX_ON command Empty trigger level is set to 0x02.

(TX)

(*1)

(NRZ encoding)

RF wake-up (210 µs)+(preamble to 22nd Data byte)x10(bit time) =

3010 µs)

-(RX)

-(TX)

SyncWord

detection

(RX)

By FIFO read, FIFO usage is under trigger level

By FIFO write, FIFO usage exceed trigger level

Full trigger level is set to 0x05.

(NRZ encoding)

500 μs (5-byte data x 10 μs (bit time))

FIFO-FULL

INT[6]

INT[7]

Wake-up timer completion

SLEEP setting

Wake-up timer is completed.

For details, please refer to the “Wake-up timer”.

Calibration timer is completed.

For details, please refer to ““Low Speed Clock Shift Detection

Function””.

Clock calibration

completion

Calibration start

INT[8]

Data reception completion

SyncWord

detection

When the length of L-field is 1 byte, and NRZ encoding is used, after

2160 μs

(L-field length (8 bit)x10(symbol time)=80 μs, data length

((Data to CRC: bit)x10(symbol time)=2080 μs))

(Format A/B) each RX CRC block calculation completion

(Format C) RX completion

INT[9]

CRC error

SyncWord

detection

-

INT[10]

Diversity search completion

SyncWord detection during diversity enable setting

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Timing from reference point to interrupt generation

or interrupt generation timing

80 μs(L-field 1 byte)

160 μs(L-field 2 byte)

-

Interrupt notification

RX Length error

Reference point

INT[11]

SyncWord

detection

-

INT[12]

INT[13]

INT[14]

INT[15]

Reserved

SyncWord detection

Field check

-

SyncWord detection

Match or mismatch detected in Field check

During RX after SyncWord detection, out-of-sync detected.

(When RXDIO_CTRL([DIO_SET: B0 0x0C(7-6)]) is set to 0b00 or

0b11)

Sync error

INT[16]

INT[17]

Data transmission

completion

TX Data request accept

completion

TX_ON command RF wake-up+[TX data+3](bit)

(*1)

=210μs+315 bit x 10μs (bit time)=3360μs

-

After full length data is written to the TX_FIFO.

(It is considered as transmitting when using FIFO trigger to write

additional data in FAST_TX mode)

INT[18]

CCA completion

CCA execution

start

(1)Normal mode

(ED value average times + IDLE_WAIT setting) x Average period

(2) IDLE detection mode

○ IDLE detection

(ED value average times + IDLE_WAIT setting) x Average period

○ BUSY detection

ED value average times x Average interval

Average interval is 16 μs.

INT[19]

INT[20]

TX Length error

TX FIFO access error

-

When setting Length for [TX_PKT_LEN_H/L: B0 0x7A/0x7B]

(1) When data was written when there was no free space on FIFO

(2) When additional data was written to FIFO, overflow occurred

(3) When there was no more data to transmit during transmission

-

INT[21]

INT[22]

Reserved

General purpose timer 1

-

Timer start

General purpose timer 1 completion

General purpose timer clock cycle * Division setting [GT_CLK_SET:

B0 0x33] * B0 0x33]) *

After general purpose timer interval setting ([GT1_TIMER: B0 0x34])

INT[23]

General purpose timer 2

completion

Timer start

General purpose timer 2 completion

General purpose timer clock cycle * Division setting [GT_CLK_SET:

B0 0x33] * B0 0x33]) *

After general purpose timer interval setting ([GT2_TIMER: B0 0x35])

(*1) Before issuing TX_ON, writing full-length TX data to the TX_FIFO.

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(2) Clearing interrupt conditions

Interrupt notification

Recommended clearing timing for interrupts

INT[0]

INT[1]

CLK stabilization completion

VCO calibration completion

Out of VCO adjusting voltage

range detected

INT[2]

INT[3]

INT[4]

PLL unlock detection

RF state transition completion

FIFO-EMPTY

Clear before the next EMPTY trigger generation timing

Clear before the next FULL trigger generation timing

INT[5]

FIFO-FULL

INT[6]

INT[7]

Wake-up timer completion

Clock calibration

INT[8]

INT[9]

Data reception completion

CRC error

Diversity search completion

RX Length error

Reserved

SyncWord detection

Field check

Clear before the next packet reception

After interrupt generated

INT[10]

INT[11]

INT[12]

INT[13]

INT[14]

INT[15]

INT[16/]

INT[17]

Sync error

Data transmission completion

TX Data request accept

completion

Clear before the next packet transmission

Clear before the next packet reception

INT[18]

CCA completion

Clear before the next CCA execution

(Note) clearing interrupt erase CCA result as well.

INT[19]

INT[20]

INT[21]

INT[22]

INT[23]

TX Length error

TX FIFO access error

Reserved

General purpose timer 1

General purpose timer 2

completion

Clear before the next packet transmission

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○Low Speed Clock Shift Detection Function

This LSI has low speed shift detection function to compensate inaccurate clock generated by RC oscillator (external clock or

internal RC oscillation circuits). By detecting frequency shift of the wake up timer, host can set wake-up timer parameters which

taking frequency shift into consideration. More accurate timer operation is possible by considering the offset of wake-up timer

clock frequency detected by this function and adjusting the wake-up timer interval setting ([WUT_INTERVAL_H/L: B0

0x2F/0x30]) or continuous operation timer interval setting ([WU_DURATION: B0 0x31]).

Setting

Register

Frequency shift detection

clock frequency setting

Calibration time

[CLK_CAL_SET: B0 0x70]

[CLK_CAL_TIME: B0 0x71]

Clock calibration result value

[CLK_CAL_H: B0 0x72] and [CLK_CAL_L: B0 0x73]

This function counts the low speed clock cycle for wake-up timer using the accurate and high speed internal clock, and the

count result is displayed in the [CLK_CAL_H/L: B0 0x72/0x73] register. Above setting and count numbers are as follows:

High speed clock counter = {Wakeup timer clock cycle[SLEEP/WU_SET:B0 0x2D(2)] *

Clock calibration time setting ([CLK_CAL_TIME:B0 0x71(5-0)]) /

{Master clock cycle (36 MHz) / Clock division setting ([CLK_CAL_SET: B0 0x70(7-4)])}

Clock calibration time is as follows:

Clock calibration time[sec] = Wakeup timer clock cycle * Clock calibration time setting

[Wake-up timer correction example]

Assuming no division in the internal high speed clock, calibration time set to 10 cycles, wake-up timer set to 1000(0x3E8)

Condition: Wake-up timer clock frequency = 32.768 kHz

Detection clock division setting CLK_CAL_DIV[3:0] ([CLK_CAL_SET: B0 0x70(7-4)])= 0b0000

Calibration time setting [CLK_CAL_TIME] = 0x0A

Wake-up timer setting [WUT_INTERVAL:B0 0x2F,30] = 0x03E8(1000)

Ideal high speed clock count is as follows:

High speed clock count = (1/32.768 kHz) * 10 / (1/36 MHz)

= 10986(0x2AEA)

If getting [CLK_CAL_H/L:B0 0x72,73] = 0x2A03 (10755)

Counter difference = 10755 - 10986 = -231

Frequency shift = 1/[{1/32.768 kHz + (-231) / 10 * 1/36 MHz}] - 32.768 kHz = 703.78 Hz

Then finding wake-up timer clock frequency accuracy is +2.18% higher. And the compensation vale (C) is calculated as

below:

C= Wake-up timer interval([WUT_INTERVAL_H/L:B0 0x2F,30]) * frequency shift / 32.768

= 1000 * 703.78Hz / 32.768kHz

= 21

Therefore, setting wale-up timer setting value = 1000 +21 = 1021 = 0x03FD enables to achieve more accurate timer interval

timing that was supposed to be set at 32.768 kHz.

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[Note]

1. If calibration time is too short or if high speed counter is divided into low speed clock, calibration may not be

accurate.

2. When the master clock is 36 MHz, setting [CLK_CAL_TIME: B0 0x71] = 0x3F exceeds the upper limit of clock

calibration result display value ([CLK_CAL_H/L: B0 0x72/73]). Set a value of 0x3E or smaller.

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■Application Circuits Example

Please refer to the Design Guide in details.

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■Package Dimensions

Remarks for surface mount type package

The surface mount type package is very sensitive to heat generated in the reflow process, moisture absorption during storage, etc.

Therefore, when considering the reflow mounting process, please contact our sales office about the product name, package name, number of

pins, package code, desired mounting conditions (reflow method, temperature, number of processes), storage conditions, etc.

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■Revision History

Page

Document No.

Release date

Revision description

Before

After

revision

FEDL7456N-01

FEDL7456N-02

2022.07.04

2022.09.12

-

46

-

46

Initial release

[Electrical Characteristics]-[RF]-[RF Characteristics] modified sensitivity

[Features] modified channel number of Functional timer and 16bit General

timers

FEDL7456N-03

2022.10.26

5

7

5

7

[Features] modified RX currnet cunsumption

[Electrical Characteristics]-[MCU]-[Analog Comparator Characteristics]

changed condition of input offset

40

[Electrical Characteristics]-[MCU]-[Successive Approximation Type A/D

Converter] modified condition

[Electrical Characteristics]-[RF]-[Power Consumption] modified RX state

41

43

41

43

(Note) Changes and corrections of writing errors/expressions are not included.

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Notes

1) The information contained herein is subject to change without notice.

2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals, application

notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating conditions, etc.) are

within the ranges specified. LAPIS Technology disclaims any and all liability for any malfunctions, failure or accident

arising out of or in connection with the use of LAPIS Technology Products outside of such usage conditions specified

ranges, or without observing precautions. Even if it is used within such usage conditions specified ranges, semiconductors

can break down and malfunction due to various factors. Therefore, in order to prevent personal injury, fire or the other

damage from break down or malfunction of LAPIS Technology Products, please take safety at your own risk measures such

as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups

and fail-safe procedures. You are responsible for evaluating the safety of the final products or systems manufactured by you.

3) Descriptions of circuits, software and other related information in this document are provided only to illustrate the standard

operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other

use of the circuits, software, and information in the design of your product or system. And the peripheral conditions must be

taken into account when designing circuits for mass production. LAPIS Technology disclaims any and all liability for any

losses and damages incurred by you or third parties arising from the use of these circuits, software, and other related

information.

4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS

Technology or any third party with respect to LAPIS Technology Products or the information contained in this document

(including but not limited to, the Product data, drawings, charts, programs, algorithms, and application examples、etc.).

Therefore LAPIS Technology shall have no responsibility whatsoever for any dispute, concerning such rights owned by

third parties, arising out of the use of such technical information.

5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer systems,

gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our Products in

applications requiring a high degree of reliability (as exemplified below), please be sure to contact a LAPIS Technology

representative and must obtain written agreement: transportation equipment (cars, ships, trains, etc.), primary

communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and

power transmission systems, etc. LAPIS Technology disclaims any and all liability for any losses and damages incurred by

you or third parties arising by using the Product for purposes not intended by us. Do not use our Products in applications

requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters,

etc.

6) The Products specified in this document are not designed to be radiation tolerant.

7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this document. However,

LAPIS Technology does not warrant that such information is error-free and LAPIS Technology shall have no responsibility

for any damages arising from any inaccuracy or misprint of such information.

8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.

LAPIS Technology shall have no responsibility for any damages or losses resulting non-compliance with any applicable

laws or regulations.

9) When providing our Products and technologies contained in this document to other countries, you must abide by the

procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US

Export Administration Regulations and the Foreign Exchange and Foreign Trade Act..

10) Please contact a ROHM sales office if you have any questions regarding the information contained in this document or

LAPIS Technology's Products.

11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Technology.

(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.

2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan

https://www.lapis-tech.com/en/

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型号：	ML7456N (新产品)
厂家：	ROHM
描述：	ML7456N是一款集成了微控制器和315MHz～920MHz频段无线单元的Sub-GHz低功耗无线LSI。ML7456N的无线单元相当于ML7414，微控制器单元配备了蓝碧石自有的16bit CPU内核、64KB Flash ROM和8KB RAM。无线控制器微控制器
文件：	总218页 (文件大小：3214K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ML7456N (新产品) [ROHM]

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