ML9092-04 [ROHM]
ML9092-01/02/03/04是带按键扫描功能的内置RAM的 LCD驱动器，非常适用于汽车音响系统的显示应用。采用位图方式，显示用RAM的1位数据与LCD面板1个点的亮灯和非亮灯相对应，因此可支持灵活性更高的显示。最多可实现60 × 10点（-01为56 × 10 点、-02/-03/-04为 60× 10点）的图形显示。另外，-01和-02内置升压电路，因此无需LCD驱动用的电源电路。（驱动大尺寸显示面板时，请使用从外部供给LCD驱动电压的-03）此外，还内置按键扫描电路（-01/04为5 × 5 按键扫描，-02/-03为6 × 4按键扫描），因此无需通过CPU进行按键扫描，从而可以更有效地使用CPU端口。;
| 型号： | ML9092-04 |
| 厂家： | 
ROHM |
| 描述： | ML9092-01/02/03/04是带按键扫描功能的内置RAM的 LCD驱动器，非常适用于汽车音响系统的显示应用。采用位图方式，显示用RAM的1位数据与LCD面板1个点的亮灯和非亮灯相对应，因此可支持灵活性更高的显示。最多可实现60 × 10点（-01为56 × 10 点、-02/-03/-04为 60× 10点）的图形显示。另外，-01和-02内置升压电路，因此无需LCD驱动用的电源电路。（驱动大尺寸显示面板时，请使用从外部供给LCD驱动电压的-03）此外，还内置按键扫描电路（-01/04为5 × 5 按键扫描，-02/-03为6 × 4按键扫描），因此无需通过CPU进行按键扫描，从而可以更有效地使用CPU端口。 汽车音响 驱动 CD 电源电路 驱动器 |
| 文件： | 总67页 (文件大小：445K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dear customer
LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October,
2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which
LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS
Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business.
Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor"
and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd."
Furthermore, there are no changes to the documents relating to our products other than
the company name, the company trademark, logo, etc.
Thank you for your understanding.
LAPIS Technology Co., Ltd.
October 1, 2020
FEDL9092-01
Issue Date: Nov. 4, 2003
ML9092-01/02/03/04
LCD Driver with Key Scanner and RAM
GENERAL DESCRIPTION
The ML9092-01/02/03/04 are LCD drivers that have internal RAM and a key scan function. They are best suited
for car audio displays.
Since 1-bit data of the display data RAM corresponds to the light-on or light-off of 1-dot of the LCD panel (a bit
map system), a flexible display is possible.
A graphic display system of a maximum of 60 10 dots (56 10 dots for ML9092-01, 60 10 dots for
ML9092-02/03/04). can be implemented.
The ML9092-01/02 do not require any power supply circuit to drive the LCD, because they have internal voltage
doublers. (If a large-sized panel is driven, use the ML9092-03, to which the LCD driving voltage is supplied
externally.)
The internal key scan circuit (5 5 key scanning for ML9092-01/04, 6 4 key scanning for ML9092-02/03) has
eliminated the needs of key scanning by the CPU, thereby enabling the efficient use of the CPU ports.
FEATURES
Logic voltage
: 4.5 to 5.5 V
LCD drive voltage
Segment output
: 4.5 to 16.5 V (positive voltage)
: 56 outputs for ML9092-01; 60 outputs for ML9092-02/03/04
Common output
Built-in bit-mapped RAM
: 10 outputs
: 60 10 = 600 bits (for ML9092-01 only: 56 10 = 560 bits for the RAM
display area)
4-pin serial interface with CPU: CS, CP, DI/O, KREQ
Built-in LCD drive bias resistors
Built-in voltage doubler circuit
For the ML9092-01/04, the built-in 5 5 key scanner makes it possible to read the status of 25 key switches and
1-channel rotary encoder. In addition, the ML9092-01/04 have an 8-bit, 3-channlel PWM circuit built in.
For the ML9092-02/03, the built-in 6 4 key scanner makes it possible to read the status of 24 key switches and
1-channel rotary encoder.
Port A output
Port B output
: 1 pin, output current = –15 mA
: 3 pins, output current = –2 mA
: Can be used for LED driving
: Applies to ML9092-01/04 (capable of PWM
output)
Port C output
Port D output
Temperature range
: 5 pin, output current = –2 mA
: 5 pins, output current = –2 mA
: –40 to +85C
: Applies to ML9092-01 only
: Applies to ML9092-01 only
Package: 100-pin plastic TQFP (TQFP100-P-1414-0.50-K)
(Product name: ML9092-01TB, ML9092-02TB, ML9092-03TB, ML9092-04TB)
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FEDL9092-01
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ML9092-01/02/03/04
Comparison between the ML9092-01, ML9092-02, ML9092-03, and ML9092-04
Item
ML9092-01
10 Max.
8 56
9 56
10 56
1
ML9092-02
10 Max.
8 60
9 60
10 60
1
ML9092-03
10 Max.
8 60
9 60
10 60
1
ML9092-04
10 Max.
8 60
9 60
10 60
1
Number of common outputs
Number of dots on the LCD screen
(selectable by program)
Number of port A outputs
Number of port B outputs
3
0
0
3
Number of port C and D outputs (see
note below)
5 each
0
0
0
Key scan (see note below)
Rotary encoder
5 5 key scan
1 channel
4 6 key scan
1 channel
Yes
4 6 key scan
5 5 key scan
1 channel
1 channel
No
Voltage doubler
Yes
No
PWM circuit
8-bit, 3-channel
No
No
8-bit, 3-channel
Note: The key scan function and port C/D cannot be used concurrently. Use either.
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
BLOCK DIAGRAM
ML9092-01
COM1 COM10 PB0 PB2 SEG1
SEG56
VIN
10 Output
3 Port
56 Output
Segment Drivers
VS1–
VC1+
VOUT
Voltage
Doubler
Common
Drivers
Drivers
Shift
Register
Data Latch
LCD Bias
Voltage
Driving
Circuit
V0
V2
Display Data RAM
56 10 Bit
I/O
Buffer
X Address Decoder
CS
CP
X Address Counter
X Address Register
DI/O
Timing
Generator
OSC1
Oscillation
Circuit
OSC2
5
5 Key Scan/10 Port Drivers
1 Port Driver
and Encoder Switch Interface
RESET
TEST
VDD
VSS
KPS
PA0
KREQ
B
A
C0/ C1/ C2/ C3/ C4/ R0/ R1/ R2/
R3/ R4/
C0 C1 C2
C3 C4
D3 D4
D0 D1 D2
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FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
ML9092-02
COM1
COM10 SEG1
SEG60
VIN
Voltage
Doubler
VS1–
VC1+
VOUT
10 Output
Common Drivers
60 Output Segment Drivers
Data Latch
Shift Register
V0
LCD Bias
Voltage
Driving
Circuit
Display Data RAM
V2
60 10 Bit
I/O Buffer
X Address Decoder
X Address Counter
X Address Register
CS
CP
DI/O
Timing
Generator
OSC1
Oscillation
Circuit
OSC2
4
6 Key Scan
1 Port Driver
and Encoder Switch Interface
RESET
TEST
VDD
VSS
KREQ
A
B
PA0
C0 C1 C2 C3 R0 R1 R2 R3 R4 R5
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FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
ML9092-03
COM1
COM10 SEG1
SEG60
VHIN
10 Output
Common Drivers
60 Output Segment Drivers
V0
LCD Bias
Voltage
Driving
V1
Shift Register
Data Latch
Circuit
V2
V3
Display Data RAM
60 10 BIT
I/O Buffer
X Address Decoder
X Address Counter
X Address Register
CS
CP
DI/O
Timing
Generator
OSC1
Oscillation
Circuit
OSC2
4
6 Key Scan
1 Port Driver
and Encoder Switch Interface
RESET
TEST
VDD
VSS
KREQ
A
B
PA0
C0 C1 C2 C3 R0 R1 R2 R3 R4 R5
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FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
ML9092-04
COM1 COM10 PB0 PB2 SEG1
SEG60
VHIN
10 Output
3 Port
60 Output
Segment Drivers
Common
Drivers
Drivers
LCD Bias
Voltage
V0
Shift
Register
Driving
Circuit
V2
Data Latch
Display Data RAM
60 10 Bit
I/O
Buffer
X Address Decoder
CS
CP
X Address Counter
X Address Register
DI/O
Timing
Generator
OSC1
Oscillation
Circuit
OSC2
5
5 Key Scan
1 Port Driver
and Encoder Switch Interface
RESET
TEST
VDD
VSS
PA0
KREQ
B
A
C0 C1 C2 C3 C4 R0 R1 R2
R3 R4
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FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
PIN CONFIGURATION (TOP VIEW)
ML9092-01
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
IN
V
SEG50
2
VC1+
SEG49
3
S1-
V
SEG48
4
VOUT
SEG47
5
O
V
SEG46
6
SEG45
NC
7
2
V
SEG44
8
VSS
RESET
KREQ
DI/O
SEG43
9
SEG42
10
SEG41
11
SEG40
12
SEG39
CP
ML9092-01
13
SEG38
CS
14
SEG37
C0/D0
C1/D1
C2/D2
C3/D3
C4/D4
R0/C0
R1/C1
R2/C2
R3/C3
R4/C4
A
15
SEG36
16
SEG35
17
SEG34
18
SEG33
19
SEG32
20
SEG31
21
SEG30
22
SEG29
23
SEG28
24
SEG27
25
SEG26
B
100-Pin Plastic TQFP
7/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
ML9092-02
VIN
1
75
SEG50
VC1+
2
74
SEG49
VS1-
3
73
SEG48
VOUT
4
72
SEG47
VO
5
71
SEG46
6
70
SEG45
NC
V2
7
69
SEG44
8
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SS
V
SEG43
9
SEG42
RESET
KREQ
DI/O
CP
CS
C0
10
SEG41
11
SEG40
12
SEG39
ML9092-02
13
SEG38
14
SEG37
15
SEG36
C1
16
SEG35
C2
17
SEG34
C3
18
SEG33
R0
19
SEG32
R1
20
SEG31
R2
21
SEG30
R3
22
SEG29
R4
23
SEG28
R5
24
SEG27
A
25
SEG26
B
100-Pin Plastic TQFP
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FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
ML9092-03
1
75
SEG50
NC
VHIN
2
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG49
3
0
V
SEG48
4
V
1
SEG47
5
SEG46
NC
6
2
V
SEG45
7
3
V
SEG44
8
SS
V
SEG43
9
SEG42
RESET
KREQ
DI/O
CP
CS
C0
10
SEG41
11
SEG40
12
SEG39
ML9092-03
13
SEG38
14
SEG37
15
SEG36
C1
16
SEG35
C2
17
SEG34
C3
18
SEG33
R0
19
SEG32
R1
20
SEG31
R2
21
SEG30
R3
22
SEG29
R4
23
SEG28
R5
24
SEG27
A
25
SEG26
B
100-Pin Plastic TQFP
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FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
ML9092-04
1
75
SEG50
OSC2
2
74
SEG49
OSC1
3
73
VDD
SEG48
4
72
VHIN
SEG47
5
71
SEG46
Vo
6
70
SEG45
NC
7
69
V2
SEG44
8
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SS
V
SEG43
9
SEG42
RESET
KREQ
DI/O
CP
CS
C0
10
SEG41
11
SEG40
12
SEG39
ML9092-04
13
SEG38
14
SEG37
15
SEG36
C1
16
SEG35
C2
17
SEG34
C3
18
SEG33
C4
19
SEG32
R0
20
SEG31
R1
21
SEG30
R2
22
SEG29
R3
23
SEG28
R4
24
SEG27
A
25
SEG26
B
100-Pin Plastic TQFP
10/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
FUNCTIONAL DESCRIPTIONS
Pin Functional Descriptions
ML9092-01
Function
Pin
63
Symbol
Type
I
Description
CS
Chip select signal input pin
Shift clock signal input pin. This pin is
connected to the Schmitt circuit internally.
64
65
CP
I
CPU interface
Serial data signal I/O pin. This pin is
connected to the Schmitt circuit internally.
DI/O
I/O
Key scan read and rotary encoder read
READY signal output pin.
66
77
KREQ
OSC1
O
I
Connect external resistors with this pin.
This pin is connected to the Schmitt circuit
internally.
If using an external clock, input it from the
OSC1 pin and leave the OSC2 pin open.
Oscillation
78
67
OSC2
O
I
Reset input. Initial settings can be
established by applying a “L” level to this
pin. This pin is connected to the Schmitt
circuit internally.
RESET
Control signal
Input pin for switching between key
scanning and ports C and D
80
79
KPS
I
I
Test input pin. This pin is connected to the
TEST
VSS pin.
Input pins that detect status of key
switches/port D output pins. When used
as input pins, these pins are connected to
the Schmitt circuit internally.
62–58
C0/D0–C4/D4
I/O
Switch signal
Key switch scan signal output pins/port C
output pins
57–53
51, 52
R0/C0–R4/C4
A, B
O
I
Rotary encoder signal input pins.
These pins are connected to the Schmitt
circuit internally.
81
84–82
50–1
100–95
94–85
76
PA0
O
O
Port A output pin
Port B output pins
Port output
PB0–PB2
SEG1–SEG56
O
LCD segment driver output pins
LCD driver output
COM1–COM10
O
—
—
LCD common driver output pins
Logic power supply pin
GND pin
VDD
VSS
68
Voltage doubler reference voltage input
pin
75
VIN
—
—
Power supply
Pins to connect a capacitor for voltage
doubler
74, 73
VC1+, VS1–
72
71, 69
70
VOUT
V0, V2
NC
—
—
—
Voltage doubler output pin
LCD bias pins
Should be left open.
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FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
ML9092-02
Function
Pin
63
Symbol
Type
I
Description
CS
Chip select signal input pin
Shift clock signal input pin. This pin is
connected to the Schmitt circuit internally.
64
65
CP
I
CPU interface
Serial data signal I/O pin. This pin is
connected to the Schmitt circuit internally.
DI/O
I/O
Key scan read and rotary encoder read
READY signal output pin.
66
77
KREQ
OSC1
O
I
Connect external resistors with this pin.
This pin is connected to the Schmitt circuit
internally.
If using an external clock, input it from the
OSC1 pin and leave the OSC2 pin open.
Oscillation
78
OSC2
O
Reset input. Initial settings can be
established by applying a “L” level to this
pin. This pin is connected to the Schmitt
circuit internally.
67
79
RESET
I
I
Control signal
Test input pin. This pin is connected to the
TEST
VSS pin.
Input pins that detect status of key
switches. These pins are connected to the
Schmitt circuit internally.
62–59
58–53
51, 52
C0–C3
R0–R5
A, B
I
O
I
Switch signal
Key switch scan signal output pins
Rotary encoder signal input pins.
These pins are connected to the Schmitt
circuit internally.
Port output
80
50–1
100–91
90–81
76
PA0
O
O
Port A output pin
SEG1–SEG60
LCD segment driver output pins
LCD driver output
COM1–COM10
O
—
—
LCD common driver output pins
Logic power supply pin
GND pin
VDD
VSS
68
Voltage doubler reference voltage input
pin
75
VIN
—
—
Power supply
Pins to connect a capacitor for voltage
doubler
74, 73
VC1+, VS1–
72
71, 69
70
VOUT
V0, V2
NC
—
—
—
Voltage doubler output pin
LCD bias pins
Should be left open.
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FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
ML9092-03
Function
Pin
63
Symbol
Type
I
Description
CS
Chip select signal input pin
Shift clock signal input pin. This pin is
connected to the Schmitt circuit internally.
64
65
CP
I
CPU interface
Serial data signal I/O pin. This pin is
connected to the Schmitt circuit internally.
DI/O
I/O
Key scan read and rotary encoder read
READY signal output pin.
66
77
KREQ
OSC1
O
I
Connect external resistors with this pin.
This pin is connected to the Schmitt circuit
internally.
If using an external clock, input it from the
OSC1 pin and leave the OSC2 pin open.
Oscillation
78
OSC2
O
Reset input. Initial settings can be
established by applying a “L” level to this
pin. This pin is connected to the Schmitt
circuit internally.
67
79
RESET
I
I
Control signal
Test input pin. This pin is connected to the
TEST
VSS pin.
Input pins that detect status of key
switches. These pins are connected to the
Schmitt circuit internally.
62–59
58–53
51, 52
C0–C3
R0–R5
A, B
I
O
I
Switch signal
Key switch scan signal output pins
Rotary encoder signal input pins.
These pins are connected to the Schmitt
circuit internally.
Port output
80
50–1,
100–91
90–81
76
PA0
O
O
Port A output pin
SEG1–SEG60
LCD segment driver output pins
LCD driver output
COM1–COM10
O
LCD common driver output pins
Logic power supply pin
GND pin
VDD
VSS
—
—
—
—
—
68
Power supply
74
VHIN
High-voltage power supply pin
LCD bias pins
73, 72, 70, 69
75, 71
V0, V1, V2, V3
NC
Should be left open.
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FEDL9092-01
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ML9092-01/02/03/04
ML9092-04
Function
Pin
63
Symbol
Type
I
Description
CS
Chip select signal input pin
Shift clock signal input pin. This pin is
connected to the Schmitt circuit internally.
64
65
CP
I
CPU interface
Serial data signal I/O pin. This pin is
connected to the Schmitt circuit internally.
DI/O
I/O
Key scan read and rotary encoder read
READY signal output pin.
66
74
KREQ
OSC1
O
I
Connect external resistors with this pin.
This pin is connected to the Schmitt circuit
internally.
If using an external clock, input it from the
OSC1 pin and leave the OSC2 pin open.
Oscillation
75
OSC2
O
Reset input. Initial settings can be
established by applying a “L” level to this
pin. This pin is connected to the Schmitt
circuit internally.
67
76
RESET
I
I
Control signal
Test input pin. This pin is connected to the
TEST
VSS pin.
Input pins that detect status of key
switches. These pins are connected to the
Schmitt circuit internally.
62–58
57–53
51, 52
C0–C4
R0–R4
A, B
I
O
I
Switch signal
Key switch scan signal output pins
Rotary encoder signal input pins.
These pins are connected to the Schmitt
circuit internally.
77
80–78
50–1,
100–91
90–81
73
PA0
Port A output pin
Port B output pins
Port output
O
O
PB0–PB2
SEG1–SEG60
LCD segment driver output pins
LCD driver output
COM1–COM10
O
LCD common driver output pins
Logic power supply pin
GND pin
VDD
VSS
—
—
—
—
—
68
Power supply
72
VHIN
V0, V2
NC
High-voltage power supply pin
LCD bias pins
71, 69
70
Should be left open.
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FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
CS
Chip select input pin. A Schmitt circuit is internally connected to this pin. An “L” level selects the chip, and an
“H” level does not select the chip. During the “L” level, internal registers can be accessed.
CP
Clock input pin for serial interface data I/O. A Schmitt circuit is internally connected to this pin. Data input to the
DI/O pin is synchronized to the rising edge of the clock. Output from the DI/O pin is synchronized to the falling
edge of the clock.
DI/O
Serial interface data I/O pin. A Schmitt circuit is internally connected to this pin. This pin is in the output state
only during the interval beginning when commands for key scan data read, RAM read or rotary encoder are written
until the CS signal rises. At all other times this pin is in the input state. (When reset, the input state is set.) The
relation between data level of this pin and operation is listed below.
Data level
“H”
LCD display
Light ON
Key status
ON
Rotary switch
Count value
Count value
“L”
Light OFF
OFF
KREQ
Key scan read and rotary encoder read READY signal output pin.
OSC1
Input pin for RC oscillation. A Schmitt circuit is internally connected to this pin. An oscillation circuit is
configured by connecting this pin and OSC2 with a resistor (R) placed across the connection (see figure below).
Make the wiring between this pin and the resistor as short as possible. If an external master oscillation clock is to
be input, input the master oscillation clock to this pin.
OSC1
R = 56 k
R
(VDD = 4.5 to 5.5 V)
OSC2
OSC2
Output pin for RC oscillation. A Schmitt circuit is internally connected to this pin. An oscillation circuit is
configured by connecting this pin and OSC1 with a resistor (R) placed across the connection (see figure above).
Make the wiring between this pin and the resistor as short as possible. If an external master oscillation clock is to
be input, leave this pin unconnected (open).
RESE
Reset signal input pin. A Schmitt circuit is internally connected to this pin. The initial state can be set by pulling
this pin to an “L” level. Refer to the “Output, I/O and Register States in Response to Reset Input” page for the
initial states of each register and display.
An internal pull-up resistor is connected to this pin. Connecting an external capacitor enables power-on reset.
TEST
Test signal input pin. Connect this pin to VSS.
15/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
R0/C0 to R4/C4 (ML9092-01), R0 to R5 (ML9092-02/03), R0 to R4 (ML9092-04)
Key switch scan signal output pins. During the scan operation, “L” level signals are output in the order of R0/C0,
R1/C1, ..., R4/C4 (ML9092-01) or R0, R1, ..., R5 (ML9092-02/03) or R0, R1, ..., R4 (ML9092-04). (Refer to the
description under the heading “Key scan” for details.) For the ML9092-01, R0 to R4 can be used as the output
ports for the general-purpose port C depending on the input signal to the KPS pin.
C0/D0 to C4/D4 (ML9092-01), C0 to C3 (ML9092-02/03), C0 to C4 (ML9092-04)
Input pins that detect the key switch status. Pull-up resistors and a Schmitt circuit are internally connected to these
pins. Assemble a key matrix between these pins and the R0/C0 to R4/C4 (ML9092-01) or R0 to R5
(ML9092-02/03) or R0 to R4 (ML9092-04) pins. For the ML9092-01, C0 to C4 can be used as the output ports for
the general-purpose port D depending on the input signal to the KPS pin.
KPS
Input pin that selects whether the R0/C0 to R4/C4 pins and C0/D0 to C4/D4 pins are used to detect the key switch
status or whether they are used as the output pins for the general-purpose ports C and D. When this pin is pulled to
a “H” level, the R0/C0 to R4/C4 pins and C0/D0 to C4/D4 pins function as pins that detect the key switch status.
When this pin is pulled to a “L” level, it functions as the output pin for the general-purpose ports C and D. This pin
must be fixed at either a “H” or “L” level.
This pin is provided only for the ML9092-01.
A, B
Input pins for encoder format rotary switches. A Schmitt circuit is internally connected to these pins. When
turning the rotary switch clockwise, input to the A pin a signal more advancing in phase than the B pin. When
turning the rotary switch counterclockwise, input to the B pin a signal more advancing in phase than the A pin.
PA0
General-purpose port A output pin. This pin can output a current of –15 mA. If this pin is used to drive an LED,
insert an external current limiting resistor in series with the LED. If this pin is not used, leave it unconnected
(open).
PB0 to PB2
Port B pins, which are used for PWM outputs. These pins are provided for the ML9092-01/04. Any pins not to be
used should be left unconnected (open).
SEG1 to SEG60(56)
Segment signal output pins for LCD driving. Any pins not to be used should be left unconnected (open). For the
ML9092-01, only SEG1 to SEG56 apply.
COM1 to COM10
Common signal output pins for LCD driving. Any pins not to be used should be left unconnected (open).
VDD
Logic power supply connection pin.
VSS
Power supply GND connection pin.
VIN
Voltage doubler reference voltage input pin. A voltage twice that which is input to this pin is output to the VOUT
pin. When the voltage doubler is not used, connect this pin to GND.
This pin is provided for the ML9092-01/02.
16/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
VS1–
Negative connection pin for the capacitor for the voltage doubler. Connect a 4.7 F (30%) capacitor between this
pin and the VC1+ pin. When the voltage doubler is not used, leave this pin unconnected (open).
This pin is provided for the ML9092-01/02.
VC1+
Positive connection pin for the capacitor for the voltage doubler. Connect a 4.7 F (30%) capacitor between this
pin and the VS1– pin. When the voltage doubler is not used, leave this pin unconnected (open).
This pin is provided for the ML9092-01/02.
VOUT
A voltage twice that which is input to the VIN pin is output to this pin. Connect a 4.7 F capacitor between this pin
and the VSS pin. When the internal voltage doubler is not used, input the specified voltage to this pin from the
outside. When built-in contrast adjustment (electronic volume) is used, leave the connection between this pin and
the V0 pin open. The LCD drive voltage will be output from the V0 pin according to the contrast adjustment value.
When built-in contrast adjustment is not used, connect this pin with the V0 pin.
This pin is provided for the ML9092-01/02.
V0, V2
LCD bias pins. A bias dividing resistor is connected to these pins.
These pins are provided for the ML9092-01/02/04.
VHIN
LCD drive high voltage power supply connection pin. When built-in contrast adjustment (electronic volume) is
used, input the LCD drive power supply voltage to this pin. The LCD drive voltage will be output from the V0 pin
according to the contrast adjustment value. When built-in contrast adjustment is not used, strap the VHIN pin and
V0 pin outside the IC, and input the LCD drive voltage into both pins.
This pin is provided for the ML9092-03/04.
V0, V1, V2, V3
LCD bias pins. A bias dividing resistor is connected to these pins. When using a large-screen LCD, however,
input the LCD bias voltage from outside the IC to these pins.
This is applicable to the ML9092-03.
17/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VDD
Condition
Ta = 25C
Ta = 25C
Rating
Unit
V
Applicable Pins
Power Supply Voltage
High Power Supply Voltage
–0.3 to +6.5
–0.3 to +18.0
VDD
VH
V
VOUT, VHIN
–0.3 to VOUT
(VHIN) + 0.3
Bias Voltage
VBI
VIN
Ta = 25C
Ta = 25C
V
V
VC1+, V0, V1, V2, V3
Voltage Doubler Reference
Voltage
–0.3 to VDD + 0.3
VIN
CS, CP, DI/O, OSC1,
C0 to C3,
Input Voltage
VI
Ta = 25C
–0.3 to VDD + 0.3
V
C0 to C4, C0/D0 to
C4/D4, KPS, A, B,
RESET
Ta = 25C
Ta = 25C
–20 to +3
–3 to +4
mA
mA
PA0
PB0 to PB2, R0/C0 to
R4/C4, C0/D0 to
C4/D4, R0 to R4,
Output Current
IO
R0 to R5, DI/O, KREQ
Power Dissipation
PD
Ta = 85C
190
mW
—
—
Storage Temperature
Tstg
—
–55 to +150
C
VSS is the reference voltage potential for all pins.
18/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VDD
Condition
—
Range
Unit
V
Applicable Pins
VDD
Power Supply Voltage
4.5 to 5.5
Voltage doubler
not used
4.5 to 16.5
4.0 to 16.5
V
VOUT
(Contrast
adjustment used)
Externally Input Power
Supply Voltage 1
Voltage doubler
not used & VOUT
pin connected
with V0 pin
VOUT
(Applies to ML9092-01/02)
V
VOUT, V0
(Contrast
adjustment not
used)
Contrast
adjustment used
4.5 to 16.5
4.0 to 16.5
V
V
VHIN
Contrast
adjustment not
used
Externally Input Power
Supply Voltage 2
VHIN
(Applies to ML9092-03/04)
VHIN, V0
(VHIN pin
connected with
V0 pin)
Bias Voltage
V0
—
4.0 to 16.5
V
V
V0
Voltage Doubler Input
Voltage
VIN
—
0.8VDD to VDD
VIN
Operating Frequency of
External Clock
fOPE
—
210 to 445
kHz
OSC1
Oscillation Resistance
Operating Temperature
R
VDD = 4.5 to 5.5 V
—
56*1
k
C
OSC1, OSC2
—
Top
–40 to +85
VSS is the reference voltage potential for all pins.
*1: Use a resistor with an accuracy of 2 %
OSC1
R
OSC2
19/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
ELECTRICAL CHARACTERISTICS
Oscillating Frequency Characteristics
(VDD = 4.5 to 5.5 V, VOUT (VHIN) = 4.5 to 16.5 V, Ta = –40 to +85C)
Condition
Typ. Max.
Parameter
Symbol
fOSC
Min.
Unit
Applicable Pins
56 k
Oscillating Frequency
210
306 445
kHz
OSC1, OSC2
(resistor with accuracy within ±2%)
DC Characteristics
(VDD = 4.5 to 5.5 V, VOUT (VHIN) = 4.5 to 16.5 V, Ta = –40 to +85C)
Parameter
Symbol
VIH1
Condition
Min.
Typ.
Max.
Unit
Applicable Pins
When input
externally
“H” Input Voltage 1
“H” Input Voltage 2
0.85VDD
0.85VDD
—
—
V
OSC1
VIH2
—
—
—
—
—
V
RESET
CP, A, B, C0–C3,
C0/D0–C4/D4,C0–C4
CS, DI/O
“H” Input Voltage 3
VIH3
0.85VDD
—
—
V
“H” Input Voltage 4
“L” Input Voltage 1
VIH4
VIL1
0.8VDD
—
—
—
—
V
V
KPS
When input
externally
0.15VDD
OSC1
“L” Input Voltage 2
“L” Input Voltage 3
“L” Input Voltage 4
VIL2
VIL3
VIL4
—
—
—
—
—
—
—
—
—
0.15VDD
0.15VDD
0.2VDD
V
V
V
RESET
CP, A , B, CS, DI/O,
KPS
C0/D0–C4/D4,C0–C3,
C0–C4
“L” Input Voltage 5
“H” Input Current 1
“H” Input Current 2
VIL5
IIH1
IIH2
—
—
—
—
—
—
—
0.23VDD
10
V
VI = VDD
VI = VDD
µA
µA
RESET
C0/D0–C4/D4,
C0–C3, C0–C4
10
DI/O, PA0, PB0–PB2,
R0/C0–R4/C4,
DI/O = Input mode,
All ports = HiZ,
VI = VDD
“H” Input Current 3
IIH3
—
—
10
µA
C0/D0–C4/D4
OSC1, CS, CP,
KPS , A , B
RESET
“H” Input Current 4
“L” Input Current 1
“L” Input Current 2
IIH4
IIL1
IIL2
VI = VDD
—
—
1
µA
mA
mA
VDD = 5 V, VI = 0 V
VDD = 5 V, VI = 0 V
–0.1
–0.9
–0.05
–0.45
–0.02
–0.18
C0/D0–C4/D4,
C0–C3,C0–C4
DI/O, PA0, PB0–PB2,
R0/C0–R4/C4,
DI/O = Input mode,
All ports = HiZ,
VI = 0 V
“L” Input Current 3
“L” Input Current 4
IIL3
–10
–1
—
—
—
—
µA
µA
C0/D–C4/D4
OSC1, CS, CP, KPS, A,
B
IIL4
VI = 0 V
20/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
Parameter
Symbol
Condition
IO = –0.4 mA
IO = –40 µA
IO = –15 mA
Min.
Typ.
—
Max.
—
Unit
V
Applicable Pins
DI/O, KREQ
OSC2
“H” Output Voltage 1
“H” Output Voltage 2
“H” Output Voltage 3
VOH1
VOH2
VOH3
VDD – 0.4
0.9VDD
—
—
V
VDD – 1.7
—
—
V
PA0
IO = –2 mA
(When R0/C0–
R4/C4 and
C0/D0–C4/D4 are
used as ports C
and D)
Only applies to
ML9092-01.
PB0–PB2,
R0/C0–R4/C4,
C0/D0–C4/D4
“H” Output Voltage 4
VOH4
VDD – 1.2
—
—
—
V
IO = –50 µA
R0/C0–R4/C4(-01),
R0–R5 (-02, -03)
R0–R4 (-04)
(When R0/C0–
R4/C4 are used
for key scanning)
“H” Output Voltage 5
VOH5
VDD – 2.0
—
V
“L” Output Voltage 1
“L” Output Voltage 2
VOL1
VOL2
IO = 0.4 mA
IO = 40 µA
—
—
—
—
0.4
V
V
DI/O, KREQ
OSC2
0.1VDD
IO = 1 mA
(When R0/C0–
R4/C4 and
C0/D0–C4/D4 are
used as ports C
and D)
PA0, PB0–PB2,
C0/D0–C4/D4,
R0/C0–R4/C4
“L” Output Voltage 3
“L” Output Voltage 4
VOL3
—
—
—
—
0.4
0.3
V
V
IO = 2.7 mA
R0/C–R4/C4 (-01),
R0–R5 (-02, -03)
R0–R4 (-04)
(When R0/C0–
R4/C4 are used
for key scanning)
VOL4
21/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
(VDD = 4.5 to 5.5 V, VOUT (VHIN) = 4.5 to 16.5 V, Ta = –40 to +85C)
Applicable
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Pins
VOS0
VOS1
VOS2
VOS3
VOC0
VOC1
VOC2
VOC3
IO = –10 µA
IO = 10 µA
IO = 10 µA
IO = +10 µA
IO = –10 µA
IO = 10 µA
IO = 10 µA
IO = +10 µA
V0 – 0.6
2/4V0 – 0.6
2/4V0 – 0.6
—
—
—
—
—
—
—
—
—
—
V
V
V
V
V
V
V
V
SEG1–SEG56
(SEG60 for
ML9092-02/03
/04)
Segment Output
Voltage 2
(1/5 bias)
2/4V0 + 0.6
2/4V0 + 0.6
VSS + 0.6
—
V0 – 0.3
3/4V0 – 0.3
1/4V0 – 0.3
—
Common Output
Voltage 1
(1/4 bias)
3/4V0 + 0.3
1/4V0 + 0.3
VSS + 0.3
COM1–
COM10
Supply Current 1
(Applies to
ML9092-01/02)
Supply Current 2
(Applies to
ML9092-01/02)
Supply Current 3
(Applies to
ML9092-01/02)
Supply Current 4
(Applies to
ML9092-01/02)
Supply Current 5
(Applies to
ML9092-03/04)
Supply Current 6
(Applies to
ML9092-03/04)
Supply Current 7
(Applies to
ML9092-03/04)
Supply Current 8
(Applies to
R = 56 k
Voltage doubler operating,
No load
External clock = 445 kHz
Voltage doubler operating,
No load
External clock = 445 kHz
Voltage doubler operating,
No load
External clock = 445 kHz
Voltage doubler not operating,
IDD1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.6
0.6
2
mA
mA
mA
mA
mA
mA
mA
A
VDD
VDD
VIN
*1
IDD2
*2
IVIN
*2
IVHIN1
1
VOUT
VDD
VDD
VHIN
VDD
No load
*3
R = 56 k
No load
IDD3
0.6
0.6
1
*4
External clock = 445 kHz
No load
IDD4
*5
*5
External clock = 445 kHz
No load
IVHIN2
R = 56 k
IDD5
100
Voltage doubler not operating,
ML9092-03/04)
No load
*6
*1:
*2:
*3:
*4:
*5:
*6:
Refer to the Current Measuring Circuit 1.
Refer to the Current Measuring Circuit 2.
Refer to the Current Measuring Circuit 3.
Refer to the Current Measuring Circuit 4.
Refer to the Current Measuring Circuit 5.
Refer to the Current Measuring Circuit 6.
22/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
(VDD = 4.5 to 5.5 V, VOUT (VHIN) = 4.5 to 16.5 V, Ta = –40 to +85C)
Applicable
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Pins
External clock = 210 kHz
VIN = 0.8 VDD to VDD
(*1)
Voltage doubler
Voltage
9.8
*3
VDB
V
VOUT
VIN 1.9 – 0.5
VIN 2
VDD = 5 V, VOUT = 10 V
(Voltage doubler not
operating, but voltage
applied externally)
Contrast data = FH,
No load
VDD = 5 V, VOUT = 10 V
(Voltage doubler not
operating, but voltage
applied externally)
Contrast data = 0H,
No load
VLCDMAX
9.5
9.8
10
V
LCD driving
voltage when
internal variable
resistor is used
V0 – VSS
VLCDMIN
6.7
5
7
9
7.3
14
V
LCD Driving
Bias Resistance
LBR
(*2)
V0 – Vss
k
*1
*3
Refer to the Voltage Doubler Voltage Measuring Circuit.
VIN = 5 V, Ta = 25C
LBR
LBR
LBR
LBR
*2
V0
V3
VSS
V2
V1
23/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
Measuring Circuits
Voltage Doubler Voltage Measuring Circuit
Voltage is doubled
(1/4 bias)
OPEN
SEG1–SEG56(60) COM1–COM10
VDD
VIN
VDD
VIN
A
+
–
VC1+
B
4.7 F
30%
–
VS1
VOUT
VO
VSS
4.7 F 30%
KREQ OPEN
+
VDB
OPEN
PA0
V
OSC2 OPEN
OSC1
100 A
OPEN
V2
f = 210 kHz
TEST
KPS
VDD
RESET
*1
VDD
CS
(C0–C3)
C0/D0–C4/D4
CP
DI/O
(R0–R5)
R0/C0–R4/C4
PB0–PB2
OPEN
Current Measuring Circuit 1
Voltage is doubled (internal oscillation)
Current Measuring Circuit 2
Voltage is doubled (external clock)
IDD1
A
IDD2
A
OPEN
OPEN
SEG1–SEG56(60)
VDD
SEG1–SEG56(60) COM1–COM10
COM1–COM10
5.5 V
5.5 V
VDD
IVIN
A
A
A
VIN
VIN
5.5 V
4.7 F
30%
+
VC1+
5.5 V
VC1+
–
B
B
4.7 F
–
30%
VSS
VSS
–
VS1
+
–
VS1
4.7 F 30%
4.7 F 30%
KREQ
PA0
OPEN
OPEN
KREQ OPEN
VOUT
VO
VOUT
VO
+
+
OPEN
PA0
OSC2
OSC1
OPEN
OSC2
R = 56 k
2%
OSC1
TEST
V2
OPEN
OPEN
V2
f = 445 kHz
VDD
TEST
KPS
KPS
RESET
VDD
*1
RESET
*1
VDD
VDD
(C0–C3)
CS
CP
CS
CP
(C0–C3)
C0/D0–C4/D4
C0/D0–C4/D4
(R0–R5)
(R0–R5)
R0/C0–R4/C4
R0/C0–R4/C4
DI/O PB0–PB2
DI/O PB0–PB2
OPEN
OPEN
*1: For ML9092-01, these are SEG1–56, PB0–PB2, KPS, C0/D0–C4/D4, and R0/C0–R4/C4.
For ML9092-02, these are SEG1–60, C0–C3, and R0–R5; PB0–PB2 and KPS are not provided.
24/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
Current Measuring Circuit 3
Current Measuring Circuit 4
External LCD voltage applied
(External clock)
External LCD voltage applied
(Internal oscillation)
IDD3
A
OPEN
OPEN
SEG1–SEG60
VDD
SEG1–SEG56(60) COM1–COM10
VDD
COM1–COM10
5.5 V
5.5 V
A
A
VIN
OPEN VC1
+
VHIN
B
B
VSS
VO
V1
V2
–
VSS
VS1
OPEN
IVHIN1
OPEN
KREQ
PA0
OPEN
OPEN
KREQ
PA0
OPEN
OPEN
VOUT
VO
A
OPEN
OPEN
OSC2 OPEN
OSC1
OSC2
V3
R = 56 k
2%
OSC1
TEST
V2
OPEN
f = 445 kHz
TEST
KPS
VDD
RESET
RESET
(R0–R4)
VDD
*2
*1
VDD
VDD
CS
CP
CS
(C0–C3)
C0/D0–C4/D4
(C0–C4)
C0–C3
CP
DI/O PB0–PB2
(R0–R5)
R0/C0–R4/C4
DI/O PB0–PB2
R0–R5
OPEN
OPEN
Current Measuring Circuit 5
External LCD voltage applied
(External clock)—2
IDD4
OPEN
A
SEG1–SEG60
COM1–COM10
5.5 V
VDD
IVHIN2
A
A
VHIN
VO
B
VSS
OPEN
V1
V2
KREQ
PA0
OPEN
OPEN
OPEN
OPEN
OPEN
OSC2
OSC1
V3
f = 445 kHz
VDD
TEST
RESET
*2
VDD
CS
(C0–C4)
(R0–R4)
R0–R5
CP
DI/O
PB0–PB2
C0–C3
OPEN
*1: For ML9092-01, these are SEG1–56, PB0–PB2, KPS, C0/D0–C4/D4, and R0/C0–R4/C4.
For ML9092-02, these are SEG1–60, C0–C3, and R0–R5; PB0–PB2 and KPS are not provided.
*2: For ML9092-03, these are C0–C3 and R0–R5; PB0–PB2 are not provided.
For ML9092-04, these are C0–C4 and R0–R4; PB0–PB2 are provided.
25/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
Current Measuring Circuit 6
External LCD voltage applied
(Internal oscillation)
IDD5
A
5.5 V
OPEN
SEG1–SEG60
COM1–COM10
VDD
A
B
VSS
VHIN
KREQ OPEN
OPEN
PA0
VO
V1
OPEN
OSC2
R = 56 k
2%
OSC1
TEST
V2
V3
OPEN
OPEN
VDD
RESET
*2
VDD
CS
CP
(R0–R4)
(C0–C4)
C0–C3 R0–R5
DI/O PB0–PB2
OPEN
*2: For ML9092-03, these are C0–C3 and R0–R5; PB0–PB2 are not provided.
For ML9092-04, these are C0–C4 and R0–R4; PB0–PB2 are provided.
26/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
Switching Characteristics
(VDD = 4.5 to 5.5 V, VOUT (VHIN) = 4.5 to 16.5 V, Ta = –40 to +85C)
Parameter
CP Clock Cycle Time
CP “H” Pulse Width
Symbol
tSYS
Condition
Min.
500
200
200
100
—
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
ns
ns
ns
ns
—
tWH
—
—
CP “L” Pulse Width
tWL
—
—
CS “H” Pulse Width
tWCH
tr, tf
—
—
CP Clock Rise/fall Time
CS Setup Time
—
50
tCSU
tCHD
tDSU
tDHD
tDOD
tDOFF
tWRE
tSES
—
30
—
CS Hold Time
—
150
50
—
DI/O Setup Time
—
—
DI/O Hold Time
—
50
—
DI/O Output Delay Time
DI/O Output OFF Delay Time
RESET Pulse Width
CL = 50 pF
—
100
100
—
CL = 50 pF
—
—
—
—
—
—
2
External Clock Cycle Time
External Clock “H” Pulse Width
External Clock “L” Pulse Width
External Clock Rise/fall Time
1612
645
645
—
3389
—
tWEH
tWEL
trE, tfE
—
50
Key Scan Characteristics
(VDD = 4.5 to 5.5 V, VOUT (VHIN) = 4.5 to 16.5 V, Ta = –40 to +85C)
Register
Oscillation frequency
setting
Parameter
Symbol
Dividing ratio
Unit
KT
0
210 kHz
306kHz
5.0
445 kHz
1/1536
1/3072
7.3
3.5
6.9
Key Scan Period
Tscn
ms
1
14.6
10.0
Frame Frequency, PWM Frequency, and Voltage Doubler Frequency Characteristics
(VDD = 4.5 to 5.5 V, VOUT (VHIN) = 4.5 to 16.5 V, Ta = –40 to +85C)
Oscillation frequency
Model
Parameter Symbol Display duty Dividing ratio
Unit
210 kHz 306 kHz
445 kHz
174
1/8
1/9
1/2560
1/2520
1/2560
82
83
82
120
121
120
ML9092-
Frame
Frequency
FRM
177
01/02/03/04
1/10
174
ML9092-
01/04
PWM
Frequency
Hz
PWM
—
—
1/1020
205
300
436
Voltage
Doubler
Frequency
ML9092-
01/02
—
1/64
3281
4781
6953
27/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
Switching Characteristics of Rotary Switch
(VDD = 4.5 to 5.5 V, VOUT (VHIN) = 4.5 to 16.5 V, Ta = –40 to +85C)
Parameter
Symbol
tSAW
Condition
Min.
950
950
950
Typ.
—
Max. Unit
Phase Recognition Time (A to B)
Phase Recognition Time (B to A)
Phase Input Fixed Time
—
—
—
s
s
s
tSBW
R = 56 k 2%,
—
tAB
—
28/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
Clock synchronous serial interface timing diagrams
Clock synchronous serial interface input timing
tWCH
– VIH3
– VIL3
CS
tCSU
tSYS
tCHD
tWH
tWL
tr
tf
– VIH3
– VIL3
CP
tDHD
tDSU
– VIH3
– VIL3
DI/O
Clock synchronous serial interface inputoutput timing
tWCH
– VIH3
– VIL3
CS
tCSU
tCHD
tSYS
tr tWH tf tWL
9th Clock
8th Clock
1st Clock
– VIH3
– VIL3
CP
tDOFF
tDOD
tDHD
tDSU
VOH1
VOL1
VIH3 VIH3
VIL3 VIL3
VOH1
VOL1
DI/O
Hiz
Reset timing
tWRE
RESET
– VIL2
External clock
trE
tWEH
tWEL
tfE
– VIH1
– VIL1
OSC1
tSES
29/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
Key scan timing
Tscn
–VDD
–VSS
Rn
Frame frequency
– V0
– V1
COM1
– V3
– VSS
1/FRM
1/FRM
PWM output frequency for port B (applies to ML9092-01/04)
1/PWM
PB0
PB1
PB2
Rotary switch input timing
A
B
tSAW
tAB
tSBW
tAB
tSBW
tAB
tSAW
tAB
30/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
Instruction Code List (ML9092-01)
Instruction Code
Data
D4
Description
No.
Instruction
Fixed bit R/W
Register No.
D7 D6 D5 D4 D3 D2 D1 D0 D7
D6
D5
D3
S3
D2
S2
D1
S1
D0
Reads scan read timing bits (ST0 to ST2) and key scan
S0 data (S0 to S4) of the key scan register.
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
ST2 ST1 ST0
S4
D4
Key scan register read
Display data RAM write
Writes display data (D0 to D7) in the display data RAM
after setting the X address of Y address.
D7
D6
D5
D3
D2
D1
D0
Reads display data (D0 to D7) from the display data RAM
after setting the X address of Y address.
1
2
Display data RAM read
X address register set
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
D7
–
D6
–
D5
–
D4
–
D3
X3
D2
X2
D1
X1
D0
X0 Sets the X address (X0 to X3) of the display data RAM.
Y0 Sets the Y address (Y0 to Y3) of the display data RAM.
3
4
5
6
7
Y address register set
Port register A set
Port register B set
Port register C set
Port register D set
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Y3
–
Y2
–
Y1
–
PTA0 Controls the output of the general-purpose port A (PTA0).
Controls the output of the general-purpose port B (PTB0
–
PTB2 PTB1 PTB0
to PTB2).
Controls the output of the general-purpose port C (PTC0
PTC4 PTC3 PTC2 PTC1 PTC0
PTD4 PTD3 PTD2 PTD1 PTD0
to PTC4).
Controls the output of the general-purpose port D (PTD0
to PTD4).
Sets the address increment X or Y direction (INC), display
data word length (WLS), key scan time (KT), common
driver shift direction (SHL), voltage doubler control (BE),
port control (PE), and display duty (DTY0, DTY1).
8
Control register 1 set
1
1
0
0
1
0
0
0
INC WLS KT
SHL
BE
PE DTY1 DTY0
9
A
B
C
Control register 2 set
Rotary encoder read
Contrast ADJ set
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
0
Q4
–
0
Q4
–
0
Q4
–
0
Q4
–
0
0
0
DISP Sets display ON/OFF (DISP).
Reads the counter bits (Q1 to Q4) of the rotary encoder.
Q1
Q4
Q3
Q2
Sets contrast adjustment values with the contrast
adjustment bits (CT0 to CT3).
CT3 CT2 CT1 CT0
Sets the pulse width to be output from general-purpose
port B (PTB0) with the bits (PW00 to PW07) of PWM0.
PWM0 register set
PW07 PW06 PW05 PW04 PW03 PW02 PW01 PW00
PW17 PW16 PW15 PW14 PW13 PW12 PW11 PW10
Sets the pulse width to be output from general-purpose
port B (PTB1) with the bits (PW10 to PW17) of PWM1.
D
E
F
PWM1 register set
PWM2 register set
Test register set
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
0
1
Sets the pulse width to be output from general-purpose
port B (PTB2) with the bits (PW20 to PW27) of PWM2.
PW27 PW26 PW25 PW24 PW23 PW22 PW21 PW20
Test instruction exclusively used by manufacturer (T1 to
T5). Customers must not use this instruction.
–
–
–
T5
T4
T3
T2
T1
Notes:
R/W
: Read/write select bit
1:Read, 0: Write
ST0 to ST2
S0 to S4
D0 to D7
X0 to X3
Y0 to Y3
PTA0
PTB0 to PTB2 : Port B output control
PTC0 to PTC4 : Port C data
PTD0 to PTD4 : Port D data
INC
WLS
KT
: Key scan read count display bits
: Key scan data
: Write or read data of the display data RAM
: X addresses of the display data RAM
: Y addresses of the display data RAM
: Port A data
PE
: Port enable/disable select bit 1: All ports enable
0: All ports go into high impedance for output
: Display duty select bits (1/8, 1/9, 1/10)
DTY0, DTY1
DISP
Q1 to Q4
CT0 to CT3
PW00 to PW07 : PWM0 setting bits
PW10 to PW17 : PWM1 setting bits
PW20 to PW2
T1 to T5
: Display ON/OFF select bit
1: Display ON, 0: Display OFF
: Rotary encoder switch count bits (2’s complement)
: Contrast adjustment bit
1: Output enable, 0: Fixed at “L”
: PWM2 setting bits
: Bits for test instruction. Customers should not access these bits.
: Display data RAM address increment. 1: X direction, 0: Y direction
: Word length select bit
1: 6 bits, 0: 8 bits
: Key scan period select bit
1: 10 ms, 0: 0.5 ms
–
: Don’t Care
SHL
: Common driver shift direction select bit
1: COM10COM1, 0: COM1COM10
1: Voltage doubler enable
BE
: Voltage doubler control bit
0: Voltage doubler disable
31/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
Instruction Code List (ML9092-02/03)
Instruction Code
Data
D4
Description
No.
0
Instruction
Fixed bit R/W
Register No.
D7 D6 D5 D4 D3 D2 D1 D0 D7
D6
D5
D3
S3
D2
S2
D1
S1
D0
Reads scan read timing bits (ST0 to ST2) and key scan
S0 data (S0 to S4) of the key scan register.
1
1
1
0
0
0
0
0
ST2 ST1 ST0
0
Key scan register read
Writes display data (D0 to D7) in the display data RAM
after setting the X address of Y address.
1
1
2
Display data RAM write
Display data RAM read
X address register set
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
D7
D7
–
D6
D6
–
D5
D5
–
D4
D4
–
D3
D3
X3
D2
D2
X2
D1
D1
X1
D0
Reads display data (D0 to D7) from the display data RAM
after setting the X address of Y address.
D0
X0 Sets the X address (X0 to X3) of the display data RAM.
3
4
Y address register set
Port register A set
1
1
1
1
0
0
0
0
0
0
0
1
1
0
1
0
–
–
–
–
–
–
–
–
Y3
–
Y2
–
Y1
–
Y0 Sets the Y address (Y0 to Y3) of the display data RAM.
PTA0 Controls the output of the general-purpose port A (PTA0).
Sets the address increment X or Y direction (INC), display
data word length (WLS), key scan time (KT), common
SHL (BE) PE DTY1 DTY0
8
Control register 1 set
1
1
0
0
1
0
0
0
INC WLS KT
driver shift direction (SHL), voltage doubler control (BE)
(only applies to ML9092-02), port control (PE), and display
duty (DTY0, DTY1).
Sets or releases standby mode (only applies to ML9092-
(STB) DISP
03) and also sets display ON/OFF (DISP).
9
Control register 2 set
Rotary encoder read
1
1
1
1
0
1
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
Reads the counter bits (Q1 to Q4) of the rotary encoder.
A
Q4
Q4
Q4
Q4
Q4
Q3
Q2
Q1
Sets contrast adjustment values with the contrast
CT3 CT2 CT1 CT0
adjustment bits (CT0 to CT3).
B
F
Contrast ADJ set
Test register set
1
1
1
1
0
0
0
0
1
1
0
1
1
1
1
1
–
–
–
–
–
–
–
Test instruction exclusively used by manufacturer (T1 to
T5). Customers should not use this instruction.
T5
T4
T3
T2
T1
Notes:
R/W
: Read/write select bit
1:Read, 0: Write
ST0 to ST2
S0 to S3
D0 to D7
X0 to X3
Y0 to Y3
PTA0
INC
WLS
KT
: Key scan read count display bits
: Key scan data
: Write or read data of the display data RAM
: X addresses of the display data RAM
: Y addresses of the display data RAM
: Port A data
PE
: Port enable/disable select bit 1: All ports enable
0: All ports go into high impedance for output
: Display duty select bits (1/8, 1/9, 1/10)
DTY0, DTY1
STB (only applies to ML9092-03)
: Standby mode/normal mode select bit
1: Standby mode, 0: Normal mode
DISP
Q1 to Q4
CT0 to CT3
: Display ON/OFF select bit
1: Display ON, 0: Display OFF
: Display data RAM address increment. 1: X direction, 0: Y direction
: Rotary encoder switch count bits (2’s complement)
: Contrast adjustment bit
: Word length select bit
1: 6 bits, 0: 8 bits
: Key scan period select bit
1: 10 ms, 0: 0.5 ms
SHL
: Common driver shift direction select bit
T1 to T5
: Bits for test instruction. Customers should not access these bits.
1: COM10COM1, 0: COM1COM10
BE (only applies to ML9092-02)
–
: Don’t Care
: Voltage doubler control bit
1: Voltage doubler enable
0: Voltage doubler disable
32/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
Instruction Code List (ML9092-04)
Instruction Code
Data
D4
Description
No.
Instruction
Fixed bit R/W
Register No.
D7 D6 D5 D4 D3 D2 D1 D0 D7
D6
D5
D3
S3
D2
S2
D1
S1
D0
Reads scan read timing bits (ST0 to ST2) and key scan
S0 data (S0 to S4) of the key scan register.
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
ST2 ST1 ST0
S4
D4
Key scan register read
Display data RAM write
Writes display data (D0 to D7) in the display data RAM
after setting the X address of Y address.
D7
D6
D5
D3
D2
D1
D0
Reads display data (D0 to D7) from the display data RAM
after setting the X address of Y address.
1
2
Display data RAM read
X address register set
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
D7
–
D6
–
D5
–
D4
–
D3
X3
D2
X2
D1
X1
D0
X0 Sets the X address (X0 to X3) of the display data RAM.
Y0 Sets the Y address (Y0 to Y3) of the display data RAM.
3
4
5
Y address register set
Port register A set
Port register B set
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
1
–
–
–
–
–
–
–
–
–
–
–
–
Y3
–
Y2
–
Y1
–
PTA0 Controls the output of the general-purpose port A (PTA0).
Controls the output of the general-purpose port B (PTB0
–
PTB2 PTB1 PTB0
to PTB2).
Sets the address increment X or Y direction (INC), display
data word length (WLS), key scan time (KT), common
driver shift direction (SHL), port control (PE), and display
duty (DTY0, DTY1).
8
Control register 1 set
1
1
0
0
1
0
0
0
INC WLS KT
SHL
–
PE DTY1 DTY0
Sets or releases standby mode and also sets display
STB DISP
ON/OFF (DISP).
9
A
B
C
Control register 2 set
Rotary encoder read
Contrast ADJ set
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
0
Q4
–
0
Q4
–
0
Q4
–
0
Q4
–
0
0
Reads the counter bits (Q1 to Q4) of the rotary encoder.
Q4
Q3
Q2
Q1
Sets contrast adjustment values with the contrast
adjustment bits (CT0 to CT3).
CT3 CT2 CT1 CT0
Sets the pulse width to be output from general-purpose
port B (PTB0) with the bits (PW00 to PW07) of PWM0.
PWM0 register set
PW07 PW06 PW05 PW04 PW03 PW02 PW01 PW00
PW17 PW16 PW15 PW14 PW13 PW12 PW11 PW10
Sets the pulse width to be output from general-purpose
port B (PTB1) with the bits (PW10 to PW17) of PWM1.
D
E
F
PWM1 register set
PWM2 register set
Test register set
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
0
1
Sets the pulse width to be output from general-purpose
port B (PTB2) with the bits (PW20 to PW27) of PWM2.
PW27 PW26 PW25 PW24 PW23 PW22 PW21 PW20
Test instruction exclusively used by manufacturer (T1 to
T5). Customers must not use this instruction.
–
–
–
T5
T4
T3
T2
T1
Notes:
R/W
: Read/write select bit
1:Read, 0: Write
ST0 to ST2
S0 to S4
D0 to D7
X0 to X3
Y0 to Y3
PTA0
: Key scan read count display bits
: Key scan data
: Write or read data of the display data RAM
: X addresses of the display data RAM
: Y addresses of the display data RAM
: Port A data
PE
: Port enable/disable select bit 1: All ports enable
0: All ports go into high impedance for output
: Display duty select bits (1/8, 1/9, 1/10)
DTY0, DTY1
STB
: Standby mode/normal mode select bit
1: Standby mode, 0: Normal mode
1: Display ON, 0: Display OFF
DISP
Q1 to Q4
CT0 to CT3
PW00 to PW07 : PWM0 setting bits
PW10 to PW17 : PWM1 setting bits
PW20 to PW2
T1 to T5
: Display ON/OFF select bit
PTB0 to PTB2 : Port B output control
1: Output enable, 0: Fixed at “L”
: Display data RAM address increment. 1: X direction, 0: Y direction
: Rotary encoder switch count bits (2’s complement)
: Contrast adjustment bit
INC
WLS
KT
: Word length select bit
1: 6 bits, 0: 8 bits
: Key scan period select bit
1: 10 ms, 0: 0.5 ms
SHL
: Common driver shift direction select bit
: PWM2 setting bits
: Bits for test instruction. Customers should not access these bits.
1: COM10COM1, 0: COM1COM10
–
: Don’t Care
33/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
Clock Synchronous Serial Transfer Example (WRITE)
Transfer start
Transfer complete
CS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CP
D5 D4 D3
D1 D0
D2
D3
D7 D6
R/W
D2
D0
D4
D1
DI/O
“1” “1”
Register bits
Instruction code
Data
Clock Synchronous Serial Continuous Data Transfer Example (WRITE: Example of display data RAM
write)
Transfer start
Transfer complete
CS
*1
9 10 15 16 17 18 23 24 41 42 47 48
1
2
7
8
CP
DI/O
Instruction code
Data 1
Data 2
Data 5
*1:
Be sure to write data in 8 bits. If the CS signal falls when data input operation in 8 bits is not
complete, the last 8-bit data write is invalid. (The previously written data is valid.)
34/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
Clock Synchronous Serial Continuous Data Transfer Example (READ)
Transfer start
Transfer complete
CS
*2
1
2
8
9 10 11 15 16 17 18 23 24 41 42 47 48
CP
DI/O
READ DATA1
Instruction code
Input state
READ DATA2
READ DATA5
Output state
*2:
A reading state appears only when the R/W bit is “1”. The read data is valid only when the register
is set to key scan read mode, rotary encoder read mode or display data read mode. Otherwise,
the read data is invalid (undefined data will be read out).
35/66
FEDL9092-01
LAPIS Semiconductor
ML9092-01/02/03/04
Output Pin, I/O Pin and Register States When Reset Is Input
Pin and register states while the RESET input is pulled to a “L” level are listed below.
Output pin, I/O pin
State
DI/O
Input state
“L” (VSS
Oscillating state
KREQ
OSC2
)
R0/C0 to R4/C4 (when these pins are used for key
scanning in ML9092-01);
“L” (VSS
)
R0 to R5 (ML9092-02/03);
R0 toR4 (ML9092-04)
R0/C0 to R4/C4 (when these pins are used as port C
outputs in ML9092-01)
High impedance
C0/D0 to C4/D4 (when these pins are used as port D
outputs in ML9092-01)
High impedance (any pull-up resistors are turned off)
PA0
High impedance
High impedance
PB0 to PB2 (ML9092-01/04)
SEG1 to SEG56 (ML9092-01);
SEG1 to SEG60 (ML9092-02/03/04)
COM1 to COM10
VSS
VSS
Register
Key scan register
State
Reset to “0”
Display data register
X address register
Display data is retained
Reset to “0”
Y address register
Reset to “0”
Port A register
Reset to “0”
Port B register (ML9092-01/04)
Port C register
Reset to “0”
Reset to “0”
Reset to “0”
(When KPS = “0” in ML9092-01)
Port D register
(When KPS = “0” in ML9092-01)
Bits INC and KT are set to “1”.
Bits WLS, SHL, PE, DTY1 and DTY0 are reset to “0”.
Display OFF, normal mode
(Standby mode is released)
Reset to “0”
Control register 1
Control register 2
Rotary encoder read register
Contrast ADJ register
Set to “F”
PWM0 register (for ML9092-01/04)
PWM1 register (for ML9092-01/04)
PWM2 register (for ML9092-01/04)
Reset to “0”
Reset to “0”
Reset to “0”
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Power-On Reset
The capacitance of an external capacitor that is connected to the RESET pin must be CRST [F] 12.5 TR [s],
where TR is the rise time taken until the power supply voltage to be supplied to the ML9092-01/02/03/04 reaches
0.9VDD (4.5 V) from 0.1VDD, and CRST is the capacitance of an external capacitor connected to the RESET pin.
(For example, if TR = 10 [ms], then CRST 125 [F])
The pulse width when an external reset signal is input should be TR or more.
Set an instruction at least 10 s after the reset signal reaches 0.85VDD or more.
Thereafter, this IC is accessible.
TR
0.9VDD
(4.5 V)
Recommended power supply
VDD
0.1VDD
voltage (5 V)
0.85VDD
Accessible time
10 s or more
RESET
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Serial Interface Operation
Instruction code
A register that transfers display data, key scan data, etc. according to the content of the instruction code is selected
(see below).
D7
“1”
D6
“1”
D5
D4
D3
D2
D1
D0
R/W
Register number
(1) D7, D6 (fixed at “1”)
When selecting the start byte register, always write a “1” to bits D7 and D6.
(2) D5 (R/W) (Read mode/write mode select bit)
1: Read mode is selected
0: Write mode is selected
(3) D4 to D0 (Register number)
The correspondence between the start byte contents and the registers and display data RAM is shown in the table
below.
D7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D5
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
D4
1
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Register name
Key scan register
1/0
0
Display data RAM
X address register
Y address register
Port A register
0
0
0
Port B register
0
Port C register
0
Port D register
0
Control register1
Control register 2
Rotary encoder register
Contrast ADJ register
PWM0 register
0
0
0
0
0
PWM1 register
0
PWM2 register
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Description of the Data Section in Instructions
Key scan register (KR)—Read (for ML9092-01/04)
D7
D6
D5
D4
S4
D3
S3
D2
S2
D1
S1
D0
S0
ST2
ST1
ST0
(1) D7 to D5 (ST2 to ST0) (Key scan read count display bits)
25-bit key scan data is divided into 5 groups and read. The read count is indicated by bits ST2 to ST0.
Every time key scan data is read, these bits are automatically incremented over the range of “000” to “100”. After
counting to “100”, this counter is reset to “000” and then again incremented from “000”, thereafter repeating this
cycle. If the CS signal is risen up during the cycle of counting, the scan read counter bits are returned to “000”.
If the RESET pin is pulled to a “L” level, these bits are reset to “0”.
(2) D4 to D0 (S4 to S0) (Key scan read data bits)
These bits are read as 25-bit serial data that expresses the key switch status (1 = ON, 0 = OFF). Data is divided into
5 groups and read. (For the read order, refer to the description below.) The read count is indicated by bits ST2 to
ST0.
The correspondence between the scan read count data, key scan data and key matrix switches is shown below.
If the RESET pin is pulled to a “L” level, these bits are reset to “0”.
ST2
0
ST1
0
ST0
0
S4
S3
S2
S1
S0
SW04
SW14
SW24
SW34
SW44
SW03
SW13
SW23
SW33
SW43
SW02
SW12
SW22
SW32
SW42
SW01
SW11
SW21
SW31
SW41
SW00
SW10
SW20
SW30
SW40
R0
R1
R2
R3
R4
0
0
1
0
1
0
0
1
1
1
0
0
Note: SW00 to SW44 indicate the corresponding switches in Figure 1.
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ML9092-01, -04
C3/D3
C3
C0/D0
C0
C2/D2
C2
C4/D4
C4
C1/D1
C1
R0/C0
R0
SW00
SW10
SW20
SW30
SW40
SW01
SW11
SW21
SW31
SW41
SW02
SW03
SW13
SW23
SW33
SW43
SW04
SW14
SW24
SW34
SW44
R1/C1
R1
SW12
R2/C2
R2
SW22
SW32
SW42
R3/C3
R3
R4/C4
R4
Figure 1
(Note) To recognize simultaneous depression of three or more key switches, add a diode in series to
each key.
Cm/Dm
Cm
Rn/Cn
Rn
Rn+ 1/C n+1
Rn+1
Connection with diodes
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Key scan register (KR)—Read (for ML9092-02/03)
D7
D6
D5
D4
0
D3
S3
D2
S2
D1
S1
D0
S0
ST2
ST1
ST0
(1) D7 to D5 (ST2 to ST0) (Key scan read count display bits)
24-bit key scan data is divided into 6 groups and read. The read count is indicated by bits ST2 to ST0.
Every time key scan data is read, these bits are automatically incremented over the range of “000” to “101”. After
counting to “101”, this counter is reset to “000” and then again incremented from “000”, thereafter repeating this
cycle. If the CS signal is risen up during the cycle of counting, the scan read counter bits are returned to “000”.
If the RESET pin is pulled to a “L” level, these bits are reset to “0”.
(2) D3 to D0 (S3 to S0) (Key scan read data bits)
These bits are read as 24-bit serial data that expresses the key switch status (1 = ON, 0 = OFF). Data is divided into
6 groups and read. (For the read order, refer to the description below.) The read count is indicated by bits ST2 to
ST0.
The correspondence between the scan read count data, key scan data and key matrix switches is shown below.
If the RESET pin is pulled to a “L” level, these bits are reset to “0”.
ST2
0
ST1
0
ST0
0
S4
0
S3
S2
S1
S0
SW03
SW13
SW23
SW33
SW43
SW53
SW02
SW12
SW22
SW32
SW42
SW52
SW01
SW11
SW21
SW31
SW41
SW51
SW00
SW10
SW20
SW30
SW40
SW50
R0
R1
R2
R3
R4
R5
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
Note: SW00 to SW53 indicate the corresponding switches in Figure 2.
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ML9092-02/03
C3
C0
C1
C2
R0
R1
SW00
SW10
SW20
SW30
SW40
SW50
SW01
SW11
SW21
SW31
SW41
SW51
SW02
SW03
SW13
SW23
SW33
SW43
SW53
SW12
SW22
SW32
SW42
SW52
R2
R3
R4
R5
Figure 2
(Note) To recognize simultaneous depression of three or more key switches, add a diode in series to
each key.
Cm
Rn
Rn+1
Connection with diodes
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Key Scan
The key scanning starts when a key switch is pressed on and ends after all key switches are detected to be off.
After the key switch is turned on, when the same key is pressed for two cycles or more, the level of the KREQ
signal changes from a “L” to “H” level. In the same manner, the level of the KREQ signal changes from “H” to
“L” two cycles after all key switches are turned off.
This signal can be used as a flag. To use it as a flag, start key-scan reading when the KREQ signal has changed
from “L” to “H.”
While the KREQ signal is at a “H” level, carry out key-scan reading periodically. Carry out key scan reading also
when the KREQ signal has changed from “H” to “L”.
The KREQ signal (the KREQ signal that is sent when the key switch is turned on) is reset when all key switches are
detected to be off or when a “L” level is applied to the RESET pin.
Key switch
R0/C0
R1/C1
R2/C2
R3/C3
R4/C4
Key switch ON.
Scanning starts.
Scanning stops
Key data reading
starts
Key switch OFF
KREQ
Notes:
1. Even when the KREQ signal changes from “L” to “H”, chattering for more than one key scan cycle is
not absorbed. This should be handled by multiple data reads by software.
2. How simultaneous depression of two keys is processed should be handled by software.
3. When three or more key switches are pressed at the same time, the device may recognize that
key(s) that has not been actually pressed has been pressed. Therefore, to recognize simultaneous
depression of three or more key switches, add a diode in series to each key (see Figures 1 and 2).
To ignore simultaneous depression of three or more key switches, a program may be required to
ignore all key data which contains three or more consecutive “1” values.
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Display data RAM (DRAM) read/write
D7
0
D6
0
D5
D4
8-bit DATA
D3
D2
D1
D0
6-bit DATA
The display data RAM read/write instruction writes and reads display data to and from the liquid crystal display
RAM. Data that is input to the address set by the X and Y address registers is written to or read from this register.
The bit length of display data can be selected by the WLS bit of control register 1. If 6-bit data has been selected,
writing to D7 and D6 is invalid, and if read, their values will always be “0”. D7 is the MSB (D5 in the case of 6-bit
data) and D0 is the LSB.
The X address and Y address should be set immediately before writing or reading display data (either X address or
Y address may be set first). However, in the case of successive writings or readings, only one-time settings of X
address and Y address are required immediately before the writing or reading, in which case X address and Y
address are automatically incremented every time data is written or read (see the description under the heading
“X•Y address Counter Auto Increment.”
The contents of this register will not change even if the RESET pin is pulled to a “L” level.
X address register (XAD) set
D7
D6
D5
D4
D3
D2
D1
D0
—
XAD
—: don’t care
The X address register set instructions sets the X address for the liquid crystal display RAM.
The address setting range is 0 to 7 (00H to 07H) when 8-bit data is selected with the WLS bit (bit D6) of the control
register 1 (WLS = “0”). In this case, this register starts incrementing the X address from the set value each time
RAM is read or written. When the count value of this register returns to 0 from the maximum value 7, the Y
address is automatically incremented as well. Thereafter, the Y address is counted in a loop fashion from 0 to 7.
The address setting range is 0 to 9 (00H to 09H) when 6-bit data is selected (WLS = “1”). In this case this register
starts incrementing the X address from the set value. When the count value of this register returns to 0 from the
maximum value 9, the Y address is automatically incremented as well. Thereafter, the Y address loops from 0 to 9.
Proper operation is not guaranteed if values outside this range are set.
Writing to bits D7 through D4 is invalid. If the RESET pin is pulled to a “L” level, these bits are reset to “0”.
Y address register (YAD) set
D7
D6
D5
D4
D3
D2
D1
D0
—
YAD
—: don’t care
The Y address register set instruction sets a Y address of RAM for the liquid crystal display.
The Y address setting range varies according to the setting of the DTY bits (bits D1 and D0) of the control register
1 (described later).
The relation between the internal RAM areas and the display RAM areas is shown in the Table below. RAM areas
that are not displayed can be used as data RAM areas.
This register starts incrementing the Y address from the set value each time RAM is read or written. When the
register count returns to 0 from the maximum value (09H), the X address is also incremented automatically.
Thereafter, the Y address is counted in a loop fashion as shown in the Table below. However, if RAM areas that
are not displayed are used, the X address is not incremented automatically.
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Y register setting range
and loop range
Duty
Invalid address setting range
1/8
1/9
0 to 7 (00H to 07H)
0 to 8 (00H to 08H)
0 to 9 (00H to 09H)
0 to 7 (00H to 07H)
0 to 8 (00H to 08H)
0 to 9 (00H to 09H)
1/10
This register is reset to “0” when the RESET pin is made low.
Port register A (PTA) set
D7
D6
D5
D4
—
D3
D2
D1
D0
PTA
—: don’t care
The port register A set instruction sets the output of port A.
When the PTA bit is set to “1”, a “H” level is output from the PA0 pin of general purpose port A. In the same way,
when the PTA bit is set to “0”, a “L” level is output from the PA0 pin. If the RESET pin is pulled to a “L” level, the
PE bit (bit D2) of the control register is reset to “0”, this register is reset to “0”, and the PA0 pin goes to high
impedance.
After the reset state is released, if the PTA bit of this register is set to “1” or “0” and then the PE bit is set to “1”, the
PA0 pin is released from its high impedance state and a “H” or “L” level that corresponds to the set status of the
PTA bit, is output from the PA0 pin.
Port register B (PTB) set
D7
D6
D5
—
D4
D3
D2
D1
D0
PTB2
PTB1
PTB0
—: don’t care
The port register B set instruction sets the output of port B. (Applies to the ML9092-01/04.)
When each bit of PTB0 to PTB2 is set to “1”, the PWM signal set in the PWM0 to PWM2 registers is output from
each of the PB0 to PB2 pins of the general purpose port B. In the same way, when each bit of PTB0 to PTB2 is set
to “0”, each of the PB0 to PB2 pins are pulled to a “L” level. If the RESET pin is pulled to a “L” level, the PE bit
(bit D2) of the control register is reset to “0”, this register is reset to “0”, and the PB0 to PB2 pins go to high
impedance.
After the reset state is released, if the a PWM value is set in the PWM0 to PWM2 registers and then the PE bit is set
to “1”, the PB0 to PB2 registers are released from their high impedance state and a PWM waveform is output.
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Port register C (PTC) set
D7
D6
—
D5
—
D4
D3
D2
D1
D0
—
PTC4
PTC3
PTC2
PTC1
PTC0
—: don’t care
The port register C set instruction sets the output of port C. (Applies to the ML9092-01 only.)
This register is enabled when a “L” level is applied to the KPS pin of ML9092-01 and the R0/C0 to R4/C4 pins are
set as port C.
When each bit of PTC4 to PTC0 is set to “1”, a “H” level is output from each of the R4/C4 to R0/C0 pins of the
general purpose port C. In the same way, when each bit of PTC4 to PTC0 is set to “0”, a “H” level is output from
each of the R4/C4 to R0/C0 pins. If the RESET pin is pulled to a “L” level, the PE bit (bit D2) of the control
register is reset to “0”, this register is reset to “0”, and the R4/C4 to R0/C0 pins go to high impedance.
After the reset state is released, if the PTC4 to PTC0 bits of this register are set to “1” or “0” and then the PE bit is
set to “1”, the R4/C4 to R0/C0 pins are released from its high impedance state and a “H” or “L” level that
corresponds to the set status of each bit of PTC4 to PTC0, is output from the R4/C4 to R0/C0 pins.
Port register D (PTD) set
D7
D6
—
D5
—
D4
D3
D2
D1
D0
—
PTD4
PTD3
PTD2
PTD1
PTD0
—: don’t care
The port register D set instruction sets the output of port D. (Applies to the ML9092-01 only.)
This register is enabled when a “L” level is applied to the KPS pin of ML9092-01 and the C0/D0 to C4/D4 pins are
set as port C.
When each bit of PTD4 to PTD0 is set to “1”, a “H” level is output from each of the C4/D4 to C0/D0 pins of the
general purpose port D. In the same way, when each bit of PTD4 to PTD0 is set to “0”, a “H” level is output from
each of the C4/D4 to C0/D0 pins. If the RESET pin is pulled to a “L” level, the PE bit (bit D2) of the control
register is reset to “0”, this register is reset to “0”, and the C4/D4 to C0/D0 pins go to high impedance.
After the reset state is released, if the PTD4 to PTD0 bits of this register are set to “1” or “0” and then the PE bit is
set to “1”, the C4/D4 to C0/D0 pins are released from its high impedance state and a “H” or “L” level that
corresponds to the set status of each bit of PTD4 to PTD0, is output from the C4/D4 to C0/D0 pins.
Control register 1 (FCR1)
D7
D6
D5
KT
D4
D3
BE
D2
PE
D1
D0
INC
WLS
SHL
DTY1
DTY0
(1) D7 (INC) Address increment direction
1: X direction address increment
0: Y direction address increment
This bit sets the address increment direction of the display RAM. The display RAM address is automatically
incremented by 1 every time data is written to the display data register. Writing a “1” to this bit sets “X address
increment,” and writing a “0” sets “Y address increment.” For further details regarding address incrementing,
refer to the page entitled “X, Y Address Counter Auto Increment.” This bit is set to “1” if the RESET pin is pulled
to a “L” level.
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(2) D6 (WLS) (Word Length Select)
1: 6-bit word length select
0: 8-bit word length select
This bit selects the word length of data to be written to and read from the display RAM. If “1” is written to this bit,
data will be read from and written to the display RAM in 6-bit units. If “0” is written to this bit, data will be read
from and written to the display RAM in 8-bit units. This bit is reset to “0” if the RESET pin is pulled to a “L” level.
(3) D5 (KT) (Key scan time) Key scan time select bit
1: 10 ms
0: 5 ms
This bit selects the key scan cycle time. In the case of a 306 kHz oscillating frequency, writing a “1” to this bit sets
the key scan cycle time at 10 ms (1/3072 divided frequency of the oscillating frequency), writing a “0” sets the key
scan cycle time at 5 ms (1/1536 divided frequency of the oscillating frequency). This bit is set to “1” if the RESET
pin is pulled to a “L” level.
(4) D4 (SHL) (Common driver shift direction select bit)
This bit selects the shift direction of common drivers.
The relationship between this bit and shift directions are shown below.
This bit is reset to “0” if the RESET pin is pulled to a “L” level.
SHL
1
Duty
1/8
Shift direction
COM8
COM9
COM10
COM1
COM1
COM1
COM1
COM1
COM1
COM8
COM9
COM10
1/9
1/10
1/8
0
1/9
1/10
(5) D3 (BE) (Voltage doubler operation control bit )
This bit controls the operation of the voltage doubler. (Applies to ML9092-01/02.)
1: Voltage doubler enable
0: Voltage doubler disable
This bit is reset to “0” if the RESET pin is pulled to a “L” level.
(6) D2 (PE) (General-purpose port output enable/disable select bit)
This bit selects high impedance output or output enable for the general-purpose port outputs A, B, C and D (C and
D apply to ML9092-01 only; B applies to ML9092-01/04).
1: Output enable
0: High-impedance output (output disable)
This bit is reset to “0” if the RESET pin is pulled to a “L” level.
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(7) D1, D0 (DTY1, DTY0) (Display duty select bits)
These bits select the display duty. The correspondence between each bit and display duty is shown in the chart
below. These bits are reset to “0” if the RESET pin is pulled to a “L” level.
DTY1
DTY0
Display duty
1/8
0
0
1
1
0
1
0
1
1/9
1/10
1/10
Control register 2 (FCR2)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
D1
D0
0
STB
DISP
(1) D1 (STB) (Standby mode select bit)
This bit is used to control the standby and normal modes. (Applies to ML9092-03/04.)
1: Standby mode
0: Normal mode
This bit is reset to “0” if the RESET pin is pulled to a “L” level.
The LSI internal status and pin status during standby mode are as follows:
- RAM data is retained.
- Common output and segment output are VSS level.
- Electronic volume values are retained.
- Port output A is at a “L” level (applies to ML9092-03/04). The status before standby is maintained for port
output B (applies to ML9092-04).
- RC oscillation is stopped. (Oscillation is started with key input, maintained while the KREQ output is at a “H”
level, and stopped when all key switches are turned off and the KREQ output is at a “L” level.)
- Rotary encoder input signals (A and B) are ignored.
- Key input allowed.
- The microcontroller interface (CS, CP, DI/O, KREQ) is operable. (However, only with a KREQ signal from the
key scan, will the KREQ pin output a “H” level.)
- VHIN and VO should be set to VSS or the floating status.
Note: When there is a key input in a standby state, this IC will start oscillating and KREQ output will go to a “H”
level. Execute key scan reading periodically during this “H” level period. Also, execute key scan reading when
the KREQ signal changes from a “H” to “L” level.
(2) D0 (DISP) (Display ON/OFF mode bit)
1: Display ON mode
0: Display OFF mode
This bit selects whether the display is ON or OFF. Writing a “1” to this bit selects the display ON mode. Writing
a “0” to this bit selects the display OFF mode. At this time, the COM and SEG pins will be at the VSS level. Even
if this bit is set to “0”, the display RAM contents will not change. If the RESET pin is pulled to a “L” level, this
register is reset to “0”.
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Rotary encoder (RE) read
D7
Q4
D6
Q4
D5
Q4
D4
Q4
D3
Q4
D2
Q3
D1
Q2
D0
Q1
The rotary encoder read instruction is used to read the count value from the rotary encoder switch input signal.
(Count values are in the 2’s complement format.)
(1) D7 to D0 (Q4 to Q1) (Count value bit)
The phase difference between the A signal and the B signal is recognized, and the value that is counted by the edge
of the signal with the slower phase is set. Count values range from negative 1000 (Q4, Q3, Q2, Q1) to positive
0111. If the count is less than negative 1000 or more than positive 0111, then it is ignored.
These bits are all reset to “0” when this instruction is executed or when the RESET pin is pulled to a “L” level.
If counterclockwise rotation is input after the count value is incremented by clockwise rotation, then count value
will be decremented. If counterclockwise rotation is further input after the count value reaches 0000, then the
count value will change to 1111 and the count value will be decremented. (The count value will remain 1000 even
if counterclockwise rotation is further input after the count value reaches negative 1000.)
After this, if clockwise rotation is input, then the count value will be incremented. If the count value reaches 1111
and clockwise rotation is further input, then the count value will become 0000 and the count value will be
incremented. (Even if clockwise rotation is further input after the count value reaches positive 0111, the count
value will maintain 0111.)
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Functional Description of the Rotary Encoder Switch
As shown in Figure 3, the rotary encoder switch circuit is made up of phase detection circuit, an interrupt
generation circuit, an up/down counter and a parallel-in/serial-out register.
A
B
Phase detection circuit
UP DOWN
Interrupt
generation circuit
To KREQ
Up/down counter
Q4 Q3 Q2 Q1
Parallel in/serial out
shift register
Output data
Figure 3 Rotary Encoder Switch Circuit
1) Phase Detection and Interrupt Generation Circuits
1-1) Clockwise Rotation
When the A and B signals are input as shown in Figure 4, the phase detection circuit outputs the UP
signal after the chattering absorption period. At this time, the KREQ output goes to a high level, so
that this signal can be used as the interrupt signal. The KREQ signal maintains a high level until the
rotary encoder read instruction is executed.
A
B
Chattering absorption period
UP (internal signal)
KREQ
Figure 4 Input/Output Timing for Clockwise Rotation
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1-2) Counterclockwise Rotation
When the A and B signals are input as shown in Figure 4, the phase detection circuit outputs the
DOWN signal after the chattering absorption period. At this time, the KREQ output goes to a
high level, so that this signal can be used as the interrupt signal. The KREQ signal maintains a
high level until the rotary encoder read instruction is executed.
A
B
Chattering absorption period
DOWN (internal signal)
KREQ
Figure 5 Input/Output Timing for Counterclockwise Rotation
2) UP/DOWN Counter
The UP/DOWN counter is incremented when an UP signal is input and decremented when a DOWN
signal is input. However, if the counter reaches “0111” and an UP signal is input, the UP/DOWN
counter will hold “0111”. In the same manner, if the UP/DOWN counter is at “1000” and a DOWN
signal is input, the UP/DOWN counter will hold “1000”.
A
B
Q4, Q3, Q2, Q1
0001
0010
0011
0100
0101
0110
0111
0111
Figure 6 When the Up Counter Overflows
A
B
Q4, Q3, Q2, Q1 1111
1110
1101
1100
1011
1010
1001
1000
1000
Figure 7 When the Down Counter Overflows
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3) Parallel-in/Serial-out Shift Register
The KREQ signal goes to a low level when the rotary encoder read instruction is executed, when the
UP/DOWN counter will be reset to “0”.
CS
1
2
8
9
10 11 12 13 14 15 16
CP
DI/O
READ DATA1
Instruction code
Output state
Input state
KREQ
Figure 8 Operation of KREQ Output
Notes:
1. The KREQ signal is output by a logical OR of the KREQ signal generated by a key scan and the
KREQ signal generated by the rotary encoder. The KREQ signal from the rotary encoder is reset by
executing the rotary encoder read instruction; however, the KREQ signal generated by a key scan is
not reset even if the key scan register read instruction is executed. Also, if the KREQ signal is
generated by a key scan, it will not be reset even if the rotary encoder read instruction is executed.
Although dependent on the components glued to this LSI, it is recommended that the rotary encoder
read instruction and key scan register read instruction be executed as a set when the KREQ signal
goes to a “H” level.
2. The maximum read cycle time for when the KREQ signal is at a “H” level is practically determined by
the signal input from the rotary encoder and the 3-bit counter built into this LSI. Therefore, make the
time taken before starting to execute the rotary encoder read instruction 12 ms or less.
3. Using a rotary encoder switch that has the click stabilizing points shown below is recommended.
A signal
B signal
Click stabilizing points
Waveform of a Recommended Rotary Encoder Switch
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Contrast ADJ (CA) set
D7
D6
—
D5
—
D4
—
D3
D2
D1
D0
—
CT3
CT2
CT1
CT0
—: don’t care
This instruction is for adjusting the liquid crystal display voltage.
(1) D3 to D0 (CT3 to CT0) (Contrast adjustment value setting bits)
When FH is written to these bits, the liquid crystal display voltage (voltage between the V0 and VSS pins) becomes
a maximum.
When 0H is written, the liquid crystal display voltage becomes a minimum.
By setting the values from 0H to FH, the liquid crystal display voltage can be adjusted just like an electronic
volume control.
These bits are all reset to “0” if the RESET pin is pulled to a “L” level.
V0 Ouput Target Voltage for Contrast ADJ Setting Values
Contrast ADJ setting values
V0 output target voltage
ML9092-01/02
CT3
1
CT2
1
CT1
1
CT0
1
ML9092-03/04
0.980VHIN
0.973VHIN
0.947VHIN
0.923VHIN
0.900VHIN
0.878VHIN
0.857VHIN
0.837VHIN
0.818VHIN
0.800VHIN
0.783VHIN
0.766VHIN
0.750VHIN
0.735VHIN
0.720VHIN
0.700VHIN
0.980VOUT
0.973VOUT
0.947VOUT
0.923VOUT
0.900VOUT
0.878VOUT
0.857VOUT
0.837VOUT
0.818VOUT
0.800VOUT
0.783VOUT
0.766VOUT
0.750VOUT
0.735VOUT
0.720VOUT
0.700VOUT
1
1
1
0
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
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PWM0/1/2 register (PWMR) set
D7
D6
D5
D4
D3
D2
D1
D0
PWx7
PWx6
PWx5
PWx4
PWx3
PWx2
PWx1
PWx0
Note: “x” stands for 0 for PB0 (port B0), 1 for PB1 (port B1) and 2 for PB2 (port B2).
This instruction sets the pulse width of the PWM signal output from port B. (Applies to ML9092-01/04.)
PWx0 is LSB and PWx7 is MSB.
This instruction should be used with a PWM data write cycle of 5.0 ms or longer.
These bits are all reset to “0” if the RESET pin is pulled to a “L” level.
Note: When inputting multiple PWM data items, be sure to input them in succession (i.e., without intervals).
PWxn = 00 H (0/255)
Fixed at “H” State at the time of reset
PWxn = 01 H (1/255)
PWxn = 02 H (2/255)
PWxn = 03 H (3/255)
PWxn = FE H (254/255)
PWxn = FF H (255/255)
Fixed at “H”
Figure 9 PWM Output Waveform
Test register (TEST) set
D7
—
D6
—
D5
—
D4
—
D3
T4
D2
T3
D1
T2
D0
T1
—: don’t care
This instruction is for testing by the manufacturer.
Customers should not use this register.
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Display Screen and Memory Address Allocation
The ML9092-01/02/03/04 has an internal display data RAM (60 bits by 10 bits) of a bitmap type.
The allocation of memory addresses varies according to the selected word length (6 bits or 8 bits) as shown in
Figure 10: 0 to 7 for selection of 8 bits per word or 0 to 9 for selection of 6 bits per word.
The X address 7 in the 6-bits/word mode has four display memory bits. The four bits (D7 to D4) starting from bit
D7 of the display data register are written in memory and the other bits (D3 to D0) are ignored.
Address Allocation in the 8-bits/word mode
Address Allocation in the 6-bits/word mode
(X address)
(X address)
0
1
2
7
0
1
2
9
0
1
0
1
(D7)
(D0)
(D5)
(D7)
(D4)
(4 bits)
(D0)
(6 bits)
(8 bits)
9
9
Figure 10 Display Memory Addresses
In the 8-bits/word mode, data to be displayed is written in display memory with the D7 data of the display data
register at address (Xn, Yn) and the D0 data at address (Xn + 7, Yn). Similarly, In the 6-bits/word mode, data to be
displayed is written in display memory with the D5 data of the display data register at address (Xn, Yn) and the D0
data at address (Xn + 5, Yn). See Figure 11.
Data “1” in display memory represents turning on the corresponding display segment and data “0” in display
memory represents turning off the corresponding display segment.
Note: In the ML9092-01, the X address range in the 8-bits/mode will be 0 to 6
Common
output
1
0
1
1
1
0
1
0
0
Y line
Y0
(COM1)
(COM2)
Y1
(D7)
(D5)
(D0) For 8 bits per word
(D0) For 6 bits per word
RAM for 60 dots by 10 dots display
(COM10)
Y9
Figure 11 Display Screen Bit Allocation and Memory Addresses
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X•Y address Counter Auto Increment
The liquid crystal display RAM has an X-address counter and a Y-address counter. Each address counter has an
Auto Increment function.
When display data is read or written, this function increments either of these X- and Y-address counters (which is
selected by the INC bit (D7 bit) of the control register 1).
INC bit = “0” selects the Y-address counter.
INC bit = “1” selects the X-address counter.
The address counting cycle of the X address counter varies according to the selected word length (8 bits or 6 bits):
X address range of 0 to 6 (ML9092-01) or 0 to7 (ML9092-02/03/04) in the 8-bits/word mode or X address range of
0 to 9 in the 6-bits/word mode.
When the X address count returns to 0 from a maximum value (6 (ML9092-01) or 7 (ML9092-02/03/04) in the
8-bits/word mode, or 9 in the 6-bits/word mode), the Y address is also incremented automatically.
The relationship between display duties and Y address count ranges is shown below.
When the Y-address counter returns to 0 from a maximum value, the X address is also incremented automatically.
Model
Duty
1/8
Y-address count range (cycle)
Maximum Y address count
0 to 7
0 to 8
0 to 9
7
8
9
ML9092-01/02/03/04
1/9
1/10
Note:
If an invalid address (outside the address count range) is given to the X- or Y- address counter,
its counting will not be assured.
Example of incrementing the X-address
(8 bits per word and 1/10 duty)
Example of incrementing the Y-address
(8 bits per word and 1/10 duty)
X address
0
1
7
X address
2
0
1
2
0
1
7
0
1
9
9
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Liquid Crystal Driving Waveform Example (1)
1/8 duty (1/4 bias)
Common
line No.
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
V0
V1
V2
V3
VSS
C0M1
C0M2
C0M8
V0
V1
V2
V3
VSS
V0
V1
V2
V3
VSS
A non-selectable waveform is output from COM9 and COM10 outputs.
Common
line No.
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2 3
V0
V1
V2
V3
VSS
SEGn
: Light ON
: Light OFF
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Liquid Crystal Driving Waveform Example (2)
1/9 duty (1/4 bias)
Common
line No.
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
V0
V1
V2
V3
VSS
C0M1
C0M2
C0M9
V0
V1
V2
V3
VSS
V0
V1
V2
V3
VSS
A non-selectable waveform is output from the COM10 output.
Common
line No.
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
V0
V1
V2
V3
VSS
SEGn
: Light ON
: Light OFF
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Liquid Crystal Driving Waveform Example (3)
1/10 duty (1/4 bias)
Common
line No.
10 1
2
3
4
5
6
7
8
9 10 1
2
3
4
5
6
7
8 9 10
V0
V1
V2
V3
VSS
C0M1
C0M2
V0
V1
V2
V3
VSS
V0
V1
V2
V3
VSS
C0M10
Common
line No.
10 1
2
3
4
5
6
7
8
9 10 1
2
3
4
5
6
7
8
9 10
V0
V1
V2
V3
VSS
SEGn
: Light ON
: Light OFF
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Flowchart for Setting the Standby Mode and Releasing the Standby Setting with KREQ by Key Input
(Applies to the ML9092-03/04)
Normal operaton
Make a setting for control
Setting of STB and DISP
register 2
LCD driving voltage: OFF
Turn external power supply (VHIN) OFF
Pull VHIN and V0 to the VSS level
or put them into a floating state.
Standby state
Standby state
Key input
NO
KREQ output =
“H” level ?
YES
Make a setting for control
Release STB.
register 2
LCD driving voltage: ON
Turn external power supply (VHIN) ON
Make a setting for control register
2 again
Make a setting of INC, WLS, KT,
SHL, BE, PE, DTY1, and DTY0
again
Make a setting for port register A
and display data RAM again
according to the specification.
Make a setting for registers
again
NO
Is initial screen
data input
complete?
YES
Set DISP of control register 2 to
“1”
Displaying of initial screen started
Settings completed
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Power-On Flowchart
Start
Turn on VDD
Turn on VIN
External reset or power-on reset
Input reset signal
Make a setting for INC, WLS, KT, SHL, BE,
PE, DTY1, and DTY0.
Make a setting for control register 1
Make a setting for registers
Make a setting for port register A, port
register B, port register C, port register D, and
display data RAM according to specifications.
Is input of initial
screen data
complete ?
No
Yes
Wait till the liquid crystal driving
voltage stabilization time is reached
Wait till the VOUT voltage stabilizes when the
voltage doubler is used.
Set DISP of control register 2 to
“1”
Displaying of initial screen started
Setting complete
Power-Off Flowchart
LCD driving state
Turn off VIN
Turn off VDD
[Caution]
The lines between output pins, and between output pins and other pins (input pins, I/O pins or power supply
pins), should not be short circuited.
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PRECAUTIONS WHEN TURNING ON THE POWER SUPPLY
To prevent the device from malfunctioning, observe the following power-on/off sequence:
For power-on, first turn on the logic power supply (VDD), then turn on the voltage doubler reference voltage (VIN)
or high voltage (VOUT or VHIN).
For power-off, first turn off the voltage doubler reference voltage (VIN) or high voltage (VOUT or VHIN), then turn
off the logic power supply (VDD).
[Voltage]
VOUT or VHIN pin voltage
VDD pin voltage
VDD = 2.0 V
[Time]
Power-On Sequence
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APPLICATION CIRCUIT
Application Example—1/10 duty, 1/4 bias, voltage doubler used (internal contrast adjustment not used)
LCD panel
56 10 dots
graphic
VDD = 5 V
COM1–COM10
SEG1–56
Temperature
compensat-
ing and
VCC
VIN
VDD
4.7
+
F
stabilizing
circuits
VC1
+
KPS
VSS
VS1–
VOUT
V0
PA0
+
4.7
F
OSC1
ML9092-01
56 k
OSC2
TEST
CPU
CS
CP
RESET
1
F
Port
or
serial port
DI/O
KREQ
R4/C4
R3/C3
R2/C2
R1/C1
Rotary
switch
L.P.F.
A, B
R0/C0
C4/D4
C0/D0 C1/D1 C2/D2 C3/D3
PB0–PB2
PWM output
ports
5
5 key matrix
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PACKAGE DIMENSIONS
(Unit: mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5μm)
0.55 TYP.
4/Oct. 28, 1996
5
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact ROHM's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions (reflow
method, temperature and times).
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REVISION HISTORY
Page
Document No.
Date
Nov. 4, 2003
Description
Previous Current
Edition
Edition
FEDL9092-01
—
—
First edition
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ML9092-01/02/03/04
NOTICE
No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS
Semiconductor Co., Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be
obtained from LAPIS Semiconductor upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor
shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples of
application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any
license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties.
LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such
technical information.
The Products specified in this document are intended to be used with general-use electronic equipment or
devices (such as audio visual equipment, office-automation equipment, communication devices, electronic
appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such
as derating, redundancy, fire control and fail-safe designs. LAPIS Semiconductor shall bear no responsibility
whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the
instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system which
requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat
to human life or create a risk of human injury (such as a medical instrument, transportation equipment,
aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). LAPIS
Semiconductor shall bear no responsibility in any way for use of any of the Products for the above special
purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales
representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled
under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit
under the Law.
Copyright 2003 - 2011 LAPIS Semiconductor Co., Ltd.
.
66/66
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