ML9484 [ROHM]
ML9484由50位移位寄存器、200位数据锁存器、50组LCD驱动器、以及公共信号生成电路组成。静态显示时可直接驱动多达50段、1/2Duty显示时可直接驱动多达100段、1/3Duty显示时可直接驱动多达150段、1/4Duty显示时可直接驱动多达200段的LCD。;
| 型号： | ML9484 |
| 厂家： | 
ROHM |
| 描述： | ML9484由50位移位寄存器、200位数据锁存器、50组LCD驱动器、以及公共信号生成电路组成。静态显示时可直接驱动多达50段、1/2Duty显示时可直接驱动多达100段、1/3Duty显示时可直接驱动多达150段、1/4Duty显示时可直接驱动多达200段的LCD。 驱动 CD 接口集成电路 锁存器 驱动器 移位寄存器 |
| 文件： | 总30页 (文件大小：308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dear customer
LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October,
2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which
LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS
Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business.
Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor"
and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd."
Furthermore, there are no changes to the documents relating to our products other than
the company name, the company trademark, logo, etc.
Thank you for your understanding.
LAPIS Technology Co., Ltd.
October 1, 2020
FEDL9484-01
Issue Date: Dec. 25, 2013
ML9484
Static, 1/2 Duty, 1/3 Duty, 1/4 Duty 50 Outputs LCD Driver
GENERAL DESCRIPTION
The ML9484 is an LCD driver LSI, consists of a 50-bit shift register, a 200-bit data latch, 50 sets of LCD drivers,
and a common signal generation circuit.
It can directly drive an LCD up to 50 segments for static display, 100 segments for 1/2-duty display, 150
segments for 1/3-duty display, and 200 segments for 1/4-duty display.
FEATURES
Logic power supply voltage
LCD drive power supply voltage : 4.5 to 5.5 V
Maximum number of segments
Static display
1/2-duty display
1/3-duty display
1/4-duty display
: 2.7 to 5.5 V
: 50 segments
: 100 segments
: 150 segments
: 200 segments
Serially interfaces with the CPU using the three signal lines of DATA, CLOCK, and LOAD
Selectable internal CR oscillator circuit or external clock input
Built-in bias circuit
Built-in common output intermediate-value voltage generation circuit
Command-selectable A-waveform or B-waveform
Package
: 64-pin plastic TQFP
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FEDL9484-01
ML9484
BLOCK DIAGRAM
SEG1
SEG50
VLCD
50-Dot Segment Driver
50-Ch Data Selector
Bias
Resi.
50
50
50
50
50-Bit
Latch4
50-Bit
Latch3
50-Bit
Latch2
50-Bit
Latch1
LATCH
SELECTOR
LOAD
50
DATA
Command
Decoder
50-bit Shift Register
CLOCK
OSC I/E
OSC
COM1
COM2
COM3
COM4
COMMON
Driver
TIMING
GENERATOR
OSC
RESETB
TEST
VDD
GND
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PIN CONFIGURATION (TOP VIEW)
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
1
2
48 SEG48
47 SEG47
46 SEG46
45 SEG45
44 SEG44
43 SEG43
42 SEG42
41 SEG41
40 SEG40
39 SEG39
38 SEG38
37 SEG37
36 SEG36
35 SEG35
34 SEG34
33 SEG33
3
4
5
6
7
8
9
10
11
SEG12 12
SEG13 13
SEG14 14
SEG15 15
SEG16 16
64-Pin Plastic TQFP
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ML9484
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Condition
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta ≦ 105°C
—
Rating
-0.3 to 6.0
-0.3 to 6.0
– 0.3 to VDD + 0.3
-2.0 to +2.0
145
Unit
V
Logic power supply voltage
LCD drive power supply voltage
Input voltage
VDD
VLCD
VI
V
V
Output short-circuit current
Power dissipation
Is
mA
mW
°C
PD
Storage temperature
TSTG
-55 to +150
Note: Do not use the ML9484 by short-circuiting one output pin to another output pin as well as to other pin
(input pin, input/output pin, or power supply pin).
RECOMMENDED OPERATION CONDITIONS
Item
Symbol
VDD
Condition
Range
Unit
Logic power supply voltage
LCD drive power supply voltage
OSC IN clock frequency
Data clock frequency
*
—
—
—
—
—
2.7 to 5.5
4.5 to 5.5
0.5 to 10
V
V
VLCD
fCP1
fCP2
Ta
*
kHz
MHz
°C
0.01 to 1.0
-40 to +105
Operating temperature
Note(*): Use at VDD VLCD
.
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ML9484
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta= -40 to +105°C)
Applicable
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
pin
"H" input voltage
VIH
VIL
IL1
—
—
0.8VDD
GND
-1
—
—
—
—
—
VDD
0.2VDD
1
V
(*1)
(*1)
(*2)
"L" input voltage
V
Input leakage current 1
Input leakage current 2
Pull-up current
VI = VDD or 0 V
μA
μA
μA
IL2
VI = VDD
-1
1
RESETB
Ipu
VDD = 5.0V,VI = 0 V
30
140
RESETB
SEG1 to
SEG50
Segment
Driver
ON resistor
Common
VOHS
VOHC
IDDS
VLCD = 5V
VLCD = 5V
—
—
—
—
5
5
1
9
15
12
7
kΩ
kΩ
μA
μA
COM 1 to
COM4
V
DD=VLCD=5.5 V
VDD
Input pin fixed to "H" or "L"
Oscillation stopped,
output no-load
Static supply current
ILCDS
15
VLCD
VDD=VLCD= 5.5 V (*3)
Clock OSC external input
IDD1
ILCD1
IDD2
2
9
10
15
82
15
μA
μA
μA
μA
VDD
—
—
—
—
Dynamic supply
current 1
VLCD
VDD
f
CP1=1.8kHz
53
9
Dynamic supply
current 2
V
DD=VLCD= 5.5 V (*4)
Internal oscillation=95Hz
ILCD2
VLCD
(*1): DATA, CLOCK, LOAD, RESETB, OSC, OSC I/E
(*2): DATA, CLOCK, LOAD, OSC, OSC I/E
(*3): 1/4-duty, 1/3-bias, OSCI/E=”L”, Output pin no-load.
(*4): 1/4-duty, 1/3-bias, OSCI/E=”H”, (F2, F, F0) = (0, 1, 1) 95 Hz, Output pin no-load.
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Switching Characteristics
OSC timing
Item
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta = -40 to +105°C)
Symbol
fCP1
Condition
Min.
Typ. Max.
Unit
Applicable pin
OSC IN clock frequency
(External input)
0.5
1.8
—
10
—
kHz OSC
Clock input from OSC.
OSC I/E = "L"
Clock pulse width
(External input)
tWCP1
tOSC
40
—
μs
μs
OSC
OSC
Clock rise and fall time
(External input)
—
(*1)
OSC open.
(F2, F1, F0)=(0, 0, 1)
OSC I/E = "H"
Internal clock frequency
(Internal oscillation)
fOSC1
18
28.8
44
kHz OSC
The relation between OSC IN clock frequency and frame frequency is as the equation below.
fFRM = fCP1 /24
(*1) tOSC is a reference value.
The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.
Make the rise as steep as possible. Reference value: max=2μs.
Serial interface timing
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta = -40 to +105°C)
Condition Min. Typ. Max. Unit Applicable pin
MHz CLOCK
Item
Symbol
Data clock frequency
Data clock pulse width
Data setup time
fCP2
tWCP2
tSU
0.01
100
50
—
—
—
—
—
—
—
1
—
—
—
—
—
—
ns CLOCK
ns DATA
ns CLOCK
ns CLOCK
ns LOAD
ns LOAD
Data hold time
tHD
50
CLOCK-LOAD timing
LOAD-CLOCK timing
LOAD pulse width
tCL
100
100
100
tLC
tWLD
CLOCK,DATA,
LOAD
Signal rise and fall time
tsr,tsf
—
—
(*2)
ns
(*2) tsr and tsf shall be reference values.
The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.
Make the rise as steep as possible. Reference value: max=10ns.
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Timing chart (OSC)
1/fCP1
tWCP1
VIH
tWCP1
VIH
VIH
OSC
(External clock)
VIL
VIL
tOSC
Timing chart (Serial interface)
VIH
VIH
VIL
tHD
VIH
VIH
DATA
VIL
VIL
VIL
tSU
tsf
tsr
tWCP2
tWCP2
VIH
VIL
VIH
VIH
VIH
CLOCK
VIL
VIL
VIL
VIL
1/fCP2
tsr
tCL
tWLD
tLC
tsf
V
IH VIH
LOAD
VIL
VIL
tsr
tsf
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ML9484
POWER ON/OFF TIMING
To turn on the power supply, raise the logic power supply first, then LCD drive power supply in order to prevent
the IC from malfunctioning.
To fall the power supply, fall the LCD drive power supply first, then the logic power supply.
For a VDD pin ranging from 0 V to VDDmin, set VDD ≥ VLCD and t1 ≥ 0 [ns].
Voltage
VLCD
VDD
t1
t1
Time
INITIALIZATION SIGNAL TIMING
Keep the RESETB pin at "L" level until the VDD reaches VDD min. (t2 ≥ 200[ns])
VDD
VDD min
RESETB
VIL
t2
The value of the current of the pull-up resistor is specified for RESETB pin.
The customer needs to select an external capacitor that meets the timing requirements shown above.
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ML9484
PIN DESCRIPTIONS
Pad
Symbol
number
I/O
O
Description
SEG1 to
1 to 50
Outputs for LCD display. Connected to the segment pins on the LCD panel.
In the display off mode, all the outputs are fixed to GND.
Outputs for LCD display. Connected to the common pins on the LCD panel.
In the display off mode, all the outputs are fixed to GND.
Power supply pin for LCD driver.
SEG50
COM1 to
51 to 54
O
COM4
55
56
VLCD
VDD
-
-
Power supply pin for logic circuit.
This input selects whether to use the external clock input mode or to use the
Internal oscillation mode. It has a schmitt circuit.
When this pin is "H", the mode is the Internal Rf oscillation mode.
When this pin is "L", the mode is the external clock input mode.
IC test pin. Has a pull-down resistor built-in.
57
OSC I/E
I
58
59
TEST
GND
I
Use it as it is connected to GND.
-
Ground pin.
Pin for oscillation. Has a Schmitt circuit built-in.
Internal Rf oscillation mode: Set the OSCI/E pin to "H", open the OSC pin.
External clock input mode: Set the OSCI/E pin to "L", input the external clock
to the OSC pin.
60
61
OSC
I
I
Reset signal input pin for initializing inside the IC. It has a schmitt circuit.
The "L" level enables the reset. This pin has an Internal pull-up resistor.
The power-on reset operation is available by connecting an external
capacitor. *1
RESETB
Input pin for the load signal of display data. It has a schmitt circuit.
The display data in the shift register is transmitted as is to the segment driver
for the "H" duration. When this pin is brought into "L", the shift register is
disconnected from the segment driver. The display data in the shift register
immediately before it become "L" is held in the data latch and transmitted to
the segment driver.
62
LOAD
I
Shift clock input pin for display data. It has a schmitt circuit.
The display data input to the DATA pin is serially input to the shift register at
the CLOCK signal rise.
63
64
CLOCK
DATA
I
I
Display data input pin. It has a schmitt circuit.
Input the display data in the order of SEG50, SEG49, ... , SEG2, and SEG1.
The display data turns on at "H" and turns off at "L".
*1: Reset circuit configuration
VDD
RESETB
CRST
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DESCRIPTION
Operation description
• Display data input
As described in the Data configuration section, the display data consists of the data field that corresponds to
each segment on/off and the command field that indicates the display data input.
When inputting the display data, the "F1" command is set in the command field. When the "F2" to "F5"
command is set in the command field, the display data in the data field becomes invalid.
The data input to the DATA pin is loaded to the shift register at the CLOCK pulse rise, transferred to the
display data latch during the LOAD pulse at the "H" level, then output via the segment driver.
CLOCK
DATA
D1 D2 D3 D4
Data field
D48 D49 D50 C0 C1 C2 C3 C4 C5
Command field
LOAD
Display output
New data
Old data
• Display on, Display off
The display becomes off at power-on reset. To display, write the display on command.
The display off is the command that makes all segments off. Writing the display off command turns off the
lights regardless of the display data.
The display on is the command to release the display off. Writing the display on command returns the display
to the original state.
CLOCK
DATA
D1 D2
C4 C5
C2 C3 C4 C5
C2 C3 C4 C5
LOAD
Display ON/OFF
RESETB
Display data input
Write Display OFF
command
Write display ON
command
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ML9484
List of Commands
Command
C5
C4
0
C3
0
C2
x
C1
x
C0
x
Operation
name
Disabled
F0
0
Data write address setting
(Co1,Co0)=(0, 0): Corresponding to common 1
(Co1,Co0)=(0, 1): Corresponding to common 2
(Co1,Co0)=(1, 0): Corresponding to common 3
(Co1,Co0)=(1, 1): Corresponding to common 4
Frame frequency setting
F1
0
0
1
Co1
Co0
x
(F2, F1, F0)=(0, 0, 0): 65Hz
(F2, F1, F0)=(0, 0, 1): 75Hz
(F2, F1, F0)=(0, 1, 0): 85Hz
(F2, F1, F0)=(0, 1, 1): 95Hz
(F2, F1, F0)=(1, 0, 0): 130Hz
(F2, F1, F0)=(1, 0, 1): 150Hz
(F2, F1, F0)=(1, 1, 0): 170Hz
(F2, F1, F0)=(1, 1, 1): 190Hz
(valid for Internal CR oscillation)
LCD Bias setting
0
1
0
F2
(0)
F1
(0)
F0
(0)
F2
BIAS="0" : 1/3-bias
0
1
1
BIAS WSEL
x
BIAS="1" : 1/2-bias
F3
(0)
(0)
LCD Driving Waveform setting
WSEL="0" : A-Waveform
WSEL="1" : B-Waveform
Display Duty setting
(D1, D0)=(0, 0): Static
(COM1=COM2=COM3=COM4)
(D1, D0)=(0, 1): 1/2-duty
(COM1=COM3, COM2=COM4)
(D1, D0)=(1, 0): 1/3-duty
(COM2=COM4)
(D1, D0)=(1, 1): 1/4-duty
1
1
0
0
0
1
D1
(0)
D0
(0)
x
x
F4
F5
Display on/off setting
DSP="0" : Off （COM=SEG=GND）
DSP="1" : On
DSP
(0)
x
Disabled
F6
F7
1
1
1
1
0
1
x
x
x
x
x
x
Disabled
x: Don't care
( ): Reset Value
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FEDL9484-01
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Data configuration
[Input data]
First bit
Corresponding to SEG50
Corresponding to SEG1
C5
C4
C3
C2
C1
C0
D50
D49
D48
D3
D2
D1
LCD display data
Command
Note 1: The commands F4 settings become valid when the least four bits of C2 to C5 are input.
(The bits from D1 to D50 and from C0 to C1 are not necessary.)
The commands F3 and F4 settings become valid when the least five bits of C1 to C5 are input.
(The bits from D1 to D50 and from C0 are not necessary.)
The commands F2 settings become valid when the least six bits of C0 to C5 are input.
(The bits from D1 to D50 are not necessary.)
Note 2: If the dummy bit is needed for the reason of number of transfer bits, put it on the first bit side.
Note 3: The command execution follows the contents of the C5 to C0 registers immediately before the LOAD
becomes "H".
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LCD Driving Waveform
• Static mode (same as A-waveform and B-waveform)
S
E
G
1
S
E
G
2
S
E
G
3
ON
COM1
OFF
fFRM
VLCD
COM1
COM2
COM3
COM4
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
SEG1
SEG2
SEG3
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
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• 1/2-duty, 1/2-bias mode (A-waveform)
S
E
G
1
S
E
G
2
S
E
G
3
COM1
COM2
ON
OFF
fFRM
VLCD
COM1
COM3
VLCD/2
GND
VLCD
COM2
COM4
VLCD/2
GND
VLCD
SEG1
SEG2
SEG3
VLCD/2
GND
VLCD
VLCD/2
GND
VLCD
VLCD/2
GND
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• 1/2-duty, 1/3-bias mode (A-waveform)
S
E
G
1
S
E
G
2
S
E
G
3
COM1
COM2
ON
OFF
fFRM
VLCD
2VLCD/3
VLCD/3
GND
COM1
COM3
VLCD
2VLCD/3
VLCD/3
GND
COM2
COM4
VLCD
2VLCD/3
VLCD/3
GND
SEG1
SEG2
SEG3
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
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• 1/3-duty, 1/2-bias mode (A-waveform)
S
E
G
1
S
E
G
2
S
E
G
3
COM1
COM2
COM3
ON
OFF
fFRM
VLCD
COM1
VLCD/2
GND
VLCD
COM2
COM4
VLCD/2
GND
VLCD
COM3
VLCD/2
GND
VLCD
SEG1
SEG2
SEG３
VLCD/2
GND
VLCD
VLCD/2
GND
VLCD
VLCD/2
GND
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• 1/3-duty, 1/3-bias mode (A-waveform)
S
E
G
1
S
E
G
2
S
E
G
3
COM1
COM2
COM3
ON
OFF
fFRM
VLCD
2VLCD/3
VLCD/3
COM1
GND
VLCD
2VLCD/3
VLCD/3
GND
COM2
COM4
VLCD
2VLCD/3
VLCD/3
GND
COM3
VLCD
2VLCD/3
VLCD/3
GND
SEG1
SEG2
SEG３
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
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• 1/4-duty, 1/2-bias mode (A-waveform)
S
E
G
1
S
S
E
G
3
E
G
2
COM1
COM2
COM3
COM4
ON
OFF
fFRM
VLCD
VLCD/2
GND
COM1
COM2
COM3
COM4
SEG1
SEG2
SEG3
VLCD
VLCD/2
GND
VLCD
VLCD/2
GND
VLCD
VLCD/2
GND
VLCD
VLCD/2
GND
VLCD
VLCD/2
GND
VLCD
VLCD/2
GND
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ML9484
• 1/4-duty, 1/3-bias mode (A-waveform)
S
E
G
1
S
E
G
2
S
E
G
3
COM1
COM2
COM3
COM4
ＯＮ
OFF
fFRM
VLCD
2VLCD/3
VLCD/3
GND
COM1
COM2
COM3
COM4
SEG1
SEG2
SEG3
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
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ML9484
• 1/2-duty, 1/2-bias mode (B-waveform)
S
E
G
1
S
E
G
2
S
E
G
3
COM1
COM2
ON
OFF
fFRM
VLCD
COM1
COM3
VLCD/2
GND
VLCD
COM2
COM4
VLCD/2
GND
VLCD
SEG1
SEG2
SEG3
VLCD/2
GND
VLCD
VLCD/2
GND
VLCD
VLCD/2
GND
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FEDL9484-01
ML9484
• 1/2-duty, 1/3-bias mode (B-waveform)
S
E
G
1
S
E
G
2
S
E
G
3
COM1
COM2
ON
OFF
fFRM
VLCD
2VLCD/3
VLCD/3
GND
COM1
COM3
VLCD
2VLCD/3
VLCD/3
GND
COM2
COM4
VLCD
2VLCD/3
VLCD/3
GND
SEG1
SEG2
SEG3
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
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• 1/3-duty, 1/2-bias mode (B-waveform)
S
E
G
1
S
E
G
2
S
E
G
3
COM1
COM2
COM3
ON
OFF
fFRM
VLCD
COM1
VLCD/2
GND
VLCD
COM2
COM4
VLCD/2
GND
VLCD
COM3
VLCD/2
GND
VLCD
SEG1
SEG2
SEG３
VLCD/2
GND
VLCD
VLCD/2
GND
VLCD
VLCD/2
GND
22/29
FEDL9484-01
ML9484
• 1/3-duty, 1/3-bias mode (B-waveform)
S
E
G
1
S
E
G
2
S
E
G
3
COM1
COM2
COM3
ON
OFF
fFRM
VLCD
2VLCD/3
VLCD/3
COM1
GND
VLCD
2VLCD/3
VLCD/3
GND
COM2
COM4
VLCD
2VLCD/3
VLCD/3
GND
COM3
VLCD
2VLCD/3
VLCD/3
GND
SEG1
SEG2
SEG３
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
23/29
FEDL9484-01
ML9484
• 1/4-duty, 1/2-bias mode (B-waveform)
S
E
G
1
S
S
E
G
3
E
G
2
COM1
COM2
COM3
COM4
ON
OFF
fFRM
VLCD
VLCD/2
GND
COM1
COM2
COM3
COM4
SEG1
SEG2
SEG3
VLCD
VLCD/2
GND
VLCD
VLCD/2
GND
VLCD
VLCD/2
GND
VLCD
VLCD/2
GND
VLCD
VLCD/2
GND
VLCD
VLCD/2
GND
24/29
FEDL9484-01
ML9484
• 1/4-duty, 1/3-bias mode (B-waveform)
S
E
G
1
S
E
G
2
S
E
G
3
COM1
COM2
COM3
COM4
ＯＮ
OFF
fFRM
VLCD
2VLCD/3
VLCD/3
GND
COM1
COM2
COM3
COM4
SEG1
SEG2
SEG3
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
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FEDL9484-01
ML9484
EXAMPLE OF APPLICATION CIRCUIT
COM1
COM2
COM3
COM4
1/4 Duty LCD Panel
SEG1
SEG50
SEG50
SEG1
COM1
COM2
COM3
COM4
VLCD
LOAD
DATA
+5 V
+5 V
ML9484
CPU
CLOCK
VDD
OSCI/E
GND
Open
OSC
RESETB
TEST
REFRESH
Although the ML9484 holds operation state by commands, excessive external noise might change the
internal state.
On a chip-mounting and system level, it is necessary to take countermeasures against preventing noise from
occurring. It is recommended to use the refresh sequence periodically to control sudden noise.
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FEDL9484-01
ML9484
PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
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FEDL9484-01
ML9484
REVISION HISTORY
Page
Previous
Document No.
FEDL9484-01
Issue Date
Description
New
Edition
Edition
Dec .25, 2013
–
–
Final edition 1 issued
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FEDL9484-01
ML9484
NOTES
No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS
Semiconductor Co., Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be
obtained from LAPIS Semiconductor upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall
bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples of
application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any
license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties.
LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such
technical information.
The Products specified in this document are intended to be used with general-use electronic equipment or
devices (such as audio visual equipment, office-automation equipment, communication devices, electronic
appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as
derating, redundancy, fire control and fail-safe designs. LAPIS Semiconductor shall bear no responsibility
whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction
manual.
The Products are not designed or manufactured to be used with any equipment, device or system which requires
an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human
life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace
machinery, nuclear-reactor controller, fuel-controller or other safety device). LAPIS Semiconductor shall bear
no responsibility in any way for use of any of the Products for the above special purposes. If a Product is
intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled under
the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the
Law.
Copyright 2013 LAPIS Semiconductor Co., Ltd.
29/29
相关型号：
ML97CS
Rectangular Connector Adapter, 9 Contacts(Side1), 9 Contacts(Side2), Panel Mount, Female-Female
MOLEX
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