SA712132COB [SAMES]

128 Bit Read-only Manchester Coded;


型号：	SA712132COB
厂家：	SAMES
描述：	128 Bit Read-only Manchester Coded
文件：	总10页 (文件大小：119K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SA7121A: 128 Bit Read-only Manchester Coded

Transponder

FEATURES

EEPROM flexibility of data configuration

No external charge storage capacitor required

128 bits of OTP data factory programmed and locked § On-chip full wave rectifier

Customer specific configuration of stored data

Data output in Manchester mode

Carrier frequency 100 to 300 kHz

On-chip resonance capacitor

On-chip data modulator

On-chip high voltage protection / regulation

On-chip RF frequency clock extractor / prescaler

Low power dissipation

Data is read at the RF interface by means of the on-chip

modulator. The stored bits are clocked out sequentially

during the read operation. An internal power-on reset is

provided which allows the device to start reading out data at

low voltages for improved tag range.

DESCRIPTION

This device is manufactured in the SAMES 1.2µm N-well

EEPROM process. It has 128 bits, factory pre-programmed

and locked in EEPROM memory. Read data is Manchester

coded.

APPLICATIONS

The device has an on-chip rectification circuit that converts

the incoming rf signal to DC power feeding V . There is

Access Control

Industrial automation

Asset tracking

also an on-chip data modulator, which works in conjunction

with the rectifier. The time base is extracted by an on-chip

RF clock extractor. High voltage protection across the coil

inputs is provided internally. The energy is stored on

capacitance on chip due to low internal power consumption.

The device has an on-chip resonance capacitor connected

between the COIL1 and COIL2 pads. These features result

in a single external component count, comprised of, only the

coil.

SPEC—1124 (REV. 1)

23-05-03

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PRELIMINARY

SA7121A

PAD CONNECTIONS

TEST

VSS

TEST

VDD

COIL1

COIL2

PAD DESCRIPTION

PAD

NAME

COIL1

COIL2

V_DD

DESCRIPTION

No.

External coil connection

Supply voltage

Test Pad

TEST

V_SS

Test Pad

Ground

TEST

Test Pad

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PRELIMINARY

SA7121A

BLOCK DIAGRAM

TEST

VSS

VDD

Control Logic

Prescaler

EEPROM

TEST

Clock

Power-on

Reset

Clock Extractor

VDD

VSS

Full Wave

Rectifier

Modulator

High Voltage

Protection

Resonance Capacitor

COIL1

COIL2

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PRELIMINARY

SA7121A

ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

MIN

MAX

UNIT

NOTE

Supply Voltage

V_DD

-0.3

9.4

1,2,3,4,5

ESD protection C= 100pF R = 1.5Kohm ,

Human body model . MIL-STD-883C method

3015

Vpesd

TBD

3,8

Peak voltage across COIL1 or COIL2 to V_SS

Peak current through COIL 1,2

Storage temperature

V_COIL1,2- V_SS

I_COIL1,2

-10

-30

-55

+10

+30

^oC

3,6

3,7

Tst

+125

Note 1: Duration not to exceed 10 seconds, and no logic switching.

Note 2:

Note 3:

Referenced to Vss

Stresses above those listed under “ absolute maximum ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operating conditions section of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect the device reliability.

Note 4: VDD level when absolute maximum current goes through coil inputs.

Note 5: VDD level when absolute maximum voltage is across coil inputs.

Note 6: Maximum peak voltage at COIL1 or COIL2 of incoming RF signal with V_SSas reference. Clamping by front-end

protection circuitry.

Note 7: Maximum allowed peak current of incoming RF signal.

Note 8: TBD - To be determined.

HANDLING PROCEDURES

Although the device has built-in ESD protection, adherence to anti-static procedures for CMOS devices is required.

ELECTRICAL CHARACTERISTICS

DC Operating Conditions

Parameter

Symbol

I_DD

Min

Typ

Max

Unit

Condition

µA

Dynamic current

Static current

V_DD= 3V

V_DD= 3V, clock stopped, COIL1 &

COIL2 shorted to V_SS

I_DDS

µA

Voltage when power-on reset

comes out of reset

V_POR

V_PORH

T_DR

1.2

200

1.6

During power-up V_DD– V_SSrising

Between coming out of reset and

going back into reset

Histereses on power-on rest

Data retention

600

years programmed

At specified current at COIL1 or

COIL2,

Supply voltage

V_DD

5.5 ₁₎

+70

Operating temperature

Top

-40

^oC

Note: 1) maximum voltage is defined when forcing 10 mA on the coil inputs.

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PRELIMINARY

SA7121A

AC Operating Conditions

Clocking

Parameter

Symbol Min

Typ

125

Max

300

Unit

Condition

RF carrier frequency at COIL1,2

f_RF

kHz

Sustained RF from base station

Number of rf carrier cycles per bit N_B

Coil Inputs

Parameter

Symbol Min

Typ

Max

Unit

Condition

Negative excursion of COIL1 or

COIL2

V_CN

-0.6

-0.65

-0.7

Peak level referenced to VSS

Unmodulated COIL1 or COIL2

Modulated voltage drop

V_CM

TBD

3.3

3.0

TBD

voltage referenced to V_SS

5.5V

Unmodulated COIL1 or COIL2

V_CM

TBD

voltage referenced to V_SS

5.0V

Unmodulated COIL1 or COIL2

voltage referenced to V_SS

= 2.5 V

Modulated voltage drop

Resonance Capacitor

V_CM

TBD 0.875 TBD

Measured between COIL1 and

COIL2

C_R

170

Note: 1) for a single batch the tolerance is ±3%. From batch to batch the tolerance is ±30%.

TBD - To be determined.

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PRELIMINARY

SA7121A

FUNCTIONAL DESCRIPTION

The circuit is built up out of several functional blocks,

control logic, coil interface, the power-on reset, and the

memory module (EEPROM). The chip activates

automatically during power-up as a result of the built in

power-on reset.

locked in that way. This gives OTP (One Time

Programmable)security.

Memory map

The flexibility of programming allows custom memory

mapping.

Coil Interface

Control logic

Power is derived from a full wave rectifier bridge. Data

modulation takes place by loading the coil inputs to the

bridge with a modulating circuit. The coil interface

includes on-chip high voltage protection. The system

clock for the chip is derived by means of a clock extractor

coupled to the rectifier circuit. The Clock extractor /

prescaler is the time base generator for data reading.

Data is read from the EEPROM to the coil interface

where the rf signal is modulated by the data in the

Manchester coded m ode.

The control logic gets its clock from the clock extractor /

prescaler and facilitates the reading of the data stored in

the data EEPROM.

TIMING SPECIFICATIONS

The COIL1 and COIL2 pads modulate the incoming rf

signal with Manchester encoded data. The data will

repeatedly be read out serially until the power is reduced

sufficiently to activate the power on reset again. There

are 64 rf carrier cycles for each data bit. This is the

nominal setting. An optional setting of 32 rf cycles per bit

can be selected during wafer manufacture.

Memory Array

Data storage:

The data EEPROM is arranged in an 16X8 bit array

composed of 16 columns of 8 bit bytes. The 128 bits of

data stored in the array can be configured in any way as

agreed with the client, and is factory programmed and

n = 64 RF clock cycles per data bit

RF CLOCK

CL0

CL1

CL2

CL3

CL4

CL5

CL6

CL7

CL8

CLn-3

CLn-2

CLn-1

DATA

Dn-1

Dn+1

DATA OUTPUT

Data output takes place according to Manchester encoding.

DATA

DATA2 DATA3 DATA4

DATA 0 DATA1

DATA5 DATA6 DATA7

DATA

MANCHESTER

DATA

DATA2 DATA3 DATA4

DATA 0 DATA1

DATA5 DATA6 DATA7

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PRELIMINARY

SA7121A

TYPICAL APPLICATION

The chip powers up via the COIL1 and COIL2 pads,

deriving its energy from the rf carrier wave through the

resonating tank circuit made up by the external inductor,

L_R, and internal capacitor, C_R. An optional additional

external capacitor can be added for special requirements.

The data will automatically start modulating the rf signal

as soon as the chip has powered up to the power-on

reset level. The built in voltage protection and regulation

insures protection against high voltage from the tank

circuit.

TEST

VSS

TEST

VDD

C_R

COIL1

COIL2

L_R

The value of L_Ris determined by the following relationship.

f_R= 1 / ( 2 p Ö L_{R *}C_R)

Where f_Ris the resonance frequency.

For a typical internal C_Rof 170 pf and for f_Rat 125 kHz,

L_R= 9.54 mH

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PRELIMINARY

SA7121A

PACKAGE AND ORDERING INFORMATION

PCB FORM

1.00 mm max

4.0mm

Optional SMD

Capacitor*

Capacitor height**

1.00 mm

0.5 mm

2.66 mm

Board thickness 0.2 mm max

*Note that an optional SMD capacitor is not required normally due to internal capacitor on chip.

The device is supplied without an SMD capacitor.

**Note that the height of some SMD capacitors could exceed the height of the glob.

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PRELIMINARY

SA7121A

CHIP FORM

144

V_SS

112

857

V_DD

1564

1322

1610

1524.5

100

144

100

COIL1

144

COIL2

151.5

1820

Dimensions are in micrometers

IC Thickness is 280 micrometers ±25 micrometers

The outer dimensions of the IC is given as the distance from saw channel centre to saw

channel centre and will be smaller than indicated due to material removed during sawing

ORDERING INFORMATION

Data rate at 32 clocks per bit

In Chip form SA7121 32 IC

In PCB form SA7121 32 COB

Data rate at 64 clocks per bit

In Chip form SA7121 64 IC

In PCB form SA7121 64 COB

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PRELIMINARY

SA7121A

Disclaimer: The information contained in this document is confidential and proprietary to South African Micro-Electronic Systems (Pty) Ltd

("SAMES") and may not be copied or disclosed to a third party, in whole or in part, without the express written consent of SAMES. The

information contained herein is current as of the date of publication; however, delivery of this document shall not under any circumstances

create any implication that the information contained herein is correct as of any time subsequent to such date. SAMES does not undertake

to inform any recipient of this document of any changes in the information contained herein, and SAMES expressly reserves the right to

make changes in such information, without notification, even if such changes would render information contained herein inaccurate or

incomplete. SAMES makes no representation or warranty that any circuit designed by ref erence to the information contained herein, will

function without errors and as intended by the designer.

Any sales or technical questions may be posted to our e-mail address below:

id_security@sames.co.za

For the latest updates on datasheets, please visit our web site:

http://www.sames.co.za

SOUTH AFRICAN MICRO-ELECTRONIC

SYSTEMS (PTY) LTD

Tel: 012 333-6021

Tel: Int +27 12 333-6021

Fax: 012 333-8071

Fax: Int +27 12 333-8071

P O Box 15888, Lynn East

0039, Republic of South Africa

33 Eland Street,

Koedoespoort Industrial Area, Pretoria

Republic of South Africa

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PRELIMINARY

SA712132COB [SAMES]

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