SA9205 [SAMES]
6/3 X 8 PORT EXPANDER; 6/3 X 8端口扩展
| 型号： | SA9205 |
| 厂家： | 
SAMES |
| 描述： | 6/3 X 8 PORT EXPANDER |
| 文件： | 总14页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
sames
SA9203/5
6/3 X 8 PORT EXPANDER
FEATURES
n
n
n
Six (SA9203) or three (SA9205) 8-Bit
I/O Ports
n
n
Readback of all control and port
registers
Interfaces directly with multiplexed
addressanddatabusmicroprocessors/
microcontrollers
Each bit of one port independently
programmable as input or output
Five (SA9203) or two (SA9205)
remaining ports can be individually
configuredasinputoroutput. (Direction
applicable to all 8 pins of each port.)
n
n
n
n
n
Internal address latch
Single +5V power supply
Low power CMOS
n
n
One 8-Bit port programmable as either
atched or transparent inputs
Completely static operation
TTL-level compatibility
Supports byte-wide and bit-wide I/O
port addressing modes on all ports
FIGURE1: PINCONNECTIONFOR
SA9203
DESCRIPTION
The SAMES SA9203/5 Port Expander is a
CMOS device suited to microprocessor
based applications requiring input/output
port expansion. The device interfaces very
simply to any microcontroller/micro-
processor with amultiplexed address/data
bus structure.
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
PF
60
59
7
6
5
4
3
2
PA
10
0
1
2
3
4
5
6
PF
PF
PA
PA
PA
PA
PA
PA
11
12
58
57 PF
56 PF
55 PF
54 PF
53 PF
13
14
The SA9203 includes 8 independently
programmable I/O pins for Port A and Port
BtoF(5ports)independentlyprogrammable
as I/O. It is packaged in a PCB efficient 68
pin PLCC package. The SA9205 includes
8 independently programmable I/O pins for
Port A with Port B and Port C as indepen-
dently programmable I/O, packaged in a
cost effective 44 pin PLCC package.
15
16
17
18
19
20
21
1
0
PA
V
V
DD
7
52
SA9203
PE
DD
51
7
PB
50 PE
49 PE
0
6
5
4
3
2
PB
PB
PB
PB
PB
1
2
PE
48
22
23
PE
PE
47
46
45
3
4
5
24
25
26
PE
1
0
PB
PB
44 PE
6
7
32 33 34
35 36
37 38 39 40 41
42 43
27 28
29 30
31
D R - 0 1 2 6 6
1/14
20-08-96
4491
PDS039-SA9203/5-001
REV. A
SA9203/5
FIGURE 2: BLOCK DIAGRAM FOR SA9203
µ
DR-01267
FIGURE 3: PIN CONNECTION FOR SA9205
6
5
4
3
1
44
43
42
41
40
7
39
38
37
36
35
34
33
32
31
30
29
PC
PC
PC
PC
ALE
RD
7
8
6
5
4
3
WR
INT
9
10
11
12
13
14
15
16
17
RST
PC
V
SA9205
V
DD
DD
STB
PC
2
1
0
7
PA
0
PC
PC
PB
PB
PA
PA
PA
1
2
3
6
19
20
21
22
23
24
25
26
27
28
18
DR-01268
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SA9203/5
FIGURE 4: BLOCK DIAGRAM FOR SA9205
STB
ALE
CS
PORT
A
PA(7:0)
PB(7:0)
RD
W R
PORT
B
RST
INT
PORT
C
PC(7:0)
µ
P
Inter-
face
CON
PRTA
CON.
PRTBC
AD(7:0)
D R - 0 1 2 6 9
ABSOLUTE MAXIMUM RATINGS*
(All voltages are with respect to VSS)
Parameter
Symbol
Min
VSS
Max
7,0
Unit
V
Supply Voltage
VDD-VSS
VM
Voltage on any pin
Current at any pin
Storage Temperature
Operating Temperature
VSS-0.3
VDD+0.3
100
V
IM
mA
°C
°C
TSTG
TO
-40
0
+125
+70
* Stressesabovethoselistedunder“AbsoluteMaximumRatings”maycausepermanent
damage to the device. This is a stress rating only. Functional operation of the device
at these or any other condition above those indicated in the operational sections of this
specification, is not implied. Exposure to Absolute Maximum Ratings for extended
periods may affect device reliability.
3/14
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SA9203/5
ELECTRICAL CHARACTERISTICS
(All measurements with respect to VSS, at 25°C, unless otherwise specified)
Parameters
Symbol Min
Typ Max Unit
Condition
Supply Voltage
Static Current
VDD
IDDS
4.75
5.0 5.25
15 50
V
µA
VDD = 5.0V
(See Note1)
Dynamic Current
Input High Voltage
Input Low Voltage
Output High Voltage
IDDD
VIH
VIL
20
mA
V
VDD = 5.0V
VDD = 5.0V
VDD = 5.0V
VDD = 5.0V
IOH = 5mA
2.0
4.5
1.0
4.7
V
VOH
V
Output Low Voltage
VOL
0.25 0.5
V
VDD = 5.0V
IOH = 5mA
Input Leakage Current
IIN
<1.0 3.0
<1.0 3.0
µA
µA
VDD = 5.0V
VDD = 5.0V
Tristate Leakage Current
ITL
Note 1:
All inputs tied to VDD or VSS with outputs not loaded.
Measurements made after RST applied.
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SA9203/5
PIN DESCRIPTION for SA9203
Pin
Type Designation
Description
18,52
1,35
VDD
VSS
+5V Supply Input
0V ground Reference
61..68 I/O AD0..AD7
3-state address/data lines that interface with the CPU
lower 8-bit address/data bus. The 8-bit address is
latched into the SA9203 internal address latch on the
falling edge of ALE. The 8-bit data is respectively
written into and read out of the SA9203 on WR and RD
signals.
2
3
4
N/C
CS
Not connected.
I
I
Active low input signal used to select the device.
ALE
This control signal latches the address on the AD0..7
lines on the falling edge of ALE.
5
6
I
I
RD
Input low on this line enables the data bus buffers.
WR
Input low on this line causes the data on the address/
data bus to be written to the I/O ports and, control
registers.
7
O
INT
If enabled via A.6, this output will be set (active edge
polarity programmed by D6 and output polarity
programmed via D7 of the Port B-F direction control
register) after data has been latched into PORT A.
8
9
I
I
RST
STB
Input low on this line resets the chip and all internal
registers and all ports to input mode (The register
contents after a reset pulse will be described later).
Input data on PORT A pins will be latched when STB is
activeandtransparentotherwise(polarityprogrammed
by D5 of the Port B-F direction control register)
10..17 I/O PA0..PA7
19..26 I/O PB0..PB7
8 general purpose I/O pins comprising PORT A. This
port supports individual input or latched output
configuration of each pin. In addition,each pin of PORT
A selected as an input can be programmed to be
latched or transparent.
8 general purpose I/O pins comprising PORT B. All 8
pins are programmed to be either latched outputs or
transparent inputs.
27..34 I/O PC0..PC7
36..43 I/O PD0..PD7
44..51 I/O PE0..PE7
53..60 I/O PF0..PF7
Identical to PORT B
Identical to PORT B
Identical to PORT B
Identical to PORT B
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SA9203/5
PIN DESCRIPTION for SA9205
Pin
2,35
Type Designation Description
VDD
VSS
+5V Supply Input
1,23
0V ground Reference
40..44
I/O
AD0..AD7
3-state address/data lines that interface with the CPU
lower 8-bit address/data bus. The 8-bit address is
latched into the SA9203 internal address latch on the
falling edge of ALE. The 8-bit data is respectively
written into and read out of the SA9203 on WR and RD
signals.
5
6
7
N/C
CS
Not connected.
I
I
Active low input signal used to select the device.
ALE
This control signal latches the address on the AD0..7
lines on the falling edge of ALE.
8
9
I
I
RD
Input low on this line enables the data bus buffers.
WR
Input low on this line causes the data on the address/
data bus to be written to the I/O ports and, control
registers.
10
O
INT
If enabled via A.6, this output will be set (active edge
polarity programmed by D6 and output polarity
programmed via D7 of the Port B-F direction control
register) after data has been latched into PORT A.
11
13
I
I
RST
STB
Input low on this line resets the chip and all internal
registers and all ports to input mode (The register
contents after a reset pulse will be described later).
Input data on PORT A pins will be latched when STB is
activeandtransparentotherwise(polarityprogrammed
by D5 of the Port B-F direction control register)
14..21
I/O
PA0..PA7
8 general purpose I/O pins comprising PORT A. This
port supports individual input or latched output
configuration of each pin . In addition,each pin of
PORT A selected as an input can be programmed to be
latched or transparent.
22,
I/O
I/O
PB0..PB7
PC0..PC7
8 general purpose I/O pins comprising PORT B. All 8
24.30
pins are programmed to be either latched outputs or
transparent inputs.
31..39
Identical to PORT B
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SA9203/5
FUNCTIONAL DESCRIPTION
The SA9203 contains the following:
•
•
Six8-bitgeneralpurposeI/Oportsprogrammabletobeeitherbyteorbitaddressable.
Two controlregistersforconfiguringthe device. Thesecontrolregisterscanberead
back.
•
•
An internal address latch for accessing a multiplexed CPU address/data bus.
The SA9203 appears to the CPU as a peripheral device occupying 256 bytes of
memory space. Certain locations in the memory map are occupied by the six I/O
ports and two control registers.
The SA9203 supports two basic I/O port addressing modes, via; byte-addressing and
bit-addressing. Any of the six I/O ports can be configured as byte-addressable /or bit-
addressable. In bit-addressing, individual bits of any I/O port can be addressed
independently. In a bit- addressing CPU read operation, D0 contains valid data while
D1..D7 should be ignored. In a bit-addressing CPU write operation, D0 will be written
to the addressed output pin while D1..D7 will be ignored. The Address Memory map
is shown in Figure 5. The bit-addressing mode applies to both the I/O ports and the
control registers. The SA9205 is a three port device with operation is identical to the
SA9203.
FIGURE 5: Address Memory Map
W
W
W
W
W
W
W
W
A7 A6 A5 A4 A3 A2 A1 A0
BM EI CR2 CR1 CR0 BM2 MB1 BM0
Bit mode address 0
Bit mode address 1
Bit mode address 2
Control register address 0
Control register address 1
Control register address 2
0: Interupt function disabled
1: Interupt function enabled
0: Bit mode addressing enabled
1: Byte mode addressing enabled
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SA9203/5
FIGURE 6: PORT A Direction Control Register Address.
A5
1
A4
1
A3
0
FIGURE 7: PORT B..F Direction Control Register / Strobe Control Register
Address
A5
1
A4
1
A3
1
FIGURE 8: PORT Addresses
A5
0
0
0
0
A4
0
0
1
1
A3
0
1
0
1
PORT
PORT A
PORT B
PORT C
PORT D *
PORT E *
PORT F *
1
1
0
0
0
1
* - n/a for the SA9205
FIGURE 9: Port Pin Addresses (Bit Mode Only).
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
PORT PIN
PORT A-F.0
PORT A-F.1
PORT A-F.2
PORT A-F.3
PORT A-F.4
PORT A-F.5
PORT A-F.6
PORT A-F.7
Note : PORT A-C for SA9205
CONTROL REGISTERS
FIGURE 10: PORT A Direction Control Register
R/W
D7
R/W
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
PA.7
PA.6
PA.5
PA.4
PA.3
PA.2
PA.1
PA.0
D = 1 Port A Pin configured as output
D = 0 Port A Pin configured as input.
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SA9203/5
FIGURE 11: PORT B-F Direction Control / Strobe Control Register Address
R/W R/W R/W R/W R/W R/W R/W R/W
D7 D6 D5 D4 D3 D2 D1 D0
IP
IE
SP DF* DE* DD* DC DB
0: PORT B Configured as input
1: PORT B Configured as output
0: PORT C Configured as input
1: PORT C Configured as output
0: PORT D Configured as input
1: PORT D Configured as output
0: PORT E Configured as input
1: PORT E Configured as output
0: PORT F Configured as input
1: PORT F Configured as output
0: PORT A data latched when
STB low and transparent when
STB high.
1 - Port A data latched when
STB high and transparent when
STB low.
0 - Interupt output (INT) set on
the rising edge of STB.
1 - Interupt output (INT) set on
the falling edge of STB.
0: Interupt output active High
1: Interupt output active low
* n/a for the SA9205
sames
9/14
SA9203/5
INT
This active high output (default after reset) operates as follows:
When disabled (via A6), INT remains reset. On either the rising or trailing edge of STB
(programmable via D6 of Port B-F direction control register), INT is set. INT remains
set until Port A (or any bit of PORT A if in bit- addressing mode) is read by the
microprocessor at which point INT is reset, remaining so until the next active edge of
STB. (See figure 14 for timing diagram). The output polarity of INT is programmed via
D7 of the Port B- F dirction control register (See Figure 11).
RST
This active low reset signal resets the contents of all registers to zero. Sets all ports to
input mode and the bi-directional data/address bus to input. A valid RST signal is
specified as an active low pulse of 100ns minimum duration.
CS
The active low CS signal is internally latched by the trailing edge of ALE.
TIMING DIAGRAMS
FIGURE 12: µP Read Waveforms
CS
t
AD
AD -8/A
0
ADDRESS
t
DATA VALID
8
t
AL
LA
ALE
t
t
RDF
RDE
t
LL
t
RD
RD
t
LC
t
CL
t
CC
t
RV
t
LD
DR-01270
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SA9203/5
FIGURE 13: µP Write Waveforms
CS
AD -8/A
0
ADDRESS
t
DATA VALID
8
t
t
DW
CL
t
AL
LA
ALE
t
WD
t
t
LC
LL
t
RV
t
CLL
WR
t
t
WT
CC
DR-01271
FIGURE 14: µP Strobe/Interrupt Waveforms
STB
OR*
STB
t
t
SS
SI
INT
or
INT
t
RDI
t
t
PSS
PHS
INPUT
DATA
FROM
PORTA
* DEPENDENT ON SP
# DEPENDENT ON IP
DR-01272
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SA9203/5
FIGURE 15: I/O Port Waveforms Transparent Output
t
RP
RD
t
PR
INPUT
DATA BUS *
X
DATA VALID
FIGURE 16: µP Read Waveforms Latched Output
WR
t
WP
DATA BUS *
DATA VALID
X
X
OUTPUT
DR-01274
Table 1: AC Characteristics for µP Interface1 - TA = 0°C to 70°C, VDD = 5V 10%
Symbol Parameter
Min
10
10
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAL
tLA
tLC
tRD
tLD
Address to Latch Setup Time
Address Hold Time after Latch
Latch to READ/WRITE Control
Valid Data Out Delay from READ Control
Latch to Data Out Valid
10
50
50
100
tAD
tLL
Address Stable to Data Out Valid
Latch Enable Width
30
0
tRDF
tCL
Data Bus Float after READ
40
READ/WRITE Control to Latch Enable
WRITE Control to Latch Enable
READ/WRITE Control Width
Data in to WRITE Setup Time
Data in Hold Time after WRITE
Recovery Time between READ/WRITE
Data Bus Enable from READ Control
10
50
60
20
20
50
10
tCLL
tCC
tDW
tWD
tRV
tRDE
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SA9203/5
Table 2: A.C. Characteristics for I/O Ports
Symbol Parameter
Min
20
Max
Units
ns
tPR
tRP
Port Input Setup Time
Port Input Hold Time
Strobe Width
0
ns
tSS
tSI
100
ns
Strobe to INT Set
100
100
ns
tRD
tPSS
tPHS
tWP
READ to INT Reset
Port Setup Time to Strobe
Port Hold Time After Strobe
WRITE to Port Output
ns
50
ns
120
ns
80
ns
Note 1: Timing parameters are preliminary and subject to change.
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SA9203/5
Disclaimer:
TheinformationcontainedinthisdocumentisconfidentialandproprietarytoSouthAfricanMicro-
Electronic Systems (Pty) Ltd ("SAMES) and may not be copied or disclosed to a third party, in whole or in part,
without the express written consent of SAMES. The information contained herein is current as of the date of
publication; however,deliveryofthisdocumentshallnotunderanycircumstancescreateanyimplicationthat the
information contained herein is correct as of any time subsequent to such date. SAMES does not undertake to
informanyrecipientofthisdocumentofanychangesintheinformationcontainedherein, andSAMESexpressly
reserves the right to make changes in such information, without notification,even if such changes would render
information contained herein inaccurate or incomplete. SAMES makes no representation or warranty that any
circuit designed by reference to the information contained herein, will function without errors and as intended by
thedesigner.
South African Micro-Electronic Systems (Pty) Ltd
P O Box 15888,
Lynn East,
0039
33 Eland Street,
Koedoespoort Industrial Area,
Pretoria,
Republic of South Africa,
Republic of South Africa
Tel:
Fax:
012 333-6021
012 333-8071
Tel:
Fax:
Int +27 12 333-6021
Int +27 12 333-8071
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