K1C6416B8D-FI700 [SAMSUNG]
Memory IC, 4MX16, CMOS, PBGA54;
| 型号： | K1C6416B8D-FI700 |
| 厂家： | 
SAMSUNG |
| 描述： | Memory IC, 4MX16, CMOS, PBGA54 |
| 文件： | 总47页 (文件大小：1168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K1C6416B8D
UtRAM2
64Mb (4M x 16 bit) Multiplexed UtRAM2
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND
IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS
OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN
SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUAR-
ANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or defense
application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Revision 3.0
Sep 2007
- 1 -
K1C6416B8D
UtRAM2
Document Title
4Mx16 bit Multiplexed Synchronous Burst Uni-Transistor Random Access Memory 2
Revision History
RevisionNo.
History
Draft Date
Dec. 14, 2006
Dec. 12, 2006
Jan. 11, 2007
Remark
Preliminary
Final
Initial
0.0
1.0
2.0
- Design Target
Finalized
- updated DC value
Finalized
Final
- corrected errata (package dimension)
Revised
Sep. 18, 2007
Final
3.0
- inserted the sentence, (p.18)
"A refresh opportunity must be provided every tCSM. A refresh
opportunity is satisfied by the condition that CS HIGH for longer
than 15ns. CS must not remain LOW longer than tCSM."
Revision 3.0
Sep 2007
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K1C6416B8D
UtRAM
Table of Contents
GENERAL DESCRIPTION...............................................................................................................................1
FEATURES ......................................................................................................................................................1
PRODUCT FAMILY..........................................................................................................................................1
PIN DESCRIPTIONS & FUNCTION BLOCK DIAGRAM..................................................................................2
BALL DESCRIPTIONS.....................................................................................................................................2
POWER UP SEQUENCE.................................................................................................................................3
ABSOLUTE MAXIMUM RATINGS...................................................................................................................4
RECOMMENDED DC OPERATING CONDITIONS.........................................................................................4
CAPACITANCE................................................................................................................................................4
DC AND OPERATING CHARACTERISTICS...................................................................................................4
CRE (CONTROL REGISTER ENABLE) ..........................................................................................................5
Bus Configuration Register.........................................................................................................................5
Refresh Configuration Register ..................................................................................................................5
Burst Length (BCR[2:0]) Default = Continuous Burst .................................................................................6
Burst Wrap (BCR[3]) Default = No Wrap ....................................................................................................6
Drive Strength (BCR[5:4]) Default = 1/2 Drive Strength .............................................................................6
WAIT Configuration (BCR[8]) Default = 1 CLK Prior. .................................................................................7
WAIT Polarity (BCR[10]) Default = Active HIGH.........................................................................................7
Operating Mode (BCR[15]) Default = Asynchronous Operation.................................................................7
Latency Counter (BCR[13:11]) Default = 3 Clock Latency .........................................................................7
Initial Access Latency (BRC[14]) Default = Variable...................................................................................7
Partial Array Refresh (RCR[2:0] Default = Full Array Refresh....................................................................9
Deep Power-Down (RCR[4]) Default = DPD Disabled ...............................................................................9
Device Identification Register .....................................................................................................................9
Software Access.........................................................................................................................................12
BUS OPERATING MODES..............................................................................................................................13
Asynchronous Mode (default mode)...........................................................................................................13
Functional Description (Asynch. mode)......................................................................................................13
Burst Mode Operation.................................................................................................................................14
Functional Description (Synch. mode)........................................................................................................15
Mixed-Mode Operation ...............................................................................................................................16
Burst Suspend ............................................................................................................................................16
Boundary Crossing .....................................................................................................................................16
WAIT Operation..........................................................................................................................................16
LB / UB Operation.......................................................................................................................................16
LOW-POWER OPERATION ............................................................................................................................17
Temperature Compensated Self Refresh...................................................................................................17
Partial Array Refresh ..................................................................................................................................17
Deep Power-Down Operation.....................................................................................................................17
AC Input/Output Reference Waveform & AC Output Load Circuit..............................................................18
TIMING REQUIREMENTS...............................................................................................................................18
Asynchronous READ Cycle Timing Requirements.....................................................................................18
Asynchronous WRITE Cycle Timing Requirements ...................................................................................18
Burst READ Cycle Timing Requirements ...................................................................................................19
Burst WRITE Cycle Timing Requirements..................................................................................................19
TIMING DIAGRAMS.........................................................................................................................................20
Asynchronous READ (CS controlled).........................................................................................................20
Asynchronous READ (OE controlled).........................................................................................................21
Asynchronous READ Followed by Asynchronous WRITE (CS Controlled)................................................22
Asynchronous READ Followed by Asynchronous WRITE (OE, WE Controlled)........................................23
Asynchronous READ Followed by WRITE at the Same Address...............................................................24
Single-Access Burst READ Operation—Variable Latency .........................................................................25
4-Word Burst READ Operation—Variable Latency ....................................................................................26
Single-Access Burst READ Operation—Fixed Latency..............................................................................27
4-Word Burst READ Operation—Fixed Latency.........................................................................................28
4-Word Burst READ Operation - Row Boundary Crossing.........................................................................29
READ Burst Suspend .................................................................................................................................30
Revision 3.0
Sep 2007
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K1C6416B8D
UtRAM
Table of Contents
Asynchronous WRITE (CS Controlled).......................................................................................................31
Asynchronous WRITE (WE, UB/LB Controlled) ........................................................................................32
Asynchronous WRITE Followed by Asynchronous READ (CS Controlled)...............................................33
Asynchronous WRITE Followed by Asynchronous READ (OE, WE Controlled).......................................34
Burst WRITE Operation—Variable Latency Mode......................................................................................35
Burst WRITE Operation—Fixed Latency Mode..........................................................................................36
4-Word Burst WRITE Operation - Row Boundary Crossing .......................................................................37
Burst WRITE Followed by Burst READ, Variable Latency .........................................................................38
Burst WRITE Followed by Burst READ, Fixed Latency..............................................................................39
Asynchronous WRITE Followed by Burst READ........................................................................................40
Asynchronous WRITE Followed by Asynchronous READ .........................................................................41
Asynchronous READ Followed by WRITE at the Same Address...............................................................42
PACKAGE DIMENSION...................................................................................................................................43
54 BALL FINE PITCH BGA(0.75mm ball pitch)..........................................................................................43
Revision 3.0
Sep 2007
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K1C6416B8D
UtRAM2
GENERAL DESCRIPTION
SAMSUNG’s UtRAM products are designed to meet the request from the customers who want to cope with the fast growing
mobile applications that need high-speed random access memory. UtRAM is the solution for the mobile market with its low cost,
high density and high performance feature. K1C6416B8D is fabricated by SAMSUNG′s advanced CMOS technology using one
transistor memory cell. The device supports the traditional SRAM like asynchronous operation (asynchronous page read and
asynchronous write), the NOR flash like synchronous operation (synchronous burst read and asynchronous write) and the fully
synchronous operation (synchronous burst read and synchronous burst write). These operation modes are defined through the
configuration register setting. It supports the special features for the standby power saving. Those are the PAR(Partial Array
Refresh) mode, DPD(Deep Power Down) mode and internal TCSR(Temperature Compensated Self Refresh). It also supports
variable and fixed latency, driver strength settings, Burst sequence (wrap or No-wrap) options and a device ID register (DIDR).
FEATURES
• Process technology: CMOS
• Organization: 4M x 16 bit
• Power supply voltage: 1.7V~1.95V
• Three state outputs
• Supports Configuration Register Set
- CRE pin set up
- Software set up
• Supports power saving modes
- PAR (Partial Array Refresh)
- DPD (Deep Power Down)
- Internal TCSR (Temperature Compensated Self Refresh)
• Supports driver strength optimization
• Support 2 operation modes
- Asynchronous mode
- Synchronous mode
• Random access time:70ns
• Synchronous burst operation
- Max. clock frequency : 104MHz
- Fixed and Variable read latency
- 4 / 8 / 16 / 32 and Continuous burst
- Wrap / No-wrap
- Latency :3(Variable) @ 104MHz
3(Variable) @ 80MHz
2(Variable) @ 66MHz
- Burst stop
- Burst read suspend
- Burst write data masking
PRODUCT FAMILY
Current Consumption
CLK Freq.
Product Family
Operating Temp.
Vcc / Vccq
Standby
Operating
Operating Mode
(Max.)
(ISB1, Max.)
(ICC2, Max.)
Asynch. Mode
Synch. Mode
180uA < 85°C
120uA < 40°C
K1C6416B8D-I
Industrial(-40~85°C)
1.7~1.95V
104MHz
40mA
Revision 3.0
Sep 2007
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K1C6416B8D
UtRAM2
PIN DESCRIPTIONS & FUNCTION BLOCK DIAGRAM
1
2
3
4
5
6
Clk gen.
Pre-charge circuit
V
CC
CCQ
SS
A
B
C
D
LB
OE
UB
RFU
RFU
RFU
RFU
RFU
CS
CRE
V
V
Memory
Array
V
SSQ
A/DQ8
A/DQ0
Row
select
Row
Addresses
A/DQ9 A/DQ10
VssQ A/DQ11
RFU
A17
RFU
RFU
A/DQ1 A/DQ2
A16~A21
A/DQ3
A/DQ4
Vcc
Vss
I/O Circuit
Data
cont
A/DQ0~A/DQ7
Column Select
VccQ A/DQ12
A/DQ14 A/DQ13
A21
A16
E
F
Data
cont
A/DQ8~A/DQ15
Data
cont
RFU
RFU
A/DQ5 A/DQ6
Column Address
A/DQ15
A19
RFU
WE
A/DQ7
G
RFU
RFU
RFU
CLK
CS
A18
RFU
CLK
RFU
ADV
RFU
RFU
A20
H
J
ADV
OE
Control Logic
WAIT
RFU
WE
UB
LB
CRE
WAIT
Top View (Ball Down)
54-FBGA - 6.00 x 8.00
BALL DESCRIPTIONS
Symbol
A/DQ[15:0]
A[21:16]
Type
Input /
Output
Description
Address / Data I/Os: These pins are a multiplexed address/data bus. As inputs for addresses, these pins behave as
A[15:0]; These lines are also used to define the value to be loaded into the BCR or the RCR.
Input
Address Inputs for addresses during READ and WRITE operations.
Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When configured
for synchronous operation, the address is latched on the first rising CLK edge when ADV is active. CLK is static LOW
during asynchronous access READ and WRITE operations.
CLK
(note1)
Input
Address valid: Indicates that a valid address is present on the address inputs. Addresses can be latched on the rising
edge of ADV during asynchronous READ and WRITE operations. ADV can be held LOW during asynchronous READ
and WRITE operations.
ADV
(note1)
Input
Control register enable: When CRE is HIGH, WRITE operations load the RCR or BCR, and READ operations access
the RCR, BCR, or DIDR.
Chip Select: Activates the device when LOW. When CS is HIGH, the device is disabled and goes into standby or deep
power-down mode.
Output enable: Enables the output buffers when LOW. When OE is HIGH,
the output buffers are disabled.
CRE
CS
Input
Input
Input
Input
OE
Write enable: Determines if a given cycle is a WRITE cycle. If WE is LOW, the cycle is a WRITE to either a configura-
tion register or to the memory array.
WE
LB
Input
Input
Lower byte enable. DQ[7:0]
Upper byte enable. DQ[15:8]
UB
Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is gated by CS. WAIT is
used to arbitrate collisions between refresh and READ/WRITE operations. WAIT is also asserted during row boundary
crossing within the burst length. WAIT is asserted and should be ignored during asynchronous operations. WAIT is
High-Z when CS is HIGH.
WAIT
(note1)
Output
RFU
VCC
-
Reserved for Future Use
Supply
Supply
Supply
Supply
Device power supply: (1.70V–1.95V) Power supply for device core operation.
I/O power supply: (1.70V–1.95V) Power supply for input/output buffers.
VSS must be connected to ground.
VCCQ
VSS
VSSQ
VSSQ must be connected to ground.
1. When using asynchronous mode exclusively, the CLK and ADV inputs can be tied to VSS. WAIT will be asserted but should be ignored during
asynchronous mode operations.
Revision 3.0
Sep 2007
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K1C6416B8D
UtRAM2
POWER UP SEQUENCE
After VCC and VCCQ reach minimum operating voltage(1.7V), drive CS High. Then the device gets into the Power Up mode. Wait
for minimum 150µs to get into the normal operation mode. During the Power Up mode, the standby current can not be guaran-
teed. To get the appropriate device operation, be sure to keep the following power up sequence. Asynch. mode is default mode
and is set up after power up.
VCC(Min)
VCC
VCCQ(Min)
VCCQ
150us
Min. 0ns
CS
Revision 3.0
Sep 2007
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K1C6416B8D
UtRAM2
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
VIN, VOUT
VCC, VCCQ
Ratings
-0.2 to VCCQ+0.3V
-0.2 to 2.5V
Unit
V
Voltage on any pin relative to Vss
Power supply voltage relative to Vss
V
Power Dissipation
Storage temperature
Operating Temperature
PD
TSTG
TA
1.0
W
°C
°C
-65 to 150
-40 to 85
1) Stresses greater than "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to be
used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Item
Symbol
VCC
Min
1.7
Typ
1.8
1.8
0
Max
1.95
Unit
V
Power supply voltage(Core)
Power supply voltage(I/O)
Ground
VCCQ
1.7
1.95
V
VSS, VSSQ
VIH
0
0
V
VCCQ+0.22)
0.4
Input high voltage
VCCQ-0.4
-
V
-0.23)
Input low voltage
VIL
-
V
1. TA=-40 to 85°C, otherwise specified.
2. Overshoot: VCCQ +1.0V in case of pulse width ≤20ns. Overshoot is sampled, not 100% tested.
3. Undershoot: -1.0V in case of pulse width ≤20ns. Undershoot is sampled, not 100% tested.
CAPACITANCE
Item
Symbol
CIN
Test Condition
VIN=0V
Min
Max
Unit
pF
Input capacitance
Input/Output capacitance
1. Freq.=1MHz, T =25°C
2. Capacitance is sampled, not 100% tested.
-
-
8
8
CIO
VIO=0V
pF
A
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
µA
Input Leakage Current
Output Leakage Current
ILI
VIN=Vss to VCCQ
-1
-1
-
-
1
1
ILO
CS=VIH, CRE=VIL, OE=VIH or WE=VIL, VIO=VSS to VCCQ
4)
µA
Average Operating
Current (Async)
Cycle time=min tRC/min tWC, IIO=0mA , 100% duty, CS=VIL, CRE=VIL,
VIN=VIL or VIH
6)
-
-
-
-
40
40
mA
mA
ICC2
4)
Average Operating
Current (Burst)
Burst Length 4, Latency 5, 80MHz, IIO=0mA , Address transition 1 time,
ICC3
CS=VIL, CRE=VIL, VIN=VIL or VIH
Output Low Voltage
Output High Voltage
VOL
VOH
IOL=0.2mA
-
-
-
-
-
-
-
-
-
-
-
-
0.2
-
V
V
IOH=-0.2mA
1.4
< 40°C
< 85°C
-
-
-
-
-
-
-
-
-
120
180
115
110
105
165
155
145
30
µA
µA
CS and ADV=VCCQ, CRE=0V, Other inputs=0V or
VCCQ (Toggle is not allowed)
1)
Standby Current(CMOS)
ISB1
5)
1/2 Block
< 40°C
< 85°C
1/4 Block
1/8 Block
1/2 Block
1/4 Block
1/8 Block
5)
µA
CS and ADV=VCCQ, CRE=0V, Other inputs=0V or
VCCQ (Toggle is not allowed)
2)
Partial Refresh Current
ISBP
5)
µA
µA
Deep Power Down Current
ISBD
CRE=0V, CS=VCCQ, Other inputs=0V or VCCQ (Toggle is not allowed)
1. ISB1 is measured after 60ms after CS high. CLK should be fixed at high or at Low.
2. Full Array Partial Refresh Current(ISBP) is same as Standby Current(ISB1).
3. Internal TCSR (Temperature Compensated Self Refresh) is used to optimize refresh cycle below 40°C.
4. IIO=0mA; This parameter is specified with the outputs disabled to avoid external loading effects.
5. VIN=0V; all inputs should not be toggle.
6. Clock should not be inserted between ADV low and WE low during Write operation.
Revision 3.0
Sep 2007
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K1C6416B8D
UtRAM2
CRE (CONTROL REGISTER ENABLE)
The control registers store the values for the various modes to make UtRAM suitable for a various applications. The configuration
register values are written via A/DQ pins. In an asynchronous WRITE, the values are latched into the configuration register on the
rising edge of ADV, CS, or WE, whichever occurs first; LB and UB are “Don’t Care.” For reads, address inputs other than A[19:18]
are “Don’t Care,” and register bits 15:0 are output as data (ADV HIGH) on A/DQ[15:0]. Immediately after performing a configura-
tion register READ or WRITE operation, reading the memory array is highly recommended.
Bus Configuration Register
The BCR defines how the device interacts with the system memory bus. The BCR is accessed with CRE HIGH and A[19:18] =
10b, or through the register access software sequence with A/DQ = 0001h on the third cycle.
A19~A18
A/DQ15
A/DQ14
A/DQ13~A/DQ11
A/DQ10
A/DQ8
A/DQ5~A/DQ4
A/DQ3
A/DQ2~A/DQ0
RS
OM
IL
LC
WP
WC
DS
BW
BL
Register Select
Operating Mode
Initial Latency
Latency Count
A19
A18
RS
A/DQ15
OM
A/DQ14
IL
A/DQ13 A/DQ12 A/DQ11
LC
0
1
0
0
0
1
RCR
BCR
DIDR
0
1
Synch.
0
1
Variable (default)
Fixed
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
Asynch (default)
1
2
3 (default)
4
5
6
7
Wait Polarity
Wait Config.
Driver Strength
Burst Wrap
Burst Length
A/DQ10
WP
A/DQ8
WC
A/DQ5 A/DQ4
DS
A/DQ3
BW
A/DQ2 A/DQ1 A/DQ0
BL
0
Active Low
0
at data
0
0
0
1
Full Drive
0
1
Wrap
0
0
0
1
1
0
4 word
1 CLK prior
(default)
1/2 Drive
(default)
No Wrap
(default)
1
Active High (default)
1
8 word
1
1
0
1
1/4 Drive
Reserved
0
1
1
0
1
0
16 word
32 word
Continuous
(default)
1
1
1
1. A/DQ6, A/DQ7, A/DQ9, A16, A17, A20, A21 are reserved and should be ’1’
2. The registers are set automatically to default value.
3. Refresh command will be denied during continuous operation. CS low should not be longer than tBC(max. 2.5us)
Refresh Configuration Register
The refresh configuration register (RCR) defines how the device performs its self refresh. Altering the refresh parameters can
reduce current consumption during standby mode. The RCR is accessed with CRE HIGH and A[19:18] = 00b; or through the reg-
ister access software sequence with A/DQ = 0000h on the third cycle.
A19~A18
A/DQ4
A/DQ2~A/DQ0
RS
DPD
PAR
Register Select
Deep Power Down
Partial Refresh
A19
A18
RS
RCR
BCR
DIDR
A/DQ4
DPD
Enable
A/DQ2
A/DQ1
A/DQ0
PAR
0
1
0
0
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Full Array (default)
Bottom 1/2 Array
Bottom 1/4 Array
Bottom 1/8 Array
None of Array
Disable (default)
Bottom 1/2 Array
Bottom 1/4 Array
Bottom 1/8 Array
1. A/DQ3, A/DQ5~A/DQ15, A16, A17, A20, A21 are reserved and should be ’1’
2. The registers are set automatically to default value.
Revision 3.0
Sep 2007
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K1C6416B8D
UtRAM2
Burst Length (BCR[2:0]) Default = Continuous Burst
Burst lengths define the number of words the device outputs during burst READ and WRITE operations. The device supports a
burst length of 4, 8, 16, or 32 words or Continuous.
Burst Wrap (BCR[3]) Default = No Wrap
The burst-wrap option determines if a 4-, 8-, 16-, or 32-word READ or WRITE burst wraps within the burst length, or steps through
sequential addresses.
Sequence and Burst Length
4 word
Starting
Address
8 word
Burst Length
16 word
Burst Length
32 word
Burst Length
Continuous
Burst
Burst Wrap
Burst
Length
BCR[3] Wrap Decimal
Linear
Linear
Linear
Linear
Linear
0
1
2
3
~
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
~
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
~
0 - 1 - 2 ~ 29-30-31
1 - 2 - 3 ~ 30-31 - 0
2 - 3 - 4 ~ 31 - 0 - 1
3 - 4 - 5 ~ 0 - 1 - 2
~
0 - 1 - 2 - 3 - 4 - 5 ~
1 - 2 - 3 - 4 - 5 - 6 ~
2 - 3 - 4 - 5 - 6 - 7 ~
3 - 4 - 5 - 6 - 7 - 8 ~
~
7 - 8 - 9 - 10-11-12
~
7-0-1-2-3-4-5-6
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
7 - 8 - 9 ~ 4 - 5 - 6
~
7
~
WRAP
Yes
~
~
15-16-17 ~ 12- 13-
14
15-16-17-18-19-20
~
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
15
~
~
~
31-32-33-34-35-36
~
31- 0 - 1 ~ 28-29-30
31
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
0- 1- 2- 3- 4- 5- 6 -7
1- 2- 3- 4- 5- 6- 7- 8
2- 3- 4- 5- 6- 7- 8- 9
3- 4- 5- 6- 7- 8- 9-10
~
0- 1- 2- 3- 4- 5- 6- 7- 8- 9- 10- 11- 12-13-14-15
1- 2- 3- 4- 5- 6- 7- 8- 9- 10- 11- 12-13-14-15-16
2- 3- 4- 5- 6- 7- 8- 9- 10- 11- 12-13-14-15-16-17
3- 4- 5- 6- 7- 8- 9- 10- 11- 12-13-14-15-16-17-18
~
0 - 1 - 2 ~ 29-30-31
1 - 2 - 3 ~ 30-31-32
2 - 3 - 4 ~ 31-32-33
3 - 4 - 5 ~ 32-33-34
~
0 - 1 - 2 - 3 - 4 - 5 ~
1 - 2 - 3 - 4 - 5 - 6 ~
2 - 3 - 4 - 5 - 6 - 7 ~
3 - 4 - 5 - 6 - 7 - 8 ~
~
0
1
2
3
~
7 - 8 - 9 - 10-11-12
~
No
WRAP
7-8-9-10-11-12-13-14
7-8-9-10-11-12-13-14-15-16-17-18-19-20-21-22
7 - 8 - 9 ~ 36-37-38
~
7
~
No
~
~
15-16-17-18-19-20
~
15-16-17-18-19-20-21-22-23-24-25-26-27-28-29-30
15-16-17 ~ 44-45-46
15
~
~
~
31-32-33 ~ 60-61-62
31-32-33-34-35-36
~
31
Drive Strength (BCR[5:4]) Default = 1/2 Drive Strength
The optimization of output driver strength is possible to adjust for the different data loadings. The device can minimize the noise
generated on the data bus during read operation. The device supports full, 1/2 and 1/4 driver strength. The device’s default mode
is 1/2 driver strength. Outputs are configured at 1/2 drive strength during testing.
Drive Strength
Driver Strength
Impedance(typ.)
Full
1 / 2
1 / 4
25~30Ω
50Ω
100Ω
CL = 15pF to 30pF
104 MHz at light load
Recommendation
CL = 30pF to 50pF
CL = 15pF or lower
1. Impedance values are typical values, not 100% tested.
Revision 3.0
Sep 2007
- 6 -
K1C6416B8D
UtRAM2
WAIT Configuration (BCR[8]) Default = 1 CLK Prior.
The WAIT signal is output signal indicating the status of the data on the bus whether or not it is valid. WAIT configuration is to
decide the timing when WAIT asserts or desserts. WAIT asserts (or desserts) one clock prior to the data when A/DQ8 is set to 0.
(WAIT asserts (or desserts) at data clock when A/DQ8 is set to 1). WAIT polarity is to decide the WAIT signal level at which data is
valid or invalid. Data is valid if WAIT signal is high when A/DQ10 is set to 0. (Data is valid if WAIT signal is low when A/DQ10 is set
to 1). All the timing diagrams in this SPEC are illustrated based on following setup; A/DQ[10]:0 and A/DQ[8]:1.
Below timing shows WAIT signal’s movement when word boundary crossing happens in No-wrap mode
WAIT Polarity (BCR[10]) Default = Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the
WAIT signal requires a pull-up or pull-down resistor to maintain the de-asserted state.
WAIT Configuration During Burst Operation
No-Wrap. Word-line Crossing. LATENCY : 2. WP : Low Enable
0
1
2
3
4
5
6
7
8
9
10
11
12
13
CLOCK
ADV
Word-line Crossing period
(Only exists in No-wrap mode or Continuous mode)
Valid
Address
A/DQ
D254 D255
D256 D257 D258 D259
D260 D261 D262
D253
1CLK
1CLK
1CLK
WAIT
A/DQ[8]:1
de-assertion
de-assertion
assertion
WAIT
A/DQ[8]:0
de-assertion
de-assertion
assertion
Note: Non-default BCR setting: WAIT active LOW.
Operating Mode (BCR[15]) Default = Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation.
Latency Counter (BCR[13:11]) Default = 3 Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first
data value transferred. For allowable latency codes.
Initial Access Latency (BRC[14]) Default = Variable
Variable initial access latency outputs data after the number of clocks set by the latency counter. However, WAIT must be moni-
tored to detect delays caused by collisions with refresh operations. Fixed initial access latency outputs the first data at a consistent
time that allows for worst-case refresh collisions. The latency counter must be configured to match the initial latency and the clock
frequency. It is not necessary to monitor WAIT with fixed initial latency. The burst begins after the number of clock cycles config-
ured by the latency counter.
Revision 3.0
Sep 2007
- 7 -
K1C6416B8D
UtRAM2
Variable Latency Configuration Codes
Latency
Refresh Collision
Max Input CLK Frequency (MHz)
BCR[13:11]
Latency Configuration
Normal
104
80
66
010
011
2(3 clocks)
3(4 clocks)-default
Reserved
2
3
-
4
6
-
66(15ns)
104(9.62ns)
-
52(19,2ns)
80(12.5ns)
-
40(25ns)
66(15ns)
-
Others
Fixed Latency Configuration Codes
Max Input CLK Frequency (MHz)
BCR[13:11]
Latency Configuration
Latency Count (N)
104
80
66
010
011
2 (3 clocks)
3 (4 clocks)
4 (5 clocks)
5 (6 clocks)
6 (7 clocks)
Reserved
2
3
4
5
6
-
33 (30ns)
52 (19.2ns)
66 (15ns)
80 (12.5ns)
104 (9.62ns)
-
20 (50ns)
40 (25ns)
52 (19.2ns)
66 (15ns)
80 (12.5ns)
-
20 (50ns)
33 (30ns)
40 (25ns)
52 (19.2ns)
66 (15ns)
-
100
101
110
Others
1. Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on the next clock cycle.
Latency Counter (Variable Initial Latency, No Refresh Collision)
VIH
CLK
VIL
VIH
ADV
VIL
VIH
VIL
VALID
A[21:16]
ADDRESS
Code 2
VOH
VOL
VIH
VIL
Valid
Output
Valid
Output
Valid
Output
VALID
Valid
Output
Valid
Output
A/DQ[15:0]
ADDRESS
Code 3 (Default)
VIH
VIL
VOH
VOL
VALID
Valid
Valid
Output
Valid
Output
Valid
Output
A/DQ[15:0]
A/DQ[15:0]
ADDRESS
Output
Code 4
VOH
VOL
VIH
VIL
VALID
ADDRESS
Valid
Output
Valid
Output
Valid
Output
Undefined
Don’t Care
Latency Counter (Fixed Latency)
N-1
N Cycle
Cycles
VIH
CLK
VIL
tAADV
VIH
ADV
VIL
VIH
VALID
ADDRESS
A[21:16]
VIL
VIH
tCO
CS
VIL
tACLK
tAA
VALID
VIH
VIL
A/DQ[15:0]
(READ)
VOH
VOL
Valid
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Output
ADDRESS
tSP
tHD
VIH
VIL
VALID
ADDRESS
Valid
Input
A/DQ[15:0]
(WRITE)
Valid
Input
Valid
Input
Valid
Input
Valid
Input
Burst Identified
(ADV = LOW)
Undefined
Don’t Care
Revision 3.0
Sep 2007
- 8 -
K1C6416B8D
UtRAM2
Partial Array Refresh (RCR[2:0] Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby cur-
rent by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array,
one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the
end of the address map.
Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
Active Section
Address Space
Size
Density
0
0
0
Full Die
000000h-3FFFFFh
4 Meg x 16
64Mb
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
One-half die
One-quarter of die
One-eighth of die
None of die
000000h-1FFFFFh
000000h-0FFFFFh
000000h-07FFFFh
0
2 Meg x 16
1 Meg x 16
512K x 16
0 Meg x 16
2 Meg x 16
1 Meg x 16
512K x 16
32Mb
16Mb
8Mb
0Mb
One-half of die
One-quarter of die
One-eighth of die
200000h-3FFFFFh
300000h-3FFFFFh
380000h-3FFFFFh
32Mb
16Mb
8Mb
Deep Power-Down (RCR[4]) Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not require the
storage provided by this memory. Any stored data will become corrupted when DPD is enabled. When refresh activity has been
re-enabled, the device will require 150µs to perform an initialization procedure before normal operations can resume. Deep
power-down is enabled by setting RCR[4] = 0 and taking CS HIGH. DPD can be enabled using CRE or the software sequence to
access the RCR. Taking CS LOW for at least 10µs disables DPD and sets RCR[4] = 1. it is not necessary to write to the RCR to
disable DPD. BCR and RCR values (other than BCR[4]) are preserved during DPD.
DPD Entry and Exit Timing Parameters & Initialization and DPD Timing Parameters
Symbol
tDPD
Min
10
Max
Unit
µs
tDPD
tDPDX
tPU
CS
Write
RCR[4] = 0
tDPDX
tPU
10
µs
DPD Enabled
DPD EXIT
Device Initialization
150
µs
Device Identification Register
The DIDR provides information on the device manufacturer, generation and the specific device configuration. This register is read-
only. The DIDR is accessed with CRE HIGH and A[19:18] = 01b, or through the register access software sequence with A/DQ =
0002h on the third cycle.
Device Identification Register Mapping
Bit Field
DIDR[15]
DIDR[14:11]
DIDR[10:8])
DIDR[7:5]
DIDR[4:0]
Field name
Row Length
Device version
Device density
UtRAM generation
Vendor ID
Bit
Setting
Bit
Setting
Bit
Setting
Bit
Setting
Bit
Setting
Length
Version
5th
Density
64Mb
Generation
UtRAM2
Options
256 words
1b
100b
010b
010b
01100b
Revision 3.0
Sep 2007
- 9 -
K1C6416B8D
UtRAM2
Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation
CRE
tAVH
tAVS
tVP
ADV
A[21:16]
OPCODE
ADDRESS
ADDRESS
(Except A[19:18])
Select Control Register
A[19:18]
tCPH
Initiate control register access
CS
OE
WE
tCW
tWP
Write address bus value to control register
LB/UB
tAVS
OPCODE
Data
Valid
ADDRESS
A/DQ[15:0]
Don’t Care
1. A[19:18] = 00b to load RCR, and 10b to load BCR.
Configuration Register WRITE, Synchronous Mode Followed by READ ARRAY Operation
0
1
2
3
4
5
6
7
CLK
tSP
tSP
tHD
tHD
CRE
ADV
A[21:16]
(Except A[19:18])
ADDRESS
ADDRESS
A[19:18]
OPCODE
tCSP
tHD
tCPH
CS
OE
tHD
tSP
WE
LB/UB
tCSW
tSP
WAIT
High-Z
tHD
Latch Control Register Address
OPCODE
ADDRESS
Data
Valid
A/DQ[15:0]
Don’t Care
1. Non-default BCR settings for synchronous mode configuration register WRITE followed by READ ARRAY operation: Latency code two (three
clocks); WAIT active LOW; WAIT asserted during delay.
2. A[19:18] = 00b to load RCR, and 10b to load BCR.
3. CS must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—additional WAIT cycles caused by refresh collisions
require a corresponding number of additional CS LOW cycles.
Revision 3.0
Sep 2007
- 10 -
K1C6416B8D
UtRAM2
Register READ, Asynchronous Mode Followed by READ ARRAY Operation
CRE
ADV
tAVS
tAA
tVP
tAAVD
tLZ
tAVH
tAVS
A[21:16]
(Except A[19:18])
Address
Address
tAA
Select Control Register
A[19:18]
tCPH
tHZ
tCO
CS
OE
Initiate Register Access
tOE
tOHZ
WE
tOLZ
LB/UB
DATA
VALID
A/DQ[15:0]
CR Valid
Address
Don’t Care
Undefined
1. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.
Register READ, Synchronous Mode Followed by READ ARRAY Operation
CLK
tSP
tHD
CRE
ADV
tSP
tSP
tHD
tHD
A[21:16]
(Except A[19:18])
ADDRESS
ADDRESS
ADDRESS
tCSP
A[19:18]
ADDRESS
tCBPH3
tABA
CS
OE
tHZ
tOHZ
tBOE
LB/UB
WAIT
tOLZ
tACLK
tKW
tHD
High-Z
High-Z
tSP
CR
Valid
DATA
VALID
ADDRESS
ADDRESS
A/DQ[15:0]
tKOH
Latch Control Register Address
Undefined
Don’t Care
1. Non-default BCR settings for synchronous mode register READ followed by READ ARRAY operation: Latency code two (three clocks);
WAIT active LOW; WAIT asserted during delay.
2. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.
3. CS must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—additional WAIT cycles caused by refresh collisions
require a corresponding number of additional CS LOW cycles.
Revision 3.0
Sep 2007
- 11 -
K1C6416B8D
UtRAM2
Software Access
Software access of the registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of
the configuration registers can be modified and all registers can be read using the software sequence. The configuration registers
are loaded using a four-step sequence consisting of two asynchronous READ operations followed by two asynchronous WRITE
operations. The read sequence is virtually identical except that an asynchronous READ is performed during the fourth operation.
The address used during all READ and WRITE operations is the highest address of the device being accessed (3FFFFF); the
contents of this address are not changed by using this sequence. The data value presented during the third operation (WRITE) in
the sequence defines whether the BCR, RCR, or the DIDR is to be accessed. If the data is 0000h, the sequence will access the
RCR; if the data is 0001h, the sequence will access the BCR; if the data is 0002h, the sequence will access the DIDR. During the
fourth operation, A/DQ[15:0] transfer data in to or out of bits 15–0 of the registers. The use of the software sequence does not
affect the ability to perform the standard (CRE-controlled) method of loading the configuration registers. However, the software
nature of this access mechanism eliminates the need for CRE. If the software mechanism is used, CRE can simply be tied to VSS.
The port line often used for CRE control purposes is no longer required.
Load Configuration Register
READ
READ
WRITE
WRITE
CS
OE
WE
LB/UB
ADV
CR VALID
IN
ADDRESS
(max)
ADDRESS
(max)
ADDRESS
(max)
ADDRESS
(max)
A/DQ[15:0]
XXXX
XXXX
RCR: 0000h
BCR: 0001h
Don’t Care
Read Configuration Register
CS
READ
READ
WRITE
READ
OE
WE
LB/UB
ADV
CR VALID
OUT
ADDRESS
(max)
ADDRESS
(max)
ADDRESS
(max)
ADDRESS
(max)
XXXX
XXXX
A/DQ[15:0]
RCR: 0000h
BCR: 0001h
Don’t Care
DIDR: 0002h
Revision 3.0
Sep 2007
- 12 -
K1C6416B8D
UtRAM2
BUS OPERATING MODES
The bus interface supports asynchronous and burst mode read and write transfers. The specific interface supported is defined by
the value loaded into the BCR.
Asynchronous Mode (default mode)
Asynchronous read operation
Asynchronous read operation starts when CS, OE and UB or LB are asserted. ADV can be taken HIGH to capture the address.
First data will be driven out of the A/DQ bus after random access time(tAA). WE should be de-asserted during read operation. The
CLK input must be held static LOW during read operation. WAIT will be driven while the device is enabled and its state should be
ignored.
Asynchronous write operation
Asynchronous write operation starts when CS, WE and UB or LB are asserted. The data to be written is latched on the rising edge
of CS, WE, or LB/UB (whichever occurs first). OE is High during write operation. WE LOW time must be limited to tCSM. The CLK
input must be held static LOW during write operation. WAIT signal is Hi-Z.
READ Operation (WE = HIGH).
WRITE Operation(OE = HIGH)
CS
CS
A[21:16]
ADV
Address
A[21:16]
ADV
Address
< tCSM
WE
OE
LB/UB
LB/UB
High-Z
A/DQ[15:0]
A/DQ[15:0]
Address
DATA
Don’t Care
Address
DATA
Undefined
Functional Description (Asynch. mode)
Asynchfonous Mode
UB /
LB
Power
Active
Active
CLK
ADV
CS
L
OE
L
WE
CRE
WAIT
Low-Z
High-Z
A/DQ[15:0] Notes
BCR[15] = 1
Read
L
L
H
L
L
L
L
Data out
Data in
1
1
Write
L
H
L
Standby
Standby
Idle
L
L
H
X
H
L
X
X
X
L
L
X
X
High-Z
Low-Z
High-Z
X
2
1
No operation
X
L
Configuration register
write
Active
Active
L
L
L
L
L
L
H
L
H
H
X
X
L
High-Z
Low-Z
High-Z
High-Z
Configuration register
read
Config.
Reg.out
H
X
Deep Power-
down
DPD
X
H
X
X
High-Z
1. The device will consume active power in this mode whenever addresses are changed.
2. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.
Revision 3.0
Sep 2007
- 13 -
K1C6416B8D
UtRAM2
Burst Mode Operation
Synchronous Burst Read Operation
Burst Read command is implemented when ADV is detected low at clock rising edge. WE should be de-asserted. Burst operation
re-starts whenever ADV is detected low at clock rising edge even in the middle of operation.
Synchronous Burst Write Operation
Burst Write command is implemented when ADV & WE are detected low at clock rising edge. Burst Write operation re-starts
whenever ADV is detected low at clock rising edge even in the middle of Burst Write operation.
Burst Mode READ (4-word burst)
CLK
CS
ADV
Latency Code 3 (4 clocks)
ADD.
ADD.
A[21:16]
VALID
VALID
OE
WE
WAIT
LB/UB
ADD.
ADD.
D[0] D[1] D[2]
D[3]
A/DQ[15:0]
VALID
VALID
READ Burst Identified
(WE = HIGH)
Undefined
Don’t Care
1. Non-default BCR settings for burst mode READ (4-word burst): Fixed or variable latency;
2. Latency code 3 (4 clocks); WAIT active LOW; WAIT asserted during delay.
3. Diagram in the figure above is representative of variable latency with no refresh collision or fixed-latency access.
Burst Mode WRITE (4-word burst)
CLK
CS
ADV
Latency Code 3 (4 clocks)
ADD.
ADD.
A[21:16]
WE
VALID
VALID
WAIT
LB/UB
ADD.
ADD.
A/DQ[15:0]
D[0] D[1] D[2] D[3]
VALID
VALID
Don’t Care
WRITE Burst Identified
(WE = LOW)
1. Non-default BCR settings for burst mode WRITE (4-word burst): Fixed or variable latency;
2. Latency code 3 (4 clocks); WAIT active LOW; WAIT asserted during delay.
Revision 3.0
Sep 2007
- 14 -
K1C6416B8D
UtRAM2
The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of four, eight,
sixteen, or thirty-two words. The initial latency for READ operations can be configured as fixed or variable (WRITE operations
always use fixed latency). Variable latency allows minimum latency at high clock frequencies, but the controller must monitor
WAIT to detect any conflict with refresh cycles. Fixed latency outputs the first data word after the worst-case access delay, includ-
ing allowance for refresh collisions. The initial latency time and clock speed determine the latency count setting. Fixed latency is
used when the controller cannot monitor WAIT. Fixed latency also provides improved performance at lower clock frequencies.
Refresh Collision During Variable-Latency READ Operation
VIH
CLK
VIL
VIH
Address
Valid
A[21:16]
VIL
VIH
ADV
VIL
VIH
CS
VIL
VIH
OE
VIL
VIH
WE
VIL
VIH
LB/UB
VIL
VOH
VOL
VIH
VIL
High-Z
WAIT
VOH
VOL
Address
Valid
D[3]
D[0]
D[1]
D[2]
A/DQ[15:0]
Undefined
Don’t Care
Additional WAIT states inserted to allow refresh completion.
1. Non-default BCR settings for refresh collision during variable-latency READ operation:
2. Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Functional Description (Synch. mode)
Burst Mode
BCR[15] = 0
UB /
LB
Power
Active
Active
CLK
ADV
CS
L
OE
L
WE
H
CRE
WAIT
A/DQ[15:0] Notes
Async read
L
L
L
L
L
L
Low-Z
High-Z
Data out
Data in
3
3
Async write
L
H
L
Standby
Standby
Idle
L
L
H
X
H
L
X
X
X
X
L
L
X
X
High-Z
Low-Z
High-Z
X
4
4
No operation
Initial burst read
Initial burst write
Active
Active
L
L
L
L
X
H
H
L
L
L
L
Low-Z
Low-Z
Address
Address
X
Data in or
Data out
Burst continue
Burst suspend
Active
Active
Active
H
X
L
L
L
L
X
H
H
X
X
L
X
X
H
L
X
X
Low-Z
Low-Z
Low-Z
3
3
X
L
High-Z
High-Z
Configuration register
write
Configuration register
read
Config.
reg.out
Active
L
L
L
H
X
H
X
L
Low-Z
High-Z
Deep power-
down
DPD
X
H
X
X
High-Z
1. CLK must be LOW during async read and async write modes.
2. When LB and UB are in select mode (LOW), A/DQ[15:0] are affected. When only LB is in select mode, A/DQ[7:0] are affected. When only UB is in
the select mode, A/DQ[15:8] are affected.
3. The device will consume active power in this mode whenever addresses are changed.
4. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.
Revision 3.0
Sep 2007
- 15 -
K1C6416B8D
UtRAM2
Mixed-Mode Operation
The device supports a combination of synchronous READ and asynchronous WRITE operations when the BCR is configured for
synchronous operation. The asynchronous WRITE operations require that the clock (CLK) remain LOW during the entire
sequence. The ADV signal can be used to latch the target address, CS can remain LOW when transitioning between mixed-mode
operations with fixed latency enabled; however, the CS LOW time must not exceed tCSM. Mixed-mode operation facilitates a
seamless interface to legacy burst mode Flash memory controllers.
Burst Suspend
To access other devices on the same bus without the timing penalty of the initial latency for a new burst, burst mode can be sus-
pended. Bursts are suspended by stopping CLK. CLK can be stopped HIGH or LOW. If another device will use the data bus while
the burst is suspended, OE should be taken HIGH to disable the outputs. otherwise, OE can remain LOW. Note that the WAIT out-
put will continue to be active, and as a result no other devices should directly share the WAIT connection to the controller. To con-
tinue the burst sequence, OE is taken LOW, then CLK is restarted after valid data is available on the bus. The CS LOW time is
limited by refresh considerations. CS must not stay LOW longer than tCSM. If a burst suspension will cause CS to remain LOW for
longer than tCSM, CS should be taken HIGH and the burst restarted with a new CS LOW/ADV LOW cycle.
Boundary Crossing
Continuous bursts or No wrap burst have the ability to start at a specified address and burst to the end of the address. It goes back
to the first address and continues the burst operation. WAIT will be asserted at the boundary of the row and be desserted after
crossing boundary of the row.
WAIT Operation
The WAIT output is typically connected to a shared systemlevel WAIT signal. The shared WAIT signal is used by the processor to
coordinate transactions with multiple memories on the synchronous bus. Once a READ or WRITE operation has been initiated,
WAIT goes active to indicate that additional time is required before data can be transferred. For READ operations, WAIT will
remain active until valid data is output from the device. For WRITE operations, WAIT will indicate to the memory controller when
data will be accepted into this device. When WAIT transitions to an inactive state, the data burst will progress on successive clock
edges. CS must remain asserted during WAIT cycles (WAIT asserted and WAIT configuration BCR[8] = 1). Bringing CS HIGH dur-
ing WAIT cycles may cause data corruption. (Note that for BCR[8] = 0, the actual WAIT cycles end one cycle after WAIT de-
asserts. When using variable initial access latency (BCR[14] = 0), the WAIT output performs an arbitration role for READ opera-
tions launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted for additional clock cycles until the
refresh has completed. When the refresh operation has completed, the READ operation will continue normally. WAIT will be
asserted but should be ignored during asynchronous READ and WRITE operations. By using fixed initial latency (BCR[14] = 1),
this device can be used in burst mode without monitoring the WAIT signal. However, WAIT can still be used to determine when
valid data is available at the start of the burst.
Wired or WAIT Configuration
UtRAM2
WAIT
External
Pull-Up
Pull-Down
Resistor
READY
WAIT
RDY
Processor
Other
Other
Device
Device
LB / UB Operation
The LB enable and UB enable signals support byte-wide data WRITEs. During WRITE operations, any disabled bytes will not be
transferred to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be
written is latched on the rising edge of CS, WE, LB, or UB, whichever occurs first. LB and UB must be LOW during READ cycles.
When both the LB and UB are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmit-
ting data. Although the device will seem to be deselected, it remains in an active mode as long as CS remains LOW.
Revision 3.0
Sep 2007
- 16 -
K1C6416B8D
UtRAM2
LOW-POWER OPERATION
Temperature Compensated Self Refresh
Temperature compensated self refresh (TCSR) allows for adequate refresh at different temperatures. This UtRAM2 device
includes an on-chip temperature sensor that automatically adjusts the refresh rate according to the operating temperature. The
device continually adjusts the refresh rate to match that temperature.
Partial Array Refresh
Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to
reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full
array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either
the beginning or the end of the address map. READ and WRITE operations to address ranges receiving refresh will not be
affected. Data stored in addresses not receiving refresh will become corrupted. When re-enabling additional portions of the array,
the new portions are available immediately upon writing to the RCR.
Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the system does not require the stor-
age provided by the UtRAM2 device. Any stored data will become corrupted when DPD is enabled. When refresh activity has
been re-enabled, the UtRAM2 device will require 150µs to perform an initialization procedure before normal operations can
resume. During this 150µs period, the current consumption will be higher than the specified standby levels, but considerably lower
than the active current specification. DPD can be enabled by writing to the RCR using CRE or the software access sequence;
DPD starts when CS goes HIGH. DPD is disabled the next time CS goes LOW and stays LOW for at least 10µs.
Revision 3.0
Sep 2007
- 17 -
K1C6416B8D
UtRAM2
AC Input/Output Reference Waveform & AC Output Load Circuit
Test Points
VccQ
1
50Ω
2
2
Output
Test Points
Input
VccQ/2
VccQ/2
VccQ/2
DUT
30pF
VssQ
1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall times (10% to 90%) <1.6ns.
2. Input timing begins at VCCQ/2 and Output timing ends at VCCQ/2.
3. All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b)
TIMING REQUIREMENTS
Asynchronous READ Cycle Timing Requirements
Parameter
Symbol
Min
Max
Unit
Notes
Address access time
ADV access time
tAA
tAADV
tAVS
tAVH
tBA
70
70
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup to ADV HIGH
Address hold from ADV HIGH
LB/UB access time
5
2
70
8
LB/UB disable to DQ High-Z output
Maximum CS Pulse Width
tBHZ
tCSM
tCSW
tCPH
tCO
1
4
2.5
7.5
CS or ADV LOW to WAIT valid
CS HIGH between subsequent Async Operations
Chip select access time
1
5
4
1
70
CS LOW to ADV HIGH
tCVS
tHZ
7
Chip disable to DQ and WAIT High-Z output
Output enable to valid output
Output disable to DQ High-Z output
Output ebable to Low-Z output
READ cycle time
8
20
8
tOE
tOHZ
tOLZ
tRC
1
2
5
80
5
ADV pulse width LOW
tVP
ADV HIGH to OE LOW
tADVOE
5
Asynchronous WRITE Cycle Timing Requirements
Parameter
Symbol
Min
Max
Unit
Notes
Address setup to ADV going HIGH
Address hold from ADV HIGH
Address valid to end of WRITE
LB/UB select to end of WRITE
CS HIGH between subsequent async operations
CS LOW to ADV HIGH
tAVS
tAVH
tAW
5
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
70
5
tBW
tCPH
tCVS
tCW
1
2
3
7
Chip enable to end of WRITE
Data HOLD from WRITE time
Data WRITE setup time
70
0
tDH
tDW
20
Chip disable to WAIT High-Z output
End WRITE to Low-Z output
ADV pulse width
tHZ
8
tOW
tVP
5
5
2
ADV setup to end of WRITE
WRITE to DQ High-Z output
CS or ADV LOW to WAIT valid
WRITE pulse width
tVS
70
tWHZ
tCSW
tWP
8
2
3
1
55
0
7.5
WRITE recovery time
tWR
ADV HIGH to WE LOW
tADVWE
5
1. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.
2. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
3. WE LOW time must be limited to tCSM (2.5µs).
4. A refresh opportunity must be provided every tCSM. A refresh opportunity is satisfied by the condition that CS HIGH for longer than 15ns.
CS must not remain LOW longer than tCSM.
Revision 3.0
Sep 2007
- 18 -
K1C6416B8D
UtRAM2
Burst READ Cycle Timing Requirements
104MHz
80MHz
66MHz
Parameter
Symbol
Unit
Notes
Min
Max
Min
Max
Min
Max
Address access time (fixed latency)
ADV access time (fixed latency)
Burst to READ access time (variable latency)
CLK to output delay
tAA
70
70
35
7
70
70
46
9
70
70
55
11
20
ns
ns
ns
ns
ns
tAADV
tABA
tACLK
tBOE
Burst OE LOW to output delay
20
20
CS HIGH between subsequent burst or mixed mode
operations
tCBPH
5
6
8
ns
3
3
Maximum CS pulse width
CS or ADV LOW to WAIT valid
CLK period
tCSM
tCSW
tCLK
tCO
2.5
7.5
2.5
7.5
2.5
7.5
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
9.62
12.5
15
Chip select access time (fixed latency)
CS setup time to active CLK edge
Hold time from active CLK edge
Chip desable to DQ and WAIT High-Z output
CLK rise or fall time
70
70
70
tCSP
tHD
3
2
4
2
5
2
tHZ
8
1.6
7
8
1.8
9
8
1
tKHKL
tKHTL
tKOH
tKP
2.0
11
CLK to WAIT valid
2
2
3
2
2
4
2
2
5
Output HOLD from CLK
CLK HIGH or LOW time
Output disable to DQ High-Z output
Output enable to Low-Z output
Setup time to active CLK edge
ADV HIGH to OE LOW
tOHZ
tOLZ
tSP
8
8
8
1
2
5
3
3
2
2
5
4
4
2
2
5
5
5
2
2
tADVO
tAVH
tAHCR
Address setup to ADV HIGH
ADV HIGH to CLK Rising
Burst WRITE Cycle Timing Requirements
104MHz
80MHz
66MHz
Parameter
Symbol
Unit
Notes
Min
Max
Min
Max
Min
Max
CS HIGH between subseuent burst or mixed mode
operations
tCBPH
5
6
8
ns
3
3
Maximum CS pulse width
CS LOW to WAIT valid
tCSM
tCSW
tCLK
tCSP
tHD
2.5
7.5
2.5
7.5
2.5
7.5
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
9.62
3
1
12.5
4
1
15
5
Clock period
CS setup to CLK active edge
Hold time from active CLK edge
Chip disable to WAIT High-Z output
Last clock to ADV LOW (fixed latency)
CLK rise or fall time
2
2
2
tHZ
8
8
8
1
tKADV
tKHKL
tKHTL
tKP
15
15
15
1.6
7
1.8
9
2.0
11
Clock to WAIT valid
2
3
3
2
2
2
4
4
2
2
2
5
5
2
2
CLK HIGH or LOW time
Setup time to activate CLK edge
Address Hold from ADV HIGH
ADV HIGH to CLK Rising
tSP
tAVH
tAHCR
1. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.
2. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
3. A refresh opportunity must be provided every tCSM. A refresh opportunity is satisfied by the condition that CS HIGH for longer than 15ns.
CS must not remain LOW longer than tCSM
Revision 3.0
Sep 2007
- 19 -
K1C6416B8D
UtRAM2
TIMING DIAGRAMS
Asynchronous READ (CS controlled)
tRC
VIH
ADV
VIL
tAADV
tVP
tVP
VIH
VIL
Valid Address
tAVS
A[21:16]
Valid Address
tAVS
tAVH
tCO
tAVH
tCPH
tCVS
tCVS
VIH
VIL
CS
tHZ
tBA
VIH
VIL
UB/ LB
tBHZ
tOHZ
tOE
tADVOE
tADVOE
VIH
VIL
OE
tOLZ
tOLZ
VIH
VIL
WE
tAA
VOH
VOL
VIH
VIL
VOH
VOL
Valid Address
Valid Address
Valid output
A/DQ[15:0]
tAVS
tAVH
Don’t Care
tAVS
tAVH
Undefined
1. Don’t care must be in VIL or VIH.
2. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
3. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
4. tOE(max) is met only when OE becomes enabled after tAA(max).
5. If invalid address signals shorter than min. tRC are continuously repeated for over 2.5us, the device needs a normal read timing(tRC) or needs to
sustain standby state for min. tRC at least once in every 2.5us.
Revision 3.0
Sep 2007
- 20 -
K1C6416B8D
UtRAM2
Asynchronous READ (OE controlled)
tRC
VIH
ADV
VIL
tAADV
tOEADV
tAADV
tVP
tVP
VIH
Valid Address
tAVS
A[21:16]
Valid Address
tAVS
VIL
tAVH
tAVH
tCVS
VIH
VIL
CS
tCO
tBA
VIH
VIL
UB/ LB
tBHZ
tOE
tADVOE
tADVOE
VIH
VIL
OE
tOLZ
tOHZ
tOLZ
VIH
VIL
WE
tAA
VOH
VOL
VIH
VIL
VOH
VOL
Valid Address
Valid Address
Valid output
A/DQ[15:0]
tAVS
tAVH
tAVS
tAVH
Undefined
Don’t Care
1. Don’t care must be in VIL or VIH.
2. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
3. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
4. tOE(max) is met only when OE becomes enabled after tAA(max).
5. If invalid address signals shorter than min. tRC are continuously repeated for over 2.5us, the device needs a normal read timing(tRC) or needs to
sustain standby state for min. tRC at least once in every 2.5us.
Revision 3.0
Sep 2007
- 21 -
K1C6416B8D
UtRAM2
Asynchronous READ Followed by Asynchronous WRITE (CS Controlled)
tVP
VIH
ADV
VIL
tAADV
tAVS
tAVH
tVP
tCVP
V
IH
IL
Valid Address
tCW
Valid Address
tAVS
A[21:16]
V
tAVH
tCPH
tCVS
VIH
CS
V
IL
tCO
tHZ
tBW
tBA
VIH
UB/ LB
VIL
tBHZ
tOHZ
tOE
tADVOE
V
IH
OE
V
IL
tOLZ
tWP
tADVWE
VIH
WE
VIL
tAW
tAA
V
IH
V
OH
Valid Address
Valid Address
Data Valid
Valid output
A/DQ[15:0]
V
IL
V
OL
tAVS
tDW
tDH
tAVH
tAVS
tAVH
Undefined
Don’t Care
Revision 3.0
Sep 2007
- 22 -
K1C6416B8D
UtRAM2
Asynchronous READ Followed by Asynchronous WRITE (OE, WE Controlled)
tVP
VIH
ADV
VIL
tAADV
tOEADV
tAVS
tAVH
tVP
V
IH
IL
Valid Address
Valid Address
tAVS
A[21:16]
V
tAVH
tCVS
V
IH
CS
V
IL
tCO
tBW
tBA
VIH
UB/ LB
VIL
tBHZ
tOHZ
tOE
tADVOE
V
IH
OE
V
IL
tOLZ
tWP
tADVWE
VIH
WE
VIL
tAW
tAA
V
IH
V
OH
Valid Address
Valid Address
Data Valid
Valid output
A/DQ[15:0]
V
IL
V
OL
tAVS
tDW
tDH
tAVH
tAVS
tAVH
Undefined
Don’t Care
Revision 3.0
Sep 2007
- 23 -
K1C6416B8D
UtRAM2
Asynchronous READ Followed by WRITE at the Same Address
VIH
Valid Address
A[21:16]
VIL
tAVS
tAADV
tVP
VIH
VIL
ADV
tBA
tBW
VIH
VIL
LB/UB
tCVS
tCO
tBHZ
tOHZ
VIH
VIL
CS
OE
WE
tADVOE
tOE
VIH
VIL
tOLZ
tWP
VIH
VIL
tAA
tAVH
tDW
tAVS
tDH
VIH
VIL
VOH
VOL
A/DQ[15:0]
IN/OUT
VIH
VIL
Valid Address
Valid Output
Valid Input
Undefined
Don’t Care
1. The end of the WRITE cycle is controlled by CS, LB/UB, or WE, whichever de-asserts first.
2. Don’t care must be in VIL or VIH.
Revision 3.0
Sep 2007
- 24 -
K1C6416B8D
UtRAM2
Single-Access Burst READ Operation—Variable Latency
(CRE=VIL)
tCLK
VIH
CLK
ADV
VIL
tSP
tHD
tHD
VIH
VIL
tSP
VIH
VIL
Valid Address
A[21:16]
CS
tAVH
tAHCR
tHD
tHZ
tCSP
VIH
VIL
tBOE
tADVO
tOHZ
VIH
VIL
OE
tOLZ
tSP
tHD
VIH
VIL
WE
tHD
tSP
VIH
VIL
LB/UB
WAIT
tKHTL
tCSW
VOH
VOL
High-Z
tSP
High-Z
tHD
tACLK
tKOH
VOH
VOL
High-Z
VOH
VOL
Valid
Output
A/DQ[15:0]
Valid Address
READ Burst Identified
(WE = HIGH)
Undefined
Don’t Care
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. Don’t care must be in VIL or VIH.
Revision 3.0
Sep 2007
- 25 -
K1C6416B8D
UtRAM2
4-Word Burst READ Operation—Variable Latency
(CRE=VIL)
tKP tKP
tCLK
tKHKL
VIH
CLK
VIL
tSP
tSP
tHD
VIH
VIL
ADV
tHD
VIH
VIL
A[21:16]
LB/UB
Valid Address
tSP
tAVH
tHD
tHD
tAHCR
VIH
VIL
tCSP
tABA
tCSM
tCBPH
VIH
VIL
CS
OE
tHZ
tADVO
tBOE
VIH
VIL
tOHZ
tKHTL
tSP
tHD
VIH
VIL
WE
tCSW
VOH
VOL
WAIT
High-Z
tKOH
tACLK
tSP
tHD
VOH
VOL
High-Z
VIH
VIL
Valid
Output
Valid
Valid
Valid
A/DQ[15:0]
Valid Address
Output Output Output
READ Burst Identified
(WE = HIGH)
Undefined
Don’t Care
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. Don’t care must be in VIL or VIH.
Revision 3.0
Sep 2007
- 26 -
K1C6416B8D
UtRAM2
Single-Access Burst READ Operation—Fixed Latency
(CRE=VIL)
tCLK
VIH
CLK
ADV
VIL
tHD
tHD
tSP
tSP
VIH
VIL
tAHCR
VIH
VIL
A[21:16]
CS
Valid Address
tHD
tHZ
tCSP
tAVH
VIH
VIL
tOHZ
tADVO
tBOE
VIH
VIL
OE
tOLZ
tSP
tHD
VIH
VIL
WE
tHD
tSP
VIH
VIL
LB/UB
WAIT
tKHTL
tCSW
VOH
VOL
High-Z
tSP
tHD
tACLK
tKOH
High-Z
VIH
VIL
A/DQ[15:0]
Valid Address
Valid Output
READ Burst Identified
(WE = HIGH)
Undefined
Don’t Care
1. Non-default BCR settings: Fixed latency; latency code four (five clocks); WAIT active LOW; WAIT asserted during delay.
2. Don’t care must be in VIL or VIH.
Revision 3.0
Sep 2007
- 27 -
K1C6416B8D
UtRAM2
4-Word Burst READ Operation—Fixed Latency
(CRE=VIL)
tKP tKP
tCLK
tKHKL
VIH
CLK
VIL
tSP tHD
VIH
ADV
tAHCR
VIL
tAADV
VIH
VIL
Valid Address
tSP
A[21:16]
LB/UB
tAVH
VIH
VIL
tCSP
tHD
tCBPH
tCSM
VIH
VIL
CS
OE
tCO
tHZ
tADVO
tBOE
VIH
VIL
tOLZ
tKHTL
tSP
tOHZ
tHD
VIH
VIL
WE
tCSW
VOH
VOL
High-Z
High-Z
WAIT
tKOH
tAA
tHD
tACLK
tSP
VOH
VOL
VIH
VIL
A/DQ[15:0]
IN/OUT
Valid
Output
Valid
Valid
Valid
Valid Address
Output Output Output
READ Burst Identified
(WE = HIGH)
Undefined
Don’t Care
1. Non-default BCR settings: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. Don’t care must be in VIL or VIH.
Revision 3.0
Sep 2007
- 28 -
K1C6416B8D
UtRAM2
4-Word Burst READ Operation - Row Boundary Crossing
(CRE=VIL)
tKP tKP
tCLK
tKHKL
VIH
VIL
CLK
ADV
tSP tHD
VIH
VIL
tAHCR
tAADV
VIH
VIL
Valid Address
tSP
A[21:16]
LB/UB
tAVH
VIH
VIL
tCSP
tHD
tCBPH
tCSM
VIH
VIL
CS
OE
tCO
tHZ
tADVO
tBOE
VIH
VIL
tOLZ
tKHTL
tSP
tOHZ
tHD
VIH
VIL
WE
tCSW
VOH
VOL
High-Z
WAIT
tKOH
tAA
tHD
tACLK
tSP
VOH
VOL
VIH
VIL
High-Z
A/DQ[15:0]
IN/OUT
Valid
Output
Valid
Output
Valid
Valid
Valid Address
Output Output
READ Burst Identified
(WE = HIGH)
End of Row
Undefined
Don’t Care
1. Non-default BCR settings: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. Don’t care must be in VIL or VIH.
Revision 3.0
Sep 2007
- 29 -
K1C6416B8D
UtRAM2
READ Burst Suspend
(CRE=VIL)
tCLK
NOTE 2
VIH
CLK
VIL
tSP tHD
VIH
VIL
ADV
tADVO
tAHCR
tHD
tSP
Valid
VIH
VIL
Valid
Address
A[21:16]
CS
Address
tCSM
tHZ
tCSP
VIH
VIL
NOTE 3
tOHZ
tOHZ
VIH
VIL
OE
WE
tSP tHD
VIH
VIL
VIH
VIL
LB/UB
tBOE
tCSW
High-Z
tOLZ
tCSW
VOH
VOL
WAIT
tKOH
tBOE
tHD
Valid
tSP
tOLZ
VIH
VIL
Valid
Address
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
A/DQ[15:0]
Address
High-Z
tACLK
Undefined
Don’t Care
1. Non-default BCR settings for READ burst suspend: Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted
during delay.
2. CLK can be stopped LOW or HIGH, but must be static, with no LOW-to-HIGH transitions during burst suspend.
3. OE can stay LOW during burst suspend. If OE is LOW, A/DQ[15:0] will continue to output valid data.
4. Don’t care must be in VIL or VIH.
Revision 3.0
Sep 2007
- 30 -
K1C6416B8D
UtRAM2
Asynchronous WRITE (CS Controlled)
tVS
tVP
tVP
VIH
ADV
VIL
tCVS
tCVP
tAVS
tAVS
tAVH
tAVH
VIH
Valid Address
Valid Address
A[21:16]
VIL
tCW
VIH
VIL
CS
UB/LB
WE
tCPH
tBW
tWP
VIH
VIL
tADVWE
tAVH
tADVWE
VIH
VIL
tAW
tAVS
VIH
VIL
A/DQ[15:0]
Valid Address
tAVS
Data Valid
tDW
tDH
Valid Address
tAVH
Don’t Care
1. Don’t care must be in VIL or VIH.
2. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for sin-
gle byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or
WE goes high or UB/LB goes high. The tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the CS going low to the end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
Revision 3.0
Sep 2007
- 31 -
K1C6416B8D
UtRAM2
Asynchronous WRITE (WE, UB/LB Controlled)
tVS
tVP
tVP
VIH
ADV
tWR
VIL
tCVS
tAVS
tAVS
tAVH
tAVH
VIH
Valid Address
Valid Address
A[21:16]
VIL
tCW
VIH
VIL
CS
UB/LB
WE
tBW
tWP
VIH
VIL
tADVWE
tADVWE
VIH
VIL
tBHZ
tAW
tAVS
tAVH
VIH
VIL
A/DQ[15:0]
Valid Address
tAVS
Data Valid
Valid Address
tDW
tDH
tAVH
Don’t Care
1. Don’t care must be in VIL or VIH.
2. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for sin-
gle byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or
WE goes high or UB/LB goes high. The tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the CS going low to the end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
Revision 3.0
Sep 2007
- 32 -
K1C6416B8D
UtRAM2
Asynchronous WRITE Followed by Asynchronous READ (CS Controlled)
tVS
tWR
tVP
VIH
ADV
VIL
tAADV
tAVS
tAVH
tVP
tCVS
VIH
A[21:16]
Valid Address
Valid Address
VIL
tAVS
tCVS
tAVH
tCPH
tCW
tBW
V
IH
CS
V
IL
tCO
tHZ
tBA
VIH
UB/ LB
VIL
tOE
tBHZ
tOHZ
tADVOE
VIH
OE
VIL
tOLZ
tWP
tADVWE
V
IH
WE
V
IL
tHZ
tAW
tAA
V
IH
V
OH
A/DQ[15:0]
Valid Address
Valid Address
Data Valid
Valid output
V
IL
V
OL
tAVS
tDW
tDH
tAVH
tAVS
tAVH
Undefined
Don’t Care
Revision 3.0
Sep 2007
- 33 -
K1C6416B8D
UtRAM2
Asynchronous WRITE Followed by Asynchronous READ (OE, WE Controlled)
tVS
tVP
tWR
VIH
ADV
VIL
tAADV
tAVS
tAVH
tVP
tCVS
VIH
A[21:16]
Valid Address
tCW
Valid Address
VIL
tAVS
tCVS
tAVH
V
IH
CS
V
IL
tCO
tHZ
tBW
tBA
VIH
UB/ LB
VIL
tOE
tBHZ
tOHZ
tADVOE
VIH
OE
VIL
tOLZ
tWP
tADVWE
V
IH
WE
V
IL
tAW
tBHZ
tAA
V
IH
V
OH
A/DQ[15:0]
Valid Address
Valid Address
Data Valid
tDW
tDH
Valid output
V
IL
V
OL
tAVS
tAVH
tAVS
tAVH
Undefined
Don’t Care
Revision 3.0
Sep 2007
- 34 -
K1C6416B8D
UtRAM2
Burst WRITE Operation—Variable Latency Mode
(CRE=VIL)
tKHKL
tKP
tCLK
tKP
VIH
CLK
VIL
tKADV
tSP tHD
VIH
ADV
VIL
tAHCR
tAVH
VIH
A[21:16]
LB/UB
Valid Address
VIL
tSP tHD
VIH
VIL
tCSM
tCBPH
tCSP
tHD
VIH
VIL
CS
OE
VIH
VIL
tSP tHD
VIH
VIL
WE
tKHTL
tHZ
tCSW
VOH
VOL
High-Z
tSP
High-Z
WAIT
NOTE 2
tSP
tHD
tHD
VIH
VIL
Valid Address
D2
A/DQ[15:0]
D1
D3
D4
WRITE Burst Identified
(WE = LOW)
Don’t Care
1. Non-default BCR settings for burst WRITE operation in variable latency mode: Latency code two (three clocks); WAIT active LOW; WAIT asserted
during delay; burst length four; burst wrap enabled.
2. WAIT asserts for LC cycles for both fixed and variable latency. LC = Latency Code (BCR[13:11]).
3. Don’t care must be in VIL or VIH.
Revision 3.0
Sep 2007
- 35 -
K1C6416B8D
UtRAM2
Unit: millimeters
tKADV
Burst WRITE Operation—Fixed Latency Mode
(CRE=VIL)
tKHKL
tKP
tCLK
tKP
VIH
VIL
CLK
ADV
tSP tHD
VIH
VIL
tAHCR
tAVH
VIH
VIL
Valid Address
A[21:16]
LB/UB
tSP tHD
VIH
VIL
tCSM
tCBPH
tCSP
tHD
VIH
VIL
CS
OE
VIH
VIL
tSP tHD
VIH
VIL
WE
tKHTL
tHZ
tCSW
High-Z
VOH
VOL
High-Z
WAIT
NOTE 2
tSP
tSP
tHD
tHD
VIH
VIL
Valid Address
D[2]
A/DQ[15:0]
D[1]
D[3]
D[4]
WRITE Burst Identified
(WE = LOW)
Don’t Care
1. Non-default BCR settings for burst WRITE operation in fixed latency mode: Fixed latency; latency code two (three clocks); WAIT active LOW;
WAIT asserted during delay; burst length four; burst wrap enabled.
2. WAIT asserts for LC cycles for both fixed and variable latency. LC = Latency Code (BCR[13:11]).
3. Don’t care must be in VIL or VIH.
Revision 3.0
Sep 2007
- 36 -
K1C6416B8D
UtRAM2
4-Word Burst WRITE Operation - Row Boundary Crossing
(CRE=VIL)
tKP tKP
tCLK
tKHKL
VIH
VIL
CLK
ADV
tSP tHD
VIH
VIL
tAHCR
tAVS
VIH
VIL
Valid Address
tSP
A[21:16]
LB/UB
tAVH
tHD
tHD
VIH
VIL
A
tCSP
tCBPH
VIH
VIL
CS
OE
VIH
VIL
tSP
tHD
VIH
VIL
WE
tHZ
tCSW
VOH
VOL
High-Z
WAIT
tSP
D1
tHD
tHD
Valid Address
tSP
VOH
VOL
VIH
VIL
High-Z
A/DQ[15:0]
IN/OUT
D2
D3
D4
WRITE Burst Identified
(OE = HIGH)
End of Row
Undefined
Don’t Care
1. Non-default BCR settings: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. Don’t care must be in VIL or VIH.
3. D2 can be written when CS goes high at Point A.
Revision 3.0
Sep 2007
- 37 -
K1C6416B8D
UtRAM2
Burst WRITE Followed by Burst READ, Variable Latency
(CRE=VIL)
tCLK
VIH
CLK
VIL
tSP
tHD
tSP
tHD
VIH
VIL
Valid
Valid
A[21:16]
Address
Address
tSP
tSP tHD
tHD
VIH
ADV
tSP
tHD
tAHCR
VIL
VIH
tAHCR
tSP
LB/UB
VIL
tCSP
tCBPH
NOTE2
tHD
VIH
VIL
CS
OE
tCSP
tADVO
tOHZ
VIH
VIL
tSP
tHD
VIH
VIL
tSP
tSP
tHD
WE
tBOE
tCSW
tSP
tCSW
VOH
VOL
VOH
VOL
High-Z
WAIT
tKOH
tSP
tHD
tHD
tHD
tACLK
VIH
VIL
Valid
Address
Valid
Address
Valid
Valid
Valid
Valid
A/DQ[15:0]
D0
D1
D2
D3
Output Output Output Output
Undefined
Don’t Care
1. Non-default BCR settings for burst WRITE followed by burst READ: Variable latency; latency code two (three clocks); WAIT active LOW; WAIT
asserted during delay.
2. A refresh opportunity must be provided every tCSM by taking CS HIGH.
3. Don’t care must be in VIL or VIH.
Revision 3.0
Sep 2007
- 38 -
K1C6416B8D
UtRAM2
Burst WRITE Followed by Burst READ, Fixed Latency
(CRE=VIL)
tCLK
VIH
CLK
VIL
tSP
tHD
tSP
tHD
VIH
VIL
Valid
Address
Valid
Address
A[21:16]
tSP
tKADV
tHD
tSP
tHD
tAVH
tAHCR
tAVH
tAHCR
VIH
ADV
tSP
tHD
VIL
VIH
tSP
LB/UB
VIL
tCSP
tCBPH
tHD
VIH
VIL
CS
OE
NOTE2
tCSP
tADVO
tOHZ
VIH
VIL
tSP
tHD
VIH
VIL
tSP
tSP
tHD
tHD
WE
tBOE
tCSW
tSP
tCSW
VOH
VOH
VOL
High-Z
WAIT
tKOH
tSP
tHD
tHD
tACLK
VIH
VIL
Valid
Address
Valid
Address
Valid
Valid
Valid
Valid
A/DQ[15:0]
D0
D1
D2
D3
Output Output Output Output
VOL
Undefined
Don’t Care
1. Non-default BCR settings for burst WRITE followed by burst READ: fixed latency; latency code two (three clocks); WAIT active LOW; WAIT
asseted during delay.
2. A refresh opportunity must be provided every tCSM by taking CS HIGH.
3. Don’t care must be in VIL or VIH.
Revision 3.0
Sep 2007
- 39 -
K1C6416B8D
UtRAM2
Asynchronous WRITE Followed by Burst READ
(CRE=VIL)
tCLK
VIH
CLK
VIL
tSP
tHD
VIH
ADV
VIL
tAHCR
tVP
tVS
tAVH
VIH
A[21:16]
Valid Address
tSP
Valid Address
VIL
tBW
VIH
LB/UB
VIL
tCVP
tCBPH2
tCSP
tCW
VIH
VIL
CS
OE
tADVO
tOE
tOHZ
VIH
VIL
tWR
tADVWE
tWP
tHD
tSP
VIH
VIL
WE
tCSW
VOH
VOL
tCSW
tAVS
High-Z
High-Z
WAIT
tAW
tACLK
tDS
tDH
tSP
tHD
tAVH
tKOH
VIH
VIL
VOH
VOL
Valid
Output
Valid
Valid
Valid
A/DQ[15:0]
Valid Address
Valid Address
tWC
Valid Data
Output Output Output
Undefined
Don’t Care
1. Non-default BCR settings for asynchronous WRITE followed by burst READ: Fixed or variable latency; latency code two (three clocks); WAIT
active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous WRITE and variable-latency burst READ operations, CS must go HIGH. CS can stay LOW when tran-
sitioning to fixed-latency burst READs. A refresh opportunity must be provided every tCSM by taking CS HIGH.
3. Don’t care must be in VIL or VIH.
Revision 3.0
Sep 2007
- 40 -
K1C6416B8D
UtRAM2
Asynchronous WRITE Followed by Asynchronous READ
(CRE=VIL)
VIH
Valid Address
A[21:16]
Valid Address
VIL
tAVS
tAVS
tAADV
tVS
tWR
tVP
VIH
VIL
ADV
tHZ
tBW
tCW
tBA
VIH
VIL
LB/UB
tBHZ
tOHZ
tCVP
tCO
tCPH
VIH
VIL
CS
OE
WE
Note 1
tADVOE
tOLZ
tOE
VIH
VIL
tADVWE
tWP
VIH
VIL
tCSW
tCSW
VOH
VOL
High-Z
WAIT
tAA
tAW
tAVH
tAVS
tAVS
tDS
tDH
VOH
VOL
A/DQ[15:0]
IN/OUT
VIH
VIL
Valid Address
Valid Address
Valid Output
Valid Input
Undefined
Don’t Care
1. CS can stay LOW when transitioning between asynchronous operations. If CS goes HIGH, it must remain HIGH for at least tCPH to schedule the
appropriate internal refresh operation.
2. Don’t care must be in VIL or VIH.
Revision 3.0
Sep 2007
- 41 -
K1C6416B8D
UtRAM2
Asynchronous READ Followed by WRITE at the Same Address
(CRE=VIL)
VIH
Valid Address
A[21:16]
VIL
tAVS
tAADV
tVP
VIH
VIL
ADV
tBA
tCO
tBW
VIH
VIL
LB/UB
tCPH
tCVP
VIH
VIL
CS
OE
WE
tADVOE
tOE
tOHZ
tWHZ
VIH
VIL
tOLZ
tWP
NOTE2
VIH
VIL
tCSW
VOH
VOL
High-Z
WAIT
tAA
tDS
tDH
tAVH
tAVS
VIH
VIL
VOH
A/DQ[15:0]
IN/OUT
VIH
VIL
Valid Address
Valid Output
Valid Input
VOL
Undefined
Don’t Care
1. The end of the WRITE cycle is controlled by CS, LB/UB, or WE, whichever de-asserts first.
2. WE must not remain LOW longer than 2.5µs (tCSM) while the device is selected (CS LOW).
3. Don’t care must be in VIL or VIH.
Revision 3.0
Sep 2007
- 42 -
K1C6416B8D
UtRAM2
PACKAGE DIMENSION
Unit: millimeters
54 BALL FINE PITCH BGA(0.75mm ball pitch)
Top View
B
Bottom View
B
B1
6
5
4
3
2
1
A
B
#A1
C
D
E
F
G
H
J
Detail A
Side View
D
A
Y
C
Min
Typ
0.75
6.00
3.75
8.00
6.00
0.45
-
Max
-
A
B
-
Notes.
5.90
6.10
-
1. Ball counts: 54(9 row x 6 column)
2. Ball pitch: (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are ±0.050 unless
specified beside figure.
B1
C
-
7.90
8.10
-
C1
D
-
0.40
-
4. Typ: Typical
0.50
1.00
-
5. Y is coplanarity
E
E1
Y
0.25
-
-
-
0.10
Revision 3.0
Sep 2007
- 43 -
相关型号：
K1C6416B8D-I0000
Pseudo Static RAM, 4MX16, 70ns, CMOS, PBGA54, 6 X 8 MM, 0.75 MM PITCH, FBGA-54
SAMSUNG
K1C6416B8E-I
Pseudo Static RAM, 4MX16, 70ns, CMOS, PBGA54, HALOGEN FREE AND ROHS COMPLIANT, FBGA-54
SAMSUNG
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