K1S321615C-FI60 [SAMSUNG]
DRAM, 2MX16, 60ns, CMOS, PBGA48;
| 型号： | K1S321615C-FI60 |
| 厂家： | 
SAMSUNG |
| 描述： | DRAM, 2MX16, 60ns, CMOS, PBGA48 动态存储器 |
| 文件： | 总10页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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UtRAM
K1S321615C
Document Title
2Mx16 bit Uni-Transistor Random Access Memory
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial Draft
April 18, 2003
Advanced
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 0.0
April 2003
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Advance
UtRAM
K1S321615C
2M x 16 bit Uni-Transistor CMOS RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology: CMOS
· Organization: 2M x16 bit
The K1S321615C is fabricated by SAMSUNG¢s advanced
CMOS technology using one transistor memory cell. The device
supports Industrial temperature range and 48 ball Chip Scale
Package for user flexibility of system design. The device also
supports dual chip selection for user interface.
· Power Supply Voltage: 2.7V~3.1V
· Three State Outputs
· Compatible with Low Power SRAM
· Deep Power Down: Memory cell data holds invalid
· Package Type: 48-FBGA-6.00x8.00
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temp.
Vcc Range
Speed
PKG Type
Standby
Operating
(ISB1, Max.)
(ICC2, Max.)
K1S321615C-I
Industrial(-40~85°C)
2.7V~3.1V
60/70ns
100mA
35mA
48-FBGA-6.00x8.00
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
Clk gen.
Precharge circuit.
A
B
C
D
E
F
LB
OE
UB
A0
A3
A1
A4
A2
ZZ
Vcc
Vss
I/O9
I/O10
Vss
CS
I/O1
I/O3
Vcc
Vss
I/O7
I/O8
A20
Row
select
Row
Addresses
Memory array
I/O11
I/O12
I/O13
I/O14
A19
A5
A6
I/O2
I/O4
I/O5
I/O6
WE
A11
A17
NC
A14
A12
A9
A7
I/O Circuit
Column select
Data
cont
I/O1~I/O8
Vcc
A16
A15
A13
A10
Data
cont
I/O9~I/O16
I/O15
I/O16
A18
Data
cont
Column Addresses
G
H
A8
CS
ZZ
48-FBGA: Top View(Ball Down)
OE
WE
UB
LB
Control Logic
Name
Function
Name
Vcc
Vss
UB
Function
CS1,CS2 Chip Select Inputs
Power
OE
WE
Output Enable Input
Write Enable Input
Address Inputs
Ground
Upper Byte(I/O9~16)
Lower Byte(I/O1~8)
Not Connected1)
A0~A20
LB
I/O1~I/O16 Data Inputs/Outputs
1) Reserved for future use.
NC
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 0.0
April 2003
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UtRAM
K1S321615C
POWER UP SEQUENCE
1. Apply power.
2. Maintain stable power(Vcc min.=2.7V) for a minimum 200ms with CS and ZZ high.
TIMING WAVEFORM OF POWER UP
VCC(Min)
VCC
Min. 0ns
ZZ
Min. 200ms
Min. 0ns
CS
Power Up Mode
Normal Operation
(POWER UP)
1. After VCC reaches VCC(Min.), wait 200ms with CS and ZZ high. Then you get into the normal operation.
STANDBY MODE STATE MACHINES
CS=VIL, UB or/and LB=VIL
Standby
ZZ=VIH
Mode
CS=VIH and ZZ=VIH
Initial State
(Wait 200ms)
CS=VIH
ZZ=VIH
Power On
Active
ZZ=VIL
ZZ=VIL
Deep Power
Down Mode
CS=VIH, ZZ=VIH
STANDBY MODE CHARACTERISTIC
Power Mode
Standby
Memory Cell Data
Standby Current(
m
A)
Wait Time(ms)
Valid
100
10
0
Deep Power Down
Invaild
200
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April 2003
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UtRAM
K1S321615C
FUNCTIONAL DESCRIPTION
CS
H
X1)
L
ZZ
H
L
OE
X1)
X1)
X1)
H
WE
X1)
X1)
X1)
H
LB
X1)
X1)
H
UB
X1)
X1)
H
I/O1~8
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
I/O9~16
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Standby
Deep Power Down
Standby
Active
Deselected
Deselected
H
H
H
H
H
H
H
H
H
Deselected
X1)
L
L
L
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
X1)
L
L
H
H
Active
L
L
H
H
Active
L
L
H
H
L
High-Z
Dout
Active
L
L
H
L
L
Dout
Active
X1)
X1)
X1)
L
L
L
H
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
Active
L
L
H
L
High-Z
Din
Active
L
L
L
L
Din
Active
1. X means don¢t care.(Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
VIN, VOUT
VCC
Ratings
-0.2 to VCC+0.3V
-0.2 to 3.6V
1.0
Unit
V
V
PD
W
Storage temperature
TSTG
-65 to 150
-40 to 85
°C
°C
Operating Temperature
TA
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reli-
ability.
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April 2003
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UtRAM
K1S321615C
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
Function
K1S321615C-FI60
K1S321615C-FI70
48-FBGA, 60ns, 2.9V
48-FBGA, 70ns, 2.9V
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Vcc
Min
2.7
0
Typ
2.9
0
Max
3.1
Unit
V
Supply voltage
Ground
Vss
0
V
VCC+0.32)
0.6
Input high voltage
Input low voltage
VIH
2.2
-0.33)
-
V
VIL
-
V
1. TA=-40 to 85°C, otherwise specified.
2. Overshoot: Vcc+1.0V in case of pulse width £20ns.
3. Undershoot: -1.0V in case of pulse width £20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1)(f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
Min
Max
8
Unit
pF
VIN=0V
VIO=0V
-
-
Input/Output capacitance
CIO
10
pF
1. Capacitance is sampled, not 100% tested.
DC AND OPERATING CHARACTERISTICS
Symbol
Item
Test Conditions
Min Typ Max Unit
Input leakage current
ILI
VIN=Vss to Vcc
-1
-1
-
-
1
1
mA
mA
CS=VIH or ZZ=VIH or OE=VIH or WE=VIL or LB=UB=VIH, VIO=Vss
to Vcc
Output leakage current
ILO
Cycle time=1ms, 100% duty, IIO=0mA, CS£0.2V, LB£0.2V or/and
UB£0.2V, ZZ³ VCC-0.2V, VIN£0.2V or VIN³ VCC-0.2V
ICC1
ICC2
-
-
-
-
7
mA
mA
Average operating current
Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, ZZ=VIH, LB=VIL
or/and UB=VIL, VIN=VIH or VIL
35
Output low voltage
VOL IOL = 2.1mA
VOH IOH = -1.0mA
-
2.4
-
-
-
-
0.4
-
V
V
Output high voltage
Standby Current(CMOS)
ISB1
100 mA
10 mA
1) CS1³ VCC-0.2V, ZZ ³ VCC-0.2V, Other inputs=0~Vcc
Deep Power Down
ISBD ZZ£0.2V, Other inputs=Vss to Vcc
-
-
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April 2003
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UtRAM
K1S321615C
Dout
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
CL
Input and output reference voltage: 1.5V
Output load (See right): CL=50pF
1. Including scope and jig capacitance
AC CHARACTERISTICS(Vcc=2.7~3.1V, TA=-40 to 85°C)
Speed Bins
70ns
Parameter List
Symbol
Units
60ns
Min
60
-
Max
Min
70
-
Max
Read Cycle Time
tRC
tAA
-
60
60
30
60
-
-
70
70
35
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
-
-
Output Enable to Valid Output
UB, LB Access Time
-
-
tBA
-
-
Chip Select to Low-Z Output
UB, LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
tLZ
10
10
5
10
10
5
Read
tBLZ
tOLZ
tHZ
-
-
-
-
0
20
20
20
-
0
25
25
25
-
tBHZ
tOHZ
tOH
tWC
tCW
tAS
0
0
0
0
10
60
50
0
5
-
70
60
0
-
Chip Select to End of Write
Address Set-up Time
-
-
-
-
Address Valid to End of Write
UB, LB Valid to End of Write
Write Pulse Width
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
50
50
451)
0
-
60
60
551)
0
-
-
-
Write
-
-
Write Recovery Time
-
-
Write to Output High-Z
0
20
-
0
25
-
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
30
0
30
0
-
-
tOW
5
-
5
-
1. tWP(min)=60ns for continuous write operation over 50 times.
Revision 0.0
April 2003
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UtRAM
K1S321615C
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)(Address Controlled, CS=OE=VIL, ZZ=WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2)(ZZ=WE=VIH)
tRC1
Address
tAA
tOH
tCO
CS
tHZ
tBA
UB, LB
tBHZ
tOE
OE
tOLZ
tBLZ
tLZ
tOHZ
High-Z
Data out
Data Valid
(READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
3. tOE(max) is met only when OE becomes enabled after tAA(max).
4. If invalid address signals shorter than min. tRC are continuously repeated for over 4us, the device needs a normal read timing(tRC) or
needs to sustain standby state for min. tRC at least once in every 4us.
Revision 0.0
April 2003
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UtRAM
K1S321615C
TIMING WAVEFORM OF WRITE CYCLE(1)(WE Controlled, ZZ=VIH)
tWC
Address
tWR(4)
tCW(2)
CS
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
tDW
tDH
High-Z
High-Z
Data in
Data Valid
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2)(CS Controlled, ZZ=VIH)
tWC
Address
CS
tCW(2)
tAS(3)
tWR(4)
tAW
tBW
UB, LB
tWP(1)
WE
tDW
tDH
Data Valid
Data in
High-Z
Data out
High-Z
Revision 0.0
April 2003
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UtRAM
K1S321615C
TIMING WAVEFORM OF WRITE CYCLE(3)(UB, LB Controlled, ZZ=VIH)
tWC
Address
tWR(4)
tCW(2)
CS
tAW
tBW
UB, LB
tAS(3)
tWP(1)
WE
tDH
tDW
Data Valid
Data in
High-Z
Data out
High-Z
(WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition
when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
TIMING WAVEFORM OF DEEP POWER DOWN MODE
Read Operation Twice or Stay High during 300ms
200ms
0.5ms
ZZ
Wake up
Suspend
Normal Operation
Normal Operation
MODE
CS
Deep Power Down Mode
(DEEP POWER DOWN MODE)
1. When you toggle ZZ pin low, the device gets into the Deep Power Down mode after 0.5ms suspend period.
2. To return to normal operation, the device needs Wake Up period.
3. Wake Up sequence is just the same as Power Up sequence shown in next page.
Revision 0.0
April 2003
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UtRAM
K1S321615C
Unit: millimeters
PACKAGE DIMENSION
48 BALL FINE PITCH BGA(0.75mm ball pitch)
Top View
B
Bottom View
B
B1
6
5
4
3
2
1
A
B
#A1
C
D
E
F
G
H
B/2
Detail A
A
Side View
D
Y
C
Min
Typ
0.75
6.00
3.75
8.00
5.25
0.45
0.90
0.55
0.35
-
Max
-
A
B
-
Notes.
5.90
6.10
-
1. Bump counts: 48(8 row x 6 column)
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are ±0.050 unless
specified beside figures.
B1
C
-
7.90
8.10
-
C1
D
-
4. Typ : Typical
0.40
0.50
1.00
-
5. Y is coplanarity: 0.08(Max)
E
-
E1
E2
Y
-
0.30
-
0.40
0.08
Revision 0.0
April 2003
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