首页 |元器件品牌

K1S3216BCC-FI70 [SAMSUNG]

Memory IC, 2MX16, CMOS, PBGA48;
K1S3216BCC-FI70
型号： K1S3216BCC-FI70
厂家： SAMSUNG    SAMSUNG
描述：

Memory IC, 2MX16, CMOS, PBGA48
文件： 总10页 (文件大小：161K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
K1S3216BCC  
UtRAM  
Document Title  
2Mx16 bit Page Mode Uni-Transistor Random Access Memory  
Revision History  
Revision No. History  
Draft Date  
Remark  
1.0  
February 25, 2004 Final  
2.0  
Revised  
September 20, 2004 Final  
- Corrected tOH from 5ns to 3ns.  
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and  
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.  
Revision 2.0  
- 1 -  
September 2004  
K1S3216BCC  
UtRAM  
2M x 16 bit Page Mode Uni-Transistor CMOS RAM  
FEATURES  
GENERAL DESCRIPTION  
• Process Technology: CMOS  
• Organization: 2M x16 bit  
The K1S3216BCC is fabricated by SAMSUNG′s advanced  
CMOS technology using one transistor memory cell. The device  
support 4 page mode operation, Industrial temperature range  
and 48 ball Chip Scale Package for user flexibility of system  
design. The device also supports deep power down mode for  
low standby current.  
• Power Supply Voltage: 1.7~2.1V  
• Three State Outputs  
• Compatible with Low Power SRAM  
• Support 4 page read mode  
• Package Type: 48-FBGA-6.00x8.00  
PRODUCT FAMILY  
Power Dissipation  
Speed  
(tRC)  
Product Family  
Operating Temp.  
Vcc Range  
PKG Type  
Standby  
Operating  
(ISB1, Max.)  
(ICC2, Max.)  
K1S3216BCC-I  
Industrial(-40~85°C)  
1.7~2.1V  
70ns  
100µA  
35mA  
48-FBGA-6.00x8.00  
FUNCTIONAL BLOCK DIAGRAM  
PIN DESCRIPTION  
1
2
3
4
5
6
Clk gen.  
Precharge circuit.  
A
B
C
D
E
F
LB  
OE  
UB  
A0  
A3  
A1  
A4  
A2  
CS2  
I/O1  
I/O3  
Vcc  
Vss  
I/O7  
I/O8  
A20  
Vcc  
Vss  
I/O9  
I/O10  
Vss  
CS1  
I/O2  
I/O4  
I/O5  
I/O6  
WE  
Row  
select  
Row  
Addresses  
Memory array  
I/O11  
I/O12  
I/O13  
I/O14  
A19  
A5  
A6  
A17  
NC  
A14  
A12  
A9  
A7  
I/O Circuit  
Column select  
Data  
cont  
I/O1~I/O8  
Vcc  
A16  
A15  
A13  
A10  
Data  
cont  
I/O9~I/O16  
I/O15  
I/O16  
A18  
Data  
cont  
Column Addresses  
G
H
A8  
A11  
CS1  
CS2  
OE  
48-FBGA: Top View(Ball Down)  
Control Logic  
WE  
UB  
LB  
Name  
Function  
Name  
Vcc  
Vss  
UB  
Function  
Power  
Ground  
CS1,CS2 Chip Select Inputs  
OE  
WE  
Output Enable Input  
Write Enable Input  
Address Inputs  
Upper Byte(I/O9~16)  
Lower Byte(I/O1~8)  
No Connection1)  
A0~A20  
LB  
I/O1~I/O16 Data Inputs/Outputs  
1) Reserved for future use  
NC  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.  
Revision 2.0  
September 2004  
- 2 -  
K1S3216BCC  
UtRAM  
POWER UP SEQUENCE  
1. Apply power.  
2. Maintain stable power(Vcc min.=1.7V) for a minimum 200µs with CS1=high.or CS2=low.  
TIMING WAVEFORM OF POWER UP(1) (CS1 controlled)  
Min. 200µs  
VCC(Min)  
VCC  
CS1  
CS2  
Power Up Mode  
NormalOperation  
POWER UP(1)  
1. After VCC reaches VCC(Min.), wait 200µs with CS1 high. Then the device gets into the normal operation.  
TIMING WAVEFORM OF POWER UP(2) (CS2 controlled)  
Min. 200µs  
VCC(Min)  
VCC  
CS1  
CS2  
Power Up Mode  
Normal Operation  
POWER UP(2)  
1. After VCC reaches VCC(Min.), wait 200µs with CS2 low. Then the device gets into the normal operation.  
Revision 2.0  
- 3 -  
September 2004  
K1S3216BCC  
UtRAM  
FUNCTIONAL DESCRIPTION  
CS1  
H
X1)  
X1)  
L
CS2  
OE  
X1)  
X1)  
X1)  
H
WE  
X1)  
X1)  
X1)  
H
LB  
X1)  
X1)  
H
UB  
X1)  
X1)  
H
I/O1~8  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Dout  
I/O9~16  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Dout  
Mode  
Power  
Standby  
Standby  
Standby  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
X1)  
L
Deselected  
Deselected  
X1)  
H
H
H
H
H
H
H
H
Deselected  
X1)  
L
L
Output Disabled  
Output Disabled  
Lower Byte Read  
Upper Byte Read  
Word Read  
X1)  
L
L
H
H
L
L
H
H
L
L
H
H
L
High-Z  
Dout  
L
L
H
L
L
Dout  
X1)  
X1)  
X1)  
L
L
L
H
Din  
High-Z  
Din  
Lower Byte Write  
Upper Byte Write  
Word Write  
L
L
H
L
High-Z  
Din  
L
L
L
L
Din  
1. X means don′t care.(Must be low or high state)  
ABSOLUTE MAXIMUM RATINGS1)  
Item  
Voltage on any pin relative to Vss  
Voltage on Vcc supply relative to Vss  
Power Dissipation  
Symbol  
VIN, VOUT  
VCC  
Ratings  
-0.2 to VCC+0.3V  
-0.2 to 2.5V  
1.0  
Unit  
V
V
PD  
W
Storage temperature  
TSTG  
-65 to 150  
-40 to 85  
°C  
°C  
Operating Temperature  
TA  
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be  
restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reli-  
ability.  
Revision 2.0  
- 4 -  
September 2004  
K1S3216BCC  
UtRAM  
PRODUCT LIST  
Industrial Temperature Product(-40~85°C)  
Part Name  
K1S3216BCC-FI70  
Function  
48-FBGA, 70ns, 1.8/2.0V  
48-FBGA, 85ns, 1.8/2.0V  
K1S3216BCC-FI85  
RECOMMENDED DC OPERATING CONDITIONS1)  
Item  
Symbol  
Vcc  
Min  
1.7  
0
Typ  
Max  
2.1  
Unit  
V
Supply voltage  
Ground  
1.8/2.0  
Vss  
0
-
0
V
Vcc+0.32)  
0.4  
Input high voltage  
Input low voltage  
VIH  
1.4  
-0.23)  
V
VIL  
-
V
1. TA=-40 to 85°C, otherwise specified.  
2. Overshoot: Vcc+1.0V in case of pulse width ≤20ns.  
3. Undershoot: -1.0V in case of pulse width ≤20ns.  
4. Overshoot and undershoot are sampled, not 100% tested.  
CAPACITANCE1)(f=1MHz, TA=25°C)  
Item  
Input capacitance  
Symbol  
CIN  
Test Condition  
Min  
Max  
8
Unit  
pF  
VIN=0V  
VIO=0V  
-
-
Input/Output capacitance  
CIO  
10  
pF  
1. Capacitance is sampled, not 100% tested.  
DC AND OPERATING CHARACTERISTICS  
Typ1)  
Symbol  
ILI  
Item  
Test Conditions  
Min  
Max  
1
Unit  
µA  
Input leakage current  
Output leakage current  
VIN=Vss to Vcc  
-1  
-1  
-
-
ILO  
CS=VIH, ZZ=VIH, OE=VIH or WE=VIL, VIO=Vss to Vcc  
1
µA  
Cycle time=1µs, 100% duty, IIO=0mA, CS≤0.2V,  
ZZ≥Vcc-0.2V, VIN≤0.2V or VIN≥VCC-0.2V  
ICC1  
-
-
5
mA  
Average operating current  
Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS=VIL, ZZ=VIH,  
VIN=VIL or VIH  
ICC2  
-
35  
mA  
Output low voltage  
VOL  
VOH  
IOL=2.1mA  
-
1.4  
-
-
-
-
0.2  
-
V
V
Output high voltage  
Standby Current(CMOS)  
IOH=-1.0mA  
2)  
CS≥Vcc-0.2V, ZZ≥Vcc-0.2V, Other inputs=Vss to Vcc  
100  
µA  
ISB1  
1. Typical values are tested at VCC=2.9V, TA=25°C and not guaranteed.  
Revision 2.0  
- 5 -  
September 2004  
K1S3216BCC  
UtRAM  
AC OPERATING CONDITIONS  
Dout  
TEST CONDITIONS(Test Load and Test Input/Output Reference)  
Input pulse level: 0.2 to Vcc-0.2V  
Input rising and falling time: 5ns  
CL  
Input and output reference voltage: 0.5 x VCC  
Output load (See right): CL=50pF  
1. Including scope and jig capacitance  
AC CHARACTERISTICS (Vcc=1.7~2.1V, TA=-40 to 85°C)  
Speed Bins  
85ns  
Parameter List  
Symbol  
Units  
70ns  
Min  
70  
-
Max  
Min  
85  
-
Max  
Read Cycle Time  
tRC  
tAA  
-
70  
70  
35  
70  
-
-
85  
85  
40  
85  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
Chip Select to Output  
tCO  
tOE  
tBA  
-
-
Output Enable to Valid Output  
UB, LB Access Time  
-
-
-
-
Chip Select to Low-Z Output  
UB, LB Enable to Low-Z Output  
Output Enable to Low-Z Output  
Chip Disable to High-Z Output  
UB, LB Disable to High-Z Output  
Output Disable to High-Z Output  
Output Hold from Address Change  
Page Cycle  
tLZ  
10  
10  
5
10  
10  
5
tBLZ  
tOLZ  
tHZ  
-
-
Read  
-
-
0
25  
25  
25  
-
0
25  
25  
25  
-
tBHZ  
tOHZ  
tOH  
tPC  
0
0
0
0
3
3
25  
-
-
25  
-
-
Page Access Time  
tPA  
20  
-
20  
-
Write Cycle Time  
tWC  
tCW  
tAS  
70  
60  
0
85  
70  
0
Chip Select to End of Write  
Address Set-up Time  
-
-
-
-
Address Valid to End of Write  
UB, LB Valid to End of Write  
Write Pulse Width  
tAW  
tBW  
tWP  
tWR  
tWHZ  
tDW  
tDH  
tOW  
60  
60  
551)  
0
-
70  
70  
601)  
0
-
-
-
Write  
-
-
Write Recovery Time  
-
-
Write to Output High-Z  
0
25  
-
0
25  
-
Data to Write Time Overlap  
Data Hold from Write Time  
End Write to Output Low-Z  
30  
0
35  
0
-
-
5
-
5
-
1. tWP(min)=70ns for continuous write operation over 50 times.  
Revision 2.0  
- 6 -  
September 2004  
K1S3216BCC  
UtRAM  
TIMING DIAGRAMS  
TIMING WAVEFORM OF READ CYCLE(1)(Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)  
tRC  
Address  
tAA  
tOH  
Data Valid  
Data Out  
Previous Data Valid  
TIMING WAVEFORM OF READ CYCLE(2)(WE=VIH)  
tRC  
Address  
tOH  
tAA  
tCO  
CS1  
CS2  
tHZ  
tBA  
UB, LB  
OE  
tBHZ  
tOE  
tOLZ  
tBLZ  
tLZ  
tOHZ  
High-Z  
Data out  
Data Valid  
TIMING WAVEFORM OF PAGE CYCLE(READ ONLY)  
Valid  
Address  
A20~A2  
Valid  
Valid  
Valid  
Valid  
Address  
A1~A0  
Address Address Address  
tAA  
tPC  
CS1  
CS2  
tCO  
OE  
tPA  
tOHZ  
tOE  
High Z  
Data  
Valid  
Data  
Valid  
Data  
Valid  
Data  
Valid  
DQ15~DQ0  
(READ CYCLE)  
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage  
levels.  
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device  
interconnection.  
3. tOE(max) is met only when OE becomes enabled after tAA(max).  
4. If invalid address signals shorter than min. tRC are continuously repeated for over 4us, the device needs a normal read timing(tRC) or  
needs to sustain standby state for min. tRC at least once in every 4us.  
Revision 2.0  
September 2004  
- 7 -  
K1S3216BCC  
UtRAM  
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)  
tWC  
tCW  
Address  
CS1  
tWR  
CS2  
tAW  
tBW  
UB, LB  
tWP  
WE  
tAS  
tDW  
tDH  
High-Z  
High-Z  
Data in  
Data Valid  
tWHZ  
tOW  
Data Undefined  
Data out  
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)  
tWC  
Address  
tWR  
tAS  
tCW  
CS1  
tAW  
CS2  
tBW  
UB, LB  
tWP  
WE  
tDW  
tDH  
Data Valid  
Data in  
High-Z  
Data out  
Revision 2.0  
- 8 -  
September 2004  
K1S3216BCC  
UtRAM  
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)  
tWC  
Address  
tWR  
tAS  
tCW  
CS1  
CS2  
tAW  
tBW  
UB, LB  
WE  
tWP(1)  
tDW  
tDH  
Data Valid  
Data in  
Data out  
High-Z  
TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)  
tWC  
Address  
CS1  
tWR  
tCW  
tAW  
CS2  
tBW  
UB, LB  
tAS  
tWP  
WE  
tDH  
tDW  
Data Valid  
Data in  
High-Z  
Data out  
NOTES (WRITE CYCLE)  
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting  
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-  
sition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.  
2. tCW is measured from the CS1 going low to the end of write.  
3. tAS is measured from the address valid to the beginning of write.  
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high.  
Revision 2.0  
September 2004  
- 9 -  
K1S3216BCC  
UtRAM  
Unit: millimeters  
PACKAGE DIMENSION  
48 BALL FINE PITCH BGA(0.75mm ball pitch)  
Top View  
B
Bottom View  
B
B1  
6
5
4
3
2
1
A
B
#A1  
C
D
E
F
G
H
Detail A  
A
Side View  
D
Y
C
Min  
Typ  
0.75  
6.00  
3.75  
8.00  
5.25  
0.45  
Max  
-
A
B
-
Notes.  
5.90  
6.10  
-
1. Bump counts: 48(8 row x 6 column)  
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)  
3. All tolerence are ±0.050 unless  
specified beside figures.  
4. Typ : Typical  
B1  
C
-
7.90  
8.10  
-
C1  
D
-
0.40  
-
0.50  
1.00  
5. Y is coplanarity  
E
E1  
Y
0.25  
-
-
0.10  
Revision 2.0  
September 2004  
- 10 -  

相关型号：

K1S3216BCC-FI700

 Pseudo Static RAM, 2MX16, 70ns, CMOS, PBGA48, 8 X 6 MM, 0.75 MM PITCH, FBGA-48
SAMSUNG

K1S3216BCC-FI70T

 Application Specific SRAM, 2MX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 0.75 MM PITCH, FBGA-48
SAMSUNG

K1S3216BCC-FI850

 Pseudo Static RAM, 2MX16, 85ns, CMOS, PBGA48, 8 X 6 MM, 0.75 MM PITCH, FBGA-48
SAMSUNG

K1S3216BCC-I0000

 Pseudo Static RAM, 2MX16, 70ns, CMOS, PBGA48, 8 X 6 MM, 0.75 MM PITCH, FBGA-48
SAMSUNG

K1S3216BCD

 2Mx16 bit Page Mode Uni-Transistor Random Access Memory
SAMSUNG

K1S3216BCD-FI70

 Pseudo Static RAM, 2MX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 0.75 MM PITCH, FBGA-48
SAMSUNG

K1S3216BCD-FI700

 Pseudo Static RAM, 2MX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 0.75 MM PITCH, FBGA-48
SAMSUNG

K1S3216BCD-FI85

 Pseudo Static RAM, 2MX16, 85ns, CMOS, PBGA48, 6 X 8 MM, 0.75 MM PITCH, FBGA-48
SAMSUNG

K1S3216BCD-FI850

 Pseudo Static RAM, 2MX16, 85ns, CMOS, PBGA48, 6 X 8 MM, 0.75 MM PITCH, FBGA-48
SAMSUNG

K1S3216BCE-FI700

 Pseudo Static RAM, 2MX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 0.75 MM PITCH, FBGA-48
SAMSUNG

K1S64161CC

 4Mx16 bit Page Mode Uni-Transistor Random Access Memory
SAMSUNG

K1S64161CC-BI70

 DRAM, 4MX16, 70ns, CMOS, PBGA48
SAMSUNG
©2020 ICPDF网 联系我们和版权申明