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K3N3C3000D-YE100 [SAMSUNG]

MASK ROM, 512KX8, 100ns, CMOS, PDSO32, 8 X 20 MM, TSOP1-32;
K3N3C3000D-YE100
型号： K3N3C3000D-YE100
厂家： SAMSUNG    SAMSUNG
描述：

MASK ROM, 512KX8, 100ns, CMOS, PDSO32, 8 X 20 MM, TSOP1-32

有原始数据的样本ROM 光电二极管 内存集成电路
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K3N3C3000D-YC(E)  
CMOS MASK ROM  
4M-Bit (512Kx8) CMOS MASK ROM  
FEATURES  
GENERAL DESCRIPTION  
The K3N3C3000D-YC(E) is a fully static mask programmable  
ROM organized 524,288 x 8bit. It is fabricated using silicon  
gate CMOS process technology.  
· 524,288 x 8 bit organization  
· Access time : 80ns(Max.)  
· Supply voltage : single +5V  
· Current consumption  
Operating : 50mA(Max.)  
Standby : 50mA(Max.)  
· Fully static operation  
· All inputs and outputs TTL compatible  
· Three state outputs  
This device operates with a 5V single power supply, and all  
inputs and outputs are TTL compatible.  
Because of its asynchronous operation, it requires no external  
clock assuring extremely easy operation.  
It is suitable for use in program memory of microprocessor, and  
data memory, character generator.  
· Package  
The K3N3C3000D-YC(E) is packaged in a 32-TSOP1.  
-. K3N3C3000D-YC(E) : 32-TSOP1-0820  
FUNCTIONAL BLOCK DIAGRAM  
PRODUCT INFORMATION  
Operating  
Temp Range  
Vcc Range Speed  
Product  
A18  
(Typical)  
(ns)  
X
MEMORY CELL  
MATRIX  
BUFFERS  
AND  
.
.
.
.
.
.
.
.
K3N3C3000D-YC  
K3N3C3000D-YE  
0°C~70°C  
5.0V  
80  
(524,288x8)  
-20°C~85°C  
DECODER  
Y
SENSE AMP.  
BUFFERS  
BUFFERS  
AND  
PIN CONFIGURATION  
DECODER  
A0  
. . .  
A11  
#1  
OE  
#32  
A9  
A8  
A10  
CE  
Q7  
Q6  
Q5  
Q4  
Q3  
VSS  
Q2  
Q1  
Q0  
A0  
CE  
OE  
Q0  
Q7  
CONTROL  
LOGIC  
A13  
A14  
A17  
N.C  
VCC  
32-TSOP1  
A18  
A16  
A15  
A12  
A7  
Pin Name  
A0 - A18  
Q0 - Q7  
CE  
Pin Function  
Address Inputs  
Data Outputs  
Chip Enable  
Output Enable  
Power(+5V)  
Ground  
A6  
A1  
A5  
A2  
#16  
#17  
A4  
A3  
OE  
K3N3C3000D-YC(E)  
VCC  
VSS  
N.C  
No Connection  
K3N3C3000D-YC(E)  
CMOS MASK ROM  
ABSOLUTE MAXIMUM RATINGS  
Item  
Symbol  
Rating  
-0.3 to +7.0  
-10 to +85  
-55 to +150  
0 to +70  
Unit  
Remark  
Voltage on Any Pin Relative to VSS  
Temperature Under Bias  
Storage Temperature  
VIN  
V
-
TBIAS  
TSTG  
°C  
°C  
°C  
°C  
-
-
K3N3C3000D-YC  
K3N3C3000D-YE  
Operating Temperature  
TA  
-20 to +85  
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the  
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may  
affect device reliability.  
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS)  
Item  
Supply Voltage  
Symbol  
Min  
4.5  
0
Typ  
5.0  
0
Max  
5.5  
0
Unit  
V
VCC  
Supply Voltage  
VSS  
V
DC CHARACTERISTICS  
Parameter  
Symbol  
Test Conditions  
Cycle=5MHz, all outputs open  
CE=OE=VIL, VIN=0.6V to 2.4V (AC Test Condition)  
CE=VIH, all outputs open  
CE=VCC, all outputs open  
VIN=0 to VCC  
Min  
Max  
Unit  
Operating Current  
ICC  
-
50  
mA  
Standby Current(TTL)  
mA  
mA  
mA  
mA  
V
ISB1  
ISB2  
ILI  
-
-
1
50  
Standby Current(CMOS)  
Input Leakage Current  
-
10  
Output Leakage Current  
Input High Voltage, All Inputs  
Input Low Voltage, All Inputs  
Output High Voltage Level  
Output Low Voltage Level  
ILO  
VOUT=0 to VCC  
-
10  
VIH  
VIL  
2.2  
-0.3  
2.4  
-
VCC+0.3  
0.8  
V
VOH  
VOL  
IOH=-400mA  
-
V
IOL=2.1mA  
0.4  
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.  
Maximum DC voltage(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.  
MODE SELECTION  
CE  
OE  
X
Mode  
Data  
High-Z  
High-Z  
Dout  
Power  
Standby  
Active  
H
Standby  
Operating  
Operating  
H
L
L
Active  
CAPACITANCE(TA=25°C, f=1.0MHz)  
Item  
Output Capacitance  
Input Capacitance  
Symbol  
Test Conditions  
VOUT=0V  
Min  
Max  
10  
Unit  
COUT  
CIN  
-
-
pF  
pF  
VIN=0V  
10  
NOTE : Capacitance is periodically sampled and not 100% tested.  
K3N3C3000D-YC(E)  
CMOS MASK ROM  
AC CHARACTERISTICS(VCC=5V±10%, unless otherwise noted.)  
TEST CONDITIONS  
Item  
Value  
Input Pulse Levels  
0.6V to 2.4V  
10ns  
Input Rise and Fall Times  
Input and Output timing Levels  
0.8V and 2.0V  
Output Loads  
1 TTL Gate and CL=100pF  
READ CYCLE  
K3N3C3000D-YC(E)08 K3N3C3000D-YC(E)10 K3N3C3000D-YC(E)12  
Item  
Symbol  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Read Cycle Time  
tRC  
tACE  
tAA  
80  
100  
120  
ns  
ns  
ns  
ns  
Chip Enable Access Time  
Address Access Time  
Output Enable Access Time  
80  
80  
40  
100  
100  
50  
120  
120  
60  
tOE  
Output or Chip Disable to  
Output High-Z  
tDF  
20  
20  
20  
ns  
ns  
Output Hold from Address Change  
tOH  
0
0
0
TIMING DIAGRAM  
READ  
ADD2  
ADD1  
ADD  
tRC  
tDF(Note)  
tACE  
CE  
tOE  
tAA  
OE  
tOH  
VALID DATA  
VALID DATA  
DOUT  
NOTE : tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or  
VOL level.  

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