K3N3V3000D-AE85 [SAMSUNG]
MASK ROM, 512KX8, 85ns, CMOS, PDSO32, 8 X 13.40 MM, TSOP1-32;
| 型号： | K3N3V3000D-AE85 |
| 厂家： | 
SAMSUNG |
| 描述： | MASK ROM, 512KX8, 85ns, CMOS, PDSO32, 8 X 13.40 MM, TSOP1-32 有原始数据的样本ROM 光电二极管 内存集成电路 |
| 文件： | 总3页 (文件大小：44K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K3N3V(U)3000D-AC(E)
CMOS MASK ROM
4M-Bit (512Kx8) CMOS MASK ROM
FEATURES
GENERAL DESCRIPTION
· 524,288 x 8 bit organization
· Fast access time(CL=30pF)
3.3V Operation : 85ns(Max.)
3.0V Operation : 95ns(Max.)
· Supply voltage : single +3.0V/ single +3.3V
· Current consumption
Operating : 25mA(Max.)
Standby : 30mA(Max.)
· Fully static operation
· All inputs and outputs TTL compatible
· Three state outputs
The K3N3V(U)3000D-AC(E) is fully static mask programma-
ble ROM organized 524,288 x 8 bit. It is fabricated using silicon
gate CMOS process technoiogy.
This device operates with 3.0V or 3.3V power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3N3V(U)3000D-AC(E) is packaged in a 32-sTSOP1.
· Package
-. K3N3V(U)3000D-AC(E) : 32-sTSOP1-0813.4
PRODUCT INFORMATION
FUNCTIONAL BLOCK DIAGRAM
Operating
Temp Range
Vcc Range
(Typical)
Speed
(ns)
Product
A18
X
MEMORY CELL
MATRIX
BUFFERS
AND
K3N3V(U)3000D-AC
0°C~70°C
.
.
.
.
.
.
.
.
3.3V/3.0V
85/95
(524,288x8)
K3N3V(U)3000D-AE -20°C~85°C
DECODER
Y
SENSE AMP.
BUFFERS
BUFFERS
AND
DECODER
A0
PIN CONFIGURATION
. . .
A11
A9
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
VSS
Q2
Q1
Q0
A0
#1
#32
A8
CE
OE
Q0
Q7
CONTROL
LOGIC
A13
A14
A17
N.C
VCC
A18
A16
A15
A12
A7
32-sTSOP1
Pin Name
A0 - A18
Q0 - Q7
CE
Pin Function
Address Inputs
Data Outputs
Chip Enable
Output Enable
Power
A6
A1
A5
A2
#17
A4
#16
A3
OE
VCC
K3N3V(U)3000D-AC(E)
VSS
Ground
N.C
No Connection
K3N3V(U)3000D-AC(E)
CMOS MASK ROM
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Rating
-0.3 to +4.5
-10 to +85
-55 to +150
0 to +70
Unit
V
Remark
Voltage on Any Pin Rela-
Temperature Under Bias
Storage Temperature
VIN
-
TBIAS
TSTG
°C
°C
°C
°C
-
-
K3N3V(U)3000D-AC
K3N3V(U)3000D-AE
Operating Temperature
TA
-20 to +85
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS)
Item
Symbol
Min
2.7/3.0
0
Typ
3.0/3.3
0
Max
3.3/3.6
0
Unit
V
VCC
Supply Voltage
VSS
V
DC CHARACTERISTICS
Min
Max
Parameter
Symbol
Test Conditions
Unit
mA
mA
mA
mA
mA
mA
V
VCC=3.3±0.3V
VCC=3.0±0.3V
-
25
20
Cycle=5MHz, all outputs open, CE=OE=VIL,
VIN=0.45V to 2.4V (AC Test Condition)
Operating Current
ICC
-
Standby Current(TTL)
ISB1
ISB2
ILI
CE=VIH, all outputs open
CE=VCC, all outputs open
VIN=0 to VCC
-
-
500
30
Standby Current(CMOS)
Input Leakage Current
-
10
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
ILO
VOUT=0 to VCC
-
10
VIH
VIL
2.0
-0.3
2.4
-
VCC+0.3
0.6
V
VOH
VOL
IOH=-400mA
-
V
IOL=2.1mA
0.4
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE
OE
X
Mode
Data
High-Z
High-Z
Dout
Power
Standby
Active
H
Standby
Operating
Operating
H
L
L
Active
K3N3V(U)3000D-AC(E)
CMOS MASK ROM
CAPACITANCE(TA=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
Test Conditions
VOUT=0V
Min
Max
10
Unit
pF
COUT
CIN
-
-
VIN=0V
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
AC CHARACTERISTICS(VCC=3.3V/3.0V±0.3V, unless otherwise noted.)
TEST CONDITIONS
Item
Value
0.45V to 2.4V
10ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
1.5V
1 TTL Gate and CL=30pF
READ CYCLE
Item
VCC=3.3V±0.3V
VCC=3.0V±0.3V
Symbol
Unit
Min
85
Max
Min
95
Max
Read Cycle Time
tRC
tACE
tAA
ns
ns
ns
ns
Chip Enable Access Time
Address Access Time
Output Enable Access Time
85
85
40
95
95
40
tOE
Output or Chip Disable to
Output High-Z
tDF
tOH
20
20
ns
ns
Output Hold from Address Change
0
0
TIMING DIAGRAM
READ
ADD1
ADD2
ADD
tRC
tDF(Note)
tACE
CE
tOE
tAA
OE
tOH
DOUT
VALID DATA
VALID DATA
NOTE : tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
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