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K3N6C3000E-DC10 [SAMSUNG]

MASK ROM, 4MX8, 100ns, CMOS, PDIP42, 0.600 INCH, DIP-42;
K3N6C3000E-DC10
型号： K3N6C3000E-DC10
厂家： SAMSUNG    SAMSUNG
描述：

MASK ROM, 4MX8, 100ns, CMOS, PDIP42, 0.600 INCH, DIP-42

有原始数据的样本ROM 光电二极管 内存集成电路
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K3N6C3000E-DC  
CMOS MASK ROM  
32M-Bit (4Mx8) CMOS MASK ROM  
FEATURES  
GENERAL DESCRIPTION  
· 4,194,304x8 bit organization  
· Fast access time  
The K3N6C3000E-DC is a fully static mask programmable  
ROM organized 4,194,304x8 bit. It is fabricated using silicon-  
gate CMOS process technology.  
100ns(Max.) : CL=50pF  
120ns(Max.) : CL=100pF  
· Supply voltage : single +5V  
· Current consumption  
Operating : 50mA(Max.)  
Standby : 50mA(Max.)  
· Fully static operation  
This device operates with a 5V single power supply, and all  
inputs and outputs are TTL compatible.  
Because of its asynchronous operation, it requires no external  
clock assuring extremely easy operation.  
It is suitable for use in program memory of microprocessor and  
data memory, character generator.  
· All inputs and outputs TTL compatible  
· Three state outputs  
The K3N6C3000E-DC is packaged in a 42-DIP.  
· Package  
-. K3N6C3000E-DC : 42-DIP-600  
FUNCTIONAL BLOCK DIAGRAM  
PIN CONFIGURATION  
A21  
X
MEMORY CELL  
MATRIX  
A19  
A18  
A8  
1
2
3
4
42  
41  
40  
39  
A20  
A9  
BUFFERS  
AND  
.
.
.
.
.
.
.
.
(4,194,304x8)  
A10  
A11  
DECODER  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
5
6
38 A12  
37 A13  
Y
SENSE AMP.  
BUFFERS  
7
36  
35  
34  
33  
A14  
A15  
BUFFERS  
AND  
8
9
A16  
A17  
DECODER  
A0  
10  
11  
12  
13  
14  
15  
16  
DIP  
CE  
32 A21  
VSS  
.
. .  
VSS  
A0  
31  
30  
29  
28  
27  
OE  
Q0  
Q7  
Q0  
Q7  
CE  
OE  
CONTROL  
LOGIC  
N.C  
Q1  
N.C  
Q6  
N.C  
17  
18  
19  
20  
21  
26 N.C  
Q2  
N.C  
Q3  
Q5  
25  
24  
23  
22  
N.C  
Q4  
Pin Name  
A0 - A21  
Q0 - Q7  
CE  
Pin Function  
Address Inputs  
N.C  
VCC  
Data Outputs  
Chip Enable  
Output Enable  
Power (+5V)  
Ground  
K3N6C3000E-DC  
OE  
VCC  
VSS  
K3N6C3000E-DC  
CMOS MASK ROM  
ABSOLUTE MAXIMUM RATINGS  
Item  
Symbol  
VIN  
Rating  
Unit  
Voltage on Any Pin Relative to VSS  
Temperature Under Bias  
Storage Temperature  
-0.3 to +7.0  
-10 to +85  
-55 to +150  
V
TBIAS  
TSTG  
°C  
°C  
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the  
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may  
affect device reliability.  
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)  
Item  
Supply Voltage  
Symbol  
Min  
4.5  
0
Typ  
5.0  
0
Max  
5.5  
0
Unit  
V
VCC  
Supply Voltage  
VSS  
V
DC CHARACTERISTICS  
Parameter  
Symbol  
Test Conditions  
Cycle=5MHz, all outputs open  
CE=OE=VIL, VIN=0.6V to 2.4V (AC Test Condition)  
CE=VIH, all outputs open  
CE=VCC, all outputs open  
VIN=0 to VCC  
Min  
Max  
Unit  
Operating Current  
ICC  
-
50  
mA  
Standby Current(TTL)  
ISB1  
ISB2  
ILI  
-
-
1
50  
mA  
mA  
mA  
mA  
V
Standby Current(CMOS)  
Input Leakage Current  
-
10  
Output Leakage Current  
Input High Voltage, All Inputs  
Input Low Voltage, All Inputs  
Output High Voltage Level  
Output Low Voltage Level  
ILO  
VOUT=0 to VCC  
-
10  
VIH  
VIL  
2.2  
-0.3  
2.4  
-
VCC+0.3  
0.8  
V
IOH=-400mA  
VOH  
VOL  
-
V
IOL=2.1mA  
0.4  
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.  
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.  
MODE SELECTION  
CE  
OE  
X
Mode  
Data  
High-Z  
High-Z  
Dout  
Power  
Standby  
Active  
H
L
L
Standby  
Operating  
Operating  
H
L
Active  
CAPACITANCE(TA=25°C, f=1.0MHz)  
Item  
Output Capacitance  
Input Capacitance  
Symbol  
Test Conditions  
VOUT=0V  
Min  
Max  
12  
Unit  
COUT  
CIN  
-
-
pF  
pF  
VIN=0V  
12  
NOTE : Capacitance is periodically sampled and not 100% tested.  
K3N6C3000E-DC  
CMOS MASK ROM  
AC CHARACTERISTICS(TA=0°C to +70°C,VCC=5V±10%, unless otherwise noted.)  
TEST CONDITIONS  
Item  
Value  
0.6V to 2.4V  
Input Pulse Levels  
Input Rise and Fall Times  
Input and Output timing Levels  
Output Loads  
10ns  
0.8V and 2.0V  
1 TTL Gate and CL=50pF or 100pF  
READ CYCLE  
K3N6C3000E-DC10  
(CL=50pF)  
K3N6C3000E-DC12  
(CL=100pF)  
K3N6C3000E-DC15  
(CL=100pF)  
Item  
Symbol  
Unit  
Min  
Max  
Min  
Max  
Min  
150  
Max  
Read Cycle Time  
tRC  
tACE  
tAA  
100  
120  
ns  
ns  
ns  
ns  
Chip Enable Access Time  
Address Access Time  
Output Enable Access Time  
100  
100  
50  
120  
120  
60  
150  
150  
70  
tOE  
Output or Chip Disable to  
Output High-Z  
tDF  
tOH  
20  
20  
30  
ns  
ns  
Output Hold from Address Change  
0
0
0
TIMING DIAGRAM  
READ  
ADD1  
ADD2  
ADD  
tRC  
tDF(Note)  
tACE  
CE  
tOE  
tAA  
OE  
tOH  
DOUT  
VALID DATA  
VALID DATA  
NOTE : tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.  

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