K3N6U4000E-DC12 [SAMSUNG]
MASK ROM, 2MX16, 120ns, CMOS, PDIP42, 0.600 INCH, DIP-42;型号: | K3N6U4000E-DC12 |
厂家: | SAMSUNG |
描述: | MASK ROM, 2MX16, 120ns, CMOS, PDIP42, 0.600 INCH, DIP-42 有原始数据的样本ROM 光电二极管 |
文件: | 总3页 (文件大小:46K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K3N6V(U)4000E-DC
CMOS MASK ROM
32M-Bit (2Mx16) CMOS MASK ROM
FEATURES
GENERAL DESCRIPTION
· 2,097,152x16 bit organization
· Fast access time
3.3V Operation : 100ns(Max.)@CL=50pF,
120ns(Max.)@CL=100pF
3.0V Operation : 120ns(Max.)@CL=100pF
· Supply voltage : single +3.0V/ single +3.3V
· Current consumption
Operating : 40mA(Max.)
Standby : 30mA(Max.)
· Fully static operation
The K3N6V(U)4000E-DC is a fully static mask programmable
ROM organized 2,097,152x16 bit. It is fabricated using silicon-
gate CMOS process technology.
This device operates with 3.0V or 3.3V power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor and
data memory, character generator.
The K3N6V(U)4000E-DC is packaged in a 42-DIP.
· All inputs and outputs TTL compatible
· Three state outputs
· Package
-. K3N6V(U)4000E-DC : 42-DIP-600
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
A20
X
MEMORY CELL
MATRIX
A18
A17
A7
1
2
42
41
40
A19
A8
BUFFERS
AND
.
.
.
.
.
.
.
.
(2,097,152x16)
3
A9
DECODER
A6
A5
A4
A3
4
39 A10
38 A11
5
6
A12
37
36
35
34
33
Y
SENSE AMP.
BUFFERS
7
A13
A14
A15
A16
BUFFERS
AND
A2
A1
8
9
DECODER
A0
A0
10
11
12
DIP
CE
VSS
OE
Q0
32 A20
.
. .
VSS
Q15
Q7
31
30
29
28
27
13
14
15
16
17
18
19
20
Q0
Q15
CE
OE
CONTROL
LOGIC
Q8
Q14
Q6
Q1
Q9
26 Q13
Q2
Q10
Q3
Q5
25
24
23
22
Q12
Q4
Pin Name
A0 - A20
Q0 - Q15
CE
Pin Function
Address Inputs
Q11
21
VCC
Data Outputs
Chip Enable
Output Enable
Power
K3N6V(U)4000E-DC
OE
VCC
VSS
Ground
K3N6V(U)4000E-DC
CMOS MASK ROM
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
VIN
Rating
Unit
Voltage on Any Pin Relative to VSS
Temperature Under Bias
Storage Temperature
-0.3 to +4.5
-10 to +85
-55 to +150
V
TBIAS
TSTG
°C
°C
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item
Supply Voltage
Symbol
Min
2.7/3.0
0
Typ
3.0/3.3
0
Max
3.3/3.6
0
Unit
V
VCC
Supply Voltage
VSS
V
DC CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Max
Unit
mA
mA
mA
mA
mA
mA
V
VCC=3.3V±0.3V
-
40
35
Cycle=5MHz, all outputs open, CE=OE=VIL,
VIN=0.45V to 2.4V (AC Test Condition)
Operating Current
ICC
VCC=3.0V±0.3V
Standby Current(TTL)
ISB1
ISB2
ILI
CE=VIH, all outputs open
CE=VCC, all outputs open
VIN=0 to VCC
500
30
Standby Current(CMOS)
Input Leakage Current
-
-
10
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
ILO
VOUT=0 to VCC
10
VIH
VIL
2.0
-0.3
2.4
-
VCC+0.3
0.6
V
IOH=-400mA
VOH
VOL
-
V
IOL=2.1mA
0.4
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE
OE
X
Mode
Data
High-Z
High-Z
Dout
Power
Standby
Active
H
L
L
Standby
Operating
Operating
H
L
Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
Test Conditions
VOUT=0V
Min
Max
12
Unit
COUT
CIN
-
-
pF
pF
VIN=0V
12
NOTE : Capacitance is periodically sampled and not 100% tested.
K3N6V(U)4000E-DC
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=3.3V/3.0V±0.3V, unless otherwise noted.)
TEST CONDITIONS
Item
Value
Input Pulse Levels
0.45V to 2.4V
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
10ns
1.5V
1 TTL Gate and CL=50pF or 100pF
READ CYCLE
K3N6V4000E-DC10
(CL=50pF)
K3N6V4000E-DC12
(CL=100pF)
K3N6U4000E-DC12
(CL=100pF)
Item
Symbol
Unit
Min
Max
Min
Max
Min
120
Max
Read Cycle Time
tRC
tACE
tAA
100
120
ns
ns
ns
ns
Chip Enable Access Time
Address Access Time
Output Enable Access Time
100
100
50
120
120
60
120
120
60
tOE
Output or Chip Disable to
Output High-Z
tDF
tOH
20
20
20
ns
ns
Output Hold from Address Change
0
0
0
TIMING DIAGRAM
READ
ADD1
ADD2
ADD
tRC
tDF(Note)
tACE
CE
tAA
tOE
OE
tOH
DOUT
VALID DATA
VALID DATA
NOTE : tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
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