K3N7V1000B-YC12 [SAMSUNG]
MASK ROM, 4MX16, 120ns, CMOS, PDSO48, 12 X 18 MM, TSOP1-48;型号: | K3N7V1000B-YC12 |
厂家: | SAMSUNG |
描述: | MASK ROM, 4MX16, 120ns, CMOS, PDSO48, 12 X 18 MM, TSOP1-48 有原始数据的样本ROM 光电二极管 内存集成电路 |
文件: | 总4页 (文件大小:55K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K3N7V(U)1000B-YC
CMOS MASK ROM
64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM
FEATURES
GENERAL DESCRIPTION
· Switchable organization
8,388,608 x 8(byte mode)
4,194,304 x 16(word mode)
· Fast access time
3.3V Operation : 100ns(Max.)@CL=50pF,
120ns(Max.)@CL=100pF
3.0V Operation : 120ns(Max.)@CL=100pF
· Supply voltage : single +3.0V/ single +3.3V
· Current consumption
The K3N7V(U)1000B-YC is a fully static mask programmable
ROM fabricated using silicon gate CMOS process technology,
and is organized either as 8,388,608 x 8 bit(byte mode) or as
4,194,304 x 16 bit(word mode) depending on BHE voltage
level.(See mode selection table)
This device operates with 3.0V or 3.3V power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
Operating : 40mA(Max.)
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
Standby : 50mA(Max.)
· Fully static operation
· All inputs and outputs TTL compatible
· Three state outputs
The K3N7V(U)1000B-YC is packaged in a 48-TSOP1.
· Package
K3N7V(U)1000B-YC : 48-TSOP1-1218
FUNCTIONAL BLOCK DIAGRAM
Pin Name
A0 - A21
Pin Function
Address Inputs
A21
X
MEMORY CELL
MATRIX
BUFFERS
AND
Q0 - Q14
Data Outputs
.
.
.
.
.
.
.
.
(4,194,304x16/
8,388,608x8)
Output 15(Word mode)/
LSB Address(Byte mode)
Q15 /A-1
DECODER
BHE
CE
Word/Byte selection
Chip Enable
Output Enable
Power
Y
SENSE AMP.
OE
BUFFERS
AND
VCC
Vss
N.C
DATA OUT
BUFFERS
Ground
DECODER
A0
No Connection
A-1
.
.
.
CE
Q0/Q8
Q7/Q15
CONTROL
LOGIC
OE
BHE
K3N7V(U)1000B-YC
CMOS MASK ROM
PIN CONFIGURATION
VSS
48
BHE
A16
A15
A14
A13
A12
A11
A10
A9
A8 10
A19
A21
A20
A18
A17
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
47 VSS
46 Q15/A-1
45 Q7
44 Q14
Q6
42 Q13
Q5
43
41
40 Q12
Q4
VCC
VCC
39
38
37
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TSOP1
36 N.C
Q11
34 Q3
Q10
Q2
31 Q9
30 Q1
29 Q8
Q0
28
27 OE
VSS
25 VSS
35
33
32
A3
A2
A1
A0
26
CE
K3N7V(U)1000B-YC
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
VIN
Rating
Unit
V
Voltage on Any Pin Relative to VSS
Temperature Under Bias
Storage Temperature
-0.3 to +4.5
-10 to +85
-55 to +150
TBIAS
TSTG
°C
°C
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item
Supply Voltage
Symbol
Min
2.7/3.0
0
Typ
3.0/3.3
0
Max
3.3/3.6
0
Unit
V
VCC
Supply Voltage
VSS
V
DC CHARACTERISTICS
Min
Max
Parameter
Symbol
Test Conditions
Unit
mA
mA
mA
mA
mA
mA
V
VCC=3.3V±0.3V
VCC=3.0V±0.3V
-
40
35
Cycle=5MHZ, all outputs open, CE=OE=VIL,
VIN=0.45V to 2.4V (AC Test Condition)
Operating Current
ICC
Standby Current(TTL)
ISB1
ISB2
ILI
CE=VIH, all outputs open
CE=VCC, all outputs open
VIN=0 to VCC
500
50
Standby Current(CMOS)
Input Leakage Current
-
-
10
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
ILO
VOUT=0 to VCC
10
VIH
VIL
2.0
-0.3
2.4
-
VCC+0.3
0.6
V
IOH=-400mA
VOH
VOL
-
V
IOL=2.1mA
0.4
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
K3N7V(U)1000B-YC
CMOS MASK ROM
MODE SELECTION
CE
H
OE
X
BHE
X
Q15/A-1
Mode
Data
High-Z
Power
Standby
Active
X
X
Standby
Operating
Operating
L
H
X
High-Z
H
Output
Q0~Q15 : Dout
Active
L
L
Q0~Q7 : Dout
Q8~Q14 : Hi-Z
L
Input
Operating
Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
Test Conditions
VOUT=0V
Min
Max
12
Unit
pF
COUT
CIN
-
-
VIN=0V
12
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
AC CHARACTERISTICS(TA=0°C to +70°C,VCC=3.3V/3.0V±0.3V, unless otherwise noted.)
TEST CONDITIONS
Item
Value
Input Pulse Levels
0.45V to 2.4V
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
10ns
1.5V
1 TTL Gate and CL=50pF or 100pF
READ CYCLE
K3N7V1000B-YC10
(CL=50pF)
K3N7V1000B-YC12
(CL=100pF)
K3N7U1000B-YC12
(CL=100pF)
Item
Symbol
Unit
Min
Max
Min
Max
Min
120
Max
Read Cycle Time
tRC
tACE
tAA
100
120
ns
ns
ns
ns
Chip Enable Access Time
Address Access Time
Output Enable Access Time
100
100
50
120
120
60
120
120
60
tOE
Output or Chip Disable to
Output High-Z
tDF
tOH
20
20
20
ns
ns
Output Hold from Address Change
0
0
0
K3N7V(U)1000B-YC
CMOS MASK ROM
TIMING DIAGRAM
READ
ADD
ADD1
ADD2
A0~A21
A-1(*1)
tRC
tDF(*3)
tACE
CE
tOE
tAA
OE
tOH
DOUT
D0~D7
VALID DATA
VALID DATA
D8~D15(*2)
NOTES :
*1.Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL)
*2. Word Mode only.(BHE = VIH)
*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
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