K3P4C1000E-TC150 [SAMSUNG]
MASK ROM, 512KX16, 150ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44;
| 型号： | K3P4C1000E-TC150 |
| 厂家： | 
SAMSUNG |
| 描述： | MASK ROM, 512KX16, 150ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44 有原始数据的样本ROM 光电二极管 |
| 文件： | 总4页 (文件大小：37K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K3P4C1000E-TC
CMOS MASK ROM
8M-Bit (1Mx8 / 512Kx16) CMOS MASK ROM
FEATURES
GENERAL DESCRIPTION
· Switchable organization
1,048,576 x 8(byte mode)
524,288 x 16(word mode)
· Fast access time
Random Access : 100ns(Max.)@CL=50pF,
120ns(Max.)@CL=100pF
The K3P4C1000E-TC is a fully static mask programmable ROM
fabricated using silicon gate CMOS process technology, and is
organized either as 1,048,576 x 8(byte mode) or as 524,288 x
16(word mode) depending on BHE voltage level.(See mode
selection table)
This device includes page read mode function, page read mode
allows 4 words (or 8 bytes) of data to read fast in the same
page, CE and A2 ~ A18 should not be changed.
Page Access
: 30ns(Max.)@CL=50pF
40ns(Max.)@CL=100pF
4 Words / 8 Bytes page access
· Supply voltage : single +5V
· Current consumption
This device operates with a 5V single power supply, and all
inputs and outputs are TTL compatible.
Operating : 80mA(Max.)
Standby : 50mA(Max.)
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
· Fully static operation
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
· All inputs and outputs TTL compatible
· Three state outputs
· Package
The K3P4C1000E-TC is packaged in a 44-TSOP2.
-. K3P4C1000E-TC : 44-TSOP2-400
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
N.C
A18
A17
A7
N.C
N.C
1
2
3
4
5
6
7
8
9
44
43
A18
X
MEMORY CELL
MATRIX
(524,288x16/
1,048,576x8)
BUFFERS
AND
DECODER
.
.
.
.
.
.
.
.
42 A8
A9
41
A6
A5
40 A10
39 A11
38 A12
37 A13
A4
A3
A2
Y
SENSE AMP.
DATA OUT
BUFFERS
BUFFERS
AND
DECODER
A14
A15
36
35
A1 10
A0 11
CE 12
A2
34 A16
TSOP2
33 BHE
32 VSS
A0~A1
A-1
. . .
VSS
13
OE 14
31 Q15/A-1
CE
Q0
Q7
30
15
Q0/Q8
Q7/Q15
CONTROL
LOGIC
Q8 16
29 Q14
28 Q6
27 Q13
26 Q5
25 Q12
OE
Q1
Q9
17
18
19
BHE
Q2
Q10 20
Q3
Q4
21
22
24
23
Pin Name
A0 - A1
Pin Function
Q11
VCC
Page Address Inputs
A2 - A18
Address Inputs
Data Outputs
K3P4C1000E-TC
Q0 - Q14
Output 15(Word mode)/
LSB Address(Byte mode)
Q15 /A-1
BHE
CE
Word/Byte selection
Chip Enable
OE
Output Enable
Power ( +5V)
Ground
VCC
VSS
N.C
No Connection
K3P4C1000E-TC
CMOS MASK ROM
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
VIN
Rating
Unit
Remark
Voltage on Any Pin Relative to VSS
Temperature Under Bias
Storage Temperature
-0.3 to +7.0
-10 to +85
-55 to +150
V
-
-
-
TBIAS
TSTG
°C
°C
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item
Symbol
Min
4.5
0
Typ
5.0
0
Max
5.5
0
Unit
V
Supply Voltage
VCC
Supply Voltage
VSS
V
DC CHARACTERISTICS
Parameter
Symbol
Test Conditions
Cycle=5MHz, all outputs open
CE=OE=VIL, VIN=0V to 3V (AC Test Condition)
CE=VIH, all outputs open
CE=VCC, all outputs open
VIN=0 to VCC
Min
Max
Unit
Operating Current
ICC
-
80
mA
Standby Current(TTL)
ISB1
ISB2
ILI
1
50
mA
mA
mA
mA
V
Standby Current(CMOS)
Input Leakage Current
-
-
10
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
ILO
VOUT=0 to VCC
10
VIH
VIL
2.2
-0.3
2.4
-
VCC+0.3
0.8
V
VOH
VOL
IOH=-400mA
-
V
IOL=2.1mA
0.4
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE
OE
BHE
X
Q15/A-1
Mode
Data
High-Z
Power
H
L
X
H
X
X
Standby
Standby
Active
X
Operating
Operating
High-Z
H
Output
Q0~Q15 : Dout
Active
L
L
Q0~Q7 : Dout
Q8~Q14 : Hi-Z
L
Input
Operating
Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
Test Conditions
VOUT=0V
Min
Max
12
Unit
pF
COUT
CIN
-
-
VIN=0V
12
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
K3P4C1000E-TC
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS
Item
Value
0V to 3V
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
10ns
0.8V and 2.0V
1 TTL Gate and CL=50pF or 100pF
READ CYCLE
K3P4C1000E-TC10
(CL=50pF)
K3P4C1000E-TC12
(CL=100pF)
K3P4C1000E-TC15
(CL=100pF)
Item
Symbol
Unit
Min
Max
Min
Max
Min
150
Max
Read Cycle Time
tRC
tACE
tAA
100
120
ns
ns
ns
ns
ns
Chip Enable Access Time
Address Access Time
100
100
30
120
120
40
150
150
50
Page Address Access Time
Output Enable Access Time
tPA
tOE
30
40
50
Output or Chip Disable to
Output High-Z
tDF
tOH
20
20
30
ns
ns
Output Hold from Address Change
0
0
0
NOTE : Page Address is determined as below.
Word mode(BHE=VIH) ; A0, A1
Byte mode(BHE=VIL) ; A-1, A0, A1
K3P4C1000E-TC
CMOS MASK ROM
TIMING DIAGRAM
READ
ADD
A0~A18
ADD1
ADD2
A-1(*1)
tRC
tDF(*3)
tACE
CE
OE
tOE
tAA
tOH
DOUT
D0~D7
VALID DATA
VALID DATA
D8~D15(*2)
PAGE READ
CE
tDF(*3)
OE
ADD
A2~A18
ADD
A0,A1
1 st
2 nd
3 rd
A-1(*1)
tAA
tPA
DOUT
D0~D7
VALID DATA
VALID DATA
VALID DATA
VALID DATA
D8~D15(*2)
NOTES
:
*1. Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL)
*2. Word Mode only.(BHE = VIH)
*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
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