K3P9V4000A-GC12 [SAMSUNG]
MASK ROM, 8MX16, 120ns, CMOS, PDSO44, 0.600 INCH, SOP-44;
| 型号： | K3P9V4000A-GC12 |
| 厂家： | 
SAMSUNG |
| 描述： | MASK ROM, 8MX16, 120ns, CMOS, PDSO44, 0.600 INCH, SOP-44 有原始数据的样本ROM 光电二极管 内存集成电路 |
| 文件： | 总4页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K3P9V(U)4000A-GC
CMOS MASK ROM
128M-Bit (8Mx16) CMOS MASK ROM
FEATURES
· 8,388,608 x 16 bit organization
· Fast access time
Random Access Time/Page Access Time
3.3V Operation : 100/30ns(Max.)@CL=50pF,
120/40ns(Max.)@CL=100pF
3.0V Operation : 120/40ns(Max.)@CL=100pF
8 Words / 16 Bytes page access
· Supply voltage : single +3.0V/ single +3.3V
· Current consumption
GENERAL DESCRIPTION
The K3P9V(U)4000A-GC is a fully static mask programmable
ROM organized as 8,388,608 x 16 bit. It is fabricated using sili-
con gate CMOS process technology.
This device includes page read mode function, page read mode
allows 8 words of data to read fast in the same page, CE and
A3 ~ A22 should not be changed.
This device operates with 3.0V or 3.3V power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
Operating : 80mA(Max.)
Standby : 30mA(Max.)
· Fully static operation
· All inputs and outputs TTL compatible
· Three state outputs
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3P9V(U)4000A-GC is packaged in a 44-SOP.
· Package
K3P9V(U)4000A-GC : 44-SOP-600
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
A22
X
MEMORY CELL
MATRIX
(8,388,608x16)
BUFFERS
AND
DECODER
A20
.
.
.
.
.
.
.
.
1
2
44
43
42
41
A21
A18
A19
A8
A17
A7
3
4
A9
A6
A5
A4
A3
40 A10
5
A11
39
SENSE AMP.
6
Y
A12
7
38
37
36
35
34
33
32
31
30
BUFFERS
AND
DECODER
DATA OUT
BUFFERS
8
A13
A14
A15
A2
A1
9
A3
10
11
12
13
14
15
16
17
18
A0
A16
A0~A2
A22
VSS
Q15
Q7
CE
VSS
OE
Q0
.
. .
SOP
Q0
Q15
CE
OE
CONTROL
LOGIC
Q8
29 Q14
28 Q6
Q1
Q9
Q13
Q5
27
26
25
24
23
Q2 19
Q10 20
Q12
Q4
Pin Name
A0 - A2
A3 - A22
Q0 - Q15
CE
Pin Function
Page Address Inputs
Q3
21
22
Q11
VCC
Address Inputs
Data Outputs
Chip Enable
Output Enable
Power
K3P9V(U)4000A-GC
OE
VCC
VSS
Ground
K3P9V(U)4000A-GC
CMOS MASK ROM
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
VIN
Rating
Unit
Voltage on Any Pin Relative to VSS
Temperature Under Bias
Storage Temperature
-0.3 to +4.5
-10 to +85
-55 to +150
V
TBIAS
TSTG
°C
°C
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item
Min
2.7/3.0
0
Symbol
VCC
Typ
3.0/3.3
0
Max
3.3/3.6
0
Unit
V
Supply Voltage
Supply Voltage
VSS
V
DC CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Max
Unit
mA
mA
mA
mA
mA
mA
V
VCC=3.3V±0.3V
VCC=3.0V±0.3V
-
80
70
Cycle=5MHZ, all outputs open, CE=OE=VIL,
VIN=0.45V to 2.4V (AC Test Condition)
Operating Current
ICC
-
Standby Current(TTL)
ISB1
ISB2
ILI
CE=VIH, all outputs open
CE=VCC, all outputs open
VIN=0 to VCC
-
-
500
30
Standby Current(CMOS)
Input Leakage Current
-
10
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
ILO
VOUT=0 to VCC
-
10
VIH
VIL
2.0
-0.3
2.4
-
VCC+0.3
0.6
-
V
IOH=-400mA
VOH
VOL
V
IOL=2.1mA
0.4
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE
OE
X
Mode
Data
High-Z
High-Z
Dout
Power
Standby
Active
H
L
L
Standby
Operating
Operating
H
L
Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
Test Conditions
VOUT=0V
Min
Max
12
Unit
COUT
CIN
-
-
pF
pF
VIN=0V
12
NOTE : Capacitance is periodically sampled and not 100% tested.
K3P9V(U)4000A-GC
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=3.3V/3.0V±0.3V, unless otherwise noted.)
TEST CONDITIONS
Item
Value
Input Pulse Levels
0.45V to 2.4V
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
10ns
1.5V
1 TTL Gate and CL=50pF or 100pF
READ CYCLE
Item
K3P9V4000A-GC10
(CL=50pF)
K3P9V4000A-GC12
(CL=100pF)
K3P9U4000A-GC12
(CL=100pF)
Symbol
Unit
Min
Max
Min
Max
Min
120
Max
Read Cycle Time
tRC
tACE
tAA
100
120
ns
ns
ns
ns
ns
Chip Enable Access Time
Address Access Time
100
100
30
120
120
40
120
120
40
Page Address Access Time
Output Enable Access Time
tPA
tOE
30
40
40
Output or Chip Disable to
Output High-Z
tDF
20
20
20
ns
ns
Output Hold from Address Change
tOH
0
0
0
NOTE : Page Address is determined as A0, A1, A2
K3P9V(U)4000A-GC
CMOS MASK ROM
TIMING DIAGRAM
READ
ADD
ADD1
ADD2
A0~A22
tRC
tDF(*3)
tACE
CE
tOE
tAA
OE
tOH
DOUT
VALID DATA
VALID DATA
D0~D15
PAGE READ
CE
OE
tDF(*1)
ADD
A3~A22
ADD
1 st
2 nd
3 rd
A0,A1,A2
tAA
tPA
DOUT
VALID DATA
VALID DATA
VALID DATA
VALID DATA
D0~D15
NOTES :
*1. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
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