K4B2G1646Q-BMH9 [SAMSUNG]
2Gb Q-die DDR3L SDRAM Only x16;型号: | K4B2G1646Q-BMH9 |
厂家: | SAMSUNG |
描述: | 2Gb Q-die DDR3L SDRAM Only x16 动态存储器 双倍数据速率 |
文件: | 总71页 (文件大小:1760K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Rev. 1.02, Aug. 2014
K4B2G1646Q
2Gb Q-die DDR3L SDRAM Only x16
96FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
1.35V
datasheet
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SPECIFICATIONS WITHOUT NOTICE.
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- 1 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
Revision History
Revision No.
History
Draft Date
Aug. 2013
Jan. 2014
Aug. 2014
Remark
Editor
S.H.Kim
S.H.Kim
J.Y.Lee
1.0
- First Spec. Release
-
-
-
1.01
1.02
- Corrected typo.
- Corrected typo.
- 2 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
Table Of Contents
2Gb Q-die DDR3L SDRAM Only x16
1. Ordering Information.....................................................................................................................................................5
2. Key Features.................................................................................................................................................................5
3. Package pinout/Mechanical Dimension & Addressing..................................................................................................6
3.1 x16 Package Pinout (Top view) : 96ball FBGA Package ........................................................................................6
3.2 FBGA Package Dimension (x16).............................................................................................................................7
4. Input/Output Functional Description..............................................................................................................................8
5. DDR3 SDRAM Addressing ...........................................................................................................................................9
6. Absolute Maximum Ratings ..........................................................................................................................................10
6.1 Absolute Maximum DC Ratings...............................................................................................................................10
6.2 DRAM Component Operating Temperature Range ................................................................................................10
7. AC & DC Operating Conditions.....................................................................................................................................10
7.1 Recommended DC operating Conditions................................................................................................................10
8. AC & DC Input Measurement Levels............................................................................................................................11
8.1 AC & DC Logic input levels for single-ended signals ..............................................................................................11
8.2 VREF Tolerances ....................................................................................................................................................13
8.3 AC & DC Logic Input Levels for Differential Signals................................................................................................14
8.3.1. Differential signals definition ............................................................................................................................14
8.3.2. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)...................................................14
8.3.3. Single-ended requirements for differential signals...........................................................................................16
8.4 Differential Input Cross Point Voltage......................................................................................................................17
8.5 Slew rate definition for Differential Input Signals.....................................................................................................18
8.6 Slew rate definitions for Differential Input Signals ...................................................................................................18
9. AC & DC Output Measurement Levels .........................................................................................................................18
9.1 Single-ended AC & DC Output Levels.....................................................................................................................18
9.2 Differential AC & DC Output Levels.........................................................................................................................18
9.3 Single-ended Output Slew Rate ..............................................................................................................................19
9.4 Differential Output Slew Rate ..................................................................................................................................20
9.5 Reference Load for AC Timing and Output Slew Rate............................................................................................20
9.6 Overshoot/Undershoot Specification.......................................................................................................................21
9.6.1. Address and Control Overshoot and Undershoot specifications......................................................................21
9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications......................................................22
9.7 34ohm Output Driver DC Electrical Characteristics.................................................................................................23
9.7.1. Output Drive Temperature and Voltage Sensitivity..........................................................................................25
9.8 On-Die Termination (ODT) Levels and I-V Characteristics......................................................................................25
9.8.1. ODT DC Electrical Characteristics...................................................................................................................26
9.8.2. ODT Temperature and Voltage sensitivity .......................................................................................................28
9.9 ODT Timing Definitions ...........................................................................................................................................29
9.9.1. Test Load for ODT Timings..............................................................................................................................29
9.9.2. ODT Timing Definitions....................................................................................................................................29
10. IDD Current Measure Method.....................................................................................................................................32
10.1 IDD Measurement Conditions ...............................................................................................................................32
11. 2Gb DDR3L SDRAM Q-die IDD Specification Table..................................................................................................41
12. Input/Output Capacitance ...........................................................................................................................................42
13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-1866......................................................................43
13.1 Clock Specification ................................................................................................................................................43
13.1.1. Definition for tCK(avg)....................................................................................................................................43
13.1.2. Definition for tCK(abs)....................................................................................................................................43
13.1.3. Definition for tCH(avg) and tCL(avg)..............................................................................................................43
13.1.4. Definition for note for tJIT(per), tJIT(per, Ick).................................................................................................43
13.1.5. Definition for tJIT(cc), tJIT(cc, Ick) .................................................................................................................43
13.1.6. Definition for tERR(nper)................................................................................................................................43
13.2 Refresh Parameters by Device Density.................................................................................................................44
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin.................................................................44
13.3.1. Speed Bin Table Notes ..................................................................................................................................48
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Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
14. Timing Parameters by Speed Grade ..........................................................................................................................49
14.1 Jitter Notes ............................................................................................................................................................53
14.2 Timing Parameter Notes........................................................................................................................................54
14.3 Address/Command Setup, Hold and Derating : ....................................................................................................55
14.4 Data Setup, Hold and Slew Rate Derating : ..........................................................................................................64
- 4 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
1. Ordering Information
[ Table 1 ] Samsung 2Gb DDR3L Q-die ordering information table
4
3
Organization
128Mx16
DDR3L-1333(9-9-9)
K4B2G1646Q-BYH9
K4B2G1646Q-BMH9
Package
96 FBGA
96 FBGA
DDR3L-1600(11-11-11)
K4B2G1646Q-BYK0
K4B2G1646Q-BMK0
DDR3L-1866(13-13-13)
K4B2G1646Q-BYMA
-
128Mx16
NOTE :
1. Speed bin is in order of CL-tRCD-tRP.
2. 13th digit stands for below.
"Y" : Commercial temp
"M" : Industrial temp
3. Backward compatible to DDRL3-1600(11-11-11), DDR3L-1333(9-9-9)
4. Backward compatible to DDR3L-1333(9-9-9)
2. Key Features
[ Table 2 ] 2Gb DDR3 Q-die Speed bins
DDR3-800
6-6-6
2.5
DDR3-1066
7-7-7
DDR3-1333
9-9-9
1.5
DDR3-1600
DDR3-1866
13-13-13
1.071
13
Speed
Unit
11-11-11
1.25
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
1.875
7
ns
nCK
ns
6
9
11
15
13.125
13.125
37.5
13.5
13.5
36
13.75
13.75
35
13.91
13.91
34
15
ns
tRAS(min)
tRC(min)
37.5
52.5
ns
50.625
49.5
48.75
47.91
ns
•
•
JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
= 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
The 2Gb DDR3 SDRAM Q-die is organized as a 16Mbit x 16 I/Os x 8 banks
device. This synchronous device achieves high speed double-data-rate
transfer rates of up to 1866Mb/sec/pin (DDR3-1866) for general applica-
tions.
V
DDQ
•
400 MHz f for 800Mb/sec/pin, 533MHz f for 1066Mb/sec/pin,
CK CK
667MHz f for 1333Mb/sec/pin, 800MHz f for 1600Mb/sec/pin
CK
CK
The chip is designed to comply with the following key DDR3 SDRAM fea-
tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,
On Die Termination using ODT pin and Asynchronous Reset .
933MHz f for 1866Mb/sec/pin
CK
•
•
•
•
8 Banks
Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11,13
Programmable Additive Latency: 0, CL-2 or CL-1 clock
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates
with a single 1.35V(1.28V~1.45V) or 1.5V(1.425V~1.575V) power supply
Programmable CAS Write Latency (CWL) = 5 (DDR3-800),
(DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600) and 9(DDR3-1866)
6
•
•
8-bit pre-fetch
Burst Length: 8 , 4 with tCCD = 4 which does not allow seamless read
or write [either On the fly using A12 or MRS]
•
•
Bi-directional Differential Data-Strobe
Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
and 1.35V(1.28V~1.45V) or 1.5V(1.425V~1.575V) V
.
DDQ
The 2Gb DDR3 Q-die device is available in 96balls FBGA(x16).
•
•
On Die Termination using ODT pin
Average Refresh Period 7.8us at lower than T
85C, 3.9us at
CASE
85C < T
< 95 C
CASE
•
Support Industrial Temp ( -4095C )
- tREFI 7.8us at -40 °C ≤ TCASE ≤ 85°C
- tREFI 3.9us at 85 °C < TCASE ≤ 95°C
•
•
•
•
Asynchronous Reset
Package : 96 balls FBGA - x16
All of Lead-Free products are compliant for RoHS
All of products are Halogen-free
NOTE : 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing
Diagram”.
2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
- 5 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
3. Package pinout/Mechanical Dimension & Addressing
3.1 x16 Package Pinout (Top view) : 96ball FBGA Package
1
2
3
4
5
6
7
8
9
V
V
V
SS
A
B
C
D
E
F
DQU5
DQU7
DQU4
DQSU
DQSU
DQU0
DML
A
B
C
D
E
F
DDQ
DDQ
V
V
V
V
V
V
DQU6
DQU2
SSQ
DD
SS
SSQ
DQU3
DQU1
DMU
DQL0
DQSL
DQSL
DQL4
RAS
CAS
WE
DDQ
DDQ
V
V
V
V
DD
SSQ
DDQ
SSQ
V
V
V
V
DDQ
SS
SSQ
SSQ
V
V
V
V
DQL2
DQL6
DQL1
DQL3
DDQ
SSQ
SSQ
V
V
V
G
H
J
G
H
J
SSQ
DD
SS
V
V
DQL7
CK
DQL5
REFDQ
DDQ
DDQ
V
V
NC
NC
SS
SS
V
V
K
L
ODT
NC
CK
CKE
NC
K
L
DD
DD
CS
BA0
A3
A10/AP
NC
ZQ
V
V
V
M
N
P
R
T
BA2
A0
M
N
P
R
T
SS
REFCA
SS
V
V
A12/BC
A1
BA1
DD
DD
V
V
A5
A2
A4
A6
A8
SS
SS
V
V
A7
A9
A11
DD
DD
V
V
RESET
A13
NC
SS
SS
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Ball Locations (x16)
Populated ball
Ball not populated
G
H
J
K
L
Top view
(See the balls through the package)
M
N
P
R
T
- 6 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
3.2 FBGA Package Dimension (x16)
Units : Millimeters
7.50 0.10
0.80 x 8 6.40
A
#A1 INDEX MARK
B
0.80
1.60
6
3.20
9
8
7
5 4 3 2 1
A
B
C
D
E
F
(Datum A)
(Datum B)
G
H
J
K
L
M
N
P
R
T
(0.30)
(0.60)
96 - 0.48 Solder ball
(Post Reflow 0.50 0.05)
0.2 A B
MOLDING AREA
M
BOTTOM VIEW
7.50 0.10
#A1
0.37 0.05
1.10 0.10
TOP VIEW
- 7 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
4. Input/Output Functional Description
[ Table 3 ] Input/Output function description
Symbol
Type
Function
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of
CK, CK
Input
the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and
output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or
Active Power-Down (Row Active in any bank). CKE is asynchronous for self refresh exit. After V
has become
REFCA
CKE
CS
Input
stable during the power on and initialization sequence, it must be maintained during all operations (including Self-
Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT
and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self -Refresh.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on
Input
Input
systems with multiple Ranks. CS is considered part of the command code.
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When
enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode
Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if the Mode Register (MR1) is pro-
grammed to disable ODT.
ODT
RAS, CAS, WE
Input
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci-
dent with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of
DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1.
DM
(DMU), (DML)
Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being
applied. Bank address also determines if the mode register or extended mode register is to be accessed during a
MRS cycle.
BA0 - BA2
A0 - A13
Input
Input
Address Inputs: Provided the row address for Active commands and the column address for Read/Write commands
to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions,
see below)
The address inputs also provide the op-code during Mode Register Set commands.
Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be per-
formed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge)
A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or
all banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses.
A10 / AP
A12 / BC
Input
Burst Chop:A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be per-
Input
Input
formed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details
Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH.
RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and
RESET
DQ
20% of V , i.e. 1.20V for DC high and 0.30V for DC low.
DD
Input/Output Data Input/ Output: Bi-directional data bus.
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For the
x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data
Input/Output strobe DQS, DQSL and DQSU are paired with differential signals DQS, DQSL and DQSU, respectively, to provide dif-
ferential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and
does not support single-ended.
DQS, (DQS)
Termination Data Strobe: TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in
MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When
disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/
x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1.
TDQS, (TDQS)
NC
Output
No Connect: No internal electrical connection is present.
V
Supply
Supply
Supply
Supply
Supply
Supply
Supply
DQ Power Supply: 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
DQ Ground
DDQ
V
SSQ
V
Power Supply: 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
Ground
DD
V
SS
V
Reference voltage for DQ
REFDQ
V
Reference voltage for CA
REFCA
ZQ
Reference Pin for ZQ calibration
NOTE : Input only pins (BA0-BA2, A0-A13, RAS, CAS, WE, CS, CKE, ODT and RESET) do not supply termination.
- 8 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
5. DDR3 SDRAM Addressing
1Gb
Configuration
# of Bank
256Mb x 4
8
128Mb x 8
8
64Mb x 16
8
Bank Address
Auto precharge
Row Address
BA0 - BA2
A10/AP
A0 - A13
A0 - A9,A11
A12/BC
1 KB
BA0 - BA2
A10/AP
A0 - A13
A0 - A9
A12/BC
1 KB
BA0 - BA2
A10/AP
A0 - A12
A0 - A9
A12/BC
2 KB
Column Address
BC switch on the fly
*1
Page size
2Gb
Configuration
# of Bank
512Mb x 4
8
256Mb x 8
8
128Mb x 16
8
Bank Address
Auto precharge
Row Address
BA0 - BA2
A10/AP
A0 - A14
A0 - A9,A11
A12/BC
1 KB
BA0 - BA2
A10/AP
A0 - A14
A0 - A9
A12/BC
1 KB
BA0 - BA2
A10/AP
A0 - A13
A0 - A9
A12/BC
2 KB
Column Address
BC switch on the fly
*1
Page size
4Gb
Configuration
# of Bank
1Gb x 4
8
512Mb x 8
8
256Mb x 16
8
Bank Address
Auto precharge
Row Address
BA0 - BA2
A10/AP
A0 - A15
A0 - A9,A11
A12/BC
1 KB
BA0 - BA2
A10/AP
A0 - A15
A0 - A9
A12/BC
1 KB
BA0 - BA2
A10/AP
A0 - A14
A0 - A9
A12/BC
2 KB
Column Address
BC switch on the fly
*1
Page size
8Gb
Configuration
# of Bank
2Gb x 4
8
1Gb x 8
8
512Mb x 16
8
Bank Address
Auto precharge
Row Address
BA0 - BA2
A10/AP
BA0 - BA2
A10/AP
A0 - A15
A0 - A9,A11
A12/BC
2 KB
BA0 - BA2
A10/AP
A0 - A15
A0 - A9
A12/BC
2 KB
A0 - A15
A0 - A9,A11,A13
A12/BC
Column Address
BC switch on the fly
*1
2 KB
Page size
NOTE 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered.
Page size is per bank, calculated as follows:
page size = 2 COLBITS * ORG8
where, COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits
- 9 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
6. Absolute Maximum Ratings
6.1 Absolute Maximum DC Ratings
[ Table 4 ] Absolute Maximum DC Ratings
Symbol
Parameter
Voltage on V pin relative to Vss
Rating
Units
NOTE
V
-0.4 V ~ 1.975 V
-0.4 V ~ 1.975 V
-0.4 V ~ 1.975 V
-55 to +100
V
1,3
DD
DD
V
Voltage on V
pin relative to Vss
DDQ
V
V
1,3
1
DDQ
V
V
Voltage on any pin relative to Vss
Storage Temperature
IN, OUT
T
C
1, 2
STG
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may be
equal to or less than 300mV.
6.2 DRAM Component Operating Temperature Range
[ Table 5 ] Temperature Range
Symbol
Parameter
rating
0 to 95
Unit
C
NOTE
1, 2, 4
1, 3, 4
Normal
T
Operating Temperature Range
OPER
Industrial
-40 to 95
C
NOTE :
1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document
JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main-
tained between 0-85C under all operating conditions
3. The Industrial Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main-
tained between -40-85C under all operating conditions
4. Some applications require operation of the Extended Temperature Range between 85C and 95C case temperature. Full specifications are guaranteed in this range, but the
following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the Manual Self-Refresh mode with Extended Temperature Range
capability (MR2 A6 = 0b and MR2 A7 = 1b).
7. AC & DC Operating Conditions
7.1 Recommended DC operating Conditions
[ Table 6 ] Recommended DC Operating Conditions
Rating
Symbol
Parameter
Operation Voltage
Units
NOTE
Min.
1.283
1.425
1.283
1.425
Typ.
1.35
1.5
Max.
1.45
1.35V
1.5V
V
V
V
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
V
Supply Voltage
DD
1.575
1.45
1.35V
1.5V
1.35
1.5
V
Supply Voltage for Output
DDQ
1.575
NOTE :
1. Under all conditions VDDQ must be less than or equal to VDD
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
.
3. V & V
rating are determined by operation voltage.
DDQ
DD
- 10 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
8. AC & DC Input Measurement Levels
8.1 AC & DC Logic input levels for single-ended signals
[ Table 7 ] Single-ended AC & DC input levels for Command and Address (1.35V)
DDR3L-800/1066/1333/1600
DDR3L-1866
Symbol
Parameter
Unit NOTE
Max.
Min.
Max.
Min.
1.35V
V
(DC90)
V
+ 90
V
V
V
+ 90
V
DD
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic lowM
AC input logic high
AC input logic low
mV
mV
mV
mV
mV
mV
mV
mV
1
IH.CA
REF
DD
REF
V
(DC90)
V
V
- 90
V
V
- 90
REF
1
IL.CA
SS
REF
SS
V
(AC160)
(AC160)
(AC135)
(AC135)
(AC125)
(AC125)
V
+ 160
REF
Note 2
-
-
1,2,5
1,2,5
1,2,5
1,2,5
1,2,5
1,2,5
IH.CA
V
V
V
- 160
Note 2
-
-
IL.CA
REF
V
+135
+135
REF
Note 2
Note 2
IH.CA
REF
V
V
-135
V
-135
REF
Note 2
Note 2
IL.CA
IH.CA
REF
V
V
+ 125
-
-
-
Note 2
REF
V
V
+ 125
-
Note 2
IL.CA
REF
Reference Voltage for ADD,
CMD inputs
V
(DC)
0.49*V
0.51*V
0.49*V
0.51*V
DD
V
3,4
REFCA
DD
DD
DD
NOTE :
1. For input only pins except RESET, VREF = VREFCA(DC)
2. See "Overshoot and Undershoot specifications" section.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV).
4. For reference: approx. VDD/2 +/- 13.5 mV
5. These levels apply for 1.35 Volt operation only. If the device is operated at 1.5 V , the respective levels in JESD79-3 (VIH/L.CA(DC100), VIH/L.CA(AC175), VIHL.CA(AC150),
VIH/L.CA(AC135), VIH/L.CA(AC125)etc.) apply. The 1.5 V levels (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIHL.CA(AC125)etc.) do not
apply when the device is operated in the 1.35 voltage range.
[ Table 8 ] Single-ended AC & DC input levels for Command and Address(1.5V)
DDR3-800/1066/1333/1600
DDR3-1866
Symbol
Parameter
Unit NOTE
Min.
Max.
Min.
Max.
1.5V
V
(DC100)
V
V
+ 100
V
V
+ 100
V
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
1,5
IH.CA
REF
DD
REF
DD
V
V
(DC100)
(AC175)
(AC175)
(AC150)
(AC150)
(AC135)
(AC135)
(AC125)
(AC125)
V
V
- 100
V
V
- 100
REF
1,6
IL.CA
SS
REF
SS
+ 175
Note 2
-
-
1,2,7
1,2,8
1,2,7
1,2,8
1,2,7
1,2,8
1,2,7
1,2,8
IH.CA
REF
V
V
- 175
Note 2
-
-
-
-
IL.CA
IH.CA
REF
V
V
+150
Note 2
-
REF
V
V
V
-150
REF
Note 2
-
IL.CA
V
+ 135
-
-
-
-
-
Note 2
IH.CA
REF
V
V
- 135
REF
-
-
-
Note 2
IL.CA
IH.CA
V
V
+125
REF
Note 2
V
V
-125
REF
Note 2
IL.CA
Reference Voltage for ADD,
CMD inputs
V
(DC)
0.49*V
0.51*V
0.49*V
0.51*V
DD
V
3,4,9
REFCA
DD
DD
DD
NOTE :
1. For input only pins except RESET, VREF = VREFCA(DC)
2. See "Overshoot and Undershoot specifications" section.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)
7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135), and VIH.CA(AC125); VIH.CA(AC175) value is used when Vref + 0.175V is
referenced, VIH.CA(AC150) value is used when Vref + 0.150V is referenced, VIH.CA(AC135) value is used when Vref + 0.135V is referenced, and VIH.CA(AC125) value is
used when Vref + 0.125V is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175), VIL.CA(AC150), VIL.CA(AC135) and VIL.CA(AC125); VIL.CA(AC175) value is used when Vref - 0.175V is
referenced, VIL.CA(AC150) value is used when Vref - 0.150V is referenced, VIL.CA(AC135) value is used when Vref - 0.135V is referenced, and VIL.CA(AC125) value is
used when Vref - 0.125V is referenced.
9. V
(DC) is measured relative to VDD at the same point in time on the same device
REFCA
- 11 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
[ Table 9 ] Single-ended AC & DC input levels for DQ and DM (1.35V)
DDR3L-800/1066
DDR3L-1333/1600
DDR3L-1866
Symbol
Parameter
Unit NOTE
Min.
Max.
Min.
Max.
Min.
Max.
1.35V
V
(DC90)
V
+ 90
V
V
+ 90
V
V
+ 90
V
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
mV
mV
mV
mV
mV
mV
mV
mV
1
IH.DQ
REF
DD
REF
DD
REF
DD
V
(DC90)
V
V
- 90
V
V
- 90
V
V
- 90
1
IL.DQ
SS
REF
SS
REF
SS
REF
V
(AC160)
(AC160)
(AC135)
(AC135)
(AC130)
(AC130)
V + 160
REF
Note 2
-
-
-
-
1,2,5
1,2,5
1,2,5
1,2,5
1,2,5
1,2,5
IH.DQ
V
V
V
- 160
REF
Note 2
-
-
-
-
IL.DQ
V
+ 135
V + 135
REF
Note 2
Note 2
-
-
IH.DQ
REF
V
V
- 135
V
- 135
Note 2
Note 2
-
-
IL.DQ
IH.DQ
REF
REF
V
V
+ 130
-
-
-
-
-
-
Note 2
REF
V
V
- 130
REF
-
-
Note 2
0.49*V
IL.DQ
Reference Voltage for DQ,
DM inputs
VREF (DC)
0.49*V
0.51*V
0.49*V
0.51*V
0.51*V
DD
V
3,4
DQ
DD
DD
DD
DD
DD
NOTE :
1. For input only pins except RESET, VREF = VREFDQ(DC)
2.See "Overshoot and Undershoot specifications" section.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV).
4. For reference: approx. VDD/2 +/- 13.5 mV.
5. These levels apply for 1.35 Volt operation only. If the device is operated at 1.5 V, the respective levels in JESD79-3 ( VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/
L.DQ(AC150), VIH/L.DQ(AC135), etc. ) apply. The 1.5 V levels (VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135), etc. ) do not apply when the
device is operated in the 1.35 voltage range.
[ Table 10 ] Single-ended AC & DC input levels for DQ and DM (1.5V)
DDR3-800/1066
Min. Max.
DDR3-1333/1600
DDR3-1866
Min. Max.
Symbol
Parameter
Unit
NOTE
Min.
Max.
1.5V
V
(DC100)
V
V
V
V
+ 100
V
V
+ 100
V
V
+ 100
V
DD
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
mV
mV
mV
mV
mV
mV
1,5
IH.DQ
REF
DD
REF
DD
REF
V
V
(DC100)
(AC175)
(AC175)
(AC150)
(AC150)
(AC135)
(AC135)
V
V
- 100
V
V
- 100
V
V
- 100
REF
1,6
IL.DQ
SS
REF
SS
REF
SS
+ 175
NOTE 2
-
-
-
-
-
1,2,7
1,2,8
1,2,7
1,2,8
IH.DQ
REF
V
V
- 175
NOTE 2
-
-
-
-
-
IL.DQ
IH.DQ
REF
V
+ 150
V
V
+ 150
NOTE 2
NOTE 2
-
REF
REF
V
V
V
- 150
V
- 150
REF
NOTE 2
NOTE 2
-
IL.DQ
REF
+ 135
+ 135
V
+ 135
NOTE 2
NOTE 2
NOTE 2
mV 1,2,7,10
mV 1,2,8,10
IH.DQ
REF
REF
REF
V
V
- 135
V
- 135
V
- 135
REF
NOTE 2
NOTE 2
NOTE 2
0.49*V
IL.DQ
REF
REF
Reference Voltage for DQ,
DM inputs
VREF (DC)
0.49*V
0.51*V
0.49*V
0.51*V
0.51*V
DD
V
3,4,9
DQ
DD
DD
DD
DD
DD
NOTE :
1. For input only pins except RESET, VREF = VREFDQ(DC)
2.See "Overshoot and Undershoot specifications" section.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100)
7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150), and VIH.DQ(AC135); VIH.DQ(AC175) value is used when Vref + 0.175V is referenced,
VIH.DQ(AC150) value is used when Vref + 0.150V is referenced, and VIH.DQ(AC135) value is used when Vref + 0.135V is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150), and VIL.DQ(AC135); VIL.DQ(AC175) value is used when Vref - 0.175V is referenced,
VIL.DQ(AC150) value is used when Vref - 0.150V is referenced, and VIL.DQ(AC135) value is used when Vref - 0.135V is referenced.
9. VREF (DC) is measured relative to VDD at the same point in time on the same device
DQ
10. Optional in DDR3 SDRAM for DDR3-800/1066/1333/1600: Users should refer to the DRAM supplier data sheetand/or the DIMM SPD to determine if DDR3 SDRAM devices
support this option.
- 12 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
8.2 VREF Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages V
and V
are illustrate in Figure 1. It shows a valid reference voltage
REFCA
REFDQ
V
V
(t) as a function of time. (V
stands for V
and V
likewise).
REFDQ
REF
REF
REF
REFCA
(DC) is the linear average of V
(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 7 on
REF
page 11. Furthermore V
(t) may temporarily deviate from V
(DC) by no more than ± 1% V
.
REF
REF
DD
voltage
VDD
VSS
time
Figure 1. Illustration of V
(DC) tolerance and VREF ac-noise limits
REF
The voltage levels for setup and hold time measurements V (AC), V (DC), V (AC) and V (DC) are dependent on V
.
IH
IH
IL
IL
REF
"V
" shall be understood as V
(DC), as defined in Figure 1 .
REF
REF
This clarifies, that dc-variations of V
affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
REF
which setup and hold is measured. System timing and voltage budgets need to account for V
data-eye of the input signals.
(DC) deviations from the optimum position within the
REF
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V
ac-noise. Timing
REF
and voltage effects due to ac-noise on V
up to the specified limit (+/-1% of V ) are included in DRAM timings and their associated deratings.
DD
REF
- 13 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
8.3 AC & DC Logic Input Levels for Differential Signals
8.3.1 Differential signals definition
tDVAC
V
.DIFF.AC.MIN
IH
V
.DIFF.MIN
0.0
IH
half cycle
V .DIFF.MAX
IL
V .DIFF.AC.MAX
IL
tDVAC
time
Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC
8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)
[ Table 11 ] Differential AC & DC Input Levels
DDR3-800/1066/1333/1600/1866
Symbol
Parameter
1.35V
1.5V
unit
NOTE
min
+0.18
max
NOTE 3
-0.18
min
+0.20
max
NOTE 3
-0.20
V
differential input high
differential input low
V
V
V
V
1
1
2
2
IHdiff
V
NOTE 3
NOTE 3
ILdiff
V
(AC)
(AC)
2 x (V (AC) - V
)
2 x (V (AC) - V
)
differential input high ac
differential input low ac
NOTE 3
NOTE 3
IHdiff
IH
REF
IH
REF
V
2 x (V (AC) - V
)
2 x (V (AC) - V
)
REF
NOTE 3
NOTE 3
ILdiff
NOTE :
1. Used to define a differential signal slew-rate.
IL
REF
IL
2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group,
then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended sig-
nals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet Specification"
- 14 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
[ Table 12 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.35V)
DDR3L-800/1066/1333/1600
DDR3L-1866
tDVAC [ps]
tDVAC [ps]
@ |VIH/Ldiff(ac)|
=270mV
tDVAC [ps]
@ |VIH/Ldiff(ac)|
tDVAC [ps] @ |V
tDVAC [ps] @ |V
IH/
IH/
Slew Rate [V/ns]
@ |VIH/Ldiff(ac)|
(AC)| = 320mV
(AC)| = 270mV
Ldiff
Ldiff
=250mV
=260mV
min
189
max
min
201
max
min
163
163
140
95
max
min
168
168
147
105
91
max
min
176
176
154
111
97
max
> 4.0
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
189
162
109
91
201
179
134
119
100
76
3.0
2.0
1.8
80
1.6
69
62
74
78
1.4
40
37
52
56
1.2
note
note
note
44
5
22
24
1.0
note
note
note
note
note
note
note
note
< 1.0
NOTE: Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.
[ Table 13 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.5V)
DDR3-800/1066/1333/1600
DDR3-1866
tDVAC [ ps ]
@ VIH/L diff(ac)
=270mv
(DQS - DQS#) only
(Optional)
tDVAC [ps]
tDVAC [ps]
@ V (AC)
tDVAC [ps]
(AC)= 350mV @ V
tDVAC [ps]
@ V
(AC)
Slew Rate [V/ns]
IH/Ldiff
IH/Ldiff
@ V
(AC)= 300mV
IH/Ldiff
IH/Ldiff
= 270mV
=250mV(CK - CK#) only
min
75
max
min
175
170
167
119
102
81
max
min
214
214
191
146
131
113
88
max
min
134
134
112
67
max
min
139
139
118
77
max
> 4.0
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
57
3.0
50
2.0
38
1.8
34
52
63
1.6
29
33
45
1.4
22
54
9
23
1.2
note
note
note
19
56
note
note
note
note
note
note
1.0
note
note
11
< 1.0
note
NOTE : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VILdiff(ac)
level.
- 15 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
8.3.3 Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for
single-ended signals.
CK and CK have to approximately reach V
min / V
max [approximately equal to the ac-levels { V (AC) / V (AC)} for ADD/CMD signals] in every
SEH
SEL IH IL
half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach V
proceeding and following a valid transition.
min / V
max [approximately the ac-levels { V (AC) / V (AC)} for DQ signals] in every half-cycle
SEL IH IL
SEH
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V 150(AC)/V 150(AC) is used for ADD/CMD sig-
IH
IL
nals, then these ac-levels apply also for the single-ended signals CK and CK .
VDD or VDDQ
VSEH min
VSEH
VDD/2 or VDDQ/2
CK or DQS
VSEL max
VSEL
VSS or VSSQ
time
Figure 3. Single-ended requirement for differential signals
Note that while ADD/CMD and DQ signal requirements are with respect to V
, the single-ended components of differential signals have a requirement
REF
with respect to V /2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-
DD
ended components of differential signals the requirement to reach V
mode characteristics of these signals.
max, V
min has no bearing on timing, but adds a restriction on the common
SEH
SEL
[ Table 14 ] Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU
DDR3-800/1066/1333/1600/1866
Symbol
Parameter
Unit
NOTE
Min
Max
(V /2)+0.175
Single-ended high-level for strobes
Single-ended high-level for CK, CK
Single-ended low-level for strobes
Single-ended low-level for CK, CK
NOTE3
NOTE3
V
V
V
V
1, 2
1, 2
1, 2
1, 2
DD
V
SEH
(V /2)+0.175
DD
(V /2)-0.175
NOTE3
NOTE3
DD
V
SEL
(V /2)-0.175
DD
NOTE :
1. For CK, CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL(AC) of DQs.
2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the
reduced level applies also here
3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(DC) max,
VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification"
- 16 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
8.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input
signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage V is measured from the actual
IX
cross point of true and complement signal to the mid level between of V and V
.
SS
DD
V
DD
CK, DQS
V
IX
V
/2
DD
V
V
IX
IX
CK, DQS
V
SS
Figure 4. VIX Definition
[ Table 15 ] Cross point voltage for differential input signals (CK, DQS) : 1.35V
DDR3L-800/1066/1333/1600/1866
Symbol
Parameter
Unit
NOTE
Min
-150
-150
Max
150
150
V
Differential Input Cross Point Voltage relative to V /2 for CK,CK
mV
mV
1
IX
DD
V
Differential Input Cross Point Voltage relative to V /2 for DQS,DQS
IX
DD
NOTE :
1. The relationbetween Vix Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + Vix(Min) - VSEL 25mV
VSEH - ((VDD/2) + Vix(Max)) 25mV
[ Table 16 ] Cross point voltage for differential input signals (CK, DQS) : 1.5V
DDR3-800/1066/1333/1600/1866
Symbol
Parameter
Unit
NOTE
Min
-150
-175
-150
Max
150
175
150
mV
mV
mV
V
V
Differential Input Cross Point Voltage relative to V /2 for CK,CK
IX
DD
1
Differential Input Cross Point Voltage relative to V /2 for DQS,DQS
IX
DD
NOTE :
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing VSEL / VSEH of at least VDD/2
±250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns.
- 17 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
8.5 Slew rate definition for Differential Input Signals
See 14.3 “Address/Command Setup, Hold and Derating :” on page 50 for single-ended slew rate definitions for address and command signals.
See 14.4 “Data Setup, Hold and Slew Rate Derating :” on page 56 for single-ended slew rate definitions for data signals.
8.6 Slew rate definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in Table 17 and Figure 5.
[ Table 17 ] Differential input slew rate definition
Measured
Description
Defined by
From
To
V
V
V
[V
[V
- V
Delta TRdiff
Differential input slew rate for rising edge (CK-CK and DQS-DQS)
Differential input slew rate for falling edge (CK-CK and DQS-DQS)
NOTE :
ILdiffmax
IHdiffmin
IHdiffmin
ILdiffmax] /
Delta TFdiff
ILdiffmax] /
V
- V
IHdiffmin
IHdiffmin
ILdiffmax
The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds.
VIHdiffmin
0
VILdiffmax
delta TFdiff
delta TRdiff
Figure 5. Differential Input Slew Rate definition for DQS, DQS, and CK, CK
9. AC & DC Output Measurement Levels
9.1 Single-ended AC & DC Output Levels
[ Table 18 ] Single-ended AC & DC output levels
Symbol
Parameter
DDR3-800/1066/1333/1600/1866
Units
NOTE
V
(DC)
(DC)
DC output high measurement level (for IV curve linearity)
0.8 x V
0.5 x V
0.2 x V
V
V
V
V
V
OH
DDQ
DDQ
DDQ
V
V
DC output mid measurement level (for IV curve linearity)
DC output low measurement level (for IV curve linearity)
AC output high measurement level (for output SR)
AC output low measurement level (for output SR)
OM
(DC)
OL
V
(AC)
(AC)
V
+ 0.1 x V
1
1
OH
TT
DDQ
DDQ
V
V
- 0.1 x V
TT
OL
NOTE : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test
load of 25 to VTT=VDDQ/2.
9.2 Differential AC & DC Output Levels
[ Table 19 ] Differential AC & DC output levels
Symbol
(AC)
Parameter
DDR3-800/1066/1333/1600/1866
Units
NOTE
V
AC differential output high measurement level (for output SR)
+0.2 x V
V
1
OHdiff
DDQ
V
(AC)
AC differential output low measurement level (for output SR)
-0.2 x V
V
1
OLdiff
DDQ
NOTE : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test
load of 25 to VTT=VDDQ/2 at each of the differential outputs.
- 18 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
9.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V (AC) and V (AC)
OL
OH
for single ended signals as shown in Table 20 and Figure 6.
[ Table 20 ] Single-ended output slew rate definition
Description
Measured
Defined by
[V (AC)-V (AC)] / Delta TRse
From
(AC)
To
(AC)
V
V
V
Single ended output slew rate for rising edge
Single ended output slew rate for falling edge
OL
OH
OH
OL
(AC)
V
(AC)
[V (AC)-V (AC)] / Delta TFse
OH OL
OH
OL
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 21 ] Single-ended output slew rate
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
Operation
Voltage
Parameter
Symbol
Units
Min
1.75
2.5
Max
Min
1.75
2.5
Max
Min
1.75
2.5
Max
Min
1.75
2.5
Max
Min
1.75
2.5
Max
1)
1)
1)
1)
1)
1.35V
1.5V
V/ns
V/ns
5
5
5
5
5
Single ended output slew rate
Description : SR : Slew Rate
SRQse
5
5
5
5
5
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals
For Ron = RZQ/7 setting
NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ signals in
the same byte lane are static (i.e they stay at either high or low).
- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining
DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.
VOH(AC)
VTT
VOL(AC)
delta TFse
delta TRse
Figure 6. Single-ended Output Slew Rate Definition
- 19 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
9.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V
(AC) and V
OH-
OLdiff
(AC) for differential signals as shown in Table 22 and Figure 7.
diff
[ Table 22 ] Differential output slew rate definition
Description
Measured
Defined by
From
To
(AC)
V
V
(AC)
V
[V
(AC)-V
(AC)-V
(AC)] / Delta TRdiff
(AC)] / Delta TFdiff
Differential output slew rate for rising edge
Differential output slew rate for falling edge
OLdiff
OHdiff
OHdiff
OLdiff
(AC)
V
(AC)
[V
OHdiff
OHdiff
OLdiff
OLdiff
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 23 ] Differential output slew rate
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
Operation
Voltage
Parameter
Symbol
Units
Min
3.5
5
Max
Min
3.5
5
Max
12
Min
3.5
5
Max
12
Min
3.5
5
Max
12
Min
3.5
5
Max
12
1.35V
1.5V
12
10
V/ns
V/ns
Differential output slew rate
Description : SR : Slew Rate
SRQdiff
10
10
10
12
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
diff : Differential Signals
For Ron = RZQ/7 setting
VOHdiff(AC)
VTT
OLdiff(AC)
V
delta TFdiff
delta TRdiff
Figure 7. Differential Output Slew Rate Definition
9.5 Reference Load for AC Timing and Output Slew Rate
Figure 8 represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate
measurements.
It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. Sys-
tem designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their
production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
V
DDQ
DQ
DQS
DQS
CK/CK
DUT
V
= V
/2
DDQ
TT
25
Reference
Point
Figure 8. Reference Load for AC Timing and Output Slew Rate
- 20 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
9.6 Overshoot/Undershoot Specification
9.6.1 Address and Control Overshoot and Undershoot specifications
[ Table 24 ] AC overshoot/undershoot specification for Address and Control pins (A0-A12, BA0-BA2. CS. RAS. CAS. WE. CKE, ODT)
Specification
Parameter
Unit
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866
1.35V
Maximum peak amplitude allowed for overshoot area (See Figure 9)
Maximum peak amplitude allowed for undershoot area (See Figure 9)
0.4
0.4
0.4
0.4
0.5
0.4
0.4
0.4
0.4
0.4
0.4
0.4
V
V
Maximum overshoot area above V (See Figure 9)
0.67
0.33
0.28
V-ns
DD
Maximum undershoot area below V (See Figure 9)
0.67
0.5
0.4
0.33
0.28
V-ns
SS
1.5V
Maximum peak amplitude allowed for overshoot area (See Figure 9)
Maximum peak amplitude allowed for undershoot area (See Figure 9)
0.4
0.4
0.4
0.4
0.5
0.4
0.4
0.4
0.4
0.4
0.4
0.4
V
V
Maximum overshoot area above V (See Figure 9)
0.67
0.33
0.28
V-ns
DD
Maximum undershoot area below V (See Figure 9)
0.67
0.5
0.4
0.33
0.28
V-ns
SS
(A0-A15, BA0-BA3, CS#, RAS#, CAS#, WE#, CKE, ODT)
NOTE:
1. The sum of the applied voltage (VDD) and peak amplitude overshoot voltage is not to exceed absolute maximum DC ratings
2. The sum of applied voltage (VDD) and the peak amplitude undershoot voltage is not to exceed absolute maximum DC ratings
Maximum Amplitude
Overshoot Area
VDD
VSS
Volts
(V)
Undershoot Area
Maximum Amplitude
Time (ns)
Figure 9. Address and Control Overshoot and Undershoot Definition
- 21 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
[ Table 25 ] AC overshoot/undershoot specification for Clock, Data, Strobe and Mask (DQ, DQS, DQS, DM, CK, CK)
Specification
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866
1.35V
0.4
Parameter
Unit
Maximum peak amplitude allowed for overshoot area (See Figure 10)
Maximum peak amplitude allowed for undershoot area (See Figure 10)
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
V
V
0.4
Maximum overshoot area above V
(See Figure 10)
(See Figure 10)
0.25
0.25
0.19
0.15
0.13
0.10
V-ns
DDQ
Maximum undershoot area below V
0.19
0.15
0.13
0.10
V-ns
SSQ
1.5V
Maximum peak amplitude allowed for overshoot area (See Figure 10)
Maximum peak amplitude allowed for undershoot area (See Figure 10)
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
V
V
Maximum overshoot area above V
(See Figure 10)
(See Figure 10)
0.25
0.19
0.15
0.13
0.10
V-ns
DDQ
Maximum undershoot area below V
0.25
0.19
0.15
0.13
0.10
V-ns
SSQ
(CK, CK#, DQ, DQS, DQS#, DM)
NOTE:
1. The sum of the applied voltage (VDD) and peak amplitude overshoot voltage is not to exceed absolute maximum DC ratings
2. The sum of applied voltage (VDD) and the peak amplitude undershoot voltage is not to exceed absolute maximum DC ratings
Maximum Amplitude
Overshoot Area
VDDQ
VSSQ
Volts
(V)
Undershoot Area
Maximum Amplitude
Time (ns)
Figure 10. Clock, Data, Strobe and Mask Overshoot and Undershoot Definition
- 22 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
9.7 34ohm Output Driver DC Electrical Characteristics
A functional representation of the output buffer is shown below. Output driver impedance RON is defined by the value of external reference resistor RZQ
as follows:
RON = RZQ/7 (Nominal 34.3ohms +/- 10% with nominal RZQ=240ohm)
34
The individual Pull-up and Pull-down resistors (RONpu and RONpd) are defined as follows
V
-V
DDQ OUT
under the condition that RONpd is turned off
RONpu =
RONpd =
l Iout l
V
OUT
under the condition that RONpu is turned off
Output Driver
l Iout l
VDDQ
Ipu
To
other
circuity
RON
Pu
DQ
Iout
RON
Pd
Vout
Ipd
VSSQ
Figure 11. Output Driver : Definition of Voltages and Currents
- 23 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
[ Table 26 ] Output Driver DC Electrical Characteristics, assuming RZQ=240ohms ;
entire operating temperature range ; after proper ZQ calibration
RONnom
Resistor
Vout
Min
Nom
Max
Units
Notes
1.35V
V
V
= 0.2 x V
0.6
0.9
0.9
0.9
0.9
0.6
0.6
0.9
0.9
0.9
0.9
0.6
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.15
1.15
1.45
1.45
1.15
1.15
1.15
1.15
1.45
1.45
1.15
1.15
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
OLdc
DDQ
= 0.5 x V
= 0.8 x V
= 0.2 x V
RON34pd
OMdc
DDQ
V
OHdc
DDQ
34Ohms
RZQ/7
V
OLdc
DDQ
V
= 0.5 x V
RON34pu
RON40pd
RON40pu
OMdc
DDQ
DDQ
DDQ
V
= 0.8 x V
= 0.2 x V
OHdc
V
V
OLdc
= 0.5 x V
= 0.8 x V
= 0.2 x V
OMdc
DDQ
DDQ
V
OHdc
40Ohms
RZQ/6
V
OLdc
DDQ
V
= 0.5 x V
OMdc
DDQ
DDQ
V
V
= 0.8 x V
= 0.5 x V
OHdc
Mismatch between Pull-up and Pull-down,
MMpupd
-10
10
%
1,2,4
OMdc
DDQ
1.5V
V
= 0.2 x V
0.6
0.9
0.9
0.9
0.9
0.6
0.6
0.9
0.9
0.9
0.9
0.6
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.1
1.1
1.4
1.4
1.1
1.1
1.1
1.1
1.4
1.4
1.1
1.1
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
OLdc
DDQ
V
= 0.5 x V
RON34pd
OMdc
DDQ
DDQ
DDQ
V
= 0.8 x V
= 0.2 x V
OHdc
34Ohms
RZQ/7
V
V
OLdc
= 0.5 x V
= 0.8 x V
= 0.2 x V
RON34pu
OMdc
DDQ
DDQ
V
OHdc
V
OLdc
DDQ
V
= 0.5 x V
RON40pd
OMdc
DDQ
DDQ
DDQ
V
= 0.8 x V
= 0.2 x V
OHdc
40Ohms
RZQ/6
V
V
OLdc
= 0.5 x V
= 0.8 x V
RON40pu
OMdc
DDQ
DDQ
V
OHdc
Mismatch between Pull-up and Pull-down,
MMpupd
V
= 0.5 x V
-10
10
%
1,2,4
OMdc
DDQ
NOTE :
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibra-
tion, see following section on voltage and temperature sensitivity
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS
3. Pull-down and pull-up output driver impedance are recommended to be calibrated at 0.5 X VDDQ. Other calibration schemes may be used to achieve the linearity spec shown
above, e.g. calibration at 0.2 X VDDQ and 0.8 X VDDQ
4. Measurement definition for mismatch between pull-up and pull-down, MMpupd: Measure RONpu and RONpd. both at 0.5 X VDDQ
:
RONpu - RONpd
x 100
MMpupd =
RONnom
- 24 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
9.7.1 Output Drive Temperature and Voltage Sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to Table 27 and Table 28.
T = T - T(@calibration); V = V
- V
(@calibration); V = V
DDQ
DDQ DD DDQ
*dR dT and dR dV are not subject to production test but are verified by design and characterization
ON
ON
[ Table 27 ] Output Driver Sensitivity Definition
Min
Max
Units
RONPU@V
RON@V
0.6 - dR dTH * |T| - dRONdVH * |V|
1.1 + dR dTH * |T| + dRONdVH * |V|
RZQ/7
RZQ/7
RZQ/7
OHDC
ON
ON
0.9 - dR dTM * |T| - dRONdVM * |V|
1.1 + dR dTM * |T| + dRONdVM * |V|
OMDC
ON
ON
RONPD@
0.6 - dR dTL * |T| - dRONdVL * |V|
1.1 + dR dTL * |T| + dRONdVL * |V|
VOLDC
ON
ON
[ Table 28 ] Output Driver Voltage and Temperature Sensitivity
Speed Bin
800/1066/1333
1600/1866
Units
Min
0
Max
1.5
Min
0
Max
1.5
dR dTM
%/C
%/mV
%/C
ON
dR dVM
0
0.15
1.5
0
0.13
1.5
ON
dR dTL
0
0
ON
dR dVL
0
0.15
1.5
0
0.13
1.5
%/mV
%/C
ON
dR dTH
0
0
ON
dR dVH
0
0.15
0
0.13
%/mV
ON
9.8 On-Die Termination (ODT) Levels and I-V Characteristics
On-Die Termination effective resistance RTT is defined by bits A9, A6 and A2 of MR1 register.
ODT is applied to the DQ,DM, DQS/DQS and TDQS,TDQS (x8 devices only) pins.
A functional representation of the on-die termination is shown below. The individual pull-up and pull-down resistors (RTTpu and RTTpd) are defined as
follows :
V
-V
DDQ OUT
under the condition that RTTpd is turned off
under the condition that RTTpu is turned off
RTTpu =
RTTpd =
l Iout l
V
OUT
l Iout l
Chip in Termination Mode
ODT
VDDQ
Ipu
Iout=Ipd-Ipu
To
RTTPu
other
circuitry
like
DQ
RCV,
...
Iout
RTTPd
VOUT
VSSQ
Ipd
Figure 12. On-Die Termination : Definition of Voltages and Currents
- 25 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
9.8.1 ODT DC Electrical Characteristics
Table 29 provides and overview of the ODT DC electrical characteristics. They values for RTT
RTT
RTT
RTT
RTT
120pu240, 40pd80,
60pd120,
60pu120,
120pd240,
RTT
RTT
RTT
RTT
RTT
are not specification requirements, but can be used as design guide lines:
40pu80,
30pd60,
30pu60,
20pd40,
20pu40
[ Table 29 ] ODT DC Electrical Characteristics, assuming RZQ=240ohm +/- 1% entire operating temperature range; after proper ZQ calibration
1.35V
MR1 (A9,A6,A2)
RTT
RESISTOR
Vout
Min
Nom
Max
Unit
Notes
V
V
(DC) 0.2XV
R
0.6
0.9
0.9
0.9
0.9
0.6
0.9
0.6
0.9
0.9
0.9
0.9
0.6
0.9
0.6
0.9
0.9
0.9
0.9
0.6
0.9
0.6
0.9
0.9
0.9
0.9
0.6
0.9
0.6
0.9
0.9
0.9
0.9
0.6
0.9
-5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.15
1.15
1.45
1.45
1.15
1.15
1.65
1.15
1.15
1.45
1.45
1.15
1.15
1.65
1.15
1.15
1.45
1.45
1.15
1.15
1.65
1.15
1.15
1.45
1.45
1.15
1.15
1.65
1.15
1.15
1.45
1.45
1.15
1.15
1.65
5
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,5
OL
DDQ
ZQ
RTT
0.5XV
R
120pd240
DDQ
ZQ
(DC) 0.8XV
R
OH
DDQ
ZQ
V
(DC) 0.2XV
R
(0,1,0)
120 ohm
OL
DDQ
ZQ
RTT
0.5XV
R
120pu240
DDQ
ZQ
V
(DC) 0.8XV
R
OH
DDQ
ZQ
RTT
V (AC) to V (AC)
R
/2
120
IL
IH
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
V
(DC) 0.2XV
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
/2
/2
/2
/2
/2
/2
/4
/3
/3
/3
/3
/3
/3
/6
/4
/4
/4
/4
/4
/4
/8
/6
/6
/6
/6
/6
/6
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,5
OL
DDQ
RTT
0.5XV
60pd120
DDQ
V
(DC) 0.8XV
OH
DDQ
V
(DC) 0.2XV
(0,0,1)
(0,1,1)
(1,0,1)
(1,0,0)
60 ohm
40 ohm
30 ohm
20 ohm
OL
DDQ
RTT
0.5XV
DDQ
60pu120
V
(DC) 0.8XV
DDQ
OH
RTT
V (AC) to V (AC)
60
IL
IH
V
(DC) 0.2XV
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,5
OL
DDQ
RTT
0.5XV
40pd80
DDQ
V
(DC) 0.8XV
OH
DDQ
V
(DC) 0.2XV
OL
DDQ
RTT
0.5XV
DDQ
40pu80
V
(DC) 0.8XV
DDQ
OH
RTT
V (AC) to V (AC)
40
IL
IH
V
(DC) 0.2XV
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,5
OL
DDQ
RTT
0.5XV
30pd60
DDQ
V
(DC) 0.8XV
OH
DDQ
V
(DC) 0.2XV
OL
DDQ
RTT
0.5XV
DDQ
30pu60
V
(DC) 0.8XV
DDQ
OH
RTT
V (AC) to V (AC)
30
IL
IH
V
(DC) 0.2XV
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,5
OL
DDQ
RTT
0.5XV
20pd40
DDQ
V
(DC) 0.8XV
OH
DDQ
V
(DC) 0.2XV
OL
DDQ
RTT
0.5XV
DDQ
20pu40
V
(DC) 0.8XV
DDQ
OH
RTT
V (AC) to V (AC)
R
/12
20
IL
IH
ZQ
Deviation of VM w.r.t VDDQ/2, VM
%
1,2,5,6
- 26 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
1.5V
Vout
MR1 (A9,A6,A2)
RTT
RESISTOR
Min
Nom
Max
Unit
Notes
V
V
(DC) 0.2XV
R
0.6
0.9
0.9
0.9
0.9
0.6
0.9
0.6
0.9
0.9
0.9
0.9
0.6
0.9
0.6
0.9
0.9
0.9
0.9
0.6
0.9
0.6
0.9
0.9
0.9
0.9
0.6
0.9
0.6
0.9
0.9
0.9
0.9
0.6
0.9
-5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.1
1.1
1.4
1.4
1.1
1.1
1.6
1.1
1.1
1.4
1.4
1.1
1.1
1.6
1.1
1.1
1.4
1.4
1.1
1.1
1.6
1.1
1.1
1.4
1.4
1.1
1.1
1.6
1.1
1.1
1.4
1.4
1.1
1.1
1.6
5
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,5
OL
DDQ
ZQ
RTT
0.5XV
R
120pd240
DDQ
ZQ
(DC) 0.8XV
R
OH
DDQ
ZQ
V
(DC) 0.2XV
R
(0,1,0)
120 ohm
OL
DDQ
ZQ
RTT
0.5XV
R
120pu240
DDQ
ZQ
V
(DC) 0.8XV
R
OH
DDQ
ZQ
RTT
V (AC) to V (AC)
R
/2
120
IL
IH
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
V
(DC) 0.2XV
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
/2
/2
/2
/2
/2
/2
/4
/3
/3
/3
/3
/3
/3
/6
/4
/4
/4
/4
/4
/4
/8
/6
/6
/6
/6
/6
/6
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,5
OL
DDQ
RTT
0.5XV
60pd240
DDQ
V
(DC) 0.8XV
OH
DDQ
V
(DC) 0.2XV
(0,0,1)
(0,1,1)
(1,0,1)
(1,0,0)
60 ohm
40 ohm
30 ohm
20 ohm
OL
DDQ
RTT
0.5XV
DDQ
60pu240
V
(DC) 0.8XV
DDQ
OH
RTT
V (AC) to V (AC)
60
IL
IH
V
(DC) 0.2XV
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,5
OL
DDQ
RTT
0.5XV
40pd240
DDQ
V
(DC) 0.8XV
OH
DDQ
V
(DC) 0.2XV
OL
DDQ
RTT
0.5XV
DDQ
40pu240
V
(DC) 0.8XV
DDQ
OH
RTT
V (AC) to V (AC)
40
IL
IH
V
(DC) 0.2XV
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,5
OL
DDQ
RTT
0.5XV
60pd240
DDQ
V
(DC) 0.8XV
OH
DDQ
V
(DC) 0.2XV
OL
DDQ
RTT
0.5XV
DDQ
60pu240
V
(DC) 0.8XV
DDQ
OH
RTT
V (AC) to V (AC)
60
IL
IH
V
(DC) 0.2XV
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,5
OL
DDQ
RTT
0.5XV
60pd240
DDQ
V
(DC) 0.8XV
OH
DDQ
V
(DC) 0.2XV
OL
DDQ
RTT
0.5XV
DDQ
60pu240
V
(DC) 0.8XV
DDQ
OH
RTT
V (AC) to V (AC)
R
/12
60
IL
IH
ZQ
Deviation of VM w.r.t VDDQ/2, VM
%
1,2,5,6
- 27 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
NOTE :
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibra-
tion, see following section on voltage and temperature sensitivity
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS
3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5XVDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g.
calibration at 0.2XVDDQ and 0.8XVDDQ
.
4. Not a specification requirement, but a design guide line
5. Measurement definition for RTT:
Apply VIH(AC) to pin under test and measure current I(VIH(AC)), then apply VIL(AC) to pin under test and measure current I(VIL(AC)) respectively
V
(AC) - V (AC)
IL
IH
RTT
=
I(V (AC)) - I(V (AC))
IH
IL
6. Measurement definition for VM and VM : Measure voltage (VM) at test pin (midpoint) with no load
2 x VM
- 1
x 100
VM
=
V
DDQ
9.8.2 ODT Temperature and Voltage sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to table below
T = T - T(@calibration); V = V
- V
(@calibration); V = V
DDQ
DDQ
DDQ
DD
[ Table 30 ] ODT Sensitivity Definition
Min
Max
Units
0.9 - dR dT * |T| - dRTTdV * |V|
1.6 + dR dT * |T| + dRTTdV * |V|
RTT
RZQ/2,4,6,8,12
TT
TT
[ Table 31 ] ODT Voltage and Temperature Sensitivity
Min
0
Max
1.5
Units
%/C
dR dT
TT
dR dV
0
0.15
%/mV
TT
NOTE : These parameters may not be subject to production test. They are verified by design and characterization.
- 28 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
9.9 ODT Timing Definitions
9.9.1 Test Load for ODT Timings
Different than for timing measurements, the reference load for ODT timings is defined in Figure 13.
VDDQ
DUT
DQ, DM
CK,CK
V
V
=
TT
SSQ
DQS , DQS
TDQS , TDQS
RTT
=25 ohm
VSSQ
Timing Reference Points
Figure 13. ODT Timing Reference Load
9.9.2 ODT Timing Definitions
Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in Table 32 and subsequent figures. Measurement reference settings are provided
in Table 33 .
[ Table 32 ] ODT Timing Definitions
Symbol
tAON
Begin Point Definition
End Point Definition
Figure
Rising edge of CK - CK defined by the end point of ODTLon
Rising edge of CK - CK with ODT being first registered high
Rising edge of CK - CK defined by the end point of ODTLoff
Rising edge of CK - CK with ODT being first registered low
Extrapolated point at V
Figure 14
Figure 15
Figure 16
Figure 17
SSQ
SSQ
tAONPD
tAOF
Extrapolated point at V
End point: Extrapolated point at V
End point: Extrapolated point at V
RTT_Nom
RTT_Nom
tAOFPD
Rising edge of CK - CK defined by the end point of ODTLcnw,
ODTLcwn4 of ODTLcwn8
End point: Extrapolated point at V
respectively
and V
RTT_Wr RTT_Nom
tADC
Figure 18
[ Table 33 ] Reference Settings for ODT Timing Measurements
Measured
RTT_Nom Setting
RTT_Wr Setting
V
[V]
V
[V]
SW2
NOTE
SW1
Parameter
R
/4
NA
NA
NA
NA
NA
NA
NA
NA
0.05
0.10
0.05
0.10
0.05
0.10
0.05
0.10
0.20
0.10
0.20
0.10
0.20
0.10
0.20
0.10
0.20
0.25
ZQ
tAON
R
/12
ZQ
R
/4
ZQ
tAONPD
tAOF
R
/12
ZQ
R
/4
ZQ
R
/12
ZQ
R
/4
ZQ
tAOFPD
tADC
R
/12
/12
ZQ
ZQ
R
R
/2
ZQ
- 29 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
Begin point : Rising edge of CK - CK
defined by the end point of ODTLon
CK
CK
V
TT
tAON
TSW2
TSW1
DQ, DM
DQS , DQS
TDQS , TDQS
VSW2
VSW1
V
V
V
V
SSQ
SSQ
End point Extrapolated point at V
SSQ
Figure 14. Definition of tAON
Begin point : Rising edge of CK - CK
with ODT being first registered high
CK
CK
V
TT
tAONPD
TSW2
TSW1
DQ, DM
DQS , DQS
TDQS , TDQS
VSW2
VSW1
V
SSQ
SSQ
End point Extrapolated point at V
SSQ
Figure 15. Definition of tAONPD
Begin point : Rising edge of CK - CK
defined by the end point of ODTLoff
CK
CK
V
TT
tAOF
End point Extrapolated point at V
RTT_Nom
V
RTT_Nom
TSW2
TSW1
DQ, DM
DQS , DQS
TDQS , TDQS
VSW2
VSW1
SSQ
TD_TAON_DEF
Figure 16. Definition of tAOF
- 30 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
Begin point : Rising edge of CK - CK
with ODT being first registered low
CK
CK
V
TT
t
AOFPD
End point Extrapolated point at V
RTT_Nom
V
RTT_Nom
T
SW2
DQ, DM
DQS , DQS
T
SW1
V
SW2
V
TDQS , TDQS
SW1
V
SSQ
Figure 17. Definition of tAOFPD
Begin point : Rising edge of CK - CK
defined by the end point of ODTLcnw
Begin point : Rising edge of CK - CK defined by
the end point of ODTLcwn4 or ODTLcwn8
CK
CK
V
TT
t
t
ADC
ADC
End point Extrapolated point at V
RTT_Nom
V
RTT_Nom
V
RTT_Nom
T
SW21
End point
Extrapolated point
at V
T
DQ, DM
DQS , DQS
TDQS , TDQS
SW22
V
SW2
T
SW11
RTT_Nom
T
SW12
V
SW1
End point Extrapolated point at V
V
RTT_Wr
RTT_Wr
V
SSQ
Figure 18. Definition of tADC
- 31 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
10. IDD Current Measure Method
10.1 IDD Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 19 shows the setup and test load for IDD and
IDDQ measurements.
- IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and
IDD7) are measured as time-averaged currents with all V balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in
DD
IDD currents.
- IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all V
balls of the DDR3 SDRAM under test tied
DDQ
together. Any IDD current is not included in IDDQ currents.
Attention : IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO
power to actual IO power as outlined in Figure 20. In DRAM module application, IDDQ cannot be measured separately since V and V
DD
DDQ
are using one merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply :
- "0" and "LOW" is defined as V <= V AC(max).
IN
IL
- "1" and "HIGH" is defined as V >= V AC(min).
IN
IH
- "FLOATING" is defined as inputs are V
= V / 2.
DD
REF
- "Timing used for IDD and IDDQ Measured - Loop Patterns" are provided in Table 34
- "Basic IDD and IDDQ Measurement Conditions" are described in Table 35
- Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 32 on page 31 through Table 39.
- IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
- Attention : The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.
- Define D = {CS, RAS, CAS, WE} := {HIGH, LOW, LOW, LOW}
- Define D = {CS, RAS, CAS, WE} := {HIGH, HIGH, HIGH, HIGH}
- RESET Stable time is : During a Cold Bood RESET (Initialization), current reading is valid once power is stable and RESET has been LOW for 1ms;
During Warm Boot RESET(while operating), current reading is valid after RESET has been LOW for 200ns + tRFC
[ Table 34 ] Timing used for IDD and IDDQ Measured - Loop Patterns
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
Parameter Bin
tCKmin(IDD)
Unit
6-6-6
2.5
6
7-7-7
1.875
7
9-9-9
1.5
9
11-11-11
1.25
11
13-13-13
1.071
13
ns
CL(IDD)
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
tRCDmin(IDD)
tRCmin(IDD)
tRASmin(IDD)
tRPmin(IDD)
6
7
9
11
13
21
15
6
27
20
7
33
24
9
39
45
28
32
11
13
x4/x8
x16
16
20
4
20
27
4
20
30
4
24
26
tFAW(IDD)
tRRD(IDD)
32
33
x4/x8
x16
5
5
4
6
5
6
6
tRFC(IDD) - 512Mb
tRFC(IDD) - 1Gb
tRFC(IDD) - 2Gb
tRFC(IDD) - 4Gb
tRFC(IDD) - 8Gb
36
44
64
104
140
48
59
86
139
187
60
74
107
174
234
72
85
88
103
150
243
328
128
208
280
- 32 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
IDD
IDDQ
VDD
VDDQ
RESET
CK/CK
CKE
CS
DQS, DQS
DQ, DM,
R
TT = 25 Ohm
VDDQ/2
RAS, CAS, WE
TDQS, TDQS
A, BA
ODT
ZQ
VSS
VSSQ
[NOTE : DIMM level Output test load condition may be different from above]
Figure 19. Measurement Setup and Test Load for IDD and IDDQ Measurements
Application specific
IDDQ
Test Load
memory channel
environment
Channel
IO Power
Simulation
IDDQ
Measurement
IDDQ
Simulation
Correlation
Correction
Channel IO Power
Number
Figure 20. Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement.
- 33 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
[ Table 35 ] Basic IDD and IDDQ Measurement Conditions
Symbol
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: High between ACT and PRE; Command, Address,
Bank Address Inputs: partially toggling according to Table 32 on page 31 ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active
at a time: 0,0,1,1,2,2,... (see Table 32); Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 32
IDD0
IDD1
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: High between ACT, RD and PRE; Command,
Address, Bank Address Inputs, Data IO: partially toggling according to Table 33 on page 32 ; DM:stable at 0; Bank Activity: Cycling with one bank active at
a time: 0,0,1,1,2,2,... (see Table 33); Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 33
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-
gling according to Table 34 on page 32 ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode
IDD2N
Registers2); ODT Signal: stable at 0; Pattern Details: see Table 34
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-
gling according to Table 35 on page 33 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode
Registers2); ODT Signal: toggling according to Table 35 ; Pattern Details: see Table 35
IDD2NT
IDDQ2NT
IDD2P0
Precharge Standby ODT IDDQ Current
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;
Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pre-
charge Power Down Mode: Slow Exi3)
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 34 on page 32; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;
Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pre-
charge Power Down Mode: Fast Exit3)
IDD2P1
IDD2Q
IDD3N
IDD3P
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;
Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-
gling according to Table 34 on page 32 ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode
Registers2); ODT Signal: stable at 0; Pattern Details: see Table 34
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;
Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: par-
tially toggling according to Table 36 on page 33 ; Data IO: seamless read data burst with different data between one burst and the next one according to
Table 36 ; DM:stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 7 on page 11); Output Buffer and
IDD4R
IDDQ4R
IDD4W
RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 36
Operating Burst Read IDDQ Current
Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: par-
tially toggling according to Table 37 on page 34 ; Data IO: seamless write data burst with different data between one burst and the next one according to
Table 37; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... (see Table 37); Output Buffer and RTT:
Enabled in Mode Registers2); ODT Signal: stable at HIGH; Pattern Details: see Table 37
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 34 on page 32 ; BL: 81); AL: 0; CS: High between REF; Command, Address, Bank Address
Inputs: partially toggling according to Table 38 on page 34 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC (see Table 38);
IDD5B
Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 38
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Normal5); CKE: Low; External clock: Off; CK and CK:
LOW; CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Self-
Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: FLOATING
IDD6
Self Refresh Current: Extended Temperature Range
TCASE: 0°C - 95°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Extended5); CKE: Low; External clock: Off; CK and
CK#: LOW; CL: see Table 34 on page 32; BL: 81); AL: 0; CS#, Command, Address, Bank Address, Data IO: MID-LEVEL;DM:stable at 0; Bank Activity:
Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: MID-LEVEL
IDD6ET
- 34 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
[ Table 35 ] Basic IDD and IDDQ Measurement Conditions
Symbol
Description
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 34 on page 32 ; BL: 81); AL: CL-1; CS: High between ACT and RDA;
Command, Address, Bank Address Inputs: partially toggling according to Table 39 on page 35 ; Data IO: read data bursts with different data between one
burst and the next one according to Table 39 ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing,
IDD7
IDD8
see Table 39 ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 39
RESET Low Current
RESET : Low; External clock : off; CK and CK : LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :
FLOATING
NOTE :
1. Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
2. Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
3. Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
4. Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
5. Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
6. Read Burst type : Nibble Sequential, set MR0 A[3]=0B
- 35 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
1)
[ Table 36 ] IDD0 Measurement - Loop Pattern
0
0
1,2
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
3,4
...
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
repeat pattern 1...4 until nRC - 1, truncate if necessary
nRAS
0
0
1
0
0
0
00
0
0
0
0
-
...
1*nRC + 0
1*nRC + 1, 2
1*nRC + 3, 4
...
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
F
F
F
0
0
0
-
-
-
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
PRE 00
1*nRC + nRAS
...
0
0
1
0
0
0
0
0
F
0
repeat 1...4 until 2*nRC - 1, truncate if necessary
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
1
2
3
4
5
6
7
2*nRC
4*nRC
6*nRC
8*nRC
10*nRC
12*nRC
14*nRC
NOTE :
1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
- 36 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
1)
[ Table 37 ] IDD1 Measurement - Loop Pattern
0
0
1,2
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
3,4
...
repeat pattern 1...4 until nRCD- 1, truncate if necessary
RD
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
repeat pattern 1...4 until nRC - 1, truncate if necessary
nRCD
...
0
1
0
1
0
0
00
00
0
0
0
0
0
0
0
0
00000000
-
nRAS
0
0
1
0
0
0
...
1*nRC+0
1*nRC + 1, 2
1*nRC + 3, 4
...
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
F
F
F
0
0
0
-
-
-
repeat pattern nRC + 1,..., 4 until nRC + nRCD - 1, truncate if necessary
RD 00
repeat pattern nRC + 1,..., 4 until nRC +nRAS - 1, truncate if necessary
1*nRC + nRCD
...
0
1
0
1
0
0
0
0
F
F
0
0
00110011
-
1*nRC + nRAS
...
PRE
0
0
1
0
0
0
00
0
0
repeat pattern nRC + 1,..., 4 until 2 * nRC - 1, truncate if necessary
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
1
2
3
4
5
6
7
2*nRC
4*nRC
6*nRC
8*nRC
10*nRC
12*nRC
14*nRC
NOTE :
1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
1)
[ Table 38 ] IDD2 and IDD3N Measurement - Loop Pattern
0
0
D
D
D
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
00
00
00
00
0
0
0
0
0
0
0
0
0
0
F
F
0
0
0
0
-
-
-
-
1
2
3
1
2
3
4
5
6
7
4-7
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
8-11
12-15
16-19
20-23
24-27
28-31
NOTE :
1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
- 37 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
1)
[ Table 39 ] IDD2NT and IDDQ2NT Measurement - Loop Pattern
0
0
D
D
D
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
00
00
00
00
0
0
0
0
0
0
0
0
0
0
F
F
0
0
0
0
-
1
2
3
1
2
3
4
5
6
7
4-7
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
8-11
12-15
16-19
20-23
24-27
28-31
NOTE :
1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
1)
[ Table 40 ] IDD4R and IDDQ4R Measurement - Loop Pattern
0
0
RD
D
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
0
0
0
00000000
1
-
2,3
D,D
RD
D
-
4
00110011
5
-
-
6,7
D,D
1
2
3
4
5
6
7
8-15
16-23
24-31
32-39
40-47
48-55
56-63
repeat Sub-Loop 0, but BA[2:0] = 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 0, but BA[2:0] = 3
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 0, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 0, but BA[2:0] = 7
NOTE :
1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
- 38 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
1)
[ Table 41 ] IDD4W Measurement - Loop Pattern
0
0
WR
D
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
0
0
0
00000000
1
-
2,3
D,D
WR
D
-
4
00110011
5
-
-
6,7
D,D
1
2
3
4
5
6
7
8-15
16-23
24-31
32-39
40-47
48-55
56-63
repeat Sub-Loop 0, but BA[2:0] = 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 0, but BA[2:0] = 3
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 0, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 0, but BA[2:0] = 7
NOTE :
1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
1)
[ Table 42 ] IDD5B Measurement - Loop Pattern
0
1
0
1,2
REF
D
0
1
1
0
0
1
0
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
0
0
F
0
0
0
-
-
-
3,4
D,D
5...8
repeat cycles 1...4, but BA[2:0] = 1
repeat cycles 1...4, but BA[2:0] = 2
repeat cycles 1...4, but BA[2:0] = 3
repeat cycles 1...4, but BA[2:0] = 4
repeat cycles 1...4, but BA[2:0] = 5
repeat cycles 1...4, but BA[2:0] = 6
repeat cycles 1...4, but BA[2:0] = 7
9...12
13...16
17...20
21...24
25...28
29...32
33...nRFC - 1
2
repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
NOTE :
1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
- 39 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
1)
[ Table 43 ] IDD7 Measurement - Loop Pattern
0
1
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
00
00
00
0
1
0
0
0
0
0
0
0
0
0
0
-
00000000
-
0
1
2
...
repeat above D Command until nRRD - 1
nRRD
nRRD + 1
nRRD + 2
...
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
00
00
00
0
1
0
0
0
0
F
F
F
0
0
0
-
00110011
-
repeat above D Command until 2*nRRD-1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 1, but BA[2:0] = 3
2
3
2 * nRRD
3 * nRRD
D
1
0
0
0
0
3
00
0
0
F
0
-
4
4 * nRRD
Assert and repeat above D Command until nFAW - 1, if necessary
repeat Sub-Loop 0, but BA[2:0] = 4
5
6
7
8
nFAW
nFAW+nRRD
nFAW+2*nRRD
nFAW+3*nRRD
repeat Sub-Loop 1, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 1, but BA[2:0] = 7
D
1
0
0
0
0
7
00
0
0
F
0
-
9
nFAW+4*nRRD
Assert and repeat above D Command until 2*nFAW - 1, if necessary
2*nFAW+0
2*nFAW+1
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
00
00
00
0
1
0
0
0
0
F
F
F
0
0
0
-
00110011
-
10
2*nFAW+2
Repeat above D Command until 2*nFAW + nRRD - 1
2*nFAW+nRRD
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
00
00
00
0
1
0
0
0
0
0
0
0
0
0
0
-
2*nFAW+nRRD+1
00000000
-
11
2*nFAW+nRRD+2
Repeat above D Command until 2*nFAW + 2*nRRD - 1
repeat Sub-Loop 10, but BA[2:0] = 2
12
13
2*nFAW+2*nRRD
2*nFAW+3*nRRD
repeat Sub-Loop 11, but BA[2:0] = 3
D
1
0
0
0
0
3
00
0
0
0
0
-
14
2*nFAW+4*nRRD
Assert and repeat above D Command until 3*nFAW - 1, if necessary
repeat Sub-Loop 10, but BA[2:0] = 4
15
16
17
18
3*nFAW
3*nFAW+nRRD
3*nFAW+2*nRRD
3*nFAW+3*nRRD
repeat Sub-Loop 11, but BA[2:0] = 5
repeat Sub-Loop 10, but BA[2:0] = 6
repeat Sub-Loop 11, but BA[2:0] = 7
D
1
0
0
0
0
7
00
0
0
0
0
-
19
3*nFAW+4*nRRD
Assert and repeat above D Command until 4*nFAW - 1, if necessary
NOTE :
1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation. DQ signals are MID-LEVEL.
- 40 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
11. 2Gb DDR3L SDRAM Q-die IDD Specification Table
[ Table 44 ] IDD Specification for 2Gb DDR3L Q-die
128Mx16 (K4B2G1646Q)
Symbol
DDR3-1333 (9-9-9)
DDR3L-1600 (11-11-11)
DDR3L-1866 (13-13-13)
Unit
NOTE
1.35V
1.5V
48
1.35V
47
1.5V
51
1.35V
49
1.5V
53
IDD0
IDD1
45
65
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
70
70
76
71
77
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
10
11
10
11
10
12
10
11
10
11
11
12
14
16
15
18
15
17
IDD2NT
IDDQ2NT
IDD2Q
16
19
17
20
18
21
126
14
132
16
126
15
132
17
126
15
132
18
IDD3P
14
15
15
16
15
16
IDD3N
35
38
37
40
39
42
IDD4R
124
96
138
100
126
133
11
144
96
159
100
144
135
11
166
96
183
100
162
135
11
IDDQ4R
IDD4W
113
130
10
130
132
10
146
132
10
IDD5B
IDD6
2
3
IDD6ET
IDD7
13
14
13
14
13
14
182
10
193
10
207
10
219
10
226
10
238
10
IDD8
NOTE :
1. VDD condition : 1.45V for 1.35V operation
2. Applicable for MR2 setting A6=0 and A7=0. Temperature range for IDD6 is 0 - 85°C at commercial temperature, -40 - 85°C at industrial temperature.
-. Commercial temperature : K4B2G1646Q-BYxx
-. Industrial temperature : K4B2G1646Q-BMxx.
3. Applicable for MR2 setting A6=0 and A7=1. Temperature range for IDD6ET is 0 - 95°C at commercial temperature & industrial temperature.
- 41 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
12. Input/Output Capacitance
[ Table 45 ] Input/Output Capacitance
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
Parameter
Symbol
Units NOTE
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
1.35V
Input/output capacitance
CIO
CCK
1.4
0.8
0
2.5
1.6
0.15
1.3
0.2
0.3
0.5
1.4
0.8
0
2.5
1.6
0.15
1.3
0.2
0.3
0.5
1.4
0.8
0
2.3
1.4
1.4
0.8
0
2.2
1.4
1.4
0.8
0
2.0
1.4
pF
pF
pF
pF
pF
pF
pF
1,2,3
2,3
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance
(CK and CK)
Input capacitance delta
(CK and CK)
CDCK
CI
0.15
1.3
0.15
1.2
0.15
1.2
2,3,4
Input capacitance
0.75
0
0.75
0
0.75
0
0.75
0
0.75
0
2,3,6
(All other input-only pins)
Input/Output capacitance delta
(DQS and DQS)
CDDQS
CDI_CTRL
0.15
0.2
0.15
0.2
0.15
0.2
2,3,5
Input capacitance delta
-0.5
-0.5
-0.5
-0.5
-0.4
-0.4
-0.4
-0.4
-0.4
-0.4
2,3,7,8
2,3,9,10
(All control input-only pins)
Input capacitance delta
CDI_ADD_CMD -0.5
0.4
0.4
0.4
(all ADD and CMD input-only pins)
Input/output capacitance delta
CDIO
CZQ
-0.5
-
0.3
3
0.3
3
-0.5
-
0.3
3
-0.5
-
0.3
3
-0.5
-
0.3
3
pF
pF
2,3,11
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input/output capacitance of ZQ pin
-
2, 3, 12
1.5V
Input/output capacitance
CIO
CCK
1.4
0.8
0
3.0
1.6
0.15
1.4
0.2
0.3
0.5
1.4
0.8
0
2.7
1.6
1.4
0.8
0
2.5
1.4
1.4
0.8
0
2.3
1.4
1.4
0.8
0
2.2
1.3
pF
pF
pF
pF
pF
pF
pF
1,2,3
2,3
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance
(CK and CK)
Input capacitance delta
(CK and CK)
CDCK
CI
0.15
0.15
1.3
0.15
1.3
0.15
1.2
2,3,4
Input capacitance
0.75
0
0.75 1.35 0.75
0.75
0
0.75
0
2,3,6
(All other input-only pins)
Input capacitance delta
(DQS and DQS)
CDDQS
CDI_CTRL
0
0.2
0.3
0.5
0
0.15
0.2
0.15
0.2
0.15
0.2
2,3,5
Input capacitance delta
-0.5
-0.5
-0.5
-0.4
-0.4
-0.4
-0.4
-0.4
-0.4
2,3,7,8
2,3,9,10
(All control input-only pins)
Input capacitance delta
CDI_ADD_CMD -0.5
0.4
0.4
0.4
(all ADD and CMD input-only pins)
Input/output capacitance delta
CDIO
CZQ
-0.5
-
0.3
3
-0.5
-
0.3
3
-0.5
-
0.3
3
-0.5
-
0.3
3
-0.5
-
0.3
3
pF
pF
2,3,11
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input/output capacitance of ZQ pin
2, 3, 12
NOTE :
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS
2. This parameter is not subject to production test. It is verified by design and characterization.
The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with
DD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). VDD=VDDQ=1.5V or 1.35V, VBIAS=VDD/2 and on-
V
die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK
5. Absolute value of CIO(DQS)-CIO(DQS)
6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.
7. CDI_CTRL applies to ODT, CS and CKE
8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))
9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))
12. Maximum external load capacitance on ZQ pin: 5pF
- 42 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-1866
13.1 Clock Specification
The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the DDR3
SDRAM device.
13.1.1 Definition for tCK(avg)
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to
rising edge.
N
tCKj
N=200
N
j=1
13.1.2 Definition for tCK(abs)
tCK(abs) is defind as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject to produc-
tion test.
13.1.3 Definition for tCH(avg) and tCL(avg)
tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses:
tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses:
N
N
tCHj
tCLj
N x tCK(avg) N=200
N x tCK(avg)
N=200
j=1
j=1
13.1.4 Definition for note for tJIT(per), tJIT(per, Ick)
tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = min/max of {tCKi-tCK(avg) where i=1 to 200}
tJIT(per) defines the single period jitter when the DLL is already locked.
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT(per) and tJIT(per,lck) are not subject to production test.
13.1.5 Definition for tJIT(cc), tJIT(cc, Ick)
tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of {tCKi+1-tCKi}
tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.
tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
tJIT(cc) and tJIT(cc,lck) are not subject to production test.
13.1.6 Definition for tERR(nper)
tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR is not subject to production test.
- 43 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
13.2 Refresh Parameters by Device Density
[ Table 46 ] Refresh parameters by device density
Parameter
Symbol
1Gb
110
7.8
2Gb
160
7.8
4Gb
260
7.8
8Gb
350
7.8
Units
ns
NOTE
All Bank Refresh to active/refresh cmd time
tRFC
0CT
85C
85C
s
CASE
-40CT
85CT
Average periodic refresh interval
tREFI
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
s
s
2
1
CASE
95C
CASE
NOTE :
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in
this material.
2. Supported only for Industrial Temperature.
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin
DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
[ Table 47 ] DDR3-800 Speed Bins
Speed
DDR3-800
6 - 6 - 6
CL-nRCD-nRP
Units
NOTE
Parameter
Symbol
tAA
min
15
max
Internal read command to first data
ACT to internal read or write delay time
PRE command period
20
ns
ns
tRCD
15
-
tRP
15
-
-
ns
ACT to ACT or REF command period
ACT to PRE command period
tRC
52.5
37.5
3.0
2.5
ns
tRAS
9*tREFI
3.3
ns
CL = 5
CWL = 5
CWL = 5
tCK(AVG)
tCK(AVG)
ns
1,2,3,4,10,11
1,2,3
CL = 6
3.3
ns
Supported CL Settings
Supported CWL Settings
5,6
5
nCK
nCK
[ Table 48 ] DR3-1066 Speed Bins
Speed
CL-nRCD-nRP
Parameter
DDR3-1066
7 - 7 - 7
Units
NOTE
Symbol
tAA
min
max
Internal read command to first data
ACT to internal read or write delay time
PRE command period
13.125
13.125
13.125
50.625
37.5
20
ns
ns
ns
ns
ns
tRCD
tRP
-
-
ACT to ACT or REF command period
ACT to PRE command period
tRC
-
tRAS
9*tREFI
1,2,3,4,5,10,
11
CWL = 5
tCK(AVG)
3.0
3.3
ns
CL = 5
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
Reserved
ns
ns
4
1,2,3,5
1,2,3,4
4
2.5
3.3
CL = 6
CL = 7
CL = 8
Reserved
Reserved
ns
ns
1.875
1.875
<2.5
<2.5
ns
1,2,3,4,9
4
Reserved
ns
ns
1,2,3
Supported CL Settings
Supported CWL Settings
5,6,7,8
5,6
nCK
nCK
- 44 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
[ Table 49 ] DDR3-1333 Speed Bins
Speed
DDR3-1333
CL-nRCD-nRP
9 -9 - 9
Units
NOTE
Parameter
Symbol
min
max
13.5
(13.125)
Internal read command to first data
tAA
20
ns
ns
ns
9
9
9
9
13.5
(13.125)
ACT to internal read or write delay time
PRE command period
tRCD
tRP
-
-
13.5
(13.125)
49.5
(49.125)
ACT to ACT or REF command period
ACT to PRE command period
tRC
tRAS
-
ns
ns
ns
36
9*tREFI
3.3
1,2,3,4,6,10,
11
CWL = 5
tCK(AVG)
3.0
CL = 5
CL = 6
CWL = 6,7
CWL = 5
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5,6
CWL = 7
CWL = 5,6
CWL = 7
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
Reserved
ns
ns
4
1,2,3,6
1,2,3,4,6
4
2.5
3.3
Reserved
Reserved
Reserved
ns
ns
ns
4
CL = 7
CL = 8
1.875
1.875
<2.5
<2.5
ns
1,2,3,4,6
1,2,3,4
4
Reserved
Reserved
ns
ns
ns
1,2,3,6
1,2,3,4
4
Reserved
Reserved
ns
ns
CL = 9
1.5
1.5
<1.875
<1.875
ns
1,2,3,4,9
4
Reserved
ns
CL = 10
ns
1,2,3
Supported CL Settings
Supported CWL Settings
5,6,7,8,9,10
5,6,7
nCK
nCK
- 45 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
[ Table 50 ] DDR3-1600 Speed Bins
Speed
DDR3-1600
CL-nRCD-nRP
11-11-11
Units
NOTE
Parameter
Symbol
min
max
13.75
(13.125)
Internal read command to first data
tAA
20
ns
ns
ns
9
9
9
9
13.75
(13.125)
ACT to internal read or write delay time
PRE command period
tRCD
tRP
-
-
13.75
(13.125)
48.75
(48.125)
ACT to ACT or REF command period
ACT to PRE command period
tRC
tRAS
-
ns
ns
ns
35
9*tREFI
3.3
1,2,3,4,7,10,
11
CWL = 5
tCK(AVG)
3.0
CL = 5
CL = 6
CWL = 6,7,8
CWL = 5
CWL = 6
CWL = 7, 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5,6
CWL = 7
CWL = 8
CWL = 5,6
CWL = 7
CWL = 8
CWL = 5,6,7
CWL = 8
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
Reserved
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
nCK
nCK
4
1,2,3,7
1,2,3,4,7
4
2.5
3.3
Reserved
Reserved
Reserved
4
1.875
1.875
<2.5
<2.5
1,2,3,4,7
1,2,3,4,7
4
CL = 7
Reserved
Reserved
Reserved
4
1,2,3,7
1,2,3,4,7
1,2,3,4
4
CL = 8
CL = 9
Reserved
Reserved
Reserved
1.5
1.5
<1.875
<1.875
<1.5
1,2,3,4,7
1,2,3,4
4
Reserved
Reserved
CL = 10
CL = 11
1,2,3,7
1,2,3,4
4
Reserved
Reserved
1.25
1,2,3,9
Supported CL Settings
Supported CWL Settings
5,6,7,8,9,10,11
5,6,7,8
- 46 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
[ Table 51 ] DDR3-1866 Speed Bins
Speed
DDR3-1866
CL-nRCD-nRP
13-13-13
Units
NOTE
Parameter
Symbol
min
max
13.91
(13.125)
Internal read command to first data
tAA
20
ns
ns
ns
12
12
12
12
13.91
(13.125)
ACT to internal read or write delay time
PRE command period
tRCD
tRP
-
-
13.91
(13.125)
47.91
(47.125)
ACT to ACT or REF command period
ACT to PRE command period
tRC
tRAS
-
ns
ns
ns
34
9*tREFI
3.3
1,2,3,4,8,10,
11
CWL = 5
tCK(AVG)
3.0
CL = 5
CL = 6
CWL = 6,7,8,9
CWL = 5
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
Reserved
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
nCK
nCK
4
2.5
3.3
1,2,3,8
CWL = 6
Reserved
Reserved
Reserved
1,2,3,4,8
CWL = 7,8,9
CWL = 5
4
4
CL = 7
CL = 8
CWL = 6
1.875
1.875
2.5
1,2,3,4,8
CWL = 7,8,9
CWL = 5
Reserved
Reserved
4
4
CWL = 6
<2.5
1,2,3,8
CWL = 7
Reserved
Reserved
Reserved
1,2,3,4,8
CWL = 8,9
CWL = 5,6
CWL = 7
4
4
1.5
1.875
1,2,3,4,8
CL = 9
CWL = 8
Reserved
Reserved
Reserved
4
4
CWL = 9
CWL = 5,6
CWL = 7
4
CL = 10
CL = 11
1.5
<1.875
1.5
1,2,3,8
1,2,3,4,8
4
CWL = 8
Reserved
Reserved
CWL = 5,6,7
CWL = 8
1.25
1,2,3,4,8
1,2,3,4
4
CWL = 9
Reserved
Reserved
Reserved
Reserved
CWL = 5,6,7,8
CWL = 9
CL = 12
CL = 13
1,2,3,4
4
CWL = 5,6,7,8
CWL = 9
1.071
<1.25
1,2,3,9
Supported CL Settings
Supported CWL Settings
5,6,7,8,9,10,11,13
5,6,7,8,9
- 47 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
13.3.1 Speed Bin Table Notes
Absolute Specification {T
; V
= V = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)};
OPER
DDQ DD
NOTE :
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements
from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guar-
anteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns],
rounding up to the next "Supported CL".
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or
1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.
4. "Reserved" settings are not allowed. User must program a different value.
5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
8. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
9. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to match. For example,
DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte
20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte
18), and tRPmin (Byte 20). DDR3-1866(CL13) devices supporting downshift to DDR3-1600(CL11) or DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in
SPD bytes for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600 devices supporting down binning to DDR3-1333 or DDR3-1066 should program
13.125ns in SPD byte for tAAmin (Byte 16), tRCDmin (Byte 18) and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be
programmed accodingly. For example, 49.125ns, (tRASmin + tRPmin = 36ns + 13.125ns) for DDR3-1333 and 48.125ns (tRASmin + tRPmin = 35ns + 13.125ns) for DDR3-
1600.
10. DDR3 800 AC timing apply if DRAM operates at lower than 800 MT/s data rate.
11. For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not mandatory in SPD coding.
12. For devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/tRPmin must be 13.125ns. SPD setting must be programed to match. For example,
DDR3-1866 devices supporting down binning to DDR3-1600 or DDR3-1333 or 1066 should program 13.125ns in SPD bytes for tAAmin(byte16), tRCDmin(Byte18) and tRP-
min (byte20). Once tRP (Byte20) is programmed to 13.125ns, tRCmin (Byte21,23) also should be programmed accordingly. For example, 47.125ns (tRASmin + tRPmin =
34ns + 13.125ns)
- 48 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
14. Timing Parameters by Speed Grade
[ Table 52 ] Timing Parameters by Speed Bin(Cont.)
Speed
Parameter
DDR3-800
DDR3-1066
MIN MAX
DDR3-1333
MIN MAX
DDR3-1600
MIN MAX
DDR3-1866
Units
NOTE
Symbol
MIN
MAX
MIN
MAX
Clock Timing
tCK(DLL_OF
F)
Minimum Clock Cycle Time (DLL off mode)
Average Clock Period
8
-
8
-
8
-
8
-
8
-
ns
ps
6
tCK(avg)
See Speed Bins Table
tCK(avg)ma
tCK(avg)ma
tCK(avg)mi
x +
tJIT(per)ma
tJIT(per)min
x
tCK(avg)ma
tCK(avg)ma
tCK(avg)ma
tCK(avg)mi
n +
tJIT(per)min
tCK(avg)mi
n +
tJIT(per)min
tCK(avg)mi
n +
tJIT(per)min
tCK(avg)mi
n +
tJIT(per)min
x +
tJIT(per)ma
x
x +
tJIT(per)ma
x
x +
tJIT(per)ma
x
x +
tJIT(per)ma
x
n +
Clock Period
tCK(abs)
ps
Average high pulse width
tCH(avg)
tCL(avg)
0.47
0.47
-100
-90
0.53
0.53
100
90
0.47
0.47
-90
0.53
0.53
90
0.47
0.47
-80
0.53
0.53
80
0.47
0.47
-70
0.53
0.53
70
0.47
0.47
-60
0.53
0.53
60
tCK(avg)
Average low pulse width
tCK(avg)
ps
Clock Period Jitter
tJIT(per)
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
tJIT(per, lck)
tJIT(cc)
-80
80
-70
70
-60
60
-50
50
ps
200
180
180
160
160
140
140
120
120
100
ps
Cycle to Cycle Period Jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
tJIT(cc, lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(10per)
tERR(11per)
tERR(12per)
ps
- 147
- 175
- 194
- 209
- 222
- 232
- 241
- 249
- 257
- 263
- 269
147
175
194
209
222
232
241
249
257
263
269
- 132
- 157
- 175
- 188
- 200
- 209
- 217
- 224
- 231
- 237
- 242
132
157
175
188
200
209
217
224
231
237
242
- 118
- 140
- 155
- 168
- 177
- 186
- 193
- 200
- 205
- 210
- 215
118
140
155
168
177
186
193
200
205
210
215
-103
-122
-136
-147
-155
-163
-169
-175
-180
-184
-188
103
122
136
147
155
163
169
175
180
184
188
-88
88
ps
-105
-117
-126
-133
-139
-145
-150
-154
-158
-161
105
117
126
133
139
145
150
154
158
161
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tERR(nper)max = (1 + 0.68ln(n))*tJIT(per)max
Cumulative error across n = 13, 14 ... 49, 50 cycles
tERR(nper)
ps
24
Absolute clock HIGH pulse width
Absolute clock Low pulse width
Data Timing
tCH(abs)
tCL(abs)
0.43
0.43
-
-
0.43
0.43
-
-
0.43
0.43
-
-
0.43
0.43
-
-
0.43
0.43
-
-
tCK(avg)
tCK(avg)
25
26
DQS,DQS to DQ skew, per group, per access
DQ output hold time from DQS, DQS
DQ low-impedance time from CK, CK
DQ high-impedance time from CK, CK
tDQSQ
tQH
-
200
-
-
150
-
-
125
-
-
100
-
-
85
-
ps
tCK(avg)
ps
13
0.38
-800
-
0.38
-600
-
0.38
-500
-
0.38
-450
-
0.38
-390
-
13, g
tLZ(DQ)
tHZ(DQ)
400
400
300
300
250
250
225
225
195
195
13,14, f
13,14, f
ps
1.35V
tDS(base)
AC160
90
140
-
40
90
-
-
45
-
-
-
-
25
-
-
-
-
-
-
-
-
-
ps
ps
ps
d, 17
d, 17
d, 17
-
-
-
-
-
-
tDS(base)
AC135
tDS(base)
AC125
-
1.5V
-
10
Data setup time to DQS, DQS referenced to
V
(AC)V (AC) levels
IH
IL
tDS(base)
AC175
75
125
-
25
75
-
-
30
-
-
10
-
-
-
-
-
-
-
-
-
ps
ps
ps
d, 17
d, 17
d, 17
-
-
-
-
-
-
tDS(base)
AC150
-
tDS(base)
AC135
-
68
1.35V
tDH(base)
DC90
160
110
75
-
55
-
30
-
ps
d, 17
-
-
Data hold time from DQS, DQS referenced to
(DC)V (DC) levels
V
IH
IL
1.5V
tDH(base)
DC100
150
600
100
490
65
-
45
-
20
-
ps
ps
d, 17
28
-
-
-
-
DQ and DM Input pulse width for each input
tDIPW
400
360
320
-
-
-
- 49 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
[ Table 52 ] Timing Parameters by Speed Bin (Cont.)
Speed
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
Units
NOTE
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Data Strobe Timing
DQS, DQS differential READ Preamble
DQS, DQS differential READ Postamble
DQS, DQS differential output high time
DQS, DQS differential output low time
DQS, DQS differential WRITE Preamble
DQS, DQS differential WRITE Postamble
tRPRE
tRPST
tQSH
0.9
0.3
Note 19
0.9
0.3
Note 19
0.9
0.3
0.4
0.4
0.9
0.3
Note 19
0.9
0.3
0.4
0.4
0.9
0.3
Note 19
0.9
0.3
0.4
0.4
0.9
0.3
NOTE 19 tCK(avg) 13, 19, g
NOTE 11 tCK(avg) 11, 13, b
Note 11
Note 11
Note 11
Note 11
0.38
0.38
0.9
-
-
-
-
0.38
0.38
0.9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
13, g
13, g
tQSL
tWPRE
tWPST
0.3
0.3
DQS, DQS rising edge output access time from rising
CK, CK
tDQSCK
tLZ(DQS)
tHZ(DQS)
-400
-800
-
400
400
400
-300
-600
-
300
300
300
-255
-500
-
255
250
250
-225
-450
-
225
225
225
-195
-390
-
195
195
195
ps
ps
ps
13,f
DQS, DQS low-impedance time (Referenced from RL-
1)
13,14,f
12,13,14
DQS, DQS high-impedance time (Referenced from
RL+BL/2)
DQS, DQS differential input low pulse width
DQS, DQS differential input high pulse width
DQS, DQS rising edge to CK, CK rising edge
DQS,DQS falling edge setup time to CK, CK rising edge
DQS,DQS falling edge hold time to CK, CK rising edge
Command and Address Timing
tDQSL
tDQSH
tDQSS
tDSS
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.27
0.18
0.18
0.55
0.55
0.27
-
0.45
0.45
-0.27
0.18
0.18
0.55
0.55
0.27
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
29, 31
30, 31
c
c, 32
c, 32
tDSH
0.2
-
0.2
-
0.2
-
-
-
DLL locking time
tDLLK
tRTP
512
-
-
512
-
-
512
-
-
512
-
-
512
-
-
nCK
max
(4nCK,7.5
ns)
max
(4nCK,7.5
ns)
max
(4nCK,7.5n
s)
max
(4nCK,7.5
ns)
max
(4nCK,7.5
ns)
internal READ Command to PRECHARGE Command
delay
e
max
(4nCK,7.5
ns)
max
(4nCK,7.5
ns)
max
(4nCK,7.5n
s)
max
(4nCK,7.5
ns)
max
(4nCK,7.5
ns)
Delay from start of internal write transaction to internal
read command
tWTR
-
-
-
-
-
e,18
e
WRITE recovery time
tWR
15
4
-
-
15
4
-
-
15
4
-
-
15
4
-
-
15
4
-
-
ns
Mode Register Set command cycle time
tMRD
nCK
max
(12nCK,15
ns)
max
(12nCK,15
ns)
max
(12nCK,15
ns)
max
(12nCK,15
ns)
max
(12nCK,15
ns)
Mode Register Set command update delay
tMOD
-
-
-
-
-
-
-
-
CAS to CAS command delay
tCCD
tDAL(min)
tMPRR
tRAS
4
4
-
4
-
4
4
nCK
nCK
nCK
ns
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
ACTIVE to PRECHARGE command period
WR + roundup (tRP / tCK(AVG))
1
-
1
-
1
-
1
-
1
-
22
e
See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin”
max
(4nCK,10n
s)
max
(4nCK,7.5
ns)
max
(4nCK,6ns
)
max
(4nCK,
5ns)
max
(4nCK,6ns)
ACTIVE to ACTIVE command period for 1KB page size
ACTIVE to ACTIVE command period for 2KB page size
tRRD
tRRD
-
-
-
-
-
-
-
-
-
-
e
e
max
(4nCK,10n
s)
max
(4nCK,10n
s)
max
(4nCK,7.5n
s)
max
(4nCK,7.5
ns)
max
(4nCK,
6ns)
Four activate window for 1KB page size
Four activate window for 2KB page size
tFAW
tFAW
40
50
-
-
37.5
50
-
-
30
45
-
-
30
40
-
-
27
35
-
-
ns
ns
e
e
1.35V
tIS(base)
AC160
215
365
-
140
290
-
80
205
-
-
-
60
185
-
-
-
-
-
-
-
-
-
ps
ps
ps
b,16
-
-
-
-
-
-
tIS(base)
AC135
b,16,27
b,16,27
tIS(base)
AC125
75
-
1.5V
-
Command and Address setup time to CK, CK refer-
enced to V (AC) / V (AC) levels
IH
IL
tIS(base)
AC175
200
125
65
45
-
-
-
-
-
-
-
-
-
-
ps
ps
ps
ps
b,16
b,16,27
b,16
-
-
-
-
-
-
-
-
tIS(base)
AC150
350
275
190
-
-
-
170
tIS(base)
AC135
-
-
-
-
-
-
-
-
65
150
tIS(base)
AC125
b,16,27
- 50 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
[ Table 52 ] Timing Parameters by Speed Bin (Cont.)
Speed
DDR3-800
DDR3-1066
DDR3-1333
MIN MAX
DDR3-1600
DDR3-1866
Units
NOTE
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Command and Address Timing
1.35V
1.5V
tIH(base)
DC90
285
210
150
-
130
-
110
-
ps
b,16
-
-
Command and Address hold time from CK, CK refer-
enced to V (DC) / V (DC) levels
IH
IL
tIH(base)
DC100
275
900
200
780
140
620
120
560
-
100
535
-
ps
ps
b,16
28
Control & Address Input pulse width for each input
tIPW
-
-
-
-
-
-
-
-
Calibration Timing
max(512n
CK,640ns
)
Power-up and RESET calibration time
Normal operation Full calibration time
tZQinitI
512
512
512
512
-
-
nCK
max(256n
CK,320ns
)
tZQoper
tZQCS
256
64
-
-
256
64
-
-
256
64
-
-
256
64
-
-
-
-
nCK
nCK
max(64nC
K,80ns)
Normal operation short calibration time
23
Reset Timing
max(5nC
K,
tRFC(min)
+ 10ns)
max(5nC
K, tRFC +
10ns)
max(5nC
K, tRFC +
10ns)
max(5nC
K, tRFC +
10ns)
max(5nC
K, tRFC +
10ns)
Exit Reset from CKE HIGH to a valid command
tXPR
-
-
-
-
-
Self Refresh Timing
max(5nC
K,tRFC +
10ns)
max(5nC
K,tRFC +
10ns)
max(5nC
K,tRFC +
10ns)
max(5nC
K,tRFC +
10ns)
max(5nC
K,tRFC(m
in) + 10ns)
Exit Self Refresh to commands not requiring a locked
DLL
tXS
-
-
-
-
-
Exit Self Refresh to commands requiring a locked
DLL
tDLLK(mi
n)
tDLLK(mi
n)
tDLLK(mi
n)
tDLLK(mi
n)
tDLLK(mi
n)
tXSDLL
tCKESR
-
-
-
-
-
-
-
-
-
-
nCK
Minimum CKE low width for Self refresh entry to exit
timing
tCKE(min
) + 1tCK
tCKE(min
) + 1tCK
tCKE(min
) + 1tCK
tCKE(min)
+ 1tCK
tCKE(min)
+ 1nCK
max(5nC
K,
10ns)
max(5nC
K,
10ns)
max(5nC
K,
10ns)
max(5nC
K,
10ns)
max(5nC
K,
10ns)
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power-Down Entry (PDE)
tCKSRE
tCKSRX
-
-
-
-
-
-
-
-
-
-
max(5nC
K,
10ns)
max(5nC
K,
10ns)
max(5nC
K,
10ns)
max(5nC
K,
10ns)
max(5nC
K,
10ns)
Valid Clock Requirement before Self Refresh Exit
(SRX) or Power-Down Exit (PDX) or Reset Exit
Power Down Timing
Exit Power Down with DLL on to any valid com-
mand;Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
max
(3nCK,
7.5ns)
max
(3nCK,
7.5ns)
max
(3nCK,6n
s)
max
(3nCK,6n
s)
max(3nC
K,6ns)
tXP
tXPDLL
tCKE
-
-
-
-
-
-
-
-
-
-
-
-
max
(10nCK,
24ns)
max
(10nCK,
24ns)
max
(10nCK,
24ns)
max
(10nCK,
24ns)
Exit Precharge Power Down with DLL frozen to com-
mands requiring a locked DLL
max(10nC
K,24ns)
2
max
(3nCK,
7.5ns)
max
(3nCK,
5.625ns)
max
(3nCK,
5.625ns)
max
(3nCK,5n
s)
max(3nC
K,5ns)
CKE minimum pulse width
-
-
-
-
-
-
Command pass disable delay
tCPDED
tPD
1
-
1
-
1
1
2
nCK
tCKE(min
)
tCKE(min
)
tCKE(min
)
Power Down Entry to Exit Timing
9*tREFI
9*tREFI
9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCK(avg)
15
Timing of ACT command to Power Down entry
Timing of PRE command to Power Down entry
Timing of RD/RDA command to Power Down entry
tACTPDEN
tPRPDEN
tRDPDEN
1
1
-
-
-
1
1
-
-
-
1
1
-
-
-
1
1
-
-
-
1
1
-
-
-
nCK
nCK
20
20
RL + 4 +1
RL + 4 +1
RL + 4 +1
RL + 4 +1
RL + 4 +1
WL + 4
+(tWR/
tCK(avg))
WL + 4
+(tWR/
tCK(avg))
WL + 4
+(tWR/
tCK(avg))
WL + 4
+(tWR/
tCK(avg))
WL + 4
+(tWR/
tCK(avg))
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDEN
tWRAPDEN
tWRPDEN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nCK
nCK
nCK
nCK
9
10
9
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
WL + 4
+WR +1
WL + 4
+WR +1
WL + 4
+WR +1
WL + 4
+WR +1
WL + 4
+WR +1
WL + 2
+(tWR/
tCK(avg))
WL + 2
+(tWR/
tCK(avg))
WL + 2
+(tWR/
tCK(avg))
WL + 2
+(tWR/
tCK(avg))
WL + 2
+(tWR/
tCK(avg))
Timing of WR command to Power Down entry
(BC4MRS)
Timing of WRA command to Power Down entry
(BC4MRS)
WL +2
+WR +1
WL +2
+WR +1
WL +2
+WR +1
WL +2
+WR +1
WL +2
+WR +1
tWRAPDEN
tREFPDEN
tMRSPDEN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
Timing of REF command to Power Down entry
Timing of MRS command to Power Down entry
ODT Timing
1
1
1
1
1
20,21
tMOD(mi
n)
tMOD(mi
n)
tMOD(mi
n)
tMOD(min
)
tMOD(min
)
ODT high time without write command or with write
command and BC4
ODTH4
ODTH8
4
6
-
-
4
6
-
-
4
6
-
-
4
6
-
-
4
6
-
-
nCK
nCK
ODT high time with Write command and BL8
- 51 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
[ Table 52 ] Timing Parameters by Speed Bin
Speed
DDR3-800
DDR3-1066
DDR3-1333
MIN MAX
DDR3-1600
DDR3-1866
Units NOTE
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
ODT Timing
Asynchronous RTT turn-on delay (Power-Down with
DLL frozen)
tAONPD
2
8.5
2
8.5
2
8.5
2
8.5
2
8.5
ns
Asynchronous RTT turn-off delay (Power-Down with
DLL frozen)
tAOFPD
tAON
2
8.5
400
0.7
0.7
2
8.5
300
0.7
0.7
2
8.5
250
0.7
0.7
2
8.5
225
0.7
0.7
2
8.5
195
0.7
0.7
ns
RTT turn-on
-400
0.3
0.3
-300
0.3
0.3
-250
0.3
0.3
-225
0.3
0.3
-195
0.3
0.3
ps
7,f
8,f
f
RTT_NOM and RTT_WR turn-off time from ODTLoff
reference
tAOF
tCK(avg)
tCK(avg)
RTT dynamic change skew
tADC
Write Leveling Timing
First DQS/DQS rising edge after write
leveling mode is programmed
tWLMRD
tWLDQSEN
tWLS
40
25
-
-
-
-
40
25
-
-
-
-
40
25
-
-
-
-
40
25
-
-
-
-
40
25
-
-
-
-
tCK(avg)
tCK(avg)
ps
3
3
DQS/DQS delay after write leveling
mode is programmed
Write leveling setup time from rising CK, CK crossing
to rising DQS, DQS crossing
325
325
245
245
195
195
165
165
140
140
Write leveling hold time from rising DQS, DQS cross-
ing to rising CK, CK crossing
tWLH
ps
Write leveling output delay
Write leveling output error
tWLO
0
0
9
2
0
0
9
2
0
0
9
2
0
0
7.5
2
0
0
7.5
2
ns
ns
tWLOE
- 52 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
14.1 Jitter Notes
Specific Note a
Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the
input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm,
another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.
Specific Note b
These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition
edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is,
these parameters should be met whether clock jitter is present or not.
Specific Note c
These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal (CK, CK)
crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative
to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.
Specific Note d
Specific Note e
These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective data
strobe signal (DQS(L/U), DQS(L/U)) crossing.
For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)},
which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the
device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge com-
mand at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter.
Specific Note f
When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input
clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = +
193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and
tDQSCK,max(derated) = tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800
derates to tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution
on the min/max usage!)
Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <=
12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.
Specific Note g
When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input
clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has
tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min +
tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) =
tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/
max usage!)
- 53 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
14.2 Timing Parameter Notes
1. Actual value dependant upon measurement level definitions see "Device Operation & Timing Diagram Datasheet".
2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register
5. Value must be rounded-up to next higher integer value
6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7. For definition of RTT turn-on time tAON see "Device Operation & Timing Diagram Datasheet"
8. For definition of RTT turn-off time tAOF see "Device Operation & Timing Diagram Datasheet".
9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
10. WR in clock cycles as programmed in MR0
11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See "Device Operation & Timing
Diagram Datasheet.
12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated
by 14.1-Jitter Notes on page 53
13. Value is only valid for RON34
14. Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method.
15. tREFI depends on T
OPER
16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,
(DC) = V DQ(DC). For input only pins except RESET, V (DC)=V CA(DC).
V
REF
REF
REF
REF
See Address/Command Setup, Hold and Derating : on page 55. .
17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,
(DC)= V DQ(DC). For input only pins except RESET, V (DC)=V CA(DC).
V
REF
REF
REF
REF
See Data Setup, Hold and Slew Rate Derating : on page 64.
18. Start of internal write transaction is defined as follows ;
For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL
19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation & Timing Diagram Data-
sheet"
20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down
IDD spec will not be applied until finishing those operations.
21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time
such as tXPDLL(min) is also required. See "Device Operation & Timing Diagram Datasheet".
22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming
the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The
appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub-
ject to in the application, is illustrated. The interval could be defined by the following formula:
ZQCorrection
(TSens x Tdriftrate) + (VSens x Vdriftrate)
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.
For example, if TSens = 1.5% /C, VSens = 0.15% / mV, Tdriftrate = 1C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calcu-
lated as:
0.5
~
~
128ms
= 0.133
(1.5 x 1) + (0.15 x 15)
24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.
26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.
27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter-
nate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].
28. Pulse width of a input signal is defined as the width between the first crossing of V
(DC) and the consecutive crossing of V
(DC)
REF
REF
29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge.
30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge.
31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
- 54 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
14.3 Address/Command Setup, Hold and Derating :
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value (see
Table 53) to the tIS and tIH derating value (see Table 55) respectively.
Example: tIS (total setup time) = tIS(base) + tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
V
(DC) and the first crossing of V (AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
REF
IH
V
(DC) and the first crossing of V (AC)max. If the actual signal is always earlier than the nominal slew rate line between shaded ’V
(DC) to ac
REF
REF
IL
region’, use nominal slew rate for derating value (see 21-Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and
tIS on page 60). If the actual signal is later than the nominal slew rate line anywhere between shaded ’V (DC) to ac region’, the slew rate of a tangent
REF
line to the actual signal from the ac level to dc level is used for derating value (see 23-Illustration of tangent line for setup time tDS (for DQ with respect to
strobe) and tIS on page 62).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V (DC)max and the first crossing of V
(DC).
REF
IL
Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V (DC)min and the first crossing of V
(DC). If
REF
IH
the actual signal is always later than the nominal slew rate line between shaded ’dc to V
(DC) region’, use nominal slew rate for derating value (see 22-
REF
Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH on page 61). If the actual signal is earlier than the nominal slew
rate line anywhere between shaded ’dc to V (DC) region’, the slew rate of a tangent line to the actual signal from the dc level to V (DC) level is used
REF
REF
for derating value (see 24-Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH on page 63).
For a valid transition the input signal has to remain above/below V (AC) for some time tVAC (see Table 51).
IH/IL
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached V
(AC) at the time of the rising clock
IH/IL
transition) a valid input signal is still required to complete the transition and reach V
(AC).
IH/IL
For slew rates in between the values listed in Table 55, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
[ Table 53 ] ADD/CMD Setup and Hold Base-Values for 1V/ns (1.35V)
[ps]
DDR3L-800
DDR3L-1066
DDR3L-1333
DDR3L-1600
DDR3L-1866 reference Note
tIS(base) AC160
tIS(base) AC135
tIS(base) AC125
tIH(base)-DC90
215
365
-
140
290
-
80
205
-
60
185
-
-
V
V
V
V
1
IH/L(AC)
IH/L(AC)
IH/L(AC)
IH/L(DC)
65
1,2
1,3
1
DDR3L
150
110
285
210
150
130
NOTE :
1. AC/DC referenced for 1V/ns Address/Command slew rate and 2 V/ns differential CK-CK# slew rate
2. The tIS(base) AC135 specifications are adjusted from the tIS(base) AC160 specification by adding an additional 125 ps for DDR3L-800/1066 or 100ps for DDR3L-1333/1600
of derating to accommodate for the lower alternate threshold of 135 mV and another 25 ps to account for the earlier reference point [(160mv - 135 mV) / 1 V/ns].
3. The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by adding an additional 75 ps for DDR3L-1866 of derating to accommodate for the
lower alternate threshold of 135 mV and another 10 ps to account for the earlier reference point [(135mv - 125 mV) / 1 V/ns].
[ Table 54 ] ADD/CMD Setup and Hold Base-Values for 1V/ns (1.5V)
[ps]
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
reference
tIS(base) AC175
tIS(base) AC150
tIS(base) AC135
tIS(base) AC125
tIS(base) AC100
200
350
-
125
275
-
65
190
-
45
170
-
-
V
V
V
V
V
IH/L(AC)
IH/L(AC)
IH/L(AC)
IH/L(AC)
IH/L(DC)
-
DDR3
65
150
100
-
-
-
-
275
200
140
120
NOTE:
1.AC/DC referenced for 1V/ns Address/Command slew rate and 2 V/ns differential CK-CK# slew rate
2.The tIS(base) AC150 specifications are adjusted from the tIS(base) AC175 specification by adding an additional 125 ps for DDR3-800/1066 or 100ps for DDR3-1333/1600 of
derating to accommodate for the lower alternate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].
3.The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by adding an additional 75 ps for DDR3-1866 and 65ps for DDR3-2133 to
accommodate for the lower alternate threshold of 125 mV and another 10 ps to account for the earlier reference point [(135 mv - 125 mV) / 1 V/ns].
- 55 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
[ Table 55 ] Derating values DDR3L-800/1066/1333/1600 tIS/tIH-AC/DC based AC160 Threshold (1.35V)
tIS, tIH Derating [ps] AC/DC based
AC160 Threshold -> V (AC) = V
(DC) + 160mV, V (AC) = V
(DC) - 160mV
IH
REF
IL
REF
CLK,CLK Differential Slew Rate
1.8 V/ns 1.6 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.4V/ns
1.2V/ns
tIS
1.0V/ns
tIS
tIS
tIH
45
tIS
tIH
45
tIS
tIH
45
tIS
tIH
53
38
8
tIS
tIH
61
46
16
13
9
tIS
104
77
24
23
21
19
16
4
tIH
69
54
24
21
17
11
4
tIH
79
64
34
31
27
21
14
4
tIH
95
80
50
47
43
37
30
20
5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
80
53
0
80
53
0
80
53
0
88
61
8
96
69
16
15
13
11
8
112
85
32
31
29
27
24
12
-8
120
93
40
39
37
35
32
20
0
30
30
30
0
0
0
CMD/
ADD
Slew
rate
-1
-3
-1
-3
-1
-3
7
5
-3
-8
-3
-8
-3
-8
5
1
-5
-13
-20
-30
-45
-5
-13
-20
-30
-45
-5
-13
-20
-30
-45
3
-5
3
V/ns
-8
-8
-8
0
-12
-22
-37
-4
-20
-40
-20
-40
-20
-40
-12
-32
-4
-14
-29
-6
-24
-16
-21
-11
[ Table 56 ] Derating values DDR3L-800/1066/1333/1600 tIS/tIH-AC/DC based - Alternate AC135 Threshold (1.35V)
tIS, tIH Derating [ps] AC/DC based
Alternate AC135 Threshold -> V (AC) = V
(DC) + 135mV, V (AC) = V
(DC) - 135mV
REF
IH
REF
IL
CLK,CLK Differential Slew Rate
1.8 V/ns 1.6 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.4V/ns
tIS
1.2V/ns
1.0V/ns
tIS
tIH
45
tIS
tIH
45
tIS
tIH
45
tIS
tIH
53
38
8
tIS
tIH
61
46
16
13
9
tIH
69
54
24
21
17
11
4
tIS
100
77
tIH
79
64
34
31
27
21
14
4
tIS
108
85
tIH
95
80
50
47
43
37
30
20
5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
68
45
0
68
45
0
68
45
0
76
53
8
84
61
16
18
19
22
25
21
14
92
69
24
26
27
30
33
29
22
30
30
30
0
0
0
32
40
CMD/
ADD
Slew
rate
2
-3
2
-3
2
-3
10
11
14
17
13
6
5
34
42
3
-8
3
-8
3
-8
1
35
43
6
-13
-20
-30
-45
6
-13
-20
-30
-45
6
-13
-20
-30
-45
-5
3
38
46
V/ns
9
9
9
-12
-22
-37
-4
41
49
5
5
5
-14
-29
-6
37
45
-3
-3
-3
-21
30
-11
38
[ Table 57 ] Derating values DDR3L-1866 tIS/tIH-AC/DC based - Alternate AC125 Threshold (1.35V)
tIS, tIH Derating [ps] AC/DC based
Alternate AC135 Threshold -> V (AC) = V
(DC) + 125mV, V (AC) = V
(DC) - 125mV
REF
IH
REF
IL
CLK,CLK Differential Slew Rate
1.8 V/ns 1.6 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.4V/ns
tIS
1.2V/ns
1.0V/ns
tIS
tIH
45
tIS
tIH
45
tIS
tIH
45
tIS
tIH
53
38
8
tIS
tIH
61
46
16
13
9
tIH
69
54
24
21
17
11
-4
tIS
95
74
32
35
38
42
48
47
45
tIH
79
64
34
31
27
21
14
4
tIS
103
82
tIH
95
80
50
47
43
37
30
20
5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
63
42
0
63
42
0
63
42
0
71
50
8
79
58
16
19
22
26
32
31
29
87
66
24
27
30
34
40
39
37
30
30
30
0
0
0
40
CMD/
ADD
Slew
rate
3
-3
3
-3
3
-3
11
14
18
24
23
21
5
43
6
-8
6
-8
6
-8
1
46
10
16
15
13
-13
-20
-30
-45
10
16
15
13
-13
-20
-30
-45
10
16
15
13
-13
-20
-30
-45
-5
3
50
V/ns
-12
-22
-37
4
56
-14
-29
-6
55
-21
-11
53
- 56 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
[ Table 58 ] Derating values DDR3-800/1066/1333/1600 tIS/tIH-AC/DC based AC175 Threshold(1.5V)
tIS, tIH Derating [ps] AC/DC based
Alternate AC175 Threshold -> V (AC) = V
(DC) + 175mV, V (AC) = V
(DC) - 175mV
REF
IH
REF
IL
CLK,CLK Differential Slew Rate
1.8 V/ns 1.6 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.4V/ns
tIS
1.2V/ns
tIS
1.0V/ns
tIS
tIH
50
tIS
tIH
50
tIS
tIH
50
tIS
tIH
58
42
8
tIS
tIH
66
50
16
12
6
tIH
74
58
24
20
14
8
tIH
84
68
34
30
24
18
8
tIS
tIH
100
84
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
88
59
0
88
59
0
88
59
0
96
67
8
104
75
16
14
10
5
112
83
24
22
18
13
7
120
91
32
30
26
21
15
-2
128
99
40
38
34
29
23
5
34
34
34
0
0
0
50
CMD/
ADD
Slew
rate
-2
-4
-2
-4
-2
-4
6
4
46
-6
-10
-16
-26
-40
-60
-6
-10
-16
-26
-40
-60
-6
-10
-16
-26
-40
-60
2
-2
40
-11
-17
-35
-62
-11
-17
-35
-62
-11
-17
-35
-62
-3
-9
-27
-54
-8
0
34
V/ns
-18
-32
-52
-1
-10
-24
-44
-2
24
-19
-46
-11
-38
-16
-36
-6
10
-30
-26
-22
-10
[ Table 59 ] Derating values DDR3-800/1066/1333/1600 tIS/tIH-AC/DC based AC150 Threshold (1.5V)
tIS, tIH Derating [ps] AC/DC based
Alternate AC150 Threshold -> V (AC) = V
(DC) + 150mV, V (AC) = V
(DC) - 150mV
REF
IH
REF
IL
CK,CK Differential Slew Rate
1.8 V/ns 1.6 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.4V/ns
tIS
1.2V/ns
1.0V/ns
tIS
tIH
50
tIS
tIH
50
tIS
tIH
50
tIS
tIH
58
42
8
tIS
tIH
66
50
16
12
6
tIH
74
58
24
20
14
8
tIS
107
82
32
32
32
32
31
22
7
tIH
84
68
34
30
24
18
8
tIS
115
90
tIH
100
84
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
75
50
0
75
50
0
75
50
0
83
58
8
91
66
16
16
16
16
15
6
99
74
24
24
24
24
23
14
-1
34
34
34
0
0
0
40
50
CMD/
ADD
Slew
rate
0
-4
0
-4
0
-4
8
4
40
46
0
-10
-16
-26
-40
-60
0
-10
-16
-26
-40
-60
0
-10
-16
-26
-40
-60
8
-2
40
40
0
0
0
8
-8
0
40
34
V/ns
-1
-10
-25
-1
-10
-25
-1
-10
-25
7
-18
-32
-52
-10
-24
-44
-2
39
24
-2
-17
-16
-36
-6
30
10
-9
-26
15
-10
[ Table 60 ] Derating values DDR3-1866 tIS/tIH-AC/DC based Alternate AC135 Threshold (1.5V)
tIS, tIH Derating [ps] AC/DC based
Alternate AC125 Threshold -> V (AC) = V
(DC) + 135mV, V (AC) = V
(DC) - 135mV
REF
IH
REF
IL
CLK,CLK Differential Slew Rate
1.8 V/ns 1.6 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.4V/ns
tIS
1.2V/ns
1.0V/ns
tIS
tIH
50
tIS
tIH
50
tIS
tIH
50
tIS
tIH
58
42
8
tIS
tIH
66
50
16
12
6
tIH
74
58
24
20
14
8
tIS
100
77
tIH
84
68
34
30
24
18
8
tIS
108
85
tIH
100
84
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
68
45
0
68
45
0
68
45
0
76
53
8
84
61
16
18
19
22
25
21
14
92
69
24
26
27
30
33
29
22
34
34
34
0
0
0
32
40
50
CMD/
ADD
Slew
rate
2
-4
2
-4
2
-4
10
11
14
17
13
6
4
34
42
46
3
-10
-16
-26
-40
-60
3
-10
-16
-26
-40
-60
3
-10
-16
-26
-40
-60
-2
35
43
40
6
6
6
-8
0
38
46
34
V/ns
9
9
9
-18
-32
-52
-10
-24
-44
-2
41
49
24
5
5
5
-16
-36
37
-6
45
10
-3
-3
-3
30
-26
38
-10
- 57 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
[ Table 61 ] Derating values DDR3-1866 tIS/tIH-AC/DC based - Alternate AC125 Threshold
tIS, tIH Derating [ps] AC/DC based
Alternate AC125 Threshold -> V (AC) = V
(DC) + 125mV, V (AC) = V
(DC) - 125mV
REF
IH
REF
IL
CLK,CLK Differential Slew Rate
1.8 V/ns 1.6 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.4V/ns
tIS
1.2V/ns
tIS
1.0V/ns
tIS
tIH
50
tIS
tIH
50
tIS
tIH
50
tIS
tIH
58
42
8
tIS
tIH
66
50
16
12
6
tIH
74
58
24
20
14
8
tIH
84
68
34
30
24
18
8
tIS
tIH
100
84
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
63
42
0
63
42
0
63
42
0
71
50
8
79
58
16
20
22
27
32
31
29
87
66
24
28
30
35
40
39
37
95
74
32
36
38
43
48
47
45
103
82
40
44
46
51
56
55
53
34
34
34
0
0
0
50
CMD/
ADD
Slew
rate
4
-4
4
-4
4
-4
12
14
19
24
23
21
4
46
6
-10
-16
-26
-40
-60
6
-10
-16
-26
-40
-60
6
-10
-16
-26
-40
-60
-2
40
11
16
15
13
11
16
15
13
11
16
15
13
-8
0
34
V/ns
-18
-32
-52
-10
-24
-44
-2
24
-16
-36
-6
10
-26
-10
[ Table 62 ] Required time t
Slew Rate[V/ns]
above V (AC) {blow V (AC)} for valid ADD/CMD transition (1.35V)
VAC
IH
IL
1.35V
DDR3L-800/1066/1333/1600
DDR3L-1866
t
@160mV [ps]
t
@135mV [ps]
t
@135mV [ps]
t @125mV [ps]
VAC
VAC
VAC
VAC
min
200
200
173
120
102
80
max
min
213
213
190
145
130
111
87
max
min
200
200
178
133
118
99
max
min
205
205
184
143
129
111
89
max
>2.0
2.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
1.0
0.9
0.8
0.7
51
75
0.6
13
55
43
59
0.5
Note
10
Note
18
< 0.5
Note
10
Note
18
NOTE : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.
- 58 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
[ Table 63 ] Required time t
above V (AC) {blow V (AC)} for valid ADD/CMD transition (1.5V)
VAC
IH
IL
1.5V
DDR3-800/1066/1333/1600
DDR3-1866
@135mV [ps] t @125mV [ps]
VAC
Slew Rate[V/ns]
t
@175mV [ps]
t
@150mV [ps]
t
VAC
VAC
VAC
min
75
max
min
175
170
167
130
113
93
max
min
168
168
145
100
85
max
min
173
173
152
110
96
max
>2.0
2.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
57
1.5
50
1.0
38
0.9
34
0.8
29
66
79
0.7
22
66
42
56
0.6
Note
Note
Note
30
10
27
0.5
Note
Note
Note
Note
Note
Note
< 0.5
NOTE : Note: Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.
- 59 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
tIH
tIH
tIS
tIS
CK
CK
DQS
DQS
tDH
tDH
tDS
tDS
V
V
DDQ
tVAC
(AC) min
IH
V
to ac
REF
region
V
(DC) min
IH
nominal
slew rate
V
(DC)
REF
nominal slew
rate
V (DC) max
IL
V
to ac
REF
region
V (AC) max
IL
tVAC
V
SS
TF
TR
Setup Slew Rate
Rising Signal
V
(AC)min - V
(DC)
REF
V
(DC) - V (AC)max
Setup Slew Rate
Falling Signal
REF
IL
IH
=
=
TF
TR
Figure 21. Illustration of nominal slew rate and t
(for ADD/CMD with respect to clock).
for setup time t (for DQ with respect to strobe) and t
IS
VAC
DS
- 60 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
tIH
tIH
tIS
tIS
CK
CK
DQS
DQS
tDH
tDH
tDS
tDS
V
V
V
DDQ
(AC) min
(DC) min
IH
IH
dc to V
region
REF
nominal
slew rate
V
(DC)
REF
nominal
slew rate
dc to V
region
REF
V (DC) max
IL
V (AC) max
IL
V
SS
TR
TF
Hold Slew Rate
Rising Signal
V
(DC) - V (DC)max
REF
IL
Hold Slew Rate
Falling Signal
V
(DC)min - V
(DC)
IH
REF
=
=
TR
TF
Figure 22. Illustration of nominal slew rate for hold time t (for DQ with respect to strobe) and t
DH
IH
(for ADD/CMD with respect to clock).
- 61 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
tIH
tIH
tIS
tIS
CK
CK
DQS
DQS
tDH
tDH
tDS
tDS
V
V
V
DDQ
tVAC
nominal
line
(AC) min
(DC) min
IH
IH
V
to ac
REF
region
tangent
line
V
(DC)
REF
tangent
line
V (DC) max
IL
V
to ac
REF
region
V (AC) max
IL
nominal
line
TR
tVAC
V
SS
tangent line[V (AC)min - V
(DC)]
REF
Setup Slew Rate
Rising Signal
IH
=
TR
TF
Setup Slew Rate tangent line[V
Falling Signal
(DC) - V (AC)max]
IL
REF
=
TF
Figure 23. Illustration of tangent line for setup time t (for DQ with respect to strobe) and t
DS
IS
(for ADD/CMD with respect to clock)
- 62 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
tIH
tIH
tIS
tIS
CK
CK
DQS
DQS
tDH
tDH
tDS
tDS
V
V
V
DDQ
(AC) min
(DC) min
IH
IH
nominal
line
dc to V
region
REF
tangent
line
V
(DC)
REF
tangent
line
dc to V
region
REF
nominal
line
V (DC) max
IL
V (AC) max
IL
V
SS
TF
TR
(DC) - V (DC)max ]
tangent line [ V
Hold Slew Rate
Rising Signal
REF
IL
=
TR
tangent line [ V (DC)min - V
(DC) ]
Hold Slew Rate
Falling Signal
IH
REF
=
TF
Figure 24. Illustration of tangent line for hold time t (for DQ with respect to strobe) and t
DH
IH
(for ADD/CMD with respect to clock)
- 63 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
14.4 Data Setup, Hold and Slew Rate Derating :
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value (see
Table 64) to the tDS and tDH (see Table 55) derating value respectively. Example: tDS (total setup time) = tDS(base) + tDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V
(DC) and the first crossing of V (AC)min.
REF
IH
Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V
(DC) and the first crossing of V (AC)max
IL
REF
(see 25-Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS on page 68). If the actual signal is always ear-
lier than the nominal slew rate line between shaded ’V
(DC) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the
REF
nominal slew rate line anywhere
between shaded ’V
(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see 27-
REF
Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS on page 70).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V (DC)max and the first crossing of V
(DC).
REF
IL
Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V (DC)min and the first crossing of V
(DC)
IH
REF
(see - on page 69). If the actual signal is always later than the nominal slew rate line between shaded ’dc level to V
(DC) region’, use nominal slew rate
REF
for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to V
(DC) region’, the slew rate of a tan-
REF
gent line to the actual signal from the dc level to V
respect to strobe) and tIH on page 71).
(DC) level is used for derating value (see 28-Illustration of tangent line for hold time tDH (for DQ with
REF
For a valid transition the input signal has to remain above/below V
(AC) for some time tVAC (see Table 56).
IH/IL
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached V
(AC) at the time of the rising clock
IH/IL
transition) a valid input signal is still required to complete the transition and reach V
(AC).
IH/IL
For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
[ Table 64 ] Data Setup and Hold Base-Values
[ps]
reference
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866 NOTE
tDS(base) AC175
tDS(base) AC150
tDS(base) AC135
tDS(base) AC135
tDH(base) DC100
tDH(base) DC100
tDS(base) AC160
tDS(base) AC135
tDS(base) AC135
tDH(base) DC90
tDH(base) DC90
V
V
V
V
V
V
V
V
V
V
V
(AC)SR=1V/ns
(AC)SR=1V/ns
(AC)SR=1V/ns
(AC)SR=2V/ns
(DC)SR=1V/ns
(DC)SR=2V/ns
(DC)SR=1V/ns
(DC)SR=1V/ns
(DC)SR=2V/ns
(DC)SR=1V/ns
(DC)SR=2V/ns
75
125
165
-
25
75
115
-
-
30
60
-
-
10
40
-
-
-
2
2
IH/L
IH/L
IH/L
IH/L
IH/L
IH/L
IH/L
IH/L
IH/L
IH/L
IH/L
-
2,3
1
DDR3
68
-
150
-
100
-
65
-
45
-
3
70
-
1
90
140
-
40
90
-
-
-
2
45
-
25
-
-
2
DDR3L
70
-
1
160
-
110
-
75
-
55
-
2
75
1
NOTE :
1. AC/DC referenced for 2V/ns DQ-slew rate and 4V/ns DQS slew rate
2. AC/DC referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate
3. Optional in DDR3 SDRAM
[ Table 65 ] Derating values DDR3L-800/1066 tDS/tDH-AC/DC based - AC160(1.35V)
tDS, tDH Derating in [ps] AC/DC based
1
AC160 Threshold -> VIH(ac)=VREF(dc)+160mV, VIL(ac)=VREF(dc)-160mV
DQS,DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
80
53
0
-
-
-
-
-
-
45
30
0
-
-
-
-
-
-
80
53
0
-1
-
-
-
-
-
45
30
0
-3
-
-
-
-
-
80
53
0
-1
-3
-
-
-
-
45
30
0
-3
-8
-
-
-
-
-
61
8
7
5
3
-
-
38
8
5
1
-5
-
-
-
-
-
16
13
9
3
-4
-
-
-
-
23
21
19
16
4
-
-
-
21
17
11
4
-6
-
-
-
-
-
-
-
-
-
-
-
-
35
32
20
0
-
-
-
-
-
37
30
20
5
16
15
13
11
8
DQ
Slew
rate
-
-
29
27
24
12
-8
27
21
14
4
V/ns
-
-
-
-
-
-
-
-
-11
NOTE : 1. Cell contents shaded in red are defined as ’not supported’.
- 64 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
[ Table 66 ] Derating values for DDR3L-800/1066/1333/1600 tDS/tDH - AC135 (1.35V)
1
tDS, tDH Derating in [ps] AC/DC based
Alternate AC135 Threshold -> VIH(ac)=VREF(dc)+135mV, VIL(ac)=VREF(dc)-135mV
DQS,DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
68
45
0
-
-
-
-
-
-
45
30
0
-
-
-
-
-
-
68
45
0
2
-
-
-
-
-
45
30
0
-3
-
-
-
-
-
68
45
0
2
3
-
-
-
-
45
30
0
-3
-8
-
-
-
-
-
-
-
-
16
13
9
3
-4
-
-
-
-
26
27
30
33
29
-
-
-
-
21
17
11
4
-6
-
-
-
-
-
35
38
41
37
30
-
-
-
-
-
-
-
-
46
49
45
38
-
-
-
-
-
37
30
20
5
53
8
10
11
14
-
38
8
5
1
-5
-
16
18
19
22
25
-
DQ
Slew
rate
-
27
21
14
4
V/ns
-
-
-
-
-
-
-11
NOTE : 1. Cell contents shaded in red are defined as ’not supported’.
[ Table 67 ] Derating values for DDR3L-1866 tDS/tDH - AC130 (1.35V)
tDS, tDH Derating in [ps] AC/DC based
1
Alternate AC130 Threshold -> VIH(ac)=VREF(dc)+130mV, VIL(ac)=VREF(dc)-130mV
DQS,DQS Differential Slew Rate
8.0 V/ns
7.0 V/ns
6.0 V/ns
5.0 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
4.0 33 23 33 23 33 23
3.5 28 19 28 19 28 19 28 19
3.0 22 15 22 15 22 15 22 15 22 15
-
-
-
-
-
-
-
-
-
13
0
-
-
-
9
0
-
-
-
-
0
-
-
-
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
13
-
-
-
-
-
-
-
-
9
-
-
-
-
-
-
-
-
-
13
0
-
-
-
-
-
-
-
9
0
-
-
-
-
-
-
-
13
0
9
0
13
0
9
0
DQ
Slew
rate
-22 -15 -22 -15 -22 -15 -22 -15 -14 -7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-65 -45 -65 -45 -65 -45 -57 -37 -49 -29
-
-
-
-
-
-
-
-
-
-
-
-
-62 -48 -62 -48 -54 -40 -46 -32 -38 -24
V/ns
-
-
-
-
-
-
-
-
-
-
-61 -53 -53 -45 -45 -37 -37 -29 -29 -19
-
-
-
-
-
-
-
-
-49 -50 -41 -42 -33 -34 -25 -24 -17 -8
-
-
-
-
-
-
-37 -49 -29 -41 -21 -31 -13 -15
-
-
-
-
-31 -51 -23 -41 -15 -25
-
-
-
-
-
-28 -56 -20 -40
NOTE : 1. Cell contents shaded in red are defined as ’not supported’.
[ Table 68 ] Derating values DDR3-800/1066 tDS/tDH - AC175 (1.5V)
tDS, tDH Derating in [ps] AC/DC based
DQS,DQS Differential Slew Rate
1.8 V/ns 1.6 V/ns
1
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
88
59
0
-
-
-
-
-
-
50
34
0
-
-
-
-
-
-
88
59
0
-2
-
-
-
-
-
50
34
0
-4
-
-
-
-
-
88
59
0
-2
-6
-
-
-
-
50
34
0
-4
-10
-
-
-
-
-
67
8
6
2
-3
-
-
42
8
-
-
-
-
16
12
6
0
-10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16
14
10
5
-1
-
DQ
Slew
rate
4
22
18
13
7
-11
-
20
14
8
-2
-16
-
-2
-8
-
-
-
26
21
15
-2
-30
24
18
8
-6
-26
-
-
29
23
6
34
24
10
-10
V/ns
-
-
-
-
-22
NOTE : 1. Cell contents shaded in red are defined as ’not supported’.
- 65 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
[ Table 69 ] Derating values for DDR3-800/1066/1333/1600 tDS/tDH - AC150 (1.5V)
1
tDS, tDH Derating in [ps] AC/DC based
DQS,DQS Differential Slew Rate
1.8 V/ns 1.6 V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
75
50
0
-
-
-
-
-
-
50
34
0
-
-
-
-
-
-
75
50
0
0
-
-
-
-
-
50
34
0
-4
-
-
-
-
-
75
50
0
0
0
-
-
-
-
50
34
0
-4
-10
-
-
-
-
-
58
8
8
8
8
-
-
42
8
-
-
-
-
16
12
6
0
-10
-
-
-
-
24
24
24
23
14
-
-
-
-
-
-
-
-
32
32
31
22
7
-
-
-
-
-
-
-
-
-
-
-
-
16
16
16
16
15
-
DQ
Slew
rate
4
20
14
8
-2
-16
-
-2
-8
-
-
-
24
18
8
-6
-26
-
-
40
39
30
15
34
24
10
-10
V/ns
-
-
-
-
NOTE : 1. Cell contents shaded in red are defined as ’not supported’.
[ Table 70 ] Derating values for DDR3-1866 tDS/tDH - AC135 (1.5V)
tDS, tDH derating in [ps] AC/DC based
Alternate AC135 Threshold -> VIH(ac)=VREF(dc)+135mV, VIL(ac)=VREF(dc)-135mV
Alternate DC 100 Threshold -> VIH(dc)=VREF(dc)+100mV, VIL(dc)=VREF(dc)-100mV
DQS,DQS Differential Slew Rate
8.0 V/ns 7.0 V/ns 6.0 V/ns 5.0 V/ns 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
4.0 34 25 34 25
3.5 29 21 29 21
3.0 23 17 23 17
34 25
29 21 29 21
23 17 23 17 23 17
14 10 14 10 14 10 14
-
-
-
-
-
-
-
-
-
-
-
-
10
0
-
-
-
-
0
-
-
-
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
14 10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
0
0
0
0
0
DQ
Slew
rate
-23 -17 -23 -17 -23 -17 -23 -17 -15 -9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-68 -50 -68 -50 -68 -50 -60 -42 -52 -34
-
-
-
-
-
-
-
-
-
-
-
-
-66 -54 -66 -54 -58 -46 -50 -38 -42 -30
V/ns
-
-
-
-
-
-
-
-
-
-
-64 -60 -56 -52 -48 -44 -40 -36 -32 -36
-
-
-
-
-
-
-
-
-53 -59 -45 -51 -37 -43 -29 -33 -21 -17
-
-
-
-
-
-
-43 -61 -35 -53 -27 -43 -19 -27
-
-
-
-
-39 -66 -31 -56 -23 -40
-
-
-38 -76 -30 -60
NOTE : 1. Cell contents shaded in red are defined as ’not supported’.
[ Table 71 ] Derating values for DDR3-800/1066/1333/1600 tDS/tDH - AC135 (1.5V)
tDS, tDH derating in [ps] AC/DC based
Alternate AC135 Threshold -> VIH(ac)=VREF(dc)+135mV, VIL(ac)=VREF(dc)-135mV
Alternate DC 100 Threshold -> VIH(dc)=VREF(dc)+100mV, VIL(dc)=VREF(dc)-100mV
DQS,DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
68
45
0
-
-
-
-
-
-
50
34
0
-
-
-
-
-
-
68
45
0
2
-
-
-
-
-
50
34
0
-4
-
-
-
-
-
68
45
0
2
3
-
-
-
-
50
34
0
-4
-10
-
-
-
-
-
53
8
10
11
14
-
-
42
8
-
-
-
-
16
12
6
0
-10
-
-
-
-
26
27
30
33
29
-
-
-
-
-
-
-
-
35
38
41
37
30
-
-
-
-
-
-
-
-
-
-
-
-
16
18
19
22
25
-
DQ
Slew
rate
4
20
14
8
-2
-16
-
-2
-8
-
-
-
24
18
8
-6
-26
-
-
46
49
45
38
34
24
10
-10
V/ns
-
-
-
-
NOTE : 1. Cell contents shaded in red are defined as ’not supported’.
- 66 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
[ Table 72 ] Required time t
Slew Rate[V/ns]
above V (AC) {blow V (AC)} for valid DQ transition (1.35V)
VAC
IH IL
1.35V
DDR3L-800/1066 (AC160)
[ps]
DDR3L-800/1066/1333/1600 (AC135)
DDR3L-1866 (AC130)
t
t
[ps]
t
[ps]
VAC
VAC
VAC
min
165
165
138
85
max
min
113
113
90
max
min
95
95
73
30
16
Note
-
max
>2.0
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
<0.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
45
67
30
45
11
16
Note
Note
Note
Note
Note
Note
Note
-
-
-
NOTE : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.
[ Table 73 ] Required time t
above V (AC) {blow V (AC)} for valid DQ transition (1.5V)
IH IL
VAC
t
[ps] DDR3-800/1066
(AC175)
t
[ps] DDR3-800/1066/
t
[ps] DDR3-800/1066/
t
[ps] DDR3-1866
(AC135)
VAC
VAC
VAC
VAC
Slew Rate[V/ns]
1333/1600 (AC150)
1333/1600 (AC135)
min
75
max
min
105
105
80
max
min
113
113
90
max
min
93
max
>2.0
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
<0.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
57
50
93
70
38
30
45
25
34
13
30
note
29
note
note
note
note
note
11
note
note
note
note
note
note
note
note
note
-
-
-
-
NOTE : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.
- 67 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
tIH
tIH
tIS
tIS
CK
CK
DQS
DQS
tDH
tDH
tDS
tDS
V
V
DDQ
tVAC
(AC) min
IH
V
to ac
REF
region
V
(DC) min
IH
nominal
slew rate
V
(DC)
REF
nominal slew
rate
V (DC) max
IL
V
to ac
REF
region
V (AC) max
IL
tVAC
V
SS
TF
TR
Setup Slew Rate
Rising Signal
V
(AC)min - V
(DC)
REF
V
(DC) - V (AC)max
Setup Slew Rate
Falling Signal
REF
IL
IH
=
=
TF
TR
Figure 25. Illustration of nominal slew rate and t
(for ADD/CMD with respect to clock).
for setup time t (for DQ with respect to strobe) and t
IS
VAC
DS
- 68 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
tIH
tIH
tIS
tIS
CK
CK
DQS
DQS
tDH
tDH
tDS
tDS
V
V
V
DDQ
(AC) min
(DC) min
IH
IH
dc to V
region
REF
nominal
slew rate
V
(DC)
REF
nominal
slew rate
dc to V
region
REF
V (DC) max
IL
V (AC) max
IL
V
SS
TR
TF
Hold Slew Rate
Rising Signal
V
(DC) - V (DC)max
REF
IL
Hold Slew Rate
Falling Signal
V
(DC)min - V
(DC)
IH
REF
=
=
TR
TF
Figure 26. Illustration of nominal slew rate for hold time t (for DQ with respect to strobe) and t
DH
IH
(for ADD/CMD with respect to clock).
- 69 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
tIH
tIH
tIS
tIS
CK
CK
DQS
DQS
tDH
tDH
tDS
tDS
V
V
V
DDQ
tVAC
nominal
line
(AC) min
(DC) min
IH
IH
V
to ac
REF
region
tangent
line
V
(DC)
REF
tangent
line
V (DC) max
IL
V
to ac
REF
region
V (AC) max
IL
nominal
line
TR
tVAC
V
SS
tangent line[V (AC)min - V
(DC)]
REF
Setup Slew Rate
Rising Signal
IH
=
TR
TF
Setup Slew Rate tangent line[V
Falling Signal
(DC) - V (AC)max]
IL
REF
=
TF
Figure 27. Illustration of tangent line for setup time t (for DQ with respect to strobe) and t
DS
IS
(for ADD/CMD with respect to clock)
- 70 -
Rev. 1.02
K4B2G1646Q
datasheet
DDR3L SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
tIH
tIH
tIS
tIS
CK
CK
DQS
DQS
tDH
tDH
tDS
tDS
V
V
V
DDQ
(AC) min
(DC) min
IH
IH
nominal
line
dc to V
region
REF
tangent
line
V
(DC)
REF
tangent
line
dc to V
region
REF
nominal
line
V (DC) max
IL
V (AC) max
IL
V
SS
TF
TR
(DC) - V (DC)max ]
tangent line [ V
Hold Slew Rate
Rising Signal
REF
IL
=
TR
tangent line [ V (DC)min - V
(DC) ]
Hold Slew Rate
Falling Signal
IH
REF
=
TF
Figure 28. Illustration of tangent line for hold time t (for DQ with respect to strobe) and t
DH
IH
(for ADD/CMD with respect to clock)
- 71 -
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