K4D261638I-LC40T_技术文档

K4D261638I

128M GDDR SDRAM

128Mbit GDDR SDRAM

2M x 16Bit x 4 Banks

Graphic Double Data Rate

Synchronous DRAM

Revision 1.2

November 2006

Notice

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

- 1 -

Rev. 1.2 November 2006

K4D261638I

128M GDDR SDRAM

Revision History

Revision

Month

Year

History

- Target Spec

- Defined target specification

0.0

March

2005

- Corrected typo.

0.1

1.0

May

2005

- Added CL2 feature in AC Characteristics.

- Finalized SPEC

- Deleted CL2.5 option

August

1.1

1.2

January

November

2006

- Corrected typo.

- 2 -

Rev. 1.2 November 2006

K4D261638I

128M GDDR SDRAM

2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM

with Bi-directional Data Strobe and DLL

1.0 FEATURES

• 2.5V + 5% power supply for device operation

• 2.5V + 5% power supply for I/O interface

• SSTL_2 compatible inputs/outputs

• 4 banks operation

• 2 DQS’s ( 1DQS / Byte )

• Data I/O transactions on both edges of Data strobe

• DLL aligns DQ and DQS transitions with Clock transition

• Edge aligned data & data strobe output

• Center aligned data & data strobe input

• DM for write masking only

• MRS cycle with address key programs

-. Read latency 2,3(clock)

-. Burst length (2, 4 and 8)

• Auto & Self refresh

-. Burst type (sequential & interleave)

• All inputs except data & DM are sampled at the positive going

edge of the system clock

• 32ms refresh period (4K cycle)

• Lead free 66pin TSOP-II (RoHS compliant)

• Maximum clock frequency up to 250MHz

• Maximum data rate up to 500Mbps/pin

• Differential clock input

• Wrtie-Interrupted by Read Function

2.0 ORDERING INFORMATION

Part NO.

K4D261638I-LC40

K4D261638I-LC50

Max Freq.

250MHz

200MHz

Max Data Rate

500Mbps/pin

400Mbps/pin

Interface

Package

SSTL_2

66pin TSOP-II

* K4D261638I-TC is the Leaded package part number.

* For K4D261638I-LC50, VDD & VDDQ = 2.375V to 2.7V.

3.0 GENERAL DESCRIPTION

FOR 2M x 16Bit x 4 Bank DDR SDRAM

The K4D261638I is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabri-

cated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance

up to 1GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst

length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.

- 3 -

Rev. 1.2 November 2006

K4D261638I

128M GDDR SDRAM

4.0 PIN CONFIGURATION (Top View)

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

VSS

1

V^DD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

NC

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

NC

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

66 PIN TSOP(II)

(400mil x 875mil)

(0.65 mm Pin Pitch)

VSSQ

UDQS

NC

V^DDQ

LDQS

NC

V^REF

V^SS

VDD

NC

UDM

CK

LDM

WE

CK

CAS

RAS

CS

22

23

CKE

NC

24

25

26

27

28

29

30

31

32

33

NC

A11

BA0

BA1

AP/A10

A0

A9

A8

A7

A6

A1

A5

A2

A4

A3

VSS

V^DD

PIN DESCRIPTION

CK,CK

CKE

CS

Differential Clock Input

Clock Enable

Chip Select

BA0, BA1

A0 ~A11

DQ0 ~ DQ15

V_DD

V_SS

Bank Select Address

Address Input

Data Input/Output

Power

RAS

Row Address Strobe

CAS

Column Address Strobe

Write Enable

Ground

WE

V_DDQ

V_SSQ

NC

Power for DQ’s

Ground for DQ’s

No Connection

L(U)DQS

Data Strobe

L(U)DM

RFU

Data Mask

Reserved for Future Use

- 4 -

Rev. 1.2 November 2006

K4D261638I

128M GDDR SDRAM

5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION

Symbol

Type

Function

The differential system clock Input.

All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are

sampled on both edges of the DQS.

CK, CK^*1

Input

Activates the CK signal when high and deactivates the CK signal when low. By deactivating

the clock, CKE low indicates the Power down mode or Self refresh mode.

CS enables the command decoder when low and disabled the command decoder when high.

When the command decoder is disabled, new commands are ignored but previous operations

continue.

CKE

CS

Input

Latches row addresses on the positive going edge of the CK with RAS low. Enables row

access & precharge.

Latches column addresses on the positive going edge of the CK with CAS low. Enables col-

umn access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

RAS

CAS

WE

Input

Data input and output are synchronized with both edge of DQS.

For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on

DQ8-DQ15.

Data in Mask. Data In is masked by DM Latency=0 when DM is

high in burst write. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons

to the data on DQ8-DQ15.

LDQS,UDQS

LDM,UDM

Input/Output

Input

DQ0 ~ DQ15

BA0, BA1

Input/Output

Input

Data inputs/Outputs are multiplexed on the same pins.

Selects which bank is to be active.

Row/Column addresses are multiplexed on the same pins.

Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA8.

A0 ~ A11

V_DD/V_SS

Input

Power Supply

Power and ground for the input buffers and core logic.

V_DDQ/V_SSQ

Isolated power supply and ground for the output buffers to provide improved noise immunity.

Reference voltage for inputs, used for SSTL interface.

V_REF

No connection/

Reserved for future use

NC/RFU

This pin is recommended to be left "No connection" on the device

*1 : The timing reference point for the differential clocking is the cross point of CK and CK.

For any applications using the single ended clocking, apply V_REFto CK pin.

- 5 -

Rev. 1.2 November 2006

K4D261638I

128M GDDR SDRAM

6.0 BLOCK DIAGRAM (2Mbit x 16I/O x 4 Bank)

16

Intput Buffer

LWE

CK, CK

Data Input Register

Serial to parallel

LDMi

Bank Select

2Mx16

32

16

x16

DQi

CK,CK

ADDR

Column Decoder

Latency & Burst Length

Data Strobe

Programming Register

LWCBR

DLL

LCKE

LRAS LCBR

LWE

LCAS

CK,CK

LDMi

Timing Register

UDM

CK,CK

CKE

CS

RAS

CAS

WE

LDM

- 6 -

Rev. 1.2 November 2006

K4D261638I

128M GDDR SDRAM

7.0 FUNCTIONAL DESCRIPTION

7.1 Power-Up Sequence

DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and keep CKE at low state (All other inputs may be undefined)

- Apply V_DDbefore V_DDQ

.

- Apply V_DDQbefore V_REF& V_TT

2. Start clock and maintain stable condition for minimum 200us.

3. The minimum of 200us after stable power and clock(CK,CK), apply NOP and take CKE to be high .

4. Issue precharge command for all banks of the device.

5. Issue a EMRS command to enable DLL

*1

6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.

*1,2 7. Issue precharge command for all banks of the device.

8. Issue at least 2 or more auto-refresh commands.

9. Issue a mode register set command with A8 to low to initialize the mode register.

*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.

*2 Sequence of 6&7 is regardless of the order.

Power up & Initialization Sequence

0

1

2

3

4

5

6

7

8

9

10 11

12 13

14 15 16 17

18 19

CK,CK

tRP

2 Clock min.

tRFC

2 Clock min.

tRFC

tRP

2 Clock min.

Command

2nd Auto

Refresh

precharge

ALL Banks

MRS

DLL Reset

precharge

ALL Banks

1st Auto

Refresh

Mode

Any

EMRS

Register Set

Command

200 Clock min.

Inputs must be

stable for 200us

* When the operating frequency is changed, DLL reset should be required again.

After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.

- 7 -

Rev. 1.2 November 2006

K4D261638I

128M GDDR SDRAM

7.2 MODE REGISTER SET(MRS)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing

mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different appli-

cations. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper

operation. The mode register is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with

CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS,

RAS, CAS and WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in

the mode register. The mode register contents can be changed using the same command and clock cycle requirements during opera-

tion as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length

uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is

used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various

burst length, addressing modes and CAS latencies.

Address Bus

BA1

BA0

0

A11

A10

A9

A8

A7

A6

A5

A4

A3

BT

A2

A1

A0

RFU^*1

DLL

TM

CAS Latency

Burst Length

Mode Register

Burst Type

DLL

Test Mode

A3

0

1

Type

Sequential

Interleave

A8

0

1

DLL Reset

No

A7

0

1

mode

Normal

Test

Yes

CAS Latency

Burst Length

BA0

0

1

An ~ A0

MRS

EMRS

A6

0

1

A5

0

1

0

1

A4

0

1

0

1

0

1

0

1

Latency

Burst Type

A2

A1

A0

Reserved

2

Sequential

Reserve

2

Interleave

Reserve

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

4

8

4

8

*1 : RFU(Reserved for future use)

should stay "0" during MRS cycle.

Reserved

Reserve

MRS Cycle

0

1

2

3

4

5

6

7

8

CK, CK

Precharge

All Banks

Any

NOP

MRS

NOP

Command

tMRD=2 tCK

tRP

*1 : MRS can be issued only at all banks precharge state.

*2 : Minimum tRP is required to issue MRS command.

- 8 -

Rev. 1.2 November 2006

K4D261638I

128M GDDR SDRAM

7.3 EXTENDED MODE REGISTER SET(EMRS)

The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the

extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL.

The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank

precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and

BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting

driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended

mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as

long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins

except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.

Address Bus

BA1

BA0

1

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Extended

RFU^*1

D.I.C

DLL

Mode Register

BA0

0

1

An ~ A0

MRS

EMRS

A6

0

A1

0

1

Output Driver Impedence Control

A0

0

1

DLL Enable

Enable

Full

Weak

Matced

Disable

1

*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.

- 9 -

Rev. 1.2 November 2006

K4D261638I

128M GDDR SDRAM

7.4 WRITE INTERRUPTED BY A READ

A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock

cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any

residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tCDLR) is required to

avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be

written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write command.

< Burst Length=8, CAS Latency=3 >

0

1

2

3

4

5

6

7

8

CK

CMD

NOP

WRITE

t

NOP

READ

NOP

t

WR

DQSSmax

t_WPREH

DQS

DQ

t_WPRES

Din 7

Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6

Dout 0

′

s

DM

The following function established how a Read command may interrupt a Write burst and which input data is not written into the memory.

1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where the Write to Read delay

is 1 clock cycle is disallowed

2. For Read commands interrupting a Write burst, the DM pin must be used to mask the input data words whcich immediately precede the interrupting

Read operation and the input data word which immediately follows the interrupting Read operation

3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller) in time to allow

the buses to turn around before the DDR SDRAM drives them during a read operation.

4. If input Write data is masked by the Read command, the DQS input is ignored by the DDR SDRAM.

5. Refer to "3.3.2 Burst write operation"

8.0 ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Storage temperature

Symbol

VIN, VOUT

VDD

Value

-0.5 ~ 3.6

-1.0 ~ 3.6

-0.5 ~ 3.6

-55 ~ +150

2.0

Unit

V

°C

W

VDDQ

TSTG

Power dissipation

PD

Short circuit current

IOS

50

mA

Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

- 10 -

Rev. 1.2 November 2006

K4D261638I

128M GDDR SDRAM

9.0 AC & DC OPERATING CONDITIONS

9.1 POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)

Parameter

Symbol

Min

Typ

Max

Unit

Note

Device Supply voltage

V_DD

2.375

2.50

2.625

V

1, 7

Output Supply voltage

Reference voltage

V_DDQ

V_REF

V_tt

2.375

0.49*V_DDQ

V_REF-0.04

V_REF+0.15

-0.30

2.50

2.625

0.51*V_DDQ

V_REF+0.04

V_DDQ+0.30

V_REF-0.15

-

V

1, 7

-

2

Termination voltage

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

Output leakage current

Note :

V_REF

V

3

V_IH

-

V

4

V_IL

V

5

V_OH

V_OL

I_IL

V_tt+0.76

-

V

I_OH=-15.2mA

V_tt-0.76

5

V

I_OL=+15.2mA

-5

uA

6

I_OL

-5

5

1. Under all conditions V_DDQmust be less than or equal to V_DD

.

2. V_REFis expected to equal 0.50*V_DDQof the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the V_REF

may not exceed + 2% of the DC value. Thus, from 0.50*V_DDQ, V_REFis allowed + 25mV for DC error and an additional + 25mV for AC noise.

3. V_ttof the transmitting device must track V_REFof the receiving device.

4. V_IH(max.)= V_DDQ+1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

5. V_IL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

6. For any pin under test input of 0V < V_IN< V_DDis acceptable. For all other pins that are not under test V_IN=0V.

7. For K4D261638I-LC50, V_DD& V_DDQ= 2.375V to 2.7V.

9.2 DC CHARACTERISTICS

Recommended operating conditions Unless Otherwise Noted ( TA=0 to 65°C)

Version

Parameter

Symbol

Test Condition

Unit

Note

-40

-50

Burst Lenth=2 tRC ≥ tRC(min)

Operating Current

ICC1

ICC2P

ICC2N

ICC3P

ICC3N

ICC4

200

180

mA

1, 2

(One Bank Active)

IOL=0mA, tCC= tCC(min)

Precharge Standby Current

in Power-down mode

45

70

40

60

CKE ≤ VIL(max), tCC= tCC(min)

CKE ≥ VIH(min), CS ≥ VIH(min),

tCC= tCC(min).

Precharge Standby Current

in Non Power-down mode

Active Standby Current

power-down mode

85

70

CKE ≤ VIL(max), tCC= tCC(min)

CKE ≥ VIH(min), CS ≥ VIH(min),

tCC= tCC(min) .

Active Standby Current in

in Non Power-down mode

135

390

110

345

Operating Current

( Burst Mode)

IOL=0mA ,tCC= tCC(min), Page Burst,

All Banks activated.

Refresh Current

ICC5

ICC6

mA

tRC ≥ tRFC(min)

CKE ≤ 0.2V

200

10

180

10

1, 2,3

1, 2

Self Refresh Current

Note :

1. Measured with output open.

2. Current meassured at V_DD(max).

3. Refresh period is 32ms.

- 11 -

Rev. 1.2 November 2006

K4D261638I

128M GDDR SDRAM

9.3 AC INPUT OPERATING CONDITIONS

Recommended operating conditions(Voltage referenced to VSS=0V, VDD=2.5V+ 5%, VDDQ=2.5V+ 5%,TA=0 to 65°C)

Parameter

Symbol

Min

Typ

Max

Unit

Note

Input High (Logic 1) Voltage; DQ

V_IH

V_REF+0.35

-

V

Input Low (Logic 0) Voltage; DQ

Clock Input Differential Voltage; CK and CK

Clock Input Crossing Point Voltage; CK and CK

Note :

V_IL

V_ID

V_IX

-

V_REF-0.35

V_DDQ+0.6

V

0.7

1

2

0.5*V_DDQ-0.2

0.5*V_DDQ+0.2

1. V_IDis the magnitude of the difference between the input level on CK and the input level on CK.

2. The value of V_IXis expected to equal 0.5*V_DDQof the transmitting device and must track variations in the DC level of the same.

3. For K4D261638I-LC50, V_DD& V_DDQ= 2.375V to 2.7V.

(VDD=2.5V+ 5%^*2, TA= 0 to 65°C)

9.4 AC OPERATING TEST CONDITIONS

Parameter

Value

Unit

Note

Input reference voltage for CK(for single ended)

0.50*V_DDQ

V

1

CK and CK signal maximum peak swing

CK signal minimum slew rate

Input Levels(VIH/VIL)

1.5

1.0

V

V/ns

V

V_REF+0.35/V_REF-0.35

Input timing measurement reference level

Output timing measurement reference level

V_REF

V_tt

V

Output load condition

Note :

See Fig.1

1. In case of differential clocks(CK and CK ), input reference voltage for clock is a CK and CK’s crossing point.

2. For K4D261638I-LC50, V_DD& V_DDQ= 2.375V to 2.7V.

Vtt=0.5*VDDQ

RT=50Ω

Output

Z0=50Ω

VREF

=0.5*VDDQ

CLOAD=30pF

(Fig. 1) Output Load Circuit

- 12 -

Rev. 1.2 November 2006

K4D261638I

9.5 CAPACITANCE

128M GDDR SDRAM

(VDD=2.5V, TA= 25°C, f=1MHz)

Parameter

Input capacitance( CK, CK )

Input capacitance(A0~A11, BA0~BA1)

Input capacitance( CKE, CS, RAS,CAS, WE )

Data & DQS input/output capacitance(DQ0~DQ15)

Input capacitance(DM0 ~ DM3)

Symbol

CIN1

CIN2

Min

1.0

Max

5.0

4.0

6.5

Unit

pF

CIN3

COUT

CIN4

pF

DECOUPLING CAPACITANCE GUIDE LINE

Recommended decoupling capacitance added to power line at board.

Parameter

Decoupling Capacitance between VDD and VSS

Decoupling Capacitance between VDDQ and VSSQ

Symbol

CDC1

CDC2

Value

0.1 + 0.01

Unit

uF

1. V_DDand V_DDQpins are separated each other. All V_DDpins are connected in chip. All V_DDQpins are connected in chip.

2. V_SSand V_SSQpins are separated each other. All V_SSpins are connected in chip. All V_SSQpins are connected in chip.

9.6 AC CHARACTERISTICS

-40

-50

Parameter

Symbol

Unit

Note

Min

7.5

4.0

0.45

-0.6

-

0.9

0.4

0.85

0

0.35

0.4

0.9

0.4

Max

10

0.55

0.6

0.4

1.1

0.6

1.15

-

Min

7.5

5.0

0.45

-0.7

-

0.9

0.4

0.8

0

0.3

0.4

1.0

0.45

Max

10

0.55

0.7

0.45

1.1

0.6

1.2

-

CL=2

CL=3

tCK

tCH

ns

tCK

ns

tCK

ns

CK cycle time

CK high level width

CK low level width

DQS out access time from CK

Output access time from CK

Data strobe edge to Dout edge

Read preamble

Read postamble

CK to valid DQS-in

DQS-In setup time

DQS-in hold time

tCL

tDQSCK

tAC

tDQSQ

tRPRE

tRPST

tDQSS

tWPRES

tWPREH

tWPST

tDQSH

tDQSL

tIS

1

-

tCK

ns

DQS write postamble

0.6

-

0.6

-

DQS-In high level width

DQS-In low level width

Address and Control input setup

Address and Control input hold

DQ and DM setup time to DQS

DQ and DM hold time to DQS

tIH

tDS

tDH

-

ns

-

ns

-

ns

tCLmin

or

tCLmin

or

Clock half period

tHP

tQH

-

ns

1

tCHmin

Data output hold time from DQS

Note 1 :

tHP-0.4

tHP-0.45

- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with

that data strobe are coincidentally valid.

- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output vaild window even then

the clock duty cycle applied to the device is better than 45/55%

- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle variation and replaces tDV

- tQHmin = tHP-X where

. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)

. X=A frequency dependent timing allowance account for tDQSQmax

- 13 -

Rev. 1.2 November 2006

K4D261638I

128M GDDR SDRAM

AC CHARACTERISTICS (II)_Continued

-40

-50

Parameter

Symbol

Unit

Note

Min

Max

Min

Max

Row cycle time

Refresh row cycle time

tRC

tRFC

52

60

-

55

70

-

ns

Row active time

tRAS

36

100K

40

100K

ns

RAS to CAS delay for Read

RAS to CAS delay for Write

Row precharge time

tRCDRD

tRCDWR

tRP

16

8

16

-

15

10

15

-

ns

2

Row active to Row active

Last data in to Row precharge @Normal Precharge

Last data in to Row precharge @Auto Precharge

Last data in to Read command

Col. address to Col. address

Mode register set cycle time

Auto precharge write recovery + Precharge

Exit self refresh to read command

Power down exit time

tRRD

tWR

12

3

2

1

2

-

10

3

2

1

2

ns

-

tCK

ns

1

tWR_A

tCDLR

tCCD

tMRD

tDAL

tXSR

tPDEX

tREF

7

200

3tCK+tIS

-

6

200

3tCK+tIS

-

Refresh interval time

7.8

us

Note :

1. For normal write operation, even numbers of Din are to be written inside DRAM.

2. tRCDWR should be always greater or equal to 2tCK.

AC CHARACTERISTICS (III)_Continued

(Unit : Number of Clock)

K4D261638F-LC40

Frequency

Cas Latency

tRC

13

11

7

tRFC

15

tRAS

tRCDRD tRCDWR

tRP

4

tRRD

tDAL

Unit

tCK

250MHz ( 4.0ns )

200MHz ( 5.0ns )

133MHz ( 7.5ns )

3

9

8

5

4

3

2

3

2

7

6

4

14

3

3 or 2

8

3

K4D261638F-LC50

Frequency

200MHz ( 5.0ns )

133MHz ( 7.5ns )

Cas Latency

tRC

11

8

tRFC

14

10

tRAS

8

6

tRCDRD tRCDWR

tRP

3

2

tRRD

2

tDAL

6

4

Unit

tCK

3

2

3 or 2

- 14 -

Rev. 1.2 November 2006

K4D261638I

128M GDDR SDRAM

10.0 SIMPLIFIED TIMING

Simplified Timing @ BL=4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

CK, CK

BA[1:0]

A10/AP

BAa

BAb

BAa

BAb

Rb

Ra

ADDR

Cb

Ca

(A0~A9

,A11)

WE

DQS

Da0 Da1 Da2 Da3

Db0 Db1 Db2 Db3

DQ

DM

ACT_A

WR_A

PRECH

ACT_A

WR_A

ACT_B

WR_B

COM

t

RCD

RP

t

RAS

t

RRD

RC

Multi Bank Interleaving Write Burst

(@ BL=4)

Normal Write Burst

(@ BL=4)

- 15 -

Rev. 1.2 November 2006

K4D261638I

128M GDDR SDRAM

11.0 IBIS : I/V Characteristics for Input and Output Buffers

(1) Full Strength Driver Characteristics

Pulldown Current (mA)

Voltage

Pullup Current (mA)

Maximum

Minimum

Maximum

Minimum

(V)

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

0

-0.9

-4.536

-7.92

0

1.368

4.968

8.46

1.716

6.996

12.32

17.512

22.616

27.544

32.12

36.564

40.612

44.176

47.388

50.028

52.184

53.812

55

55.88

56.54

56.98

57.332

57.64

57.86

58.08

58.256

58.388

58.52

58.652

58.784

-0.924

-6.424

-11.572

-16.588

-21.472

-26.136

-30.756

-35.024

-39.204

-42.988

-46.508

-49.808

-52.668

-55.22

-57.464

-59.356

-60.896

-62.172

-63.272

-64.24

11.808

14.904

17.892

20.376

22.716

24.624

26.208

27.432

28.224

28.836

29.268

29.592

29.808

29.988

30.168

30.348

30.456

30.564

30.708

30.78

-11.196

-14.328

-17.208

-19.908

-22.428

-24.732

-26.748

-28.476

-29.952

-31.176

-32.22

-33.048

-33.696

-34.308

-34.812

-35.244

-35.64

-36

-65.032

-65.736

-66.352

-66.924

-67.452

-67.936

-68.332

-36.288

-36.576

-36.648

-36.747

-36.72

30.807

30.879

30.924

30.969

- 16 -

Rev. 1.2 November 2006

K4D261638I

128M GDDR SDRAM

11.0 IBIS : I/V Characteristics for Input and Output Buffers

(2) Weak Strength Driver Characteristics

Pulldown Current (mA)

Voltage

Pullup Current (mA)

Maximum

Minimum

Maximum

Minimum

(V)

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

0

1.332

4.752

7.992

11.008

13.968

16.74

19.08

21.24

1.716

6.776

-1.08

-4.212

-2.272

-10.152

-12.96

-1.144

-5.94

-10.56

-15.092

-19.36

11.704

16.456

21.076

25.784

30.052

34.144

37.884

41.404

44.308

46.772

48.664

50.248

51.348

52.14

52.756

53.196

53.768

53.988

54.164

54.296

54.472

54.604

54.692

54.824

-15.48

-23.496

-27.588

-31.284

-35.024

-38.368

-41.492

-44.352

-46.816

-49.06

-50.864

-52.448

-53.812

-54.956

-55.88

-56.672

-57.376

-57.992

-58.476

-59.004

-59.444

-59.84

-17.856

-20.052

-21.996

-23.832

-25.308

-26.64

-27.684

-28.548

-29.232

-29.844

-30.312

-30.78

23.04

24.516

25.596

26.388

26.964

27.36

27.648

27.828

28.008

28.188

28.296

28.44

28.548

28.62

28.728

28.8

28.908

28.953

28.998

-31.14

-31.464

-31.752

-32.04

-32.157

-32.328

-32.418

-32.472

-32.508

-60.28

- 17 -

Rev. 1.2 November 2006

K4D261638I

128M GDDR SDRAM

11.0 IBIS : I/V Characteristics for Input and Output Buffers

(3) Matched Strength Driver Characteristics

Pulldown Current (mA)

Voltage

Pullup Current (mA)

Maximum

Minimum

Maximum

Minimum

(V)

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

0

1.152

2.988

4.788

6.48

8.028

9.396

10.692

11.7

12.564

13.248

13.716

14.04

14.292

14.472

14.616

14.724

14.796

14.868

14.94

14.976

15.048

15.12

15.192

15.228

15.264

15.3

1.452

4.312

7.084

9.724

-0.972

-2.916

-4.824

-6.516

-8.172

-9.756

-11.16

-12.42

-13.572

-14.544

-15.372

-16.056

-16.632

-17.1

-17.496

-17.82

-18.108

-18.324

-18.54

-18.756

-18.9

-1.276

-4.224

-7.04

-9.768

-12.364

-14.872

-17.292

-19.624

-21.736

-23.672

-25.476

-27.06

-28.468

-29.656

-30.668

-31.504

-32.208

-32.78

-33.264

-33.66

-34.056

-34.408

-34.716

-35.2

12.232

14.74

16.984

19.184

21.164

22.792

24.2

25.256

26.136

26.752

27.148

27.544

27.764

27.984

28.116

28.204

28.336

28.38

-19.08

-19.224

-19.332

-19.431

-19.611

-19.692

28.512

28.6

28.644

28.732

28.776

-35.42

-35.64

15.372

- 18 -

Rev. 1.2 November 2006

K4D261638I

128M GDDR SDRAM

12.0 PACKAGE DIMENSIONS (66pin TSOP-II)

Units : Millimeters

#66

#34

(10

×)

(10×)

#1

#33

+0.075

-0.035

0.125

(1.50)

22.22±0.10

(10

×

)

0.10 MAX

0.25TYP

(0.71)

0.65TYP

0.65 0.08

0.30±0.08

[

]

0.075 MAX

±

(10×

NOTE

1. (

0×~8×

) IS REFERENCE

2. [

] IS ASS’Y OUT QUALITY

- 19 -

Rev. 1.2 November 2006


型号：	K4D261638I-LC40T
厂家：	SAMSUNG
描述：	DDR DRAM, 8MX16, 0.6ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66 时钟动态存储器双倍数据速率光电二极管内存集成电路
文件：	总19页 (文件大小：350K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K4D261638I-LC40T [SAMSUNG]

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