K4D263238F-QC400 [SAMSUNG]
DDR DRAM, 4MX32, 0.6ns, CMOS, PQFP100, 20 X 14 MM, 0.65 MM PITCH, TQFP-100;
| 型号： | K4D263238F-QC400 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM, 4MX32, 0.6ns, CMOS, PQFP100, 20 X 14 MM, 0.65 MM PITCH, TQFP-100 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总17页 (文件大小：237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Target spec
128M DDR SDRAM
K4D263238F
128Mbit DDR SDRAM
1M x 32Bit x 4 Banks
Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
Revision 0.0
January 2003
- 1 -
Rev. 0.0 (Jan. 2003)
Target spec
128M DDR SDRAM
K4D263238F
Revision History
Revision 0.0 (January 20, 2003)- Target spec
• Define target spec.
- 2 -
Rev. 0.0 (Jan. 2003)
Target spec
128M DDR SDRAM
K4D263238F
1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
• 2.5V ± 5% power supply
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except data & DM are sampled at the positive
going edge of the system clock
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• 100pin TQFP package
• Maximum clock frequency up to 250MHz
• Maximum data rate up to 500Mbps/pin
• Differential clock input
• No Write Interrupted by Read function
ORDERING INFORMATION
Part NO.
Max Freq.
250MHz
200MHz
Max Data Rate
500Mbps/pin
400Mbps/pin
Interface
Package
K4D263238F-QC40
K4D263238F-QC50
SSTL_2
100 TQFP
GENERAL DESCRIPTION
FOR 1M x 32Bit x 4 Bank DDR SDRAM
The K4D263238F is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words by
32 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 2.0GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
- 3 -
Rev. 0.0 (Jan. 2003)
Target spec
128M DDR SDRAM
K4D263238F
PIN CONFIGURATION (Top View)
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
DQ29
VSSQ
DQ30
DQ31
VSS
A7
A6
A5
A4
VSS
A9
VDDQ
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
A11
A10
VDD
A3
N.C
N.C
100 Pin TQFP
N.C
2
N.C
20 x 14 mm
VSSQ
RFU
0.65mm pin Pitch
DQS
VDDQ
VDD
DQ0
DQ1
A2
VSSQ
DQ2
A1
A0
PIN DESCRIPTION
CK,CK
CKE
CS
Differential Clock Input
BA0, BA1
A0 ~A11
DQ0 ~ DQ31
VDD
Bank Select Address
Address Input
Data Input/Output
Power
Clock Enable
Chip Select
RAS
CAS
WE
Row Address Strobe
Column Address Strobe
Write Enable
VSS
Ground
VDDQ
Power for DQ′s
Ground for DQ′s
Must Connect Low
DQS
DMi
Data Strobe
VSSQ
Data Mask
MCL
RFU
Reserved for Future Use
- 4 -
Rev. 0.0 (Jan. 2003)
Target spec
128M DDR SDRAM
K4D263238F
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Function
The differential system clock Input.
CK, CK*1
Input
Input
Input
All of the inputs are sampled on the rising edge of the clock except
DQ′s and DM′s that are sampled on both edges of the DQS.
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CKE
CS
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
RAS
CAS
Input
Input
Input
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
DQS
Input/Output
Input
Data input and output are synchronized with both edge of DQS.
Data In mask. Data In is masked by DM Latency=0 when DM is high
in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for
DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31.
DM0 ~ DM3
DQ0 ~ DQ31
BA0, BA1
Input/Output
Input
Data inputs/Outputs are multiplexed on the same pins.
Selects which bank is to be active.
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7.
Column address CA8 is used for auto precharge.
A0 ~ A11
Input
VDD/VSS
Power Supply
Power Supply
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VDDQ/VSSQ
VREF
MCL
Power Supply
Reference voltage for inputs, used for SSTL interface.
Must connect Low
Must Connect Low
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply VREF to CK pin.
- 5 -
Rev. 0.0 (Jan. 2003)
Target spec
128M DDR SDRAM
K4D263238F
BLOCK DIAGRAM (1Mbit x 32I/O x 4 Bank)
32
Intput Buffer
LWE
CK, CK
Data Input Register
Serial to parallel
LDMi
Bank Select
64
1Mx32
1Mx32
1Mx32
1Mx32
64
32
x32
DQi
CK,CK
ADDR
Column Decoder
Latency & Burst Length
Data Strobe
Programming Register
LWCBR
DLL
LCKE
LRAS LCBR
LWE
LCAS
CK,CK
LDMi
Timing Register
CK,CK
CKE
CS
RAS
CAS
WE
DMi
- 6 -
Rev. 0.0 (Jan. 2003)
Target spec
128M DDR SDRAM
K4D263238F
FUNCTIONAL DESCRIPTION
• Power-Up Sequence
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high.
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
*1
6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
*1,2 7. Issue precharge command for all banks of the device.
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order.
Power up & Initialization Sequence
0
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15 16 17
18
19
CK
CK
tRP
2 Clock min.
tRFC
tRFC
2 Clock min.
tRP
2 Clock min.
Command
precharge
ALL Banks
MRS
DLL Reset
precharge
ALL Banks
1st Auto
Refresh
2nd Auto
Refresh
Mode
Register Set
Any
Command
EMRS
200 Clock min.
Inputs must be
stable for 200us
* When the operating frequency is changed, DLL reset should be required again.
After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.
- 7 -
Rev. 0.0 (Jan. 2003)
Target spec
128M DDR SDRAM
K4D263238F
MODE REGISTER SET(MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register must be
written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and
WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of
address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.
Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2,
addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is
used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes
for various burst length, addressing modes and CAS latencies.
Address Bus
BA1
BA0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A11
Mode
Register
RFU
0
RFU
DLL
TM
CAS Latency
BT
Burst Length
Burst Type
A3
Test Mode
A7
DLL
Type
mode
A8
0
DLL Reset
No
0
1
Sequential
Interleave
0
1
Normal
Test
1
Yes
0
Burst Length
Burst Type
CAS Latency
A2
A1
A0
Sequential Interleave
BA0
0
An ~ A0
MRS
A6 A5 A4 Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserve
2
Reserve
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
3
1
EMRS
4
4
8
8
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
Reserve
Reserve
Reserve
Full page
Reserve
Reserve
Reserve
Reserve
Reserved
Reserved
Reserved
Reserved
MRS Cycle
0
1
2
3
4
5
6
7
8
CK, CK
Precharge
All Banks
Any
Command
NOP
NOP
NOP
MRS
NOP
NOP
NOP
Command
tMRD=2 tCK
tRP
*1: MRS can be issued only at all banks precharge state.
*2: Minimum tRP is required to issue MRS command.
- 8 -
Rev. 0.0 (Jan. 2003)
Target spec
128M DDR SDRAM
K4D263238F
EXTENDED MODE REGISTER SET(EMRS)
The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The
default value of the extended mode register is not defined, therefore the extend mode register must be written after power
up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high
on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode
register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going
low are written in the extended mode register. A1 and A6 are used for setting driver strength to weak or matched imped-
ance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register
contents can be changed using the same command and clock cycle requirements during operation as long as all banks
are in the idle state. A0 is used for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins
except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
Address Bus
BA1
RFU
BA0
1
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Extended
Mode Register
RFU
D.I.C
RFU
D.I.C
DLL
BA0
0
An ~ A0
A0
0
DLL Enable
Enable
Output Driver Impedance Control
A6 A1
MRS
Weak
0
1
1
1
1
EMRS
1
Disable
Matched
* RFU(Reserved for future use)
should stay "0" during EMRS
cycle.
Figure 7. Extend Mode Register set
- 9 -
Rev. 0.0 (Jan. 2003)
Target spec
128M DDR SDRAM
K4D263238F
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD
Value
Unit
V
-0.5 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ 3.6
V
VDDQ
TSTG
V
-55 ~ +150
°C
W
Power dissipation
PD
1.8
50
Short circuit current
IOS
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)
Parameter
Device Supply voltage
Output Supply voltage
Reference voltage
Symbol
VDD
VDDQ
VREF
Vtt
Min
2.375
Typ
Max
2.625
Unit
V
Note
2.50
1
2.375
2.50
2.625
V
1
0.49*VDDQ
VREF-0.04
VREF+0.15
-0.30
-
0.51*VDDQ
VREF+0.04
VDDQ+0.30
VREF-0.15
-
V
2
Termination voltage
VREF
V
3
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
VIH
-
-
-
-
-
-
V
4
VIL
V
5
VOH
VOL
IIL
Vtt+0.76
-
V
IOH=-15.2mA
Vtt-0.76
5
V
IOL=+15.2mA
-5
uA
uA
6
6
IOL
-5
5
Note :
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to
peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error
and an additional + 25mV for AC noise.
3. Vtt of the transmitting device must track VREF of the receiving device.
4. VIH(max.)= VDDQ +1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate.
5. VIL(min.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
6. For any pin under test input of 0V ≤ VIN ≤ VDD is acceptable. For all other pins that are not under test VIN=0V.
- 10 -
Rev. 0.0 (Jan. 2003)
Target spec
128M DDR SDRAM
K4D263238F
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C)
Version
Unit
Note
Parameter
Symbol
Test Condition
-40
-50
Burst Lenth=2 tRC ≥ tRC(min)
IOL=0mA, tCC= tCC(min)
Operating Current
(One Bank Active)
ICC1
TBD
TBD
mA
mA
mA
mA
mA
mA
1
Precharge Standby Current
in Power-down mode
ICC2P
ICC2N
ICC3P
ICC3N
ICC4
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
CKE ≤ VIL(max), tCC= tCC(min)
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min).
Precharge Standby Current
in Non Power-down mode
Active Standby Current
power-down mode
CKE ≤ VIL(max), tCC= tCC(min)
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min) .
Active Standby Current in
in Non Power-down mode
Operating Current
( Burst Mode)
IOL=0mA ,tCC= tCC(min), Page
Burst, All Banks activated.
TBD
TBD
TBD
TBD
Refresh Current
ICC5
ICC6
mA
mA
2
tRC ≥ tRFC(min)
CKE ≤ 0.2V
Self Refresh Current
TBD
Note: 1. Measured with outputs open.
2. Refresh period is 32ms.
AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS=0V, VDD/ VDDQ=2.5V+ 5%, TA=0 to 65°C)
Parameter
Symbol
VIH
Min
VREF+0.35
-
Typ
Max
Unit
Note
Input High (Logic 1) Voltage; DQ
-
-
-
-
-
V
V
V
V
Input Low (Logic 0) Voltage; DQ
VIL
VREF-0.35
VDDQ+0.6
0.5*VDDQ+0.2
Clock Input Differential Voltage; CK and CK
Clock Input Crossing Point Voltage; CK and CK
VID
0.7
1
2
VIX
0.5*VDDQ-0.2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input level on CK
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same
- 11 -
Rev. 0.0 (Jan. 2003)
Target spec
128M DDR SDRAM
K4D263238F
AC OPERATING TEST CONDITIONS (VDD/ VDDQ=2.5V+ 5% , TA= 0 to 65°C)
Parameter
Value
Unit
V
Note
Input reference voltage for CK(for single ended)
CK and CK signal maximum peak swing
CK signal minimum slew rate
0.50*VDDQ
1.5
V
1.0
VREF+0.35/VREF-0.35
VREF
V/ns
V
Input Levels(VIH/VIL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
V
Vtt
V
See Fig.1
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
VREF
=0.5*VDDQ
CLOAD=30pF
(Fig. 1) Output Load Circuit
CAPACITANCE (VDD=2.5V, TA= 25°C, f=1MHz)
Parameter
Input capacitance( CK, CK )
Symbol
CIN1
Min
1.0
Max
5.0
Unit
pF
pF
Input capacitance(A0~A11, BA0~BA1)
CIN2
1.0
4.0
Input capacitance
( CKE, CS, RAS,CAS, WE )
CIN3
1.0
4.0
pF
Data & DQS input/output capacitance(DQ0~DQ31)
Input capacitance(DM0 ~ DM3)
COUT
CIN4
1.0
1.0
6.0
6.0
pF
pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
CDC1
Value
Unit
Decoupling Capacitance between VDD and VSS
Decoupling Capacitance between VDDQ and VSSQ
0.1 + 0.01
0.1 + 0.01
uF
uF
CDC2
Note :
1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
- 12 -
Rev. 0.0 (Jan. 2003)
Target spec
128M DDR SDRAM
K4D263238F
AC CHARACTERISTICS
-40
-50
Parameter
Symbol
tCK
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
Unit
Note
Min
4.0
Max
10
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
Min
5.0
Max
10
CK cycle time
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
CL=3
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLmin
or
tCHmin
0.45
0.45
-0.7
-0.7
-
0.9
0.4
0.8
0
0.25
0.4
0.4
0.4
1.0
0.55
0.55
+0.7
+0.7
+0.45
1.1
0.6
1.2
-
1
-
-
DQS write postamble
0.6
0.6
0.6
-
-
-
0.6
0.6
0.6
-
-
-
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
tIH
tDS
tDH
1.0
ns
ns
ns
0.45
0.45
tCLmin
or
tCHmin
tHP-0.45
-
-
Clock half period
tHP
tQH
-
-
-
-
ns
ns
1
1
Data output hold time from DQS
tHP-0.4
Simplified Timing @ BL=2, CL=3
tCH
tCL
tCK
8
0
1
2
3
4
5
6
7
CK, CK
CS
tIS
tIH
tDQSCK
tDQSS
tDQSH
tWPST
tRPST
Da2
tRPRE
Hi-Z
Hi-Z
tWPREH
DQS
DQ
tWPRES
tDQSQ
tDS tDH
tAC
Da1
Db0
Db1
DM
COMMAND
WRITEB
READA
- 13 -
Rev. 0.0 (Jan. 2003)
Target spec
128M DDR SDRAM
K4D263238F
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case
output valid window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is defined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
tQH Timing (CL3, BL2)
tHP
0
1
2
3
4
5
CK, CK
CS
DQS
tDQSQ(max)
tQH
tDQSQ(max)
Da0
DQ
Da1
COMMAND
READA
- 14 -
Rev. 0.0 (Jan. 2003)
Target spec
128M DDR SDRAM
K4D263238F
AC CHARACTERISTICS (I)
-40
-50
Parameter
Row cycle time
Symbol
Unit
Note
Min
Max
Min
Max
tRC
15
-
12
-
tCK
Refresh row cycle time
Row active time
tRFC
tRAS
17
10
5
3
5
3
3
2
1
-
100K
-
14
8
4
2
4
2
2
2
1
2
-
100K
-
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
RAS to CAS delay for Read
RAS to CAS delay for Write
Row precharge time
Row active to Row active
Last data in to Row precharge
Last data in to Read command
Col. address to Col. address
Mode register set cycle time
Auto precharge write recovery + Pre-
charge
tRCDRD
tRCDWR
tRP
tRRD
tWR
tCDLR
tCCD
tMRD
-
-
-
-
-
-
-
-
-
-
-
-
1
1
2
tDAL
8
-
6
-
tCK
Exit self refresh to read command
Power down exit time
Refresh interval time
tXSR
tPDEX
tREF
200
1tCK+tIS
7.8
-
-
-
200
1tCK+tIS
7.8
-
-
-
tCK
ns
us
Note :1 For normal write operation, even numbers of Din are to be written inside DRAM
(Unit : Number of Clock)
AC CHARACTERISTICS (II)
K4D263238F-QC40
Unit
tCK
tCK
Frequency
250MHz ( 4.0ns )
200MHz ( 5.0ns )
Cas Latency
tRC
15
12
tRFC
17
14
tRAS
10
8
tRCDRD tRCDWR
tRP
5
4
tRRD
3
2
tDAL
8
6
3
3
5
4
3
2
K4D623238F-QC50
Frequency
200MHz ( 5.0ns )
183MHz ( 5.5ns )
166MHz ( 6.0ns )
Unit
tCK
tCK
tCK
Cas Latency
tRC
12
12
tRFC
14
14
tRAS
tRCDRD tRCDWR
tRP
4
4
tRRD
tDAL
3
3
3
8
8
7
4
4
3
2
2
2
2
2
2
6
6
5
10
12
3
* 183/166MHz were supported in K4D263238F-QC50
- 15 -
Rev. 0.0 (Jan. 2003)
Target spec
128M DDR SDRAM
K4D263238F
Simplified Timing(2) @ BL=4, CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
CK, CK
BA[1:0]
BAa
BAa
BAa
BAa
Ra
BAb
Rb
BAa
Ca
BAb
Cb
A8/AP
Ra
Ra
ADDR
(A0~A7,
A9~,A11)
Ca
Ra
Ra
Rb
WE
DQS
DQ
DM
Da0
Da1
Da2
Da3
Da0
Da1
Da2
Da3
Db0
Db1
Db2
Db3
COMMAND
ACTIVEA
WRITEA
PRECH
ACTIVEA
ACTIVEB
WRITEA
WRITEB
tRCD
tRAS
tRP
tRC
tRRD
Normal Write Burst
(@ BL=4)
Multi Bank Interleaving Write Burst
(@ BL=4)
- 16 -
Rev. 0.0 (Jan. 2003)
Target spec
128M DDR SDRAM
K4D263238F
PACKAGE DIMENSIONS (TQFP)
Dimensions in Millimeters
0 ~ 7°
17.20 ± 0.20
14.00 ± 0.10
#100
#1
23.20 ± 0.20
20.00 ± 0.10
0.825
0.30 ± 0.08
0.65
0.09~0.20
0.13 MAX
1.00 ± 0.10
1.20 MAX *
0.10 MAX
0.05 MIN
0.80 ± 0.20
- 17 -
Rev. 0.0 (Jan. 2003)
相关型号：
K4D263238F-QC50
1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL
SAMSUNG
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