K4D551638D-TC2A0 [SAMSUNG]
DDR DRAM, 16MX16, 0.6ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66;
| 型号： | K4D551638D-TC2A0 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM, 16MX16, 0.6ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 时钟 动态存储器 双倍数据速率 光电二极管 内存集成电路 |
| 文件： | 总18页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256M GDDR SDRAM
K4D551638D-TC
256Mbit GDDR SDRAM
4M x 16Bit x 4 Banks
Graphic Double Data Rate
Synchronous DRAM
Revision 1.8
October 2003
Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
Revision History
Revision 1.8 (October 6, 2003)
• Added Lead free package part number in the data sheet.
Revision 1.7 (August 5, 2003)
• Added K4D551638D-TC45 in the spec
Revision 1.6 (July 21, 2003)
• Removed K4D551638D-TC30 from the spec
• Added K4D551638D-TC2A in the spec
Revision 1.5 (July 14, 2003)
• Added K4D551638D-TC30 in the spec
Revision 1.4 (June 16, 2003)
• Changed tRCDRD of K4D551638D-TC33/36 from 4tCK to 5tCK
• Changed tRCDWR of K4D551638D-TC33/36 from 2tCK to 3tCK
Revision 1.3 (April 11, 2003)
• Added K4D551638D-TC60 in the spec.
• Changed AC/DC parameters’ value of K4D551638D-TC50.
• Refresh cycle period of K4D551638D-TC50/60 is 8K/64ms.
Revision 1.1 (March 21, 2003)
• Changed VDD and VDDQ spec from 2.5V+5% to 2.6V+0.1V for all the frequency
Revision 1.0 (February 27, 2003)
• Changed the CAS Latency (CL) of K4D551638D-TC40 from 3 to 4
• Defined DC spec.
Revision 0.0 (January 16, 2003) - Target Spec
• Defined Target Specification
- 2 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
4M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
• 2.6V + 0.1V power supply for device operation
• 2.6V + 0.1V power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• 2 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• MRS cycle with address key programs
-. Read latency 3, 4 (clock)
-. Burst length (2, 4 and 8)
• Auto & Self refresh
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive
going edge of the system clock
• 32ms refresh period (4K cycle) for -TC2A/33/36/40/45
• 64ms refresh period (8K cycle) for -TC50/60
• 66pin TSOP-II
• Differential clock input
• Maximum clock frequency up to 350MHz
• Maximum data rate up to 700Mbps/pin
• No Wrtie-Interrupted by Read Function
ORDERING INFORMATION
Part NO.
Max Freq.
350MHz
300MHz
275MHz
250MHz
222MHz
200MHz
166MHz
Max Data Rate
700Mbps/pin
600Mbps/pin
550Mbps/pin
500Mbps/pin
444Mbps/pin
400Mbps/pin
333Mbps/pin
Interface
Package
K4D551638D-TC2A*
K4D551638D-TC33
K4D551638D-TC36
K4D551638D-TC40
K4D551638D-TC45
K4D551638D-TC50
K4D551638D-TC60*
SSTL_2
66pin TSOP-II
1. For the K4D551638D-TC2A, VDD & VDDQ = 2.8V+0.1V
2. For the K4D551638D-TC60, VDD & VDDQ = 2.5V+5%.
3. K4D551638D-LC is the Lead free package part number
GENERAL DESCRIPTION
FOR 4M x 16Bit x 4 Bank DDR SDRAM
The K4D551638D is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 4,194,304 words by
16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 1.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
- 3 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
PIN CONFIGURATION (Top View)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
1
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm Pin Pitch)
VSSQ
UDQS
NC
VDDQ
LDQS
NC
VREF
VSS
VDD
NC
UDM
CK
LDM
WE
CK
CAS
RAS
CS
22
23
CKE
NC
24
25
26
27
28
29
30
31
32
33
A12
NC
A11
BA0
BA1
AP/A10
A0
A9
A8
A7
A6
A1
A5
A2
A4
A3
VSS
VDD
PIN DESCRIPTION
CK,CK
CKE
Differential Clock Input
Clock Enable
BA0, BA1
A0 ~A12
DQ0 ~ DQ15
VDD
Bank Select Address
Address Input
Data Input/Output
Power
CS
Chip Select
RAS
Row Address Strobe
Column Address Strobe
Write Enable
CAS
VSS
Ground
WE
VDDQ
Power for DQ’s
Ground for DQ’s
No Connection
Reference voltage
L(U)DQS
L(U)DM
RFU
Data Strobe
VSSQ
Data Mask
NC
Reserved for Future Use
VREF
- 4 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Function
The differential system clock Input.
CK, CK*1
Input
Input
Input
All of the inputs are sampled on the rising edge of the clock except
DQ’s and DM’s that are sampled on both edges of the DQS.
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CKE
CS
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
RAS
CAS
WE
Input
Input
Input
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Data input and output are synchronized with both edge of DQS.
For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS
corresponds to the data on DQ8-DQ15.
LDQS,UDQS
LDM,UDM
Input/Output
Input
Data in Mask. Data In is masked by DM Latency=0 when DM is
high in burst write. For the x16, LDM corresponds to the data on
DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15.
DQ0 ~ DQ15
BA0, BA1
Input/Output
Input
Data inputs/Outputs are multiplexed on the same pins.
Selects which bank is to be active.
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA12, Column addresses : CA0 ~ CA8.
A0 ~ A12
VDD/VSS
Input
Power Supply
Power Supply
Power Supply
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VDDQ/VSSQ
VREF
Reference voltage for inputs, used for SSTL interface.
NC/RFU
No connection/
This pin is recommended to be left "No connection" on the device
Reserved for future use
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply VREF to CK pin.
- 5 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
BLOCK DIAGRAM (4Mbit x 16I/O x 4 Bank)
16
Intput Buffer
LWE
CK, CK
Data Input Register
Serial to parallel
LDMi
Bank Select
4Mx16
4Mx16
4Mx16
4Mx16
32
16
x16
DQi
CK,CK
ADDR
Column Decoder
Latency & Burst Length
Data Strobe
Programming Register
LWCBR
DLL
LCKE
LRAS LCBR
LWE
LCAS
CK,CK
LDMi
Timing Register
UDM
CK,CK
CKE
CS
RAS
CAS
WE
LDM
- 6 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
FUNCTIONAL DESCRIPTION
• Power-Up Sequence
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
*1
6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
*1,2 7. Issue precharge command for all banks of the device.
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order.
Power up & Initialization Sequence
0
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15 16 17
18
19
CK,CK
tRP
2 Clock min.
tRFC
tRFC
2 Clock min.
tRP
2 Clock min.
Command
precharge
ALL Banks
MRS
DLL Reset
precharge
ALL Banks
1st Auto
Refresh
2nd Auto
Refresh
Mode
Register Set
Any
Command
EMRS
200 Clock min.
Inputs must be
stable for 200us
* When the operating frequency is changed, DLL reset should be required again.
After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.
- 7 -
Rev 1.8 (Oct. 2003)
(
Day of Eligah
)
(
)
256M GDDR SDRAM
K4D551638D-TC
MODE REGISTER SET(MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register must be
written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and
WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of
address pins A0 ~ A12 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.
Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2,
addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is
used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes
for various burst length, addressing modes and CAS latencies.
Address Bus
BA1 BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RFU
0
RFU
DLL
TM
CAS Latency
BT
Burst Length
Mode Register
Burst Type
DLL
Test Mode
A7
A3
0
Type
A8
0
DLL Reset
No
mode
Sequential
Interleave
0
1
Normal
Test
1
1
Yes
0
Burst Length
Burst Type
Sequential Interleave
CAS Latency
A2
A1
A0
BA0
0
An ~ A0
MRS
A6 A5 A4 Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserve
2
Reserve
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
3
1
EMRS
4
4
8
8
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
4
Reserved
Reserved
Reserved
MRS Cycle
0
1
2
3
4
5
6
7
8
CK, CK
Precharge
All Banks
Any
Command
Command
NOP
NOP
NOP
MRS
NOP
NOP
NOP
tMRD=2 tCK
tRP
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum tRP is required to issue MRS command.
- 8 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
EXTENDED MODE REGISTER SET(EMRS)
The extended mode register stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore the extened mode register
must be written after power up for enabling or disabling DLL. The extended mode register is written by assert-
ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A12
and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1
and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are
required to complete the write operation in the extended mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in
the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address
pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific
codes.
BA1
BA0
1
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
Extended
Mode Register
RFU
RFU
D.I.C
RFU
D.I.C DLL
A0
0
DLL Enable
Enable
Disable
BA0
An ~ A0
MRS
Output Driver Impedence Control
A6 A1
0
1
Weak
0
1
1
EMRS
*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.
- 9 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD
Value
Unit
-0.5 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ 3.6
-55 ~ +150
2.0
V
V
VDDQ
TSTG
V
°C
W
mA
Power dissipation
PD
Short circuit current
IOS
50
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)
Parameter
Device Supply voltage
Output Supply voltage
Reference voltage
Symbol
VDD
Min
2.5
Typ
Max
Unit
V
Note
2.6
2.7
2.7
1,7,8
VDDQ
VREF
Vtt
2.5
2.6
V
1,7,8
0.49*VDDQ
VREF-0.04
VREF+0.15
-0.30
-
0.51*VDDQ
VREF+0.04
VDDQ+0.30
VREF-0.15
-
V
2
Termination voltage
VREF
V
3
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
VIH(DC)
VIL(DC)
VOH
-
-
-
-
-
-
V
4
V
5
Vtt+0.76
-
V
IOH=-15.2mA
VOL
Vtt-0.76
5
V
IOL=+15.2mA
IIL
-5
uA
uA
6
6
IOL
-5
5
Note :
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to
peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error
and an additional + 25mV for AC noise.
3. Vtt of the transmitting device must track VREF of the receiving device.
4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V.
7. For the K4D551638D-TC2A, VDD & VDDQ = 2.8V+0.1V.
8. For the K4D551638D-TC60, VDD & VDDQ = 2.5V+5%.
- 10 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C)
Version
Parameter
Symbol
Test Condition
Unit Note
-2A
-33
-36
-40
-45
-50
-60
Operating Current
(One Bank Active)
Burst Lenth=2 tRC ≥ tRC(min)
IOL=0mA, tCC= tCC(min)
ICC1
TBD
230
220
210
200
145
125
mA
mA
mA
mA
mA
mA
1
Precharge Standby Current
in Power-down mode
ICC2P
ICC2N
ICC3P
ICC3N
ICC4
CKE ≤ VIL(max), tCC= tCC(min)
70
90
4
3
Precharge Standby Current
in Non Power-down mode
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
TBD
TBD
TBD
100
80
80
70
70
65
30
55
75
25
35
55
Active Standby Current
power-down mode
CKE ≤ VIL(max), tCC= tCC(min)
75
Active Standby Current in
in Non Power-down mode
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
150
140
430
130
120
Operating Current
( Burst Mode)
tRC ≥ tRFC(min)tRC ≥ tRFC(min)
Page Burst, All Banks activated.
TBD
TBD
450
390
410
370
390
360
250
200
200
180
Refresh Current
ICC5
ICC6
tRC ≥ tRFC(min)
CKE ≤ 0.2V
380
4
mA
mA
2
Self Refresh Current
3
Note : 1. Measured with outputs open.
2. Refresh period is 32ms for -TC2A/33/36/40/45 (4K/32ms)
Refresh period is 64ms for -TC50/60 (8K/64ms)
AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS=0V, VDD=2.6V+ 0.1V, VDDQ=2.6V+ 0.1V ,TA=0 to 65°C)
Parameter
Symbol
VIH
Min
VREF+0.35
-
Typ
Max
-
Unit
V
Note
Input High (Logic 1) Voltage; DQ
-
-
-
-
Input Low (Logic 0) Voltage; DQ
VIL
VREF-0.35
VDDQ+0.6
0.5*VDDQ+0.2
V
Clock Input Differential Voltage; CK and CK
Clock Input Crossing Point Voltage; CK and CK
VID
0.7
V
1
2
VIX
0.5*VDDQ-0.2
V
Note :
1. VID is the magnitude of the difference between the input level on CK and the input level on CK
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same
3. For the K4D551638D-TC2A, VDD & VDDQ = 2.8V+0.1V.
4. For the K4D551638D-TC60, VDD & VDDQ = 2.5V+5%.
- 11 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
AC OPERATING TEST CONDITIONS (VDD=2.6V±0.1V, TA= 0 to 65°C)
Parameter
Value
Unit
V
Note
Input reference voltage for CK(for single ended)
CK and CK signal maximum peak swing
CK signal minimum slew rate
0.50*VDDQ
1.5
V
1.0
VREF+0.35/VREF-0.35
VREF
V/ns
V
Input Levels(VIH/VIL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
V
Vtt
V
See Fig.1
1. For the K4D551638D-TC2A, VDD & VDDQ = 2.8V+0.1V.
2. For the K4D551638D-TC60, VDD & VDDQ = 2.5V+5%.
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
VREF
=0.5*VDDQ
CLOAD=30pF
(Fig. 1) Output Load Circuit
CAPACITANCE (VDD=2.6V, TA= 25°C, f=1MHz)
Parameter
Input capacitance( CK, CK )
Symbol
CIN1
Min
Max
5.0
Unit
1.0
1.0
pF
pF
Input capacitance(A0~A12, BA0~BA1)
CIN2
4.0
Input capacitance
( CKE, CS, RAS,CAS, WE )
CIN3
1.0
4.0
pF
Data & DQS input/output capacitance(DQ0~DQ15)
Input capacitance(DM0 ~ DM3)
COUT
CIN4
1.0
1.0
6.5
6.5
pF
pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
CDC1
Value
Unit
Decoupling Capacitance between VDD and VSS
Decoupling Capacitance between VDDQ and VSSQ
0.1 + 0.01
0.1 + 0.01
uF
uF
CDC2
Note :
1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
- 12 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
AC CHARACTERISTICS
-2A
-33
-36
-40
-45
Parameter
Symbol
Unit Note
Min
-
Max
Min
-
Max
Min
-
Max
Min
-
Max
Min
4.5
-
Max
CL=3
CL=4
ns
ns
CK cycle time
tCK
10
10
10
10
10
2.86
0.45
0.45
-0.6
-0.6
-
3.3
0.45
0.45
-0.6
-0.6
-
3.6
0.45
0.45
-0.6
-0.6
-
4.0
0.45
0.45
-0.6
-0.6
-
CK high level width
CK low level width
tCH
0.55
0.55
0.6
0.6
0.35
1.1
0.6
1.15
-
0.55
0.55
0.6
0.6
0.35
1.1
0.6
1.15
-
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
0.45
0.45
-0.7
-0.7
-
0.55
0.55
0.7
0.7
0.45
1.1
0.6
1.2
-
tCK
tCK
ns
tCL
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
tDQSCK
tAC
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
ns
tCK
tCK
tCK
ns
1
0.9
0.4
0.85
0
0.9
0.4
0.85
0
0.9
0.4
0.85
0
0.9
0.4
0.85
0
0.9
0.4
0.8
0
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
0.35
0.4
0.4
0.4
0.9
0.9
0.35
0.35
-
0.35
0.4
0.4
0.4
0.9
0.9
0.35
0.35
-
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
-
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
-
0.3
0.4
0.45
0.45
1.0
1.0
0.45
0.45
-
tCK
tCK
tCK
tCK
ns
DQS write postamble
DQS-In high level width
DQS-In low level width
0.6
0.6
0.6
-
0.6
0.6
0.6
-
0.6
0.6
0.6
-
0.6
0.6
0.6
-
0.6
0.55
0.55
-
Address and Control input setup tIS
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
tIH
-
-
-
-
-
ns
tDS
tDH
-
-
-
-
-
ns
-
-
-
-
-
ns
tCLmin
or
tCHmin
tHP-
tCLmin
or
tCHmin
tHP-
tCLmin
or
tCHmin
tHP-
0.4
tCLmin
or
tCHmin
tHP-
0.4
tCLmin
or
tCHmin
tHP-
Clock half period
tHP
tQH
-
-
-
-
-
-
-
-
-
-
ns
ns
1
1
Data output hold time from DQS
0.35
0.35
0.45
AC CHARACTERISTICS (I)
-2A
-33
-36
-40
-45
Parameter
Symbol
Unit Note
Min
15
17
10
5
Max
Min
15
17
10
5
Max
Min
15
17
10
5
Max
Min
13
15
9
Max
Min
12
14
8
Max
Row cycle time
tRC
-
-
-
-
-
tCK
tCK
tCK
tCK
Refresh row cycle time
Row active time
tRFC
-
100K
-
-
100K
-
-
100K
-
-
100K
-
-
100K
-
tRAS
RAS to CAS delay for Read
tRCDRD
tRCDW
4
4
RAS to CAS delay for Write
3
-
3
-
3
-
2
-
2
-
tCK
Row precharge time
tRP
5
3
-
-
5
3
-
-
5
3
-
-
4
3
-
-
4
3
-
-
tCK
tCK
Row active to Row active
Last data in to Row precharge
@Normal Precharge
tRRD
tWR
3
3
-
-
3
3
-
-
3
3
-
-
3
3
-
-
3
3
-
-
tCK
tCK
1
Last data in to Row precharge
@Auto Precharge
tWR_A
1
1
Last data in to Read command
Col. address to Col. address
Mode register set cycle time
Auto precharge write recovery +
Precharge
tCDLR
tCCD
tMRD
3
1
2
-
-
-
3
1
2
-
-
-
2
1
2
-
-
-
2
1
2
-
-
-
2
1
2
-
-
-
tCK
tCK
tCK
tDAL
8
-
-
-
-
8
-
-
-
-
8
-
-
-
-
7
-
-
-
-
7
-
-
-
-
tCK
tCK
ns
Exit self refresh to read command tXSR
200
3tCK
+tIS
7.8
200
3tCK
+tIS
7.8
200
3tCK
+tIS
7.8
200
3tCK
+tIS
7.8
200
3tCK
+tIS
7.8
Power down exit time
Refresh interval time
tPDEX
tREF
us
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
- 13 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
AC CHARACTERISTICS
-50
-60
Parameter
Symbol
Unit
Note
Min
5.0
Max
Min
6.0
Max
CL=3
CL=4
ns
ns
CK cycle time
tCK
10
12
-
-
CK high level width
CK low level width
tCH
0.45
0.45
-0.55
-0.65
-
0.55
0.45
0.45
-0.6
-0.7
-
0.55
tCK
tCK
ns
tCL
0.55
0.55
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
tDQSCK
tAC
0.55
0.6
0.65
0.7
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
0.4
0.45
ns
1
0.9
1.1
0.9
1.1
tCK
tCK
tCK
ns
Read postamble
0.4
0.6
0.4
0.6
CK to valid DQS-in
0.72
0
1.28
0.75
0
1.25
DQS-In setup time
-
-
DQS-in hold time
0.25
0.4
-
0.25
0.4
-
tCK
tCK
tCK
tCK
ns
DQS write postamble
0.6
0.6
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
0.35
0.35
0.6
-
-
-
-
-
-
0.35
0.35
0.8
-
-
-
-
-
-
tIH
0.6
0.8
ns
tDS
0.4
0.45
0.45
tCLmin
or
tCHmin
tHP-0.55
ns
tDH
0.4
ns
tCLmin
or
tCHmin
tHP- 0.5
Clock half period
tHP
tQH
-
-
-
-
ns
ns
1
1
Data output hold time from DQS
AC CHARACTERISTICS (I)
-50
-60
Parameter
Symbol
Unit
Note
Min
12
14
8
Max
Min
10
12
7
Max
Row cycle time
tRC
-
-
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Refresh row cycle time
Row active time
tRFC
-
-
tRAS
100K
100K
RAS to CAS delay for Read
RAS to CAS delay for Write
Row precharge time
tRCDRD
tRCDWR
tRP
4
-
-
-
-
3
-
-
-
-
2
2
4
3
Row active to Row active
Last data in to Row precharge @Nor-
mal Precharge
tRRD
2
2
tWR
3
3
-
-
3
3
-
-
tCK
tCK
1
Last data in to Row precharge @Auto
Precharge
tWR_A
1
1
Last data in to Read command
Col. address to Col. address
Mode register set cycle time
Auto precharge write recovery + Pre-
charge
tCDLR
tCCD
tMRD
2
1
2
-
-
-
1
1
2
-
-
-
tCK
tCK
tCK
tDAL
7
-
6
-
tCK
Exit self refresh to read command
Power down exit time
tXSR
tPDEX
tREF
200
1tCK+tIS
7.8
-
-
-
200
1tCK+tIS
7.8
-
-
-
tCK
ns
Refresh interval time
us
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
- 14 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming
the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
- 15 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
AC CHARACTERISTICS (II)
(Unit : Number of Clock)
K4D551638D-TC2A
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Frequency
Cas Latency
tRC
15
15
15
13
12
12
10
tRFC
17
17
17
15
14
14
12
tRAS
10
10
10
9
8
8
7
tRCDRD tRCDWR
tRP
5
5
5
4
4
4
3
tRRD
tDAL
350MHz ( 2.86ns )
300MHz ( 3.3ns )
275MHz ( 3.6ns )
250MHz ( 4.0ns )
222MHz ( 4.5ns )
200MHz ( 5.0ns )
166MHz ( 6.0ns )
4
4
4
4
4
3
3
5
5
5
4
4
4
3
3
3
3
2
2
2
2
3
3
3
3
3
3
3
8
8
8
7
7
7
6
K4D551638D-TC33
Frequency
Cas Latency
tRC
15
15
13
12
12
10
tRFC
17
17
15
14
tRAS
tRCDRD tRCDWR
tRP
5
5
4
4
tRRD
tDAL
Unit
tCK
tCK
tCK
tCK
tCK
tCK
300MHz ( 3.3ns )
275MHz ( 3.6ns )
250MHz ( 4.0ns )
222MHz ( 4.5ns )
200MHz ( 5.0ns )
166MHz ( 6.0ns )
4
4
4
4
3
3
10
10
9
8
8
5
5
4
4
4
3
3
3
2
2
2
2
3
3
3
3
3
3
8
8
7
7
7
6
14
12
4
3
7
K4D551638D-TC36
Frequency
Cas Latency
tRC
15
13
12
12
tRFC
17
15
14
14
tRAS
10
9
8
8
tRCDRD tRCDWR
tRP
5
4
4
4
tRRD
tDAL
Unit
tCK
tCK
tCK
tCK
tCK
275MHz ( 3.6ns )
250MHz ( 4.0ns )
222MHz ( 4.5ns )
200MHz ( 5.0ns )
166MHz ( 6.0ns )
4
4
4
3
3
5
4
4
4
3
3
2
2
2
2
3
3
3
3
3
8
7
7
7
6
10
12
7
3
K4D551638D-TC40
Frequency
250MHz ( 4.0ns )
222MHz ( 4.5ns )
200MHz ( 5.0ns )
166MHz ( 6.0ns )
Cas Latency
tRC
13
12
12
10
tRFC
15
14
14
12
tRAS
tRCDRD tRCDWR
tRP
4
4
4
3
tRRD
tDAL
Unit
tCK
tCK
tCK
tCK
4
4
3
3
9
8
8
7
4
4
4
3
2
2
2
2
3
3
3
3
7
7
7
6
K4D551638D-TC45
Frequency
222MHz ( 4.5ns )
200MHz ( 5.0ns )
166MHz ( 6.0ns )
Unit
tCK
tCK
tCK
Cas Latency
tRC
12
12
tRFC
14
14
tRAS
tRCDRD tRCDWR
tRP
4
4
tRRD
tDAL
4
3
3
8
8
7
4
4
3
2
2
2
3
3
3
7
7
6
10
12
3
K4D551638D-TC50
Frequency
200MHz ( 5.0ns )
166MHz ( 6.0ns )
Cas Latency
tRC
12
10
tRFC
14
12
tRAS
8
7
tRCDRD tRCDWR
tRP
4
3
tRRD
3
3
tDAL
7
6
Unit
tCK
tCK
3
3
4
3
2
2
K4D551638D-TC60
Frequency
Cas Latency
tRC
tRFC
tRAS
tRCDRD tRCDWR
tRP
tRRD
tDAL
Unit
166MHz ( 6.0ns )
3
10
12
7
3
2
3
3
6
tCK
- 16 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
Simplified Timing @ BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
CK, CK
BA[1:0]
BAa
BAa
BAa
BAa
BAb BAa
Rb
BAb
A10/AP
Ra
Ra
Ra
Ra
ADDR
(A0~A9,
A11,A12)
Ca
Ca
Rb
Cb
Ra
WE
DQS
DQ
Da0
Da1 Da2 Da3
Da0 Da1 Da2 Da3
Db0 Db1
Db2
Db3
DM
COMMAND
ACTIVEA
WRITEA
PRECH
ACTIVEA
ACTIVEB WRITEA
WRITEB
tRCD
tRAS
tRP
tRC
tRRD
Normal Write Burst
(@ BL=4)
Multi Bank Interleaving Write Burst
(@ BL=4)
- 17 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
PACKAGE DIMENSIONS (66pin TSOP-II)
Units : Millimeters
#66
#34
(10×)
(10×)
#1
#33
+0.075
-0.035
0.125
(1.50)
22.22±0.10
(10×)
(10×)
0.10 MAX
0.25TYP
(0.71)
0.65TYP
0.65±0.08
0.30±0.08
[
]
0.075 MAX
NOTE
1. (
0×~8×
) IS REFERENCE
2. [
] IS ASS’Y OUT QUALITY
- 18 -
Rev 1.8 (Oct. 2003)
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