K4D553235F-GC33 [SAMSUNG]
256M GDDR SDRAM; 256M GDDR SDRAM型号: | K4D553235F-GC33 |
厂家: | SAMSUNG |
描述: | 256M GDDR SDRAM |
文件: | 总18页 (文件大小:387K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
256M GDDR SDRAM
K4D553235F-GC
256Mbit GDDR SDRAM
Revision 1.6
March 2005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev 1.6 (May 2005)
256M GDDR SDRAM
K4D553235F-GC
Revision History
Revision 1.6 (May 26, 2005)
• Added CL3 of MRS table
Revision 1.5 (March 16, 2005)
• Corrected the spec revision history from 1.1 ~ 1.4 as below.
Revision 1.4 (March 10, 2005)
• Added a tCK(min) value for -GC33@CL=3
Revision 1.3 (March 04, 2005)
• Removed K4D553235F-GC22 from the datasheet
Revision 1.2 (February 03, 2005)
• Removed -GJ from the spec which is no longer valid.
• Added a couple of note below AC timing table.
Revision 1.1 (December 14, 2004)
• Removed K4D553235F-GC20 from the specification.
• Dualized the 400MHz part’s part number by its operating voltage. Newly added -GJ25 operating voltage is equal to 2.0V(typical) which is in mass pro-
• Addduecdtioan ncoowu.pTlheeo4f00nMoHtez bpaerltowwithAVCDDtim&iVnDgDtQa=bl1e.8. V(typical) which represented as -GC25 will be available by the 2nd quarter of ’05
Revision 1.0 (September 21, 2004)
• Defined DC specification
Revision 0.1 (June 16, 2004) - Target Spec
• Defined target specification
Revision 0.0 (May 07, 2004) - Target Spec
• Defined target specification
- 2 -
Rev 1.6 (May 2005)
256M GDDR SDRAM
K4D553235F-GC
2M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
• 1.8V ± 0.1V power supply for device operation
• 1.8V ± 0.1V power supply for I/O interface
• SSTL_18 compatible inputs/outputs
• 4 banks operation
• No Wrtie-Interrupted by Read Function
• 4 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• MRS cycle with address key programs
-. Read latency 4, 5 and 6 (clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive
going edge of the system clock
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• 144-Ball FBGA
• Differential clock input
• Maximum clock frequency up to 450MHz
• Maximum data rate up to 900Mbps/pin
ORDERING INFORMATION
Part NO.
Max Freq.
400MHz
350MHz
300MHz
Max Data Rate
800Mbps/pin
700Mbps/pin
600Mbps/pin
Interface
Package
K4D553235F-GC25
K4D553235F-GC2A
K4D553235F-GC33
SSTL_18
144-Ball FBGA
* K4D553235F-VC is the Lead Free package part number.
GENERAL DESCRIPTION
FOR 2M x 32Bit x 4 Bank DDR SDRAM
The K4D553235F is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by
32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 3.6GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
- 3 -
Rev 1.6 (May 2005)
256M GDDR SDRAM
K4D553235F-GC
PIN CONFIGURATION (Top View)
2
3
4
5
6
7
8
9
10
11
12
13
B
C
D
E
F
DQS0
DM0
VSSQ
DQ3
DQ2
DQ0
DQ31
DQ29
DQ28
VSSQ
DM3
DQS3
DQ4
DQ6
VDDQ
DQ5
VDDQ
DQ16
DQ18
DM2
DQ20
DQ23
WE
NC
VSSQ
VDD
VDDQ
VDDQ
NC
VDDQ
VSSQ
VSS
DQ1
VDDQ
VDD
VDDQ
VDD
DQ30
VSSQ
VDDQ
VSSQ
VSS
NC
VDDQ
DQ26
VDDQ
DQ15
DQ13
DM1
DQ11
DQ9
DQ27
DQ25
DQ24
DQ14
DQ12
DQS1
DQ10
DQ8
VSSQ
VSSQ
VDD
DQ7
VSSQ
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
DQ17
DQ19
DQS2
DQ21
DQ22
CAS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VDDQ
VDDQ
NC
Thermal Thermal Thermal Thermal
VSS
VSS
VSS
VSS
G
H
J
Thermal Thermal Thermal Thermal
VSS VSS VSS VSS
Thermal Thermal Thermal Thermal
VSS VSS VSS VSS
VDDQ
VDDQ
VDD
NC
VDDQ
VDDQ
VDD
Thermal Thermal Thermal Thermal
VSS
A10
A2
VSS
VDD
A11
A3
VSS
VDD
A9
VSS
RFU1
A5
K
L
NC
NC
RAS
NC
BA1
RFU2
A7
CK
CK
MCL
M
N
CS
NC
BA0
A0
A1
A4
A6
A8/AP
CKE
VREF
NOTE:
1. RFU1 is reserved for A12
2. RFU2 is reserved for BA2
3. VSS Thermal balls are optional
PIN DESCRIPTION
CK,CK
CKE
CS
Differential Clock Input
Clock Enable
BA0, BA1
A0 ~A11
Bank Select Address
Address Input
Data Input/Output
Power
Chip Select
DQ0 ~ DQ31
VDD
RAS
CAS
WE
Row Address Strobe
Column Address Strobe
Write Enable
VSS
Ground
VDDQ
VSSQ
NC
Power for DQ’s
Ground for DQ’s
No Connection
Must Connect Low
DQS
DM
Data Strobe
Data Mask
RFU
Reserved for Future Use
MCL
- 4 -
Rev 1.6 (May 2005)
256M GDDR SDRAM
K4D553235F-GC
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Function
The differential system clock Input.
CK, CK*1
Input
Input
Input
All of the inputs are sampled on the rising edge of the clock except
DQ’s and DM’s that are sampled on both edges of the DQS.
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CKE
CS
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
RAS
CAS
WE
Input
Input
Input
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Data input and output are synchronized with both edge of DQS.
DQS0 for DQ0 ~ DQ7, DQS1 for DQ8 ~ DQ15, DQS2 for DQ16 ~ DQ23,
DQS3 for DQ24 ~ DQ31.
DQS0 ~ DQS3
DM0 ~ DM3
Input/Output
Input
Data In mask. Data In is masked by DM Latency=0 when DM is high
in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for
DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31.
DQ0 ~ DQ31
BA0, BA1
Input/Output
Input
Data inputs/Outputs are multiplexed on the same pins.
Selects which bank is to be active.
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7, CA9
Column address CA8 is used for auto precharge.
A0 ~ A11
Input
VDD/VSS
Power Supply
Power Supply
Power Supply
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VDDQ/VSSQ
VREF
Reference voltage for inputs, used for SSTL interface.
NC/RFU
No connection/
Reserved for future use
This pin is recommended to be left "No connection" on the device
MCL
Must Connect Low
Must connect low
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply VREF to CK pin.
- 5 -
Rev 1.6 (May 2005)
256M GDDR SDRAM
K4D553235F-GC
BLOCK DIAGRAM (1Mbit x 32I/O x 4 Bank)
32
Intput Buffer
LWE
CK, CK
Data Input Register
Serial to parallel
LDMi
Bank Select
64
2Mx32
2Mx32
2Mx32
2Mx32
64
32
x32
DQi
CK,CK
ADDR
Column Decoder
Latency & Burst Length
Data Strobe
(DQS0~DQS3)
Programming Register
LWCBR
DLL
LCKE
LRAS LCBR
LWE
LCAS
CK,CK
LDMi
Timing Register
CK,CK
CKE
CS
RAS
CAS
WE
DMi
- 6 -
Rev 1.6 (May 2005)
256M GDDR SDRAM
K4D553235F-GC
FUNCTIONAL DESCRIPTION
• Power-Up Sequence
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
*1
6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
*1,2 7. Issue precharge command for all banks of the device.
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order
Power up & Initialization Sequence
CK,CK
tRP
tMRD.
tRFC
tRFC
tMRD
tRP
tMRD
Command
precharge
ALL Banks
MRS
DLL Reset
precharge
ALL Banks
1st Auto
Refresh
2nd Auto
Refresh
Mode
Any
EMRS
Register Set
Command
200 Clock min.
Inputs must be
stable for 200us
* When the operating frequency is changed, DLL reset should be required again.
After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.
- 7 -
Rev 1.6 (May 2005)
256M GDDR SDRAM
K4D553235F-GC
MODE REGISTER SET(MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register must be
written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and
WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of
address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.
Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2,
addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is
used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes
for various burst length, addressing modes and CAS latencies.
Address Bus
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register
RFU
0
RFU
DLL
TM
CAS Latency
BT
Burst Length
Burst Type
A3
DLL
Test Mode
A7
Type
A8
0
1
DLL Reset
No
mode
0
1
Sequential
Interleave
0
1
Normal
Test
Yes
0
Burst Length
Burst Type
Sequential Interleave
CAS Latency
A2
A1
A0
BA0
0
1
An ~ A0
MRS
EMRS
A6 A5 A4 Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
2
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
4
8
4
8
3
4
5
6
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MRS Cycle
0
1
2
6
10
11
12
CK, CK
Precharge
All Banks
Any
Command
Command
NOP
NOP
NOP
MRS
NOP
NOP
NOP
tMRD=4 tCK
tRP
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum tRP is required to issue MRS command.
- 8 -
Rev 1.6 (May 2005)
256M GDDR SDRAM
K4D553235F-GC
EXTENDED MODE REGISTER SET(EMRS)
The extended mode register stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore the extened mode register
must be written after power up for enabling or disabling DLL. The extended mode register is written by assert-
ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11
and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1
and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are
required to complete the write operation in the extended mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in
the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address
pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific
codes.
Address Bus
BA1
BA0
1
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Extended
Mode Register
RFU
RFU
D.I.C
RFU
D.I.C DLL
BA0
0
1
An ~ A0
MRS
EMRS
A0
0
1
DLL Enable
Enable
Disable
Output Driver Impedence Control
A6 A1
Full
Weak
N/A
100%
60%
0
0
1
1
0
1
0
1
Do not use
30%
Matched
*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.
Figure 7. Extended Mode Register set
- 9 -
Rev 1.6 (May 2005)
256M GDDR SDRAM
K4D553235F-GC
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD
Value
Unit
-0.5 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ 3.6
-55 ~ +150
3.3
V
V
VDDQ
TSTG
V
°C
W
mA
Power dissipation
PD
Short circuit current
IOS
50
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS(SSTL In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)
Parameter
Device Supply voltage
Output Supply voltage
Reference voltage
Symbol
VDD
Min
1.7
Typ
1.8
Max
1.9
Unit
V
Note
1
VDDQ
VREF
Vtt
1.7
1.8
1.9
V
1
0.49*VDDQ
VREF-0.04
VREF+0.15
-0.30
-
0.51*VDDQ
VREF+0.04
VDDQ+0.30
VREF-0.15
-
V
2
Termination voltage
VREF
V
3
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
VIH(DC)
VIL(DC)
VOH
-
-
-
-
-
-
V
4
V
5
Vtt+0.76
-
V
IOH=-15.2mA, 7
VOL
Vtt-0.76
5
V
IOL=+15.2mA, 7
IIL
-5
uA
uA
6
6
IOL
-5
5
Note :
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to
peak noise on the VREF may not exceed + 2% of the DC value.
3. Vtt of the transmitting device must track VREF of the receiving device.
4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V.
7. Output logic high voltage and low voltage is depend on output channel condition.
- 10 -
Rev 1.6 (May 2005)
256M GDDR SDRAM
K4D553235F-GC
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C)
Version
Parameter
Symbol
Test Condition
Unit
Note
-25
-2A
-33
Burst Lenth=2 tRC ≥ tRC(min)
Operating Current
ICC1
270
242
238
mA
mA
mA
mA
mA
mA
(One Bank Active)
IOL=0mA, tCC= tCC(min)
Precharge Standby Current
in Power-down mode
ICC2P
ICC2N
ICC3P
ICC3N
ICC4
CKE ≤ VIL(max), tCC= tCC(min)
10
57
10
52
10
47
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
Precharge Standby Current
in Non Power-down mode
Active Standby Current
power-down mode
CKE ≤ VIL(max), tCC= tCC(min)
60
55
48
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
Active Standby Current
in Non Power-down mode
201
368
183
342
164
314
Operating Current
( Burst Mode)
IOL=0mA ,tCC= tCC(min),
Page Burst, All Banks activated.
Refresh Current
ICC5
ICC6
ICC7
314
7
286
7
274
7
mA
mA
1
tRC ≥ tRFC(min)
CKE ≤ 0.2V
Self Refresh Current
Operating Current
(4Bank interleaving)
Burst Length=4 tRC ≥ tRC(min)
615
533
479
mA
IOL=0mA, tCC= tCC(min)
Note : 1 Refresh period is 32ms
AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)
Parameter
Input High (Logic 1) Voltage ;DQ
Symbol
VIH
Min
VREF+0.35
-
Typ
Max
-
Unit
Note
-
-
-
-
V
V
V
V
Input Low (Logic 0) Voltage; DQ
VIL
VREF-0.35
VDDQ+0.6
Clock Input Differential Voltage; CK and CK
Clock Input Crossing Point Voltage; CK and CK
VID
0.7
1
2
VIX
0.5*VDDQ-0.2
0.5*VDDQ+0.2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input level on CK
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same
- 11 -
Rev 1.6 (May 2005)
256M GDDR SDRAM
K4D553235F-GC
AC OPERATING TEST CONDITIONS (TA= 0 to 65°C)
Parameter
Value
0.50*VDDQ
Unit
V
Note
1
Input reference voltage for CK(for single ended)
CK and CK signal maximum peak swing
CK signal minimum slew rate
1.5
V
1.0
VREF+0.4/VREF-0.4
VREF
V/ns
V
Input Levels(VIH/VIL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
V
Vtt
V
See Fig.1
Note 1 : In case of differential clocks(CK and CK ), input reference voltage for clock is a CK and CK’s crossing point.
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
VREF
=0.5*VDDQ
CLOAD=30pF
(Fig. 1) Output Load Circuit
CAPACITANCE (TA= 25°C, f=1MHz)
Parameter
Input capacitance( CK, CK )
Symbol
CIN1
Min
1.0
Max
5.0
Unit
pF
Input capacitance(A0~A11, BA0~BA1)
CIN2
1.0
4.0
pF
Input capacitance
( CKE, CS, RAS,CAS, WE )
CIN3
1.0
4.0
pF
Data & DQS input/output capacitance(DQ0~DQ31)
Input capacitance(DM0 ~ DM3)
COUT
CIN4
1.0
1.0
6.5
6.5
pF
pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
CDC1
Value
Unit
Decoupling Capacitance between VDD and VSS
Decoupling Capacitance between VDDQ and VSSQ
0.1 + 0.01
0.1 + 0.01
uF
uF
CDC2
Note :
1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
- 12 -
Rev 1.6 (May 2005)
256M GDDR SDRAM
K4D553235F-GC
AC CHARACTERISTICS (I)
-25
-2A
-33
Parameter
Symbol
Unit
Note
Min
-
Max
Min
-
Max
Min
5
Max
CL=3
CL=4
CL=5
CL=6
ns
ns
-
-
3.3
CK cycle time
tCK
10.0
10.0
10.0
2.5
-
0.45
0.45
-0.45
-0.45
-
0.9
0.4
0.85
0
0.35
0.4
2.86
-
0.45
0.45
-0.55
-0.55
-
0.9
0.4
0.85
0
0.35
0.4
-
-
ns
ns
CK high level width
CK low level width
tCH
tCL
0.55
0.55
0.45
0.45
0.28
1.1
0.6
1.15
-
0.55
0.55
0.55
0.55
0.35
1.1
0.6
1.15
-
0.45
0.45
-0.55
-0.55
-
0.9
0.4
0.85
0
0.35
0.4
0.55
0.55
0.55
0.55
0.35
1.1
0.6
1.15
-
tCK
tCK
ns
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
tDQSCK
tAC
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
ns
1
tCK
tCK
tCK
ns
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
-
-
-
tCK
tCK
tCK
tCK
ns
DQS write postamble
0.6
0.55
0.55
-
0.6
0.55
0.55
-
0.6
0.55
0.55
-
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
0.45
0.45
0.6
0.45
0.45
0.8
0.45
0.45
0.8
tIH
0.6
-
0.8
-
0.8
-
ns
tDS
0.3
-
0.35
0.35
tCLmin
or
-
0.35
0.35
tCLmin
or
-
ns
tDH
0.3
-
-
-
ns
tCLmin
Clock half period
tHP
or
-
-
-
ns
1
1
tCHmin
-
tCHmin
-
tHP-
tQHS
tCHmin
-
tHP-
tQHS
Data Hold skew factor
tQHS
tQH
0.4
-
0.4
-
0.4
-
ns
ns
tHP-
tQHS
Data output hold time from DQS
Simplified Timing @ BL=2, CL=4
tCH
tCL
0
1
2
tCK3
4
5
6
7
8
CK, CK
tIS
CS
tIH
tDQSCK
tDQSS
tWPREH
tDQSH
tDQSL
tRPST
tRPRE
DQS
tWPRES
tDQSQ
tDS tDH
tAC
DQ
DM
Qa2
Qa1
Db0
Db1
COMMAND
WRITEB
READA
- 13 -
Rev 1.6 (May 2005)
256M GDDR SDRAM
K4D553235F-GC
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
tQH Timing (CL4, BL2)
tHP
3
4
0
1
2
5
CK, CK
CS
DQS
tDQSQ(max)
Qa1
tQH
tDQSQ(max)
Qa0
DQ
COMMAND
READA
Power Down Timing
CK, CK
t
IS
CKE
3t
CK
t
IS
Command
VALID
NOP
NOP
NOP
NOP
NOP
NOP
VALID
Enter Power Down mode
(Read or Write operation
must not be in progress)
Exit Powr Down mode
- 14 -
Rev 1.6 (May 2005)
256M GDDR SDRAM
K4D553235F-GC
AC CHARACTERISTICS (II)
-25
-2A
-33
Parameter
Symbol
Unit
Note
Min
45
Max
Min
45.8
51.5
28.6
16.5
11.4
16.5
Max
Min
49.5
56.1
33
16.5
11.4
16.5
Max
Row cycle time
Refresh row cycle time
Row active time
tRC
-
-
-
ns
ns
ns
ns
ns
ns
2,5
5
5
5
4,5
5
tRFC
50
-
-
-
tRAS
28.6
15
10
15
100K
100K
100K
RAS to CAS delay for Read
RAS to CAS delay for Write
Row precharge time
tRCDRD
tRCDWR
tRP
-
-
-
-
-
-
-
-
-
Last data in to Row precharge @Normal
tWR
15
-
16.5
-
16.5
-
ns
1,5
Precharge
Last data in to Row precharge @Auto Pre-
charge
tWR_A
6
-
6
-
5
-
tCK
1,3
3,5
Auto precharge write recovery + Precharge tDAL
30
4
-
-
-
-
-
-
33
4
-
-
-
-
-
-
33
3
-
-
-
-
-
-
ns
Row active to Row active
tRRD
tCDLR
tCCD
tMRD
tXSR
tCK
tCK
tCK
tCK
tCK
Last data in to Read command
Col. address to Col. address
Mode register set cycle time
Exit self refresh to read command
2
2
2
1
1
1
1
4
3
3
200
3tCK+
tIS
7.8
200
3tCK+
tIS
7.8
200
3tCK+
tIS
7.8
Power down exit time
Refresh interval time
tPDEX
tREF
-
-
-
-
-
-
ns
us
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
2. The number of clock of tRC is restricted by the number of clock of tRAS and tRP
3. The number of clock of tWR_A is fixed. It can’t be changed by tCK. tWR_A is related with CL. It is equal to CL+1tCK.
4. tRCDWR is equal to tRCDRD-2tCK and the number of clock can not be lower than 2tCK.
5. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer unconditionally.
- 15 -
Rev 1.6 (May 2005)
256M GDDR SDRAM
K4D553235F-GC
AC CHARACTERISTICS (II)
K4D553235F-GC25
(Unit : Number of Clock)
Unit
tCK
Frequency
Cas Latency
tRC
tRFC
20
tRAS
12
tRCDRD tRCDWR
tRP
6
tRRD
4
tDAL
12
400MHz ( 2.5ns )
5
18
6
4
K4D553235F-GC2A
Frequency
350MHz ( 2.86ns )
300MHz ( 3.3ns )
Unit
tCK
tCK
Cas Latency
tRC
16
15
tRFC
18
17
tRAS
10
10
tRCDRD tRCDWR
tRP
6
5
tRRD
4
3
tDAL
12
10
5
4
6
5
4
3
K4D553235F-GC33
Frequency
300MHz ( 3.3ns )
Unit
tCK
Cas Latency
tRC
15
tRFC
17
tRAS
10
tRCDRD tRCDWR
tRP
5
tRRD
3
tDAL
10
4
5
3
- 16 -
Rev 1.6 (May 2005)
256M GDDR SDRAM
K4D553235F-GC
Simplified Timing(2) @ BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
CK, CK
BA[1:0]
BAa
BAa
BAa
BAa
BAb BAa
Rb
BAb
A8/AP
Ra
Ra
Ra
a
ADDR
(A0~A7,
A9,A10)
Ca
Ca
Rb
Cb
Ra
WE
DQS
DQ
Da0
Da1 Da2 Da3
Da0 Da1 Da2 Da3
Db0 Db1
Db2
Db3
DM
COMMAND
ACTIVEA
WRITEA
PRECH
ACTIVEA
ACTIVEB WRITEA
WRITEB
tRCD
tRAS
tRP
tRC
tRRD
Normal Write Burst
(@ BL=4)
Multi Bank Interleaving Write Burst
(@ BL=4)
- 17 -
Rev 1.6 (May 2005)
256M GDDR SDRAM
K4D553235F-GC
PACKAGE DIMENSIONS (144-Ball FBGA)
A1 INDEX MARK
12.0
12.0
<Top View>
0.8x11=8.8
A1 INDEX MARK
0.10 Max
0.8
0.8
B
C
D
E
F
0.45 ± 0.05
G
H
J
0.40
K
L
M
N
13 12 11 10 9
8 7 6 5 4 3 2
0.35 ± 0.05
1.40 Max
0.40
<Bottom View>
Unit : mm
- 18 -
Rev 1.6 (May 2005)
相关型号:
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