K4E660412E-JP60T [SAMSUNG]
EDO DRAM, 16MX4, 60ns, CMOS, PDSO32,;
| 型号： | K4E660412E-JP60T |
| 厂家： | 
SAMSUNG |
| 描述： | EDO DRAM, 16MX4, 60ns, CMOS, PDSO32, 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总21页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
16M x 4bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 16,777,216 x 4 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Nor-
mal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden
refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 16Mx4 EDO Mode DRAM family is fabricated
using Samsung¢s advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
• Extended Data Out Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Part Identification
- K4E660412E-JI/P(3.3V, 8K Ref., SOJ)
- K4E640412E-JI/P(3.3V, 4K Ref., SOJ)
- K4E660412E-TI/P(3.3V, 8K Ref., TSOP)
- K4E640412E-TI/P(3.3V, 4K Ref., TSOP)
• Active Power Dissipation
Unit : mW
4K
Speed
-45
8K
• Available in Plastic SOJ and TSOP(II) packages
• +3.3V±0.3V power supply
324
288
252
432
396
360
-50
•
Industrial Temperature operating ( -40~85°C )
-60
• Refresh Cycles
FUNCTIONAL BLOCK DIAGRAM
Part
NO.
Refresh
cycle
Refresh time
Normal
L-ver
RAS
CAS
W
Vcc
Vss
Control
Clocks
K4E660412E*
K4E640412E
8K
4K
64ms
128ms
VBB Generator
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS -before-RAS & Hidden refresh mode
Row Decoder
Refresh Timer
Data in
Buffer
Refresh Control
Memory Array
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
DQ0
to
DQ3
16,777,216 x 4
Refresh Counter
• Performance Range
Cells
Speed
-45
Data out
Buffer
tRAC
45ns
50ns
60ns
tCAC
12ns
13ns
15ns
tRC
tHPC
17ns
20ns
25ns
Row Address Buffer
A0~A12
(A0~A11)*1
74ns
84ns
104ns
Col. Address Buffer
Column Decoder
A0~A10
(A0~A11)*1
-50
-60
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
PIN CONFIGURATION (Top Views)
• K4E660412E-T
• K4E640412E-T
• K4E660412E-J
• K4E640412E-J
VCC
DQ0
DQ1
N.C
N.C
N.C
N.C
W
1
2
3
4
5
6
7
8
9
32
VSS
VCC
DQ0
DQ1
N.C
N.C
N.C
N.C
W
RAS
A0
A1
A2
A3
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
31 DQ3
30 DQ2
29 N.C
28 N.C
27 N.C
26 CAS
25 OE
24 A12(N.C)*
23 A11
22 A10
21 A9
DQ3
DQ2
N.C
N.C
N.C
CAS
OE
A12(N.C)*
A11
A10
A9
RAS
9
A0 10
A1 11
A2 12
A3 13
A4 14
A5 15
10
11
12
13
14
15
16
20 A8
19 A7
18 A6
17
A8
A7
A6
VSS
A4
A5
VCC
VCC
16
VSS
(J : 400mil SOJ)
(T : 400mil TSOP(II))
* (N.C) : N.C for 4K Refresh product
Pin Name
A0 - A12
A0 - A11
DQ0 - 3
VSS
Pin Function
Address Inputs(8K Product)
Address Inputs(4K Product)
Data In/Out
Ground
RAS
Row Address Strobe
Column Address Strobe
Read/Write Input
Data Output Enable
Power(+3.3V)
CAS
W
OE
VCC
N.C
No Connection
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Voltage on VCC supply relative to V SS
Storage Temperature
Symbol
Rating
Units
V
VIN, VOUT
VCC
-0.5 to +4.6
-0.5 to +4.6
-55 to +150
1
V
Tstg
°C
Power Dissipation
PD
W
Short Circuit Output Current
IOS Address
50
mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= -40 to 85°C)
Parameter
Supply Voltage
Symbol
VCC
VSS
Min
3.0
0
Typ
Max
3.6
0
Units
3.3
V
V
V
V
Ground
0
-
*1
Input High Voltage
Input Low Voltage
VIH
2.0
Vcc+0.3
0.8
*2
VIL
-
-0.3
*1 : Vcc+1.3V at pulse width£15ns which is measured at VCC
*2 : -1.3 at pulse width£15ns which is measured at V SS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0£VIN£VCC+0.3V,
all other pins not under test=0 Volt)
II(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V£VOUT£VCC)
IO(L)
-5
5
uA
Output High Voltage Level(IOH=-2mA)
Output Low Voltage Level(IOL=2mA)
VOH
VOL
2.4
-
-
V
V
0.4
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Max
Symbol
Power
Speed
Units
K4E660412E
K4E640412E
-45
-50
-60
90
80
70
120
110
100
mA
mA
mA
ICC1
ICC2
ICC3
Don¢t care
Normal
L
1
1
1
1
mA
mA
Don¢t care
-45
-50
-60
90
80
70
120
110
100
mA
mA
mA
Don¢t care
Don¢t care
-45
-50
-60
100
90
80
100
90
80
mA
mA
mA
ICC4
ICC5
ICC6
Normal
L
0.5
200
0.5
200
mA
uA
Don¢t care
-45
-50
-60
120
110
100
120
110
100
mA
mA
mA
Don¢t care
ICC7
L
L
Don¢t care
Don¢t care
350
350
350
350
uA
uA
ICCS
ICC1* : Operating Current (RAS and CAS, Address cycling @tRC=min.)
ICC2 : Standby Current (RAS=CAS=W=V IH)
ICC3* : RAS-only Refresh Current (CAS=V IH, RAS, Address cycling @tRC=min.)
ICC4* : Extended Data Out Mode Current (RAS=VIL , CAS, Address cycling @tHPC=min.)
ICC5 : Standby Current (RAS=CAS=W=V CC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=CAS-before-RAS cycling or 0.2V
W, OE =VIH, Address=Don¢t care, DQ=Open, TRC=31.25us
ICCS : Self Refresh Current
RAS=CAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ3=V CC-0.2V, 0.2V or Open
*Note :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=V IL. In ICC4,
address can be changed maximum once within one EDO mode cycle time, tHPC.
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz)
Parameter
Input capacitance [A0 ~ A12]
Symbol
CIN1
Min
Max
Units
pF
-
-
-
5
7
7
Input capacitance [RAS , CAS, W, OE ]
Output capacitance [DQ0 - DQ3]
CIN2
pF
CDQ
pF
AC CHARACTERISTICS (-40°C£TA£85°C, See note 2)
Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
-45
-50
-60
Parameter
Symbol
Units
Note
Min
74
Max
Min
Max
Min
104
138
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
84
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
101
113
tRWC
tRAC
tCAC
tAA
45
12
23
50
13
25
60
15
30
3,4,10,12
Access time from CAS
3,4,5,12
Access time from column address
CAS to output in Low-Z
3,10,12
3
3
3
3
3
3
3
6,13
3
tCLZ
tCEZ
tOLZ
tT
Output buffer turn-off delay fromCAS
OE to output in Low-Z
13
50
13
50
13
50
3
3
3
Transition time (rise and fall)
RAS precharge time
1
1
1
2
25
45
8
30
50
8
40
60
10
40
10
14
12
5
tR P
RAS pulse width
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tW P
10K
10K
10K
RAS hold time
CAS hold time
35
7
38
8
CAS pulse width
5K
33
22
10K
37
10K
45
16
4
RAS to CAS delay time
11
9
11
9
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
25
30
10
5
5
0
0
0
7
7
10
0
Column address set-up time
Column address hold time
Column address toRAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
0
0
7
7
10
30
0
23
0
25
0
0
0
0
8
8
0
0
0
7
7
10
10
10
10
0
6
7
tRWL
tCWL
tD S
8
8
7
7
0
0
9
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
AC CHARACTERISTICS (Continued)
-45
-50
-60
Parameter
Symbol
Units
Note
Min
Max
Min
Max
Min
Max
Data hold time
7
7
10
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
9
tDH
Refresh period (Normal)
64
64
64
tREF
tREF
tWCS
tCWD
tRWD
tAWD
tCSR
tCHR
tRPC
tCPA
Refresh period (L-ver)
128
128
128
Write command set-up time
CAS to W delay time
0
24
57
35
5
0
27
64
39
5
0
7
7
7
7
32
77
47
5
RAS to W delay time
Column address toW delay time
CAS set-up time (CAS -before-RAS refresh)
CAS hold time (CAS -before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Hyper Page cycle time
10
5
10
5
10
5
24
28
35
3
17
47
6.5
45
24
20
47
7
25
56
10
60
35
14
14
tHPC
tHPRWC
tC P
Hyper Page read-modify-write cycle time
CAS precharge time (Hyper page cycle)
RAS pulse width (Hyper page cycle)
RAS hold time from CAS precharge
OE access time
200K
12
50
30
200K
13
200K
15
tRASP
tRHCP
tOEA
tOED
tCPWD
tOEZ
tOEH
tWTS
tWTH
tWRP
tWRH
tDOH
tREZ
tWEZ
tWED
tOCH
tCHO
tOEP
tWPE
tRASS
tRPS
tCHS
3
6
OE to data delay
8
36
3
10
41
3
13
52
3
CAS precharge to W delay time
Output buffer turn off delay time fromOE
OE command hold time
11
13
13
5
5
5
Write command set-up time (Test mode in)
Write command hold time (Test mode in)
W to RAS precharge time (C-B-R refresh)
W to RAS hold time (C-B-R refresh)
Output data hold time
10
10
10
10
4
10
10
10
10
5
10
10
10
10
5
11
11
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
3
13
13
3
13
13
3
13
13
6,13
6
3
3
3
8
15
5
15
5
OE to CAS hold time
5
CAS hold time to OE
5
5
5
OE precharge time
5
5
5
W pulse width (Hyper Page Cycle)
RAS pulse width (C-B-R self refresh)
RAS precharge time (C-B-R self refresh)
CAS hold time (C-B-R self refresh)
5
5
5
100
74
-50
100
90
-50
100
110
-50
15,16,17
15,16,17
15,16,17
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
TEST MODE CYCLE
( Note 11 )
-45
-50
-60
Parameter
Symbol
Units
Note
Min
79
Max
Min
89
Max
Min
109
145
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
110
121
tRWC
tRAC
tCAC
tAA
50
17
55
18
65
20
3,4,10,12
3,4,5,12
3,10,12
Access time from CAS
Access time from column address
RAS pulse width
28
30
35
50
12
18
39
28
29
62
40
22
52
50
10K
10K
55
13
18
43
30
35
72
47
25
53
55
10K
10K
65
15
20
50
35
39
84
54
30
61
65
10K
10K
tRAS
tCAS
tRSH
tCSH
tRAL
tCWD
tRWD
tAWD
tHPC
tHPRWC
tRASP
tCPA
CAS pulse width
RAS hold time
CAS hold time
Column Address to RAS lead time
CAS to W delay time
7
7
RAS to W delay time
Column Address to W delay time
Hyper Page cycle time
Hyper Page read-modify-write cycle time
RAS pulse width (Hyper page cycle)
Access time from CAS precharge
OE access time
7
14
14
200K
29
200K
33
200K
40
3
3
17
18
20
tOEA
tOED
tOEH
OE to data delay
13
13
18
18
20
20
OE command hold time
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition
times are measured between VIH(min) and VIL (max) and are assumed to be 2ns for all inputs.
2.
3. Measured with a load equivalent to 1 TTL load and 100pF.
4. Operation within thetRCD(max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC .
Assumes that tRCD³ tRCD(max).
5.
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric charac-
teristics only. If tWCS³ tWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD³ tCWD(min), tRWD³ tRWD(min) and tAWD³ tAWD(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
8.
9.
Either tRCH or tRRH must be satisfied for a read cycle.
This parameters are referenced to the CAS falling edge in early write cycles and to the W falling edge inOE controlled write
cycle and read-modify-write cycles.
10. Operation within thetRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.
If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA.
11.
These specifications are applied in the test mode.
12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
13. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
14. tASC³ 6ns, Assume tT = 2.0ns, if tASC£6ns, then tHPC (min) and tCAS (min) must be increased by the value of "6ns-tASC ".
15. If tRASS³ 100us, then RAS precharge time must use tRPS instead oftR P.
For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed
within 64ms before and after self refresh, in order to meet refresh specification.
16.
17. For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before
and after self refresh in order to meet refresh specification.
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
READ CYCLE
tRC
tRAS
tR P
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
CAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
tRCH
tRRH
VIH -
VIL -
W
tWEZ
tCEZ
tOEZ
tAA
VIH -
VIL -
OE
tOEA
tOLZ
tCAC
tCLZ
DQ0 ~ DQ3(7)
tREZ
DATA-OUT
tRAC
VOH -
VOL -
OPEN
Don¢t care
Undefined
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tR P
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
CAS
VIL -
tCAS
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tCWL
tRWL
tWCH
tWCS
VIH -
VIL -
tW P
W
VIH -
VIL -
OE
tDS
DQ0 ~ DQ3(7)
VIH -
tDH
DATA-IN
VIL -
Don¢t care
Undefined
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
CAS
tRAD
tASC
tRAL
tASR
tRAH
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
W
tCWL
tRWL
VIH -
VIL -
tWP
VIH -
VIL -
OE
tOEH
tOED
tDS
DQ0 ~ DQ3(7)
VIH -
tDH
DATA-IN
VIL -
Don¢t care
Undefined
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
READ - MODIFY - WRITE CYCLE
tRWC
tRAS
tRP
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
VIH -
CAS
tCAS
tCSH
VIL -
tRAD
tRAH
tASR
tASC
tCAH
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
A
tAWD
tRWL
tCWL
tCWD
VIH -
VIL -
W
tW P
tRWD
tOEA
VIH -
VIL -
OE
tOLZ
tCLZ
tCAC
tAA
tOED
tOEZ
tD S
tDH
DQ0 ~ DQ3(7)
VI/OH -
tRAC
VALID
DATA-OUT
VALID
DATA-IN
VI/OL -
Don¢t care
Undefined
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
HYPER PAGE READ CYCLE
tRP
tRASP
VIH -
RAS
VIL -
¡ó
tRHCP
tCAS
tCSH
tHPC
tCAS
tHPC
tCAS
tHPC
tCAS
tCRP
tRCD
tC P
tC P
tC P
VIH -
CAS
VIL -
tRAD
tASR
tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
tREZ
VIH -
VIL -
ROW
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDR
COLUMN
A
ADDR
ADDRESS
tRAL
tRRH
tRCS
tRCH
VIH -
VIL -
W
tCPA
tCAC
tCAC
tAA
tCPA
tCAC
tAA
tAA
tCPA
tAA
tCHO
tOEP
tOCH
VIH -
VIL -
tOEA
tOEA
OE
tOEP
tOEA
tCAC
tDOH
tOEZ
tOEZ
DQ0 ~ DQ3(7)
VOH -
tOEZ
tRAC
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
VOL -
tOLZ
tCLZ
VALID
DATA-OUT
Don¢t care
Undefined
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
HYPER PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRP
tRASP
VIH -
VIL -
tRHCP
RAS
¡ó
tHPC
tHPC
tRSH
tCRP
tASR
tRCD
tC P
tCP
VIH -
VIL -
tCAS
tCAS
tCAS
CAS
tRAD
¡ó
tCSH
tASC
tRAH
tCAH
tASC
tCAH
tASC
tCAH
¡ó
¡ó
VIH -
VIL -
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
COLUMN
ADDRESS
A
ADDRESS
tRAL
tWCH
tWCS
tWCS
tWP
tWCH
tWCS
tWCH
tWP
¡ó
tW P
VIH -
VIL -
W
tCWL
tCWL
tCWL
tRWL
¡ó
¡ó
VIH -
VIL -
OE
tDS
tDH
tD S
tDH
tDS
tDH
DQ0 ~ DQ3(7)
VIH -
¡ó
¡ó
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
VIL -
Don¢t care
Undefined
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
HYPER PAGE READ-MODIFY-WRITE CYCLE
tRP
tRASP
VIH -
VIL -
tCSH
tRSH
RAS
CAS
tHPRWC
tCRP
tRCD
tCP
tCRP
VIH -
VIL -
tCAS
tCAS
tRAL
tRAD
tRAH
tCAH
tCAH
tASR
tASC
tASC
VIH -
VIL -
ROW
ADDR
COL.
COL.
ADDR
A
W
ADDR
tRWL
tCWL
tRCS
tCWL
VIH -
VIL -
tWP
tW P
tCWD
tAWD
tRWD
tCWD
tAWD
tCPWD
VIH -
VIL -
tOEA
tOEA
OE
tOED
tOED
tCAC
tCAC
tDH
tDH
tAA
tAA
tOEZ
tOEZ
tD S
tDS
DQ0 ~ DQ3(7)
tRAC
VI/OH -
VI/OL -
tCLZ
tCLZ
VALID
tOLZ
tOLZ
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-IN
DATA-IN
Don¢t care
Undefined
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
HYPER PAGE READ AND WRITE MIXED CYCLE
tR P
tRASP
VIH -
VIL -
READ( tCAC)
READ(tCPA)
WRITE
READ(tAA )
RAS
tRHCP
tHPC
tHPC
tHPC
tCP
tC P
tCP
VIH -
VIL -
tCAS
tCAH
tCAS
tCAS
tCAH
tCAS
tCAH
CAS
tRAD
tASR
tRAH
tASC
tCAH
tASC
tASC
tASC
VIH -
VIL -
ROW
ADDR
COLUMN
COLUMN
COL.
ADDR
COL.
A
ADDRESS
ADDRESS
ADDR
tRAL
tRCS
tRCH
tRCS
tRCH
tWCH
tRCH
VIH -
VIL -
tWCS
W
tWPE
tCPA
tCLZ
tWED
VIH -
VIL -
OE
tDH
tD S
tOEA
tWEZ
tCAC
tAA
tRAC
tAA
tREZ
tWEZ
DQ0 ~ DQ3(7)
tCLZ
VI/OH -
VALID
DATA-OUT
VALID
DATA-OUT
VALID
VALID
DATA-IN
DATA-OUT
VI/OL -
Don¢t care
Undefined
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
RAS - ONLY REFRESH CYCLE*
NOTE : W, OE, DIN = Don¢t care
DOUT= OPEN
tRC
tR P
VIH -
RAS
VIL -
tRAS
tRPC
tCRP
tCRP
VIH -
CAS
VIL -
tASR
tRAH
VIH -
VIL -
ROW
ADDR
A
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tRPC
tCP
tCSR
VIH -
CAS
VIL -
tCHR
tWRP
tWRH
VIH -
W
VIL -
DQ0 ~ DQ3(7)
tCEZ
VOH -
OPEN
VOL -
Don¢t care
Undefined
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
HIDDEN REFRESH CYCLE ( READ )
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
VIL -
CAS
tRAD
tRAL
tCAH
COLUMN
tASR
tRAH
tASC
tRCS
VIH -
VIL -
ROW
ADDRESS
A
W
ADDRESS
tWRH
VIH -
VIL -
tAA
VIH -
VIL -
tOEA
tOLZ
OE
tCEZ
tCAC
tREZ
tWEZ
tCLZ
tRAC
DQ0 ~ DQ3(7)
VOH -
tOEZ
DATA-OUT
OPEN
VOL -
Don¢t care
Undefined
* In Hidden refresh cycle of 64Mb A-dile & B-die, whenCAS signal transits from Low to High, the valid data may be cut off.
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRC
tRAS
tR P
tR P
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
CAS
VIL -
tRAD
tRAL
tCAH
tASR
tRAH
tASC
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
W
tWRH
tWRP
tWCS
tWCH
VIH -
VIL -
tWP
VIH -
VIL -
OE
tDS
tDH
DATA-IN
DQ0 ~ DQ3(7)
VIH -
VIL -
Don¢t care
Undefined
Industrial Temperature
K4E660412E,K4E640412E
CMOS DRAM
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don¢t care
tRP
tRASS
tRPS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCHS
tCSR
VIH -
CAS
VIL -
DQ0 ~ DQ3(7)
tCEZ
VOH -
OPEN
VOL -
VIH -
VIL -
W
tWRP
tWRH
TEST MODE IN CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tR P
VIH -
RAS
tRAS
VIL -
tRPC
tCP
tRPC
tCSR
tWTS
VIH -
VIL -
tCHR
CAS
W
tWTH
VIH -
VIL -
tOFF
DQ0 ~ DQ3(7)
VOH -
OPEN
VOL -
Don¢t care
Undefined
Industrial Temperature
K4E660412E,K4E640412E
PACKAGE DIMENSION
32 SOJ 400mil
CMOS DRAM
Units : Inches (millimeters)
#32
0.006 (0.15)
0.012 (0.30)
#1
0.027 (0.69)
MIN
0.841 (21.36)
MAX
0.820 (20.84)
0.830 (21.08)
0.0375 (0.95)
0.050 (1.27)
0.026 (0.66)
0.032 (0.81)
0.015 (0.38)
0.021 (0.53)
32 TSOP(II) 400mil
Units : Inches (millimeters)
0.004 (0.10)
0.010 (0.25)
0.841 (21.35)
MAX
0.821 (20.85)
0.829 (21.05)
0.047 (1.20)
MAX
0.010 (0.25)
TYP
0.002 (0.05)
0.037 (0.95)
0.050 (1.27)
MIN
0.012 (0.30)
0.020 (0.50)
0~8O
0.018 (0.45)
0.030 (0.75)
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