K4E660812D-JP60T [SAMSUNG]
DRAM;
| 型号： | K4E660812D-JP60T |
| 厂家： | 
SAMSUNG |
| 描述： | DRAM 动态存储器 |
| 文件： | 总21页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
8M x 8bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 8,388,608 x 8 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Nor-
mal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden
refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 8Mx8 EDO Mode DRAM family is fabricated using
Samsung¢s advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
• Extended Data Out Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• Part Identification
- K4E660812D-JI/P(3.3V, 8K Ref.)
- K4E640812D-JI/P(3.3V, 4K Ref.)
- K4E660812D-TI/P(3.3V, 8K Ref.)
- K4E640812D-TI/P(3.3V, 4K Ref.)
• LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Active Power Dissipation
Unit : mW
Speed
-45
8K
4K
• Available in Plastic SOJ and TSOP(II) packages
• +3.3V ±0.3V power supply
324
288
252
432
396
360
-50
• Industrial Temperature operating ( -40~85°C)
-60
• Refresh Cycles
FUNCTIONAL BLOCK DIAGRAM
Part
NO.
Refresh
cycle
Refresh time
Normal
L-ver
RAS
CAS
W
Vcc
Vss
K4E660812D*
K4E640812D
8K
4K
Control
Clocks
64ms
128ms
VBB Generator
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS -before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
Row Decoder
Refresh Timer
Data in
Buffer
Refresh Control
Refresh Counter
Memory Array
8,388,608 x 8
Cells
DQ0
to
¡
Ü
Performance Range:
DQ7
Data out
Buffer
Row Address Buffer
Col. Address Buffer
A0~A12
(A0~A11)*1
Speed
-45
tRAC
45ns
50ns
60ns
tCAC
12ns
13ns
15ns
tRC
tHPC
17ns
20ns
25ns
OE
74ns
84ns
104ns
A0~A9
(A0~A10)*1
Column Decoder
-50
Note) *1 : 4K Refresh
-60
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
PIN CONFIGURATION (Top Views)
• K4E660812D-T
• K4E640812D-T
• K4E660812D-J
• K4E640812D-J
VCC
DQ0
DQ1
DQ2
DQ3
N.C
VCC
W
1
2
3
4
5
6
7
8
9
32
VSS
VCC
DQ0
DQ1
DQ2
DQ3
N.C
VCC
W
RAS
A0
A1
A2
A3
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
31 DQ7
30 DQ6
29 DQ5
28 DQ4
DQ7
DQ6
DQ5
DQ4
VSS
CAS
OE
A12(N.C)*
A11
A10
A9
27
VSS
26 CAS
25 OE
24 A12(N.C)*
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17
RAS
9
A0 10
A1 11
A2 12
A3 13
A4 14
A5 15
10
11
12
13
14
15
16
A8
A7
A6
VSS
A4
A5
VCC
VCC
16
VSS
(J : 400mil SOJ)
(T : 400mil TSOP(II))
* (N.C) : N.C for 4K Refresh product
Pin Name
A0 - A12
A0 - A11
DQ0 - 7
VSS
Pin Function
Address Inputs(8K Product)
Address Inputs(4K Product)
Data In/Out
Ground
RAS
Row Address Strobe
Column Address Strobe
Read/Write Input
Data Output Enable
Power(+3.3V)
CAS
W
OE
VCC
N.C
No Connection
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
Symbol
VIN, VOUT
VCC
Rating
-0.5 to +4.6
-0.5 to +4.6
-55 to +150
1
Units
V
V
Tstg
°C
Power Dissipation
PD
W
Short Circuit Output Current
IOS Address
50
mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= -40 to 85°C)
Parameter
Supply Voltage
Symbol
VCC
VSS
Min
3.0
0
Typ
Max
3.6
0
Units
3.3
V
V
V
V
Ground
0
-
*1
Input High Voltage
Input Low Voltage
VIH
2.0
Vcc+0.3
0.8
*2
VIL
-
-0.3
*1 : Vcc+1.3V at pulse width£15ns which is measured at VCC
*2 : -1.3 at pulse width£15ns which is measured at V SS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0£VIN£VCC+0.3V,
all other pins not under test=0 Volt)
II(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V£VOUT£VCC)
IO(L)
-5
5
uA
Output High Voltage Level(IOH=-2mA)
Output Low Voltage Level(IOL =2mA)
VOH
VOL
2.4
-
-
V
V
0.4
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Max
Symbol
Power
Speed
Units
K4E660812D
K4E640812D
-45
-50
-60
90
80
70
120
110
100
mA
mA
mA
ICC1
ICC2
ICC3
Don¢t care
Normal
L
1
1
1
1
mA
mA
Don¢t care
-45
-50
-60
90
80
70
120
110
100
mA
mA
mA
Don¢t care
Don¢t care
-45
-50
-60
100
90
80
100
90
80
mA
mA
mA
ICC4
ICC5
ICC6
Normal
L
0.5
200
0.5
200
mA
uA
Don¢t care
-45
-50
-60
120
110
100
120
110
100
mA
mA
mA
Don¢t care
ICC7
ICCS
L
L
Don¢t care
Don¢t care
350
350
350
350
uA
uA
ICC1* : Operating Current (RAS and CAS, Address cycling @tRC=min.)
ICC2 : Standby Current (RAS=CAS=W=V IH)
ICC3* : RAS-only Refresh Current (CAS =VIH, RAS cycling @tRC=min.)
ICC4* : Extended Data Out Mode Current (RAS=VIL , CAS, Address cycling @tHPC=min.)
ICC5 : Standby Current (RAS=CAS=W=V CC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL )=0.2V, CAS=CAS-before-RAS cycling or 0.2V
W, OE=V IH, Address=Don¢t care, DQ=Open, TRC=31.25us
ICCS : Self Refresh Current
RAS=CAS=0.2V, W=OE =A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ7=V CC-0.2V, 0.2V or Open
*Note :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=V IL. In ICC4,
address can be changed maximum once within one EDO mode cycle time, tHPC.
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz)
Parameter
Input capacitance [A0 ~ A12]
Symbol
CIN1
Min
Max
Units
pF
-
-
-
5
7
7
Input capacitance [RAS, CAS , W, OE]
Output capacitance [DQ0 - DQ7]
CIN2
pF
CDQ
pF
AC CHARACTERISTICS (-40°C£TA£85°C, See note 2)
Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
-45
-50
-60
Parameter
Symbol
Units
Note
Min
74
Max
Min
Max
Min
104
138
Max
Random read or write cycle time
Read-modify-write cycle time
Access time fromRAS
84
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
101
113
tRWC
tRAC
tCAC
tAA
45
12
23
50
13
25
60
15
30
3,4,10
3,4,5
3,10
3
Access time fromCAS
Access time from column address
CAS to output in Low-Z
3
3
3
3
3
tCLZ
tCEZ
tOLZ
tT
Output buffer turn-off delay from CAS
OE to output in Low-Z
13
50
13
50
3
13
50
6,13
3
3
3
3
Transition time (rise and fall)
RAS precharge time
1
1
1
2
tR P
25
45
8
30
50
8
40
60
10
40
10
14
12
5
RAS pulse width
10K
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tW P
RAS hold time
CAS hold time
35
7
38
8
CAS pulse width
5K
33
22
10K
37
10K
45
14
4
RAS to CAS delay time
11
9
11
9
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
25
30
10
5
5
0
0
0
7
7
10
0
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command toRAS lead time
Write command toCAS lead time
Data set-up time
0
0
7
7
10
30
0
23
0
25
0
0
0
0
8
8
0
0
0
7
7
10
10
10
10
0
6
7
8
8
tRWL
tCWL
tD S
7
7
0
0
9
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
AC CHARACTERISTICS (Continued)
-45
-50
-60
Parameter
Symbol
Units
Note
Min
Max
Min
Max
Min
Max
Data hold time
7
7
10
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
9
tDH
Refresh period (Normal)
tREF
tREF
tWCS
tCWD
tRWD
tAWD
tCSR
tCHR
tRPC
tCPA
tHPC
tHPRWC
tC P
64
64
64
Refresh period (L-ver)
128
128
128
Write command set-up time
CAS to W delay time
0
24
57
35
5
0
27
64
39
5
0
32
77
47
5
7
7
7
7
RAS to W delay time
Column address toW delay time
CAS set-up time (CAS -before-RAS refresh)
CAS hold time (CAS -before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Hyper Page cycle time
10
5
10
5
10
5
24
28
35
3
17
47
6.5
45
24
20
47
7
25
56
10
60
35
14
14
Hyper Page read-modify-write cycle time
CAS precharge time (Hyper page cycle)
RAS pulse width (Hyper page cycle)
RAS hold time from CAS precharge
OE access time
200K
12
50
30
200K
13
200K
15
tRASP
tRHCP
tOEA
tOED
tCPWD
tOEZ
tOEH
tWTS
tWTH
tWRP
tWRH
tDOH
tREZ
tWEZ
tWED
tOCH
tCHO
tOEP
tWPE
tRASS
tRPS
tCHS
3
6
OE to data delay
8
36
3
10
41
3
13
52
3
CAS precharge to W delay time
Output buffer turn off delay time from OE
OE command hold time
11
13
13
5
5
5
Write command set-up time (Test mode in)
Write command hold time (Test mode in)
W to RAS precharge time (C-B-R refresh)
W to RAS hold time (C-B-R refresh)
Output data hold time
10
10
10
10
4
10
10
10
10
5
10
10
10
10
5
11
11
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
3
13
13
3
13
13
3
13
13
6,13
6
3
3
3
8
15
5
15
5
OE to CAS hold time
5
CAS hold time to OE
5
5
5
OE precharge time
5
5
5
W pulse width (Hyper Page Cycle)
RAS pulse width (C-B-R self refresh)
RAS precharge time (C-B-R self refresh)
CAS hold time (C-B-R self refresh)
5
5
5
100
74
-50
100
90
-50
100
110
-50
15,16,17
15,16,17
15,16,17
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
( Note 11 )
TEST MODE CYCLE
-45
-50
-60
Parameter
Symbol
Units
Note
Min
79
Max
Min
89
Max
Min
109
145
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
110
121
tRWC
tRAC
tCAC
tAA
50
17
55
18
65
20
3,4,10,12
3,4,5,12
3,10,12
Access time from CAS
Access time from column address
RAS pulse width
28
30
35
50
12
18
39
28
29
62
40
22
52
50
10K
10K
55
13
18
43
30
35
72
47
25
53
55
10K
10K
65
15
20
50
35
39
84
54
30
61
65
10K
10K
tRAS
tCAS
tRSH
tCSH
tRAL
tCWD
tRWD
tAWD
tHPC
tHPRWC
tRASP
tCPA
tOEA
tOED
tOEH
CAS pulse width
RAS hold time
CAS hold time
Column Address to RAS lead time
CAS to W delay time
7
7
RAS to W delay time
Column Address to W delay time
Hyper Page cycle time
Hyper Page read-modify-write cycle time
RAS pulse width (Hyper page cycle)
Access time from CAS precharge
OE access time
7
14
14
200K
29
200K
33
200K
40
3
3
17
18
20
OE to data delay
13
13
18
18
20
20
OE command hold time
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition
times are measured between VIH(min) and VIL (max) and are assumed to be 2ns for all inputs.
3. Measured with a load equivalent to 1 TTL load and 100pF.
4. Operation within thetRCD(max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC .
Assumes that tRCD³ tRCD(max).
5.
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric charac-
teristics only. If tWCS³ tWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD³ tCWD(min), tRWD³ tRWD(min) and tAWD ³ tAWD(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
8. Either tRCH or tRRH must be satisfied for a read cycle.
9.
This parameters are referenced to the CAS falling edge in early write cycles and to the W falling edge inOE controlled write
cycle and read-modify-write cycles.
10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
11.
12.
These specifications are applied in the test mode.
In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
13.
14. tASC³ 6ns, Assume tT = 2.0ns, if tASC£6ns, then tHPC (min) and tCAS (min) must be increased by the value of "6ns-tASC ".
15. If tRASS³ 100us, then RAS precharge time must use tRPS instead oftR P.
16. For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed
within 64ms before and after self refresh, in order to meet refresh specification.
17. For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before
and after self refresh in order to meet refresh specification.
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
READ CYCLE
tRC
tRAS
tR P
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
CAS
tCAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
VIH -
ROW
ADDRESS
COLUMN
ADDRESS
A
VIL -
tRCH
tRRH
VIH -
W
VIL -
tWEZ
tCEZ
tOEZ
tAA
VIH -
OE
tOEA
tOLZ
VIL -
tCAC
tCLZ
DQ0 ~ DQ3(7)
VOH -
tREZ
DATA-OUT
tRAC
OPEN
VOL -
Don¢t care
Undefined
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tR P
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
CAS
VIL -
tCAS
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tCWL
tRWL
tWCH
tWCS
VIH -
VIL -
tW P
W
VIH -
VIL -
OE
tDS
DQ0 ~ DQ3(7)
VIH -
tDH
DATA-IN
VIL -
Don¢t care
Undefined
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tR C
tR A S
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tC A S
V IH -
V IL -
C A S
tRAD
tR A L
tA S R
tRAH
tASC
tC A H
C O L U M N
A D D R E S S
VIH -
VIL -
R O W
A D D R E S S
A
W
tCWL
tR W L
VIH -
VIL -
tW P
VIH -
VIL -
OE
tO E H
tO E D
tDS
DQ0 ~ DQ3(7)
VIH -
tDH
DATA-IN
VIL -
D o n¢t c a r e
U n d e f i n e d
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
R E A D - M O D I F Y - W R I T E C Y C L E
tR W C
tR A S
tRP
V IH -
R A S
V IL
-
tC R P
tR C D
tR S H
V IH -
V IL -
tC A S
C A S
tR A D
tRAH
tA S R
tA S C
tCAH
tCSH
V IH -
V IL -
ROW
A D D R
C O L U M N
A
ADDRESS
tA W D
tR W L
tC W L
tCWD
V IH -
W
tW P
V IL
-
tRWD
tO E A
V IH -
V IL -
O E
tOLZ
tCLZ
tCAC
tA A
tOED
tOEZ
tD S
tDH
D Q 0
~ D Q 3 ( 7 )
tRAC
V I/OH -
V I/OL -
VALID
VALID
DATA-IN
DATA-OUT
D o n ¢t c a r e
U n d e f i n e d
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
H Y P E R P A G E R E A D C Y C L E
tRP
tRASP
V IH -
R A S
V IL -
¡ó
tR H C P
tCSH
tHPC
tHPC
tH P C
tC R P
tC P
tC P
tC P
tR C D
tC A S
tC A S
tC A S
tC A S
V IH -
V IL
C A S
-
tRAD
tA S R
tRAH tASC
tCAH
tA S C
tCAH
tA S C
tCAH
tA S C
tCAH
tR E Z
V IH -
V IL -
R O W
ADDR
C O L U M N
A D D R E S S
C O L U M N
A D D R E S S
C O L U M N
A D D R
C O L U M N
A
A D D R E S S
tRAL
tRRH
tR C S
tR C H
V IH -
V IL -
W
tC P A
tC A C
tCAC
tC A C
tAA
tA A
tA A
tC P A
tC P A
tCHO
tO E P
tA A
tO C H
V IH -
tOEA
tOEA
O E
V IL
-
tO E P
tO E A
tCAC
tD O H
tO E Z
tO E Z
D Q 0
~
D Q 3 ( 7 )
V O H
tO E Z
tRAC
-
-
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
V O L
tOLZ
tCLZ
VALID
DATA-OUT
D o n ¢t c a r e
U n d e f i n e d
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
H Y P E R P A G E W R I T E C Y C L E ( E A R L Y W R I T E )
N O T E
: D O U T = O P E N
tRP
tR A S P
V IH -
tR H C P
R A S
V IL -
¡ó
tH P C
tHPC
tRSH
tC R P
tR C D
tC P
tCP
V IH -
V IL -
tC A S
tC A S
tC A S
¡ó
C A S
tR A D
tC S H
tA S C
tA S R
tRAH
tCAH
tA S C
tCAH
tASC
tCAH
¡ ó
¡ ó
V IH -
V IL -
R O W
A D D R .
C O L U M N
A D D R E S S
C O L U M N
C O L U M N
A D D R E S S
A
A D D R E S S
tRAL
tWCH
tW P
tW C S
tW C S
tW P
tW C H
tW C S
tW C H
tW P
¡ ó
V IH -
V IL -
W
tC W L
tC W L
tC W L
tR W L
¡ ó
¡ ó
V IH
V IL
-
O E
-
tDS
tDH
tD S
tD H
tDS
tD H
D Q 0
~
D Q 3 ( 7 )
V IH -
¡ó
¡ó
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
V IL -
D o n ¢t care
U n d e f i n e d
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
H Y P E R P A G E R E A D - M O D I F Y - W R I T E C Y C L E
tRP
tR A S P
V IH -
V IL
tCSH
tR S H
R A S
-
tH P R W C
tC R P
tR C D
tCP
tC R P
V IH -
V IL
tC A S
tC A S
tRAL
C A S
-
tRAD
tRAH
tC A H
tCAH
tA S R
tA S C
tA S C
V IH -
R O W
A D D R
COL.
COL.
A D D R
A
ADDR
V IL
-
tRWL
tCWL
tR C S
tC W L
V IH
V IL
-
tW P
tW P
W
-
tC W D
tA W D
tR W D
tCWD
tA W D
tC P W D
V IH -
V IL -
tO E A
tO E A
O E
tOED
tO E D
tCAC
tC A C
tD H
tDH
tA A
tA A
tO E Z
tO E Z
tD S
tDS
D Q 0
~
D Q 3 ( 7 )
V I/OH -
tRAC
V I/OL -
tCLZ
tCLZ
tOLZ
tOLZ
VALID
VALID
DATA-IN
VALID
VALID
DATA-IN
D A T A - O U T
D A T A - O U T
D o n ¢t c a r e
U n d e f i n e d
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
H Y P E R P A G E R E A D A N D W R I T E M I X E D C Y C L E
tR P
tRASP
V IH -
V IL -
READ( tCAC)
R E A D (t CPA)
R E A D (tAA )
W R I T E
R A S
tR H C P
tHPC
tHPC
tH P C
tCP
tC P
tCP
V IH -
tC A S
tC A H
tC A S
tC A S
tC A H
tC A S
C A S
tRAD
V IL
-
tRAH
tA S C
tC A H
tA S R
tCAH
tASC
tA S C
tASC
V IH -
V IL -
C O L U M N
COL.
A D D R
COL.
R O W
ADDR
C O L U M N
A D D R E S S
A
A D D R E S S
A D D R
tR A L
tR C S
tR C H
tR C S
tR C H
tW C H
tR C H
V IH -
V IL -
tW C S
W
tW P E
tC P A
tCLZ
tW E D
V IH -
O E
V IL
-
tDH
tD S
tOEA
tWEZ
tCAC
tA A
tRAC
tR E Z
tW E Z
tA A
D Q 0
~ D Q 3 ( 7 )
tCLZ
V I/OH -
VALID
DATA-OUT
VALID
VALID
VALID
DATA-OUT
DATA-IN
DATA-OUT
V I/OL -
D o n ¢t c a r e
U n d e f i n e d
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
R A S - O N L Y R E F R E S H C Y C L E *
N O T E : W , O E , D IN
= D o n ¢t c a r e
D O U T = O P E N
tRC
tR P
V IH -
R A S
tR A S
V IL
-
tRPC
tCRP
tCRP
V IH -
V IL -
C A S
tASR
tRAH
V IH -
R O W
A D D R
A
V IL
-
C A S - BEFORE - R A S R E F R E S H C Y C L E
N O T E : O E , A = D o n¢t care
tR C
tRP
tRP
tR A S
V IH -
R A S
V IL -
tRPC
tRPC
tCP
tC S R
V IH -
C A S
V IL -
tC H R
tW R P
tWRH
V IH
-
W
V IL -
D Q 0
~
D Q 3 ( 7 )
V O H -
tC E Z
O P E N
V O L
-
D o n ¢t care
U n d e f i n e d
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
H I D D E N R E F R E S H C Y C L E ( R E A D )
tRC
tRC
tRP
tRP
tR A S
tRAS
V IH -
R A S
V IL -
tC R P
tR C D
tRSH
tC H R
V IH -
V IL -
C A S
tRAD
tRAL
tA S R
tRAH
tA S C
tCAH
C O L U M N
V IH -
R O W
A D D R E S S
A
A D D R E S S
V IL
-
tW R H
tR C S
V IH -
V IL -
W
tA A
V IH -
V IL -
tO E A
tOLZ
O E
tCEZ
tCAC
tR E Z
tW E Z
tC L Z
D Q 0
~
D Q 3 ( 7 )
V O H -
tRAC
tO E Z
D A T A - O U T
O P E N
V O L
-
D o n ¢t c a r e
U n d e f i n e d
*
I n H i d d e n r e f r e s h c y c l e o f 6 4 M b A - d i l e & B - d i e , w h e n C A S s i g n a l t r a n s i t s f r o m L o w t o H i g h , t h e v a l i d d a t a m a y b e c u t o f f .
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
HIDDEN REFRESH CYCLE ( WRITE )
N O T E
: D O U T = O P E N
tRC
tR A S
tRC
tR A S
tR P
tR P
V IH -
R A S
V IL -
tC R P
tRCD
tRSH
tC H R
V IH -
C A S
V IL -
tRAD
tRAL
tCAH
tA S R
tR A H
tASC
V IH -
A
R O W
ADDRESS
C O L U M N
ADDRESS
V IL -
tWRH
tW R P
tW C S
tW C H
V IH -
tW P
W
V IL -
V IH -
O E
V IL
-
tDS
tDH
D Q 0
~
D Q 3 ( 7 )
V IH -
V IL
DATA-IN
-
D o n ¢t c a r e
U n d e f i n e d
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
C A S - BEFORE - R A S S E L F R E F R E S H C Y C L E
N O T E : O E , A = D o n ¢t care
tRP
tR A S S
tR P S
V IH -
R A S
V IL
-
tRPC
tCP
tR P C
tC H S
tC S R
V IH -
C A S
V IL
-
D Q 0
~
D Q 3 ( 7 )
V O H
tC E Z
-
-
O P E N
V OL
V IH -
W
V IL
-
tW R P
tW R H
T E S T M O D E I N C Y C L E
N O T E : O E , A = D o n ¢t care
tR C
tRP
tR P
V IH -
R A S
tR A S
V IL
-
tR P C
tCP
tRPC
tC S R
V IH -
tC H R
C A S
V IL
-
tW T S
tW T H
V IH -
W
V IL
-
tOFF
D Q 0
~
D Q 3 ( 7 )
V O H
-
-
O P E N
V OL
D o n ¢t c a r e
U n d e f i n e d
Industrial Temperature
K4E660812D,K4E640812D
CMOS DRAM
P A C K A G E D I M E N S I O N
32 SOJ 400mil
U n i t s
:
I n c h e s ( m i l l i m e t e r s )
#32
0.006 (0.15)
0.012 (0.30)
#1
0.027 (0.69)
MIN
0.841 (21.36)
M A X
0.820 (20.84)
0.830 (21.08)
0.0375 (0.95)
0.050 (1.27)
0.026 (0.66)
0.032 (0.81)
0.015 (0.38)
0.021 (0.53)
32 TSOP(II) 400mil
U n i t s
:
I n c h e s ( m i l l i m e t e r s )
0.004 (0.10)
0.010 (0.25)
0.841 (21.35)
M A X
0.821 (20.85)
0.829 (21.05)
0.047 (1.20)
M A X
0.010 (0.25)
TYP
0.002 (0.05)
0.037 (0.95)
0.050 (1.27)
MIN
0.012 (0.30)
0.020 (0.50)
0~8O
0.018 (0.45)
0.030 (0.75)
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