K4F151611D-T50 [SAMSUNG]
DRAM;
| 型号： | K4F151611D-T50 |
| 厂家： | 
SAMSUNG |
| 描述： | DRAM 动态存储器 |
| 文件： | 总34页 (文件大小：352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
1M x 16Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 1,048,576 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K Ref.), access time (-50 or -60), power
consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-
before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This
1Mx16 Fast Page Mode DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
FEATURES
• Fast Page Mode operation
• Part Identification
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
- K4F171611D-J(T) (5V, 4K Ref.)
- K4F151611D-J(T) (5V, 1K Ref.)
- K4F171612D-J(T) (3.3V, 4K Ref.)
- K4F151612D-J(T) (3.3V, 1K Ref.)
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Active Power Dissipation
Unit : mW
5V
• Available in 42-pin SOJ 400mil and 50(44)-pin TSOP(II)
3.3V
400mil packages
• Single +5V±10% power supply (5V product)
Speed
4K
324
288
1K
4K
1K
770
715
• Single +3.3V±0.3V power supply (3.3V product)
-50
-60
504
468
495
440
FUNCTIONAL BLOCK DIAGRAM
• Refresh Cycles
Part
NO.
Refresh
cycle
Refresh period
Normal L-ver
VCC
RAS
UCAS
LCAS
W
Vcc
Vss
Control
Clocks
VBB Generator
K4F171611D
5V
4K
1K
64ms
128ms
16ms
Lower
K4F171612D 3.3V
K4F151611D 5V
Data in
DQ0
to
Refresh Timer
Refresh Control
Row Decoder
Buffer
DQ7
K4F151612D 3.3V
Lower
Data out
Buffer
Memory Array
1,048,576 x16
Cells
OE
Refresh Counter
Row Address Buffer
Col. Address Buffer
Upper
Data in
Buffer
• Perfomance Range
A0-A11
(A0 - A9)*1
A0 - A7
DQ8
to
DQ15
Speed
-50
Remark
35ns 5V/3.3V
tRAC
50ns
60ns
tCAC
tRC
tPC
Upper
Data out
Buffer
15ns
90ns
Column Decoder
(A0 - A9)*1
-60
15ns 110ns 40ns 5V/3.3V
Note) *1 : 1K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
PIN CONFIGURATION (Top Views)
• K4F17(5)1611(2)D-T
• K4F17(5)1611(2)D-J
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
N.C
VSS
VCC
1
2
3
4
5
6
7
8
9
10
42 VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
N.C 11
N.C 12
W
RAS
41 DQ15
40 DQ14
39 DQ13
38 DQ12
37 VSS
36 DQ11
35 DQ10
34 DQ9
33 DQ8
32 N.C
31 LCAS
30 UCAS
29 OE
28 A9
27 A8
26 A7
25 A6
24 A5
23 A4
22 VSS
9
10
11
DQ8
N.C
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
N.C
N.C
W
N.C
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
13
14
15
*A11(N.C)
*A10(N.C) 16
RAS
*A11(N.C)
*A10(N.C)
A0
A0
A1
A2
A3
VCC
17
18
19
20
21
A1
A2
A3
VCC
VSS
*A10 and A11 are N.C for K4F151611(2)D(5V/3.3V, 1K Ref. product)
J : 400mil 42 SOJ
T : 400mil 50(44) TSOP II
Pin Name
A0 - A11
A0 - A9
DQ0 - 15
VSS
Pin Function
Address Inputs (4K Product)
Address Inputs (1K Product)
Data In/Out
Ground
RAS
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Read/Write Input
UCAS
LCAS
W
OE
Data Output Enable
Power(+5V)
VCC
Power(+3.3V)
N.C
No Connection
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Units
3.3V
-0.5 to +4.6
-0.5 to +4.6
-55 to +150
1
5V
Voltage on any pin relative to VSS
Voltage on VCC supply relative to V SS
Storage Temperature
VIN,VOUT
VCC
-1.0 to +7.0
-1.0 to +7.0
-55 to +150
1
V
V
Tstg
°C
W
Power Dissipation
PD
Short Circuit Output Current
IOS Address
50
50
mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)
3.3V
5V
Typ
5.0
0
Parameter
Symbol
Units
Min
3.0
0
Typ
Max
3.6
0
Min
4.5
0
Max
5.5
0
Supply Voltage
VCC
VSS
VIH
VIL
3.3
V
V
V
V
Ground
0
-
*1
*1
Input High Voltage
Input Low Voltage
2.0
2.4
-
VCC+0.3
0.8
VCC+1.0
0.8
*2
*2
-
-
-0.3
-1.0
*1 : VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC
*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at V SS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Max
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0£VIN£VIN+0.3V,
all other input pins not under test=0 Volt)
II(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V£VOUT£VCC)
IO(L)
-5
5
uA
3.3V
Output High Voltage Level(IOH=-2mA)
Output Low Voltage Level(IOL=2mA)
VOH
VOL
2.4
-
-
V
V
0.4
Input Leakage Current (Any input 0£VIN£VIN+0.5V,
all other input pins not under test=0 Volt)
II(L)
-5
-5
5
5
uA
uA
Output Leakage Current
(Data out is disabled, 0V£VOUT£VCC)
IO(L)
5V
Output High Voltage Level(IOH=-5mA)
Output Low Voltage Level(IOL=4.2mA)
VOH
VOL
2.4
-
-
V
V
0.4
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Max
Symbol
Power
Speed
Units
K4F171612D
K4F151612D
K4F171611D
K4F151611D
-50
-60
90
80
140
130
90
80
140
130
mA
mA
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
Don¢t care
Normal
L
1
1
1
1
2
1
2
1
mA
mA
Don¢t care
-50
-60
90
80
140
130
90
80
140
130
mA
mA
Don¢t care
Don¢t care
-50
-60
90
80
90
80
90
80
90
80
mA
mA
Normal
L
0.5
200
0.5
200
1
200
1
200
mA
uA
Don¢t care
-50
-60
90
80
140
130
90
80
140
130
mA
mA
Don¢t care
ICC7
ICCS
L
L
Don¢t care
Don¢t care
300
150
200
150
350
200
250
200
uA
uA
ICC1* : Operating Current (RAS and UCAS, LCAS cycling @tRC=min.)
ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH)
ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS cycling @tRC=min.)
ICC4* : Fast Page Mode Current (RAS=VIL , UCAS or LCAS, Address cycling @tPC=min.)
ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS, UCAS or LCAS cycling @tRC=min.)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=0.2V,
DQ=Don¢t care, TRC=31.25us(4K/L-ver), 125us(1K/L-ver),
TRAS=TRASmin~300ns
ICCS : Self Refresh Current
RAS=UCAS=LCAS=VIL , W=OE=A0 ~ A11=VCC-0.2V or 0.2V,
DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open
*Note :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL . In ICC4,
address can be changed maximum once within one fast page mode cycle time, tPC .
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)
Parameter
Input capacitance [A0 ~ A11]
Symbol
Min
Max
Units
pF
CIN1
CIN2
CDQ
-
-
-
5
7
7
Input capacitance [RAS, UCAS, LCAS, W, OE]
Output capacitance [DQ0 - DQ15]
pF
pF
AC CHARACTERISTICS (0°C£TA£70°C, See note 1,2)
Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
-50
-60
Parameter
Symbol
Units
Notes
Min
90
Max
Min
110
155
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
tRWC
tRAC
tCAC
tAA
133
50
15
25
60
15
30
3,4,10
3,4,5
3,10
3
Access time from CAS
Access time from column address
CAS to output in Low-Z
0
0
0
tCLZ
tOFF
tT
Output buffer turn-off delay
Transition time (rise and fall)
RAS precharge time
13
50
0
15
50
6
3
3
2
30
50
13
50
13
20
15
5
40
60
15
60
15
20
15
5
tR P
RAS pulse width
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tW P
RAS hold time
CAS hold time
CAS pulse width
10K
37
10K
45
RAS to CAS delay time
4
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
25
30
10
0
0
10
0
10
0
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command toRAS lead time
Write command toCAS lead time
11
11
10
25
0
10
30
0
0
0
8
8
0
0
10
10
13
13
10
10
15
15
tRWL
tCWL
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
AC CHARACTERISTICS (Continued)
-50
-60
Parameter
Symbol
Units
Notes
Min
Max
Min
Max
Data set-up time
Data hold time
0
0
ns
9,17
9,17
tD S
10
10
ns
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
tDH
Refresh period (1K, Normal)
Refresh period (4K, Normal)
Refresh period (L-ver)
16
64
16
64
tREF
tREF
tREF
tWCS
tCWD
tRWD
tAWD
tCPWD
tCSR
tCHR
tRPC
tCPA
128
128
Write command set-up time
0
0
7
7,13
7
CAS to W delay time
36
73
48
53
5
40
85
55
60
5
RAS to W delay time
Column address to W delay time
CAS precharge to W delay time
CAS set-up time (CAS-before-RAS refresh)
CAS hold time (CAS-before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Fast Page mode cycle time
7
7
15
16
10
5
10
5
30
35
3
12
3
35
76
10
50
30
40
80
10
60
35
tPC
Fast Page read-modify-write cycle time
CAS precharge time (Fast Page cycle)
RAS pulse width (Fast Page cycle)
RAS hold time from CAS precharge
OE access time
tPRWC
tC P
200K
13
200K
15
tRASP
tRHCP
tOEA
tOED
tOEZ
tOEH
tRASS
tRPS
tCHS
OE to data delay
13
0
15
0
Output buffer turn off delay time from OE
OE command hold time
13
15
13
100
90
-50
15
RAS pulse width (C-B-R self refresh)
RAS precharge time (C-B-R self refresh)
CAS hold time (C-B-R self refresh)
100
110
-50
18,19,20
18,19,20
18,19,20
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS -only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
1.
2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 100pF.
4.
Operation within thetRCD(max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC .
5. Assumes that tRCD³ tRCD(max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
7. tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. IftWCS³ tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD³ tCWD(min), tRWD³ tRWD(min), tAWD³ tAWD(min) and tCPWD³ tCPWD (min), then the cycle is a read-
modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions
is satisfied, the condition of the data out is indeterminate.
8.
Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle
and read-modify-write cycles.
Operation within thetRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.
10.
If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA.
tASC, tCAH are referenced to the earlier CAS falling edge.
11.
12.
tC P is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.
K4F17(5)1611(2)D Truth Table
RAS
LCAS
UCAS
W
X
X
H
H
H
L
OE
X
DQ0 - DQ7
Hi-Z
DQ8-DQ15
Hi-Z
STATE
Standby
H
L
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
Hi-Z
Hi-Z
Refresh
L
DQ-OUT
Hi-Z
Hi-Z
Byte Read
Byte Read
Word Read
Byte Write
Byte Write
Word Write
-
H
L
L
DQ-OUT
DQ-OUT
-
L
L
DQ-OUT
DQ-IN
-
L
H
L
H
H
H
H
H
L
L
DQ-IN
DQ-IN
Hi-Z
L
L
DQ-IN
Hi-Z
L
L
H
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
13. tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.
14. tCWL is specified fromW falling edge to the earlier CAS rising edge.
15.
16.
tCSR is referenced to the earlier CAS falling edge before RAS transition low.
tCHR is referenced to the later CAS rising edge after RAS transition low.
RAS
LCAS
UCAS
tCSR
tCHR
tDS, tDH is independently specified for lower byte DQ(0-7), upper byte DQ(8-15)
17.
18. If tRASS³ 100us, then RAS precharge time must use tRPS instead of tRP.
19. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/1024(1K) cycles of burst refresh must be executed
within 64ms/16ms before and after self refresh, in order to meet refresh specification.
20.
For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately
before and after self refresh in order to meet refresh specification.
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
WORD READ CYCLE
tRC
tRAS
tR P
VIH -
RAS
VIL -
tCSH
tCSH
tCRP
tCRP
tRCD
tRCD
tRSH
tCAS
VIH -
UCAS
VIL -
tCRP
tCRP
tRSH
VIH -
LCAS
tCAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDRESS
A
W
tRCH
tRRH
VIH -
VIL -
tAA
VIH -
VIL -
OE
tOEA
tCAC
tOFF
tOFF
tCLZ
DQ0 ~ DQ7
tOEZ
DATA-OUT
tRAC
tRAC
VOH -
OPEN
VOL -
tCAC
tCLZ
DQ8 ~ DQ15
tOEZ
DATA-OUT
VOH -
OPEN
VOL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
LOWER BYTE READ CYCLE
NOTE : DIN = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCRP
tRPC
VIH -
UCAS
VIL -
tCSH
tCRP
tRCD
tASC
tRCS
tRSH
VIH -
tCAS
LCAS
VIL -
tRAD
tRAL
tASR
tRAH
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
W
tRCH
tRRH
VIH -
VIL -
tOFF
tOEZ
tAA
VIH -
VIL -
OE
tOEA
tCAC
tCLZ
DQ0 ~ DQ7
tRAC
VOH -
OPEN
DATA-OUT
VOL -
DQ8 ~ DQ15
VOH -
OPEN
VOL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
UPPER BYTE READ CYCLE
NOTE : DIN = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
UCAS
VIL -
tRPC
tCRP
VIH -
LCAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
W
tRCH
tRCS
tRRH
VIH -
VIL -
tOFF
tOEZ
tAA
VIH -
VIL -
OE
tOEA
DQ0 ~ DQ7
VOH -
OPEN
VOL -
tCAC
tCLZ
DQ8 ~ DQ15
tRAC
VOH -
DATA-OUT
OPEN
VOL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
WORD WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
UCAS
VIL -
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
LCAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
W
tWCS
tWCH
VIH -
VIL -
tW P
VIH -
VIL -
OE
tDS
tDS
DQ0 ~ DQ7
VIH -
tDH
DATA-IN
VIL -
tDH
DATA-IN
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
VIL -
RAS
UCAS
LCAS
tCRP
tCRP
tRPC
VIH -
VIL -
tCSH
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDRESS
A
W
tWCS
tWCH
VIH -
VIL -
tW P
VIH -
VIL -
OE
tDS
DQ0 ~ DQ7
VIH -
tDH
DATA-IN
VIL -
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tR P
VIH -
VIL -
RAS
UCAS
LCAS
tCSH
tCRP
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
tRPC
VIH -
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tWCS
tWCH
VIH -
VIL -
W
tWP
VIH -
VIL -
OE
DQ0 ~ DQ7
VIH -
VIL -
tDS
tDH
DATA-IN
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
WORD WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
UCAS
LCAS
VIL -
tCSH
tCRP
tCRP
tRCD
tASC
tRSH
VIH -
VIL -
tCAS
tRAD
tRAL
tASR
tRAH
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
W
tCWL
tRWL
VIH -
VIL -
tWP
VIH -
VIL -
OE
tOEH
tOED
tDS
tDS
DQ0 ~ DQ7
VIH -
tDH
DATA-IN
VIL -
tDH
DATA-IN
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tR P
VIH -
RAS
VIL -
tCRP
tRPC
VIH -
UCAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
LCAS
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tCWL
tRWL
VIH -
VIL -
tWP
W
VIH -
VIL -
tOEH
OE
tOED
tDS
tDH
DATA-IN
DQ0 ~ DQ7
VIH -
VIL -
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
UCAS
LCAS
tCRP
tRPC
VIH -
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tCWL
tRWL
VIH -
VIL -
W
tWP
VIH -
VIL -
tOEH
OE
tOED
DQ0 ~ DQ7
VIH -
VIL -
tDS
tDH
DATA-IN
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
WORD READ - MODIFY - WRITE CYCLE
tRWC
tRAS
tR P
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
VIH -
tCAS
tCAS
UCAS
VIL -
tCRP
tRCD
tRSH
tCSH
VIH -
LCAS
VIL -
tRAD
tRAH
tASR
tASC
tCAH
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
A
tRWL
tAWD
tCWL
tWP
tCWD
VIH -
VIL -
W
tRWD
tOEA
VIH -
VIL -
OE
tCLZ
tCAC
tOED
tOEZ
tAA
tDS
tDH
DQ0 ~ DQ7
tRAC
VI/OH -
VI/OL -
VALID
VALID
DATA-IN
DATA-OUT
tCLZ
tCAC
tOED
tOEZ
tAA
tDS
tDH
DQ8 ~ DQ15
tRAC
VI/OH -
VALID
VALID
DATA-OUT
DATA-IN
VI/OL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
LOWER-BYTE READ - MODIFY - WRITE CYCLE
tRWC
tRAS
tR P
VIH -
RAS
VIL -
tRPC
tCRP
VIH -
UCAS
VIL -
tCRP
tRCD
tRSH
VIH -
tCAS
LCAS
VIL -
tRAD
tRAH
tCSH
tASR
tASC
tCAH
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
A
tRWL
tCWL
tWP
tAWD
tCWD
VIH -
VIL -
W
tRWD
tOEA
VIH -
VIL -
OE
tCLZ
tCAC
tOED
tOEZ
tAA
tD S
tDH
DQ0 ~ DQ7
tRAC
VI/OH -
VI/OL -
VALID
VALID
DATA-IN
DATA-OUT
DQ8 ~ DQ15
VI/OH -
OPEN
VI/OL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
UPPER-BYTE READ - MODIFY - WRITE CYCLE
tRWC
tR P
tRAS
VIH -
VIL -
RAS
UCAS
LCAS
tCRP
tCRP
tRCD
tRSH
VIH -
VIL -
tCAS
tRPC
VIH -
VIL -
tRAD
tRAH
tCSH
tASR
tASC
tCAH
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
A
tRWL
tAWD
tCWL
tWP
tCWD
VIH -
VIL -
W
tRWD
tOEA
VIH -
VIL -
OE
DQ0 ~ DQ7
VI/OH -
VI/OL -
OPEN
tCLZ
tCAC
tOED
tAA
tDS
tDH
DQ8 ~ DQ15
tRAC
tOEZ
VI/OH -
VALID
DATA-OUT
VALID
DATA-IN
VI/OL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
FAST PAGE MODE WORD READ CYCLE
tRP
tRASP
¡ó
VIH -
RAS
VIL -
tRHCP
tCAS
tCSH
tPC
tPC
tPC
tCAS
tCRP
tC P
tC P
tC P
tRPC
tRPC
tRCD
tCAS
tCAS
VIH -
VIL -
UCAS
tRAL
tCAS
tCRP
tASR
tC P
tCP
tC P
tRCD
tCAS
tCAH
tCAS
tCAH
tCAS
tCAH
VIH -
VIL -
LCAS
tRAD
tRAH tASC
tASC
tASC
tASC
tCAH
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
COLUMN
COLUMN
ADDR
COLUMN
ADDRESS
A
ADDRESS
tRCS
tRCH
tRCS
tRCH
tRCS
tRRH
tRCH
tRCS
tRCH
VIH -
VIL -
W
tCAC
tCAC
tCAC
tAA
tAA
tAA
tCPA
tOEA
tAA
tOEA
tCPA
tCPA
tOEA
tOEA
VIH -
VIL -
OE
tCAC
tRAC
tOFF
tOEZ
tOFF
tOEZ
tOFF
tOEZ
tOFF
tOEZ
DQ0 ~ DQ7
VOH -
VALID
VALID
VALID
VALID
DATA-OUT
DATA-OUT
DATA-OUT
VOL -
DATA-OUT
tCLZ
tCAC
tOFF
tOEZ
tOFF
tOEZ
tOFF
tOEZ
tOFF
tOEZ
DQ8 ~ DQ15
VOH -
tRAC
VALID
VALID
VALID
VALID
VOL -
DATA-OUT
DATA-OUT
DATA-OUT
DATA-OUT
tCLZ
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
FAST PAGE MODE LOWER BYTE READ CYCLE
tRASP
tR P
VIH -
VIL -
RAS
¡ó
tRHCP
tCRP
tRPC
tRPC
VIH -
VIL -
UCAS
tRAL
tCSH
tPC
tCAS
tPC
tCAS
tPC
tCAS
tCRP
tASR
tCP
tCP
tC P
tRCD
tCAS
tCAH
VIH -
VIL -
LCAS
tRAD
tRAH
tASC tCAH
tASC tCAH
tASC
tCAH
tASC
VIH -
VIL -
ROW
ADDR
COLUMN
COLUMN
COLUMN
ADDR
COLUMN
A
ADDRESS
ADDRESS
ADDRESS
tRCS
tRCS
tRCH
tRCS
tRRH
tRCH
tRCS
tRCH
tRCH
VIH -
VIL -
W
tCAC
tCAC
tCAC
tAA
tCPA
tOEA
tAA
tAA
tAA
tOEA
tCPA
tOEA
tCPA
tOEA
VIH -
VIL -
OE
tCAC
tRAC
tOFF
tOEZ
tOFF
tOEZ
tOFF
tOEZ
tOFF
tOEZ
DQ0 ~ DQ7
VOH -
VALID
DATA-OUT
VALID
VALID
VALID
DATA-OUT
DATA-OUT
DATA-OUT
VOL -
tCLZ
DQ8 ~ DQ15
VOH -
OPEN
VOL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
FAST PAGE MODE UPPER BYTE READ CYCLE
tR P
tRASP
VIH -
VIL -
RAS
¡ó
tCSH
tRHCP
tCAS
tPC
tCAS
tPC
tCAS
tPC
tCAS
tCRP
tCP
tCP
tC P
tRCD
tRPC
tRPC
VIH -
VIL -
UCAS
tCRP
tASR
VIH -
VIL -
LCAS
tRAL
tCAH
tRAD
tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH
tASC
VIH -
VIL -
ROW
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDR
COLUMN
A
ADDRESS
tRCS
ADDR
tRCS
tRCS
tRCH
tRRH
tRCH
tRCS
tRCH
tRCH
VIH -
VIL -
W
tCAC
tCAC
tCAC
tAA
tAA
tAA
tCPA
tOEA
tAA
tOEA
tCPA
tCPA
tOEA
tOEA
VIH -
VIL -
OE
DQ0 ~ DQ7
VOH -
OPEN
VOL -
tCAC
tOFF
tOEZ
tOFF
tOEZ
tOFF
tOEZ
tOFF
tOEZ
tRAC
DQ8 ~ DQ15
VOH -
VALID
DATA-OUT
VALID
VALID
DATA-OUT
VALID
DATA-OUT
DATA-OUT
VOL -
tCLZ
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
FAST PAGE MODE WORD WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRASP
tRP
VIH -
RAS
tRHCP
VIL -
¡ó
tPC
tPC
tPC
tPC
tRSH
tCRP
tRCD
tRCD
tC P
tCP
tCRP
VIH -
VIL -
tCAS
tCAS
tCAS
¡ó
tCAS
UCAS
LCAS
tRSH
tCRP
tC P
tC P
VIH -
VIL -
tCAS
¡ó
tCAS
tRAD
tRAL
tCAH
tCSH
tASC
tASR
tRAH
tCAH
tASC
tCAH
COLUMN
tASC
¡ó
¡ó
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
A
ADDRESS
tWCS
tWP
tWCH
tWCS
tWCH
tW P
tWCS
tWCH
tWP
¡ó
VIH -
VIL -
W
¡ó
¡ó
VIH -
VIL -
OE
tDS
tDS
tDH
tD S
tDH
tDS
tDH
DQ0 ~ DQ7
¡ó
VIH -
VALID
DATA-IN
VALID
VALID
DATA-IN
DATA-IN
VIL -
¡ó
tDH
tD S
tDH
tDS
tDH
DQ8 ~ DQ15
¡ó
¡ó
VIH -
VALID
VALID
VALID
DATA-IN
DATA-IN
DATA-IN
VIL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
FAST PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRASP
tRP
VIH -
tRHCP
RAS
VIL -
¡ó
tRPC
tCRP
¡ó
VIH -
UCAS
VIL -
tPC
tPC
tRSH
tCRP
tRCD
tCP
tCP
VIH -
VIL -
tCAS
tCAS
¡ó
tCAS
LCAS
tRAD
tRAL
tCAH
tCSH
tASC
tASR
tRAH
tCAH
tASC
tCAH
tASC
¡ó
¡ó
VIH -
VIL -
ROW
ADDR
COLUMN
COLUMN
COLUMN
ADDRESS
A
ADDRESS
ADDRESS
tWCS
tWP
tWCH
tWCS
tWCH
tWP
tWCS
tWCH
tW P
¡ó
VIH -
VIL -
W
¡ó
¡ó
VIH -
VIL -
OE
tDS
tDH
tDS
tDH
tDS
tDH
DQ0 ~ DQ7
¡ó
¡ó
VIH -
VIL -
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
FAST PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRASP
tRP
VIH -
tRHCP
RAS
VIL -
¡ó
tPC
tPC
tRSH
tCRP
tRCD
tCP
tCP
VIH -
VIL -
tCAS
tCAS
tCAS
UCAS
LCAS
¡ó
tRPC
tCRP
VIH -
VIL -
tRAD
tRAH
tRAL
tCAH
tCSH
tASC
tASR
tCAH
tASC
tCAH
tASC
¡ó
¡ó
VIH -
VIL -
ROW
ADDR.
COLUMN
COLUMN
COLUMN
ADDRESS
A
ADDRESS
ADDRESS
tWCS tWCH
tW P
tWCS
tWCH
tWP
tWCS
tWCH
tW P
¡ó
VIH -
VIL -
W
¡ó
¡ó
VIH -
VIL -
OE
DQ0 ~ DQ7
¡ó
¡ó
VIH -
VIL -
tDS
tDH
tDS
tDH
tDS
tDH
DQ8 ~ DQ15
¡ó
¡ó
VIH -
VIL -
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
FAST PAGE MODE WORD READ-MODIFY-WRITE CYCLE
tR P
tRASP
VIH -
VIL -
tCSH
RAS
tPRWC
tRSH
tCRP
tCRP
tCRP
tCRP
tRCD
tRCD
tC P
tC P
VIH -
VIL -
tCAS
tCAS
UCAS
LCAS
VIH -
VIL -
tCAS
tRAL
tCAS
tRAD
tRAH
tCAH
tCAH
tASR
tASC
tASC
VIH -
VIL -
ROW
ADDR
COL.
COL.
A
W
ADDR
ADDR
tRWL
tCWL
tRCS
tCWL
tRCS
VIH -
VIL -
tWP
tW P
tCWD
tAWD
tRWD
tCWD
tAWD
tCPWD
VIH -
VIL -
tOEA
tOEA
OE
tOED
tOED
tCAC
tAA
tCAC
tAA
tDH
tDH
tDS
tOEZ
tD S
DQ0 ~ DQ7
tRAC
tOEZ
VI/OH -
VI/OL -
tCLZ
tCLZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
tOED
tOED
tCAC
tAA
tCAC
tAA
tDH
tDH
tDS
tOEZ
tD S
DQ8 ~ DQ15
tRAC
tCLZ
tOEZ
VI/OH -
VI/OL -
tCLZ
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-OUT
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
FAST PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE
tR P
tRASP
VIH -
VIL -
tCSH
RAS
tCRP
tCRP
tRPC
VIH -
VIL -
UCAS
LCAS
tPRWC
tCAS
tRSH
tCAS
tCRP
tRCD
tCP
VIH -
VIL -
tRAD
tRAH
tRAL
tCAH
tCAH
tASR
tASC
tASC
VIH -
VIL -
ROW
ADDR
COL.
ADDR
COL.
A
ADDR
tRWL
tCWL
tRCS
tCWL
tRCS
VIH -
VIL -
tWP
tW P
W
tCWD
tAWD
tRWD
tCWD
tAWD
tCPWD
VIH -
VIL -
tOEA
tOEA
OE
tOED
tOED
tCAC
tAA
tCAC
tAA
tDH
tDH
tDS
tOEZ
tD S
DQ0 ~ DQ7
tRAC
tOEZ
VI/OH -
VI/OL -
tCLZ
tCLZ
VALID
DATA-OUT
VALID
VALID
DATA-OUT
VALID
DATA-IN
DATA-IN
DQ8 ~ DQ15
VI/OH -
OPEN
VI/OL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
FAST PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE
tRP
tRASP
VIH -
VIL -
tCSH
RAS
tCRP
tCRP
tPRWC
tRSH
tCAS
tCRP
tRCD
tC P
VIH -
VIL -
tCAS
UCAS
LCAS
tRPC
VIH -
VIL -
tRAD
tRAH
tRAL
tCAH
tASR
tCAH
tASC
tASC
VIH -
VIL -
ROW
ADDR
COL.
COL.
A
W
ADDR
ADDR
tRWL
tCWL
tRCS
tCWL
tRCS
VIH -
VIL -
tWP
tWP
tCWD
tAWD
tRWD
tCWD
tAWD
tCPWD
VIH -
VIL -
tOEA
tOEA
OE
DQ0 ~ DQ7
VI/OH -
OPEN
VI/OL -
tOED
tOED
tCAC
tAA
tCAC
tAA
tDH
tDH
tOEZ
tOEZ
tDS
tD S
DQ8 ~ DQ15
tRAC
VI/OH -
VI/OL -
tCLZ
tCLZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
RAS - ONLY REFRESH CYCLE
NOTE : W, OE , DIN = Don¢t care
DOUT = OPEN
tRC
tRP
VIH -
RAS
VIL -
tRAS
tRPC
tCRP
VIH -
UCAS
VIL -
tCRP
VIH -
LCAS
VIL -
tASR
tRAH
VIH -
VIL -
ROW
ADDR
A
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tCRP
tCP
tRPC
tCSR
tCSR
VIH -
VIL -
tCHR
tCHR
UCAS
LCAS
tCP
VIH -
VIL -
DQ0 ~ DQ7
tOFF
VOH -
OPEN
VOL -
DQ8 ~ DQ15
VOH -
OPEN
VOL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
HIDDEN REFRESH CYCLE ( READ )
tRC
tRC
tRAS
tRP
tRP
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tRSH
tCHR
VIH -
UCAS
VIL -
tCRP
tRCD
tCHR
VIH -
LCAS
VIL -
tRAD
tRAL
tCAH
tASR
tRAH
tASC
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
W
tWRH
tRCS
VIH -
VIL -
tAA
VIH -
VIL -
tOEA
OE
tOFF
tCAC
tCLZ
tRAC
DQ0 ~ DQ7
tOEZ
DATA-OUT
VOH -
OPEN
VOL -
DQ8 ~ DQ15
VOH -
DATA-OUT
OPEN
VOL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
tRC
tR P
tR P
tRAS
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tCHR
tRSH
tRSH
VIH -
UCAS
VIL -
tCRP
tRCD
tCHR
VIH -
LCAS
VIL -
tRAD
tRAL
tCAH
COLUMN
tASR
tRAH
tASC
VIH -
VIL -
ROW
ADDRESS
A
W
ADDRESS
tWRH
tWRP
tWCS
tWCH
VIH -
VIL -
tWP
VIH -
VIL -
OE
tDS
tD S
tDH
tDH
DQ0 ~ DQ7
VIH -
DATA-IN
VIL -
DQ8 ~ DQ15
VIH -
DATA-IN
VIL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE , A = Don¢t care
tRP
tRASS
tRPS
VIH -
RAS
VIL -
tRPC
tC P
tRPC
tCHS
tCHS
tCSR
VIH -
UCAS
VIL -
tC P
tCSR
VIH -
VIL -
LCAS
DQ0 ~ DQ7
tOFF
VOH -
OPEN
OPEN
VOL -
DQ8 ~ DQ15
VOH -
VOL -
tWRP
tWRH
VIH -
VIL -
W
TEST MODE IN CYCLE
NOTE : OE , A = Don¢t care
tRC
tR P
tRP
VIH -
RAS
VIL -
tRAS
tCRP
tRPC
tCP
tCSR
tCSR
VIH -
VIL -
tCHR
tCHR
UCAS
LCAS
tCP
VIH -
VIL -
tWTS
VIH -
VIL -
tWTH
W
tOFF
DQ0 ~ DQ15
VOH -
OPEN
VOL -
Don¢t care
Undefined
K4F171611D, K4F151611D
K4F171612D, K4F151612D
CMOS DRAM
PACKAGE DIMENSION
42 SOJ 400mil
Units : Inches (millimeters)
#42
0.006 (0.15)
0.012 (0.30)
#1
0.027 (0.69)
MIN
1.091 (27.71)
MAX
1.070 (27.19)
1.080 (27.43)
0.0375 (0.95)
0.050 (1.27)
0.026 (0.66)
0.032 (0.81)
0.015 (0.38)
0.021 (0.53)
50(44) TSOP(II) 400mil
Units : Inches (millimeters)
0.004 (0.10)
0.010 (0.25)
0.841 (21.35)
MAX
0.821 (20.85)
0.829 (21.05)
0.047 (1.20)
MAX
0.010 (0.25)
TYP
0.034 (0.875)
0.0315 (0.80)
0.002 (0.05)
MIN
0.010 (0.25)
0.018 (0.45)
0~8 O
0.018 (0.45)
0.030 (0.75)
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