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K4F660812C-JC45 [SAMSUNG]

Fast Page DRAM, 8MX8, 45ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32;
K4F660812C-JC45
型号： K4F660812C-JC45
厂家： SAMSUNG    SAMSUNG
描述：

Fast Page DRAM, 8MX8, 45ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32

动态存储器 光电二极管
文件： 总20页 (文件大小：368K)
中文：  中文翻译
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K4F660812C,K4F640812C  
CMOS DRAM  
8M x 8bit CMOS Dynamic RAM with Fast Page Mode  
DESCRIPTION  
This is a family of 8,388,608 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells  
within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power) are  
optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Fur-  
thermore, Self-refresh operation is available in L-version. This 8Mx8 Fast Page Mode DRAM family is fabricated using Samsung¢s  
advanced CMOS process to realize high band-width, low power consumption and high reliability.  
FEATURES  
• Fast Page Mode operation  
• Part Identification  
- K4F660812C-JC/L(3.3V, 8K Ref., SOJ)  
- K4F640812C-JC/L(3.3V, 4K Ref., SOJ)  
- K4F660812C-TC/L(3.3V, 8K Ref., TSOP)  
- K4F640812C-TC/L(3.3V, 4K Ref., TSOP)  
• CAS-before-RAS refresh capability  
• RAS-only and Hidden refresh capability  
• Self-refresh capability (L-ver only)  
• Fast parallel test mode capability  
• LVTTL(3.3V) compatible inputs and outputs  
• Early Write or output enable controlled write  
• JEDEC Standard pinout  
• Active Power Dissipation  
Unit : mW  
4K  
• Available in Plastic SOJ and TSOP(II) packages  
• +3.3V±0.3V power supply  
Speed  
-45  
8K  
324  
288  
252  
432  
396  
360  
-50  
-60  
• Refresh Cycles  
FUNCTIONAL BLOCK DIAGRAM  
Part  
NO.  
Refresh  
cycle  
Refresh time  
Normal  
64ms  
L-ver  
K4F660812C*  
K4F640812C  
8K  
4K  
RAS  
CAS  
W
Vcc  
Vss  
128ms  
Control  
Clocks  
VBB Generator  
* Access mode & RAS only refresh mode  
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)  
CAS-before-RAS & Hidden refresh mode  
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)  
Row Decoder  
Refresh Timer  
Refresh Control  
Data in  
Buffer  
Memory Array  
8,388,608 x 8  
Cells  
DQ0  
to  
DQ7  
Refresh Counter  
Row Address Buffer  
Col. Address Buffer  
• Performance Range  
Speed  
Data out  
Buffer  
tRAC  
45ns  
50ns  
60ns  
tCAC  
12ns  
13ns  
15ns  
tRC  
tPC  
A0~A12  
(A0~A11)*1  
OE  
-45  
-50  
-60  
80ns  
90ns  
110ns  
31ns  
35ns  
40ns  
A0~A9  
(A0~A10)*1  
Column Decoder  
Note) *1 : 4K Refresh  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  
K4F660812C,K4F640812C  
CMOS DRAM  
PIN CONFIGURATION (Top Views)  
• K4F660812C-T  
• K4F640812C-T  
• K4F660812C-J  
• K4F640812C-J  
VCC  
DQ0  
DQ1  
DQ2  
DQ3  
N.C  
VCC  
W
1
2
3
4
5
6
7
8
9
32 VSS  
VCC  
DQ0  
DQ1  
DQ2  
DQ3  
N.C  
VCC  
W
RAS  
A0  
A1  
A2  
A3  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
VSS  
31 DQ7  
30 DQ6  
29 DQ5  
28 DQ4  
27 VSS  
26 CAS  
25 OE  
24 A12(N.C)*  
23 A11  
22 A10  
21 A9  
DQ7  
DQ6  
DQ5  
DQ4  
VSS  
CAS  
OE  
A12(N.C)*  
A11  
A10  
A9  
RAS  
9
A0 10  
A1 11  
A2 12  
A3 13  
A4 14  
A5 15  
VCC 16  
10  
11  
12  
13  
14  
15  
16  
20 A8  
19 A7  
18 A6  
17 VSS  
A8  
A7  
A6  
VSS  
A4  
A5  
VCC  
(J : 400mil SOJ)  
(T : 400mil TSOP(II))  
* (N.C) : N.C for 4K Refresh product  
Pin Name  
A0 - A12  
A0 - A11  
DQ0 - 7  
VSS  
Pin Function  
Address Inputs(8K Product)  
Address Inputs(4K Product)  
Data In/Out  
Ground  
RAS  
Row Address Strobe  
Column Address Strobe  
Read/Write Input  
Data Output Enable  
Power(+3.3V)  
CAS  
W
OE  
VCC  
N.C  
No Connection  
K4F660812C,K4F640812C  
CMOS DRAM  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Symbol  
VIN,VOUT  
VCC  
Rating  
-0.5 to +4.6  
-0.5 to +4.6  
-55 to +150  
1
Units  
V
Voltage on any pin relative to VSS  
Voltage on VCC supply relative to VSS  
Storage Temperature  
V
Tstg  
°C  
W
Power Dissipation  
PD  
Short Circuit Output Current  
IOS Address  
50  
mA  
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to  
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended  
periods may affect device reliability.  
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)  
Parameter  
Supply Voltage  
Symbol  
VCC  
VSS  
Min  
3.0  
0
Typ  
Max  
3.6  
0
Units  
3.3  
V
V
V
V
Ground  
0
-
*1  
Input High Voltage  
Input Low Voltage  
VIH  
2.0  
Vcc+0.3  
0.8  
*2  
VIL  
-
-0.3  
*1 : Vcc+1.3V at pulse width£15ns which is measured at VCC  
*2 : -1.3 at pulse width£15ns which is measured at VSS  
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)  
Parameter  
Symbol  
Min  
Max  
Units  
Input Leakage Current (Any input 0£VIN£VCC+0.3V,  
all other pins not under test=0 Volt)  
II(L)  
-5  
5
uA  
Output Leakage Current  
(Data out is disabled, 0V£VOUT£VCC)  
IO(L)  
-5  
5
uA  
Output High Voltage Level(IOH=-2mA)  
Output Low Voltage Level(IOL=2mA)  
VOH  
VOL  
2.4  
-
-
V
V
0.4  
K4F660812C,K4F640812C  
CMOS DRAM  
DC AND OPERATING CHARACTERISTICS (Continued)  
Max  
Symbol  
Power  
Speed  
Units  
K4F660812C  
K4F640812C  
-45  
-50  
-60  
90  
80  
70  
120  
110  
100  
mA  
mA  
mA  
ICC1  
Don¢t care  
Normal  
L
1
1
1
1
mA  
mA  
ICC2  
ICC3  
Don¢t care  
-45  
-50  
-60  
90  
80  
70  
120  
110  
100  
mA  
mA  
mA  
Don¢t care  
Don¢t care  
-45  
-50  
-60  
70  
60  
50  
70  
60  
50  
mA  
mA  
mA  
ICC4  
ICC5  
ICC6  
Normal  
L
0.5  
200  
0.5  
200  
mA  
uA  
Don¢t care  
-45  
-50  
-60  
120  
110  
100  
120  
110  
100  
mA  
mA  
mA  
Don¢t care  
ICC7  
ICCS  
L
L
Don¢t care  
Don¢t care  
350  
350  
350  
350  
uA  
uA  
ICC1* : Operating Current (RAS and CAS, Address cycling @tRC=min.)  
ICC2 : Standby Current (RAS=CAS=W=VIH)  
ICC3* : RAS-only Refresh Current (CAS=VIH, RAS, Address cycling @tRC=min.)  
ICC4* : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @tPC=min.)  
ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)  
ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min)  
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode  
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=CAS-before-RAS cycling or 0.2V,  
W, OE=VIH, Address=Don¢t care, DQ=Open, TRC=31.25us  
ICCS : Self Refresh Current  
RAS=CAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ7=VCC-0.2V, 0.2V or Open  
*Note :  
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.  
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4,  
address can be changed maximum once within one fast page mode cycle time, tPC.  
K4F660812C,K4F640812C  
CMOS DRAM  
CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz)  
Parameter  
Input capacitance [A0 ~ A12]  
Symbol  
CIN1  
Min  
Max  
Units  
pF  
-
-
-
5
7
7
Input capacitance [RAS, CAS, W, OE]  
Output capacitance [DQ0 - DQ7]  
CIN2  
pF  
CDQ  
pF  
AC CHARACTERISTICS (0°C£TA£70°C, See note 2)  
Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V  
-45  
-50  
-60  
Parameter  
Symbol  
Units  
Note  
Min  
80  
Max  
Min  
Max  
Min  
110  
153  
Max  
Random read or write cycle time  
Read-modify-write cycle time  
Access time from RAS  
90  
tRC  
ns  
ns  
115  
133  
tRWC  
tRAC  
tCAC  
tAA  
45  
12  
23  
50  
13  
25  
60  
15  
30  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
3,4,10  
3,4,5  
3,10  
3
Access time from CAS  
Access time from column address  
CAS to output in Low-Z  
0
0
0
0
0
tCLZ  
tOFF  
tT  
Output buffer turn-off delay  
Transition time (rise and fall)  
RAS precharge time  
13  
50  
13  
50  
0
13  
50  
6
1
1
1
2
25  
45  
12  
45  
12  
18  
13  
5
30  
50  
13  
50  
13  
20  
15  
5
40  
60  
15  
60  
15  
20  
15  
5
tRP  
RAS pulse width  
10K  
10K  
10K  
tRAS  
tRSH  
tCSH  
tCAS  
tRCD  
tRAD  
tCRP  
tASR  
tRAH  
tASC  
tCAH  
tRAL  
tRCS  
tRCH  
tRRH  
tWCH  
tWP  
RAS hold time  
CAS hold time  
CAS pulse width  
10K  
33  
10K  
37  
10K  
45  
RAS to CAS delay time  
4
RAS to column address delay time  
CAS to RAS precharge time  
Row address set-up time  
Row address hold time  
22  
25  
30  
10  
0
0
0
8
10  
0
10  
0
Column address set-up time  
Column address hold time  
Column address to RAS lead time  
Read command set-up time  
Read command hold time referenced to CAS  
Read command hold time referenced to RAS  
Write command hold time  
Write command pulse width  
Write command to RAS lead time  
Write command to CAS lead time  
Data set-up time  
0
8
10  
25  
0
10  
30  
0
23  
0
0
0
0
8
8
0
0
0
8
10  
10  
15  
13  
0
10  
10  
15  
15  
0
8
13  
12  
0
tRWL  
tCWL  
tDS  
9
9
Data hold time  
10  
10  
10  
tDH  
K4F660812C,K4F640812C  
CMOS DRAM  
AC CHARACTERISTICS (Continued)  
-45  
-50  
-60  
Parameter  
Symbol  
Units  
Note  
Min  
Max  
64  
Min  
Max  
64  
Min  
Max  
64  
Refresh period (Normal)  
ms  
ms  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
us  
ns  
ns  
tREF  
Refresh period (L-ver)  
128  
128  
128  
tREF  
Write command set-up time  
0
0
0
7
7
7
7
tWCS  
tCWD  
tRWD  
tAWD  
tCPWD  
tCSR  
tCHR  
tRPC  
tCPA  
tPC  
CAS to W delay time  
32  
67  
43  
48  
5
36  
73  
48  
53  
5
38  
83  
53  
60  
5
RAS to W delay time  
Column address to W delay time  
CAS precharge W delay time  
CAS set-up time (CAS -before-RAS refresh)  
CAS hold time (CAS -before-RAS refresh)  
RAS to CAS precharge time  
10  
5
10  
5
10  
5
Access time from CAS precharge  
Fast Page mode cycle time  
26  
30  
35  
3
31  
70  
9
35  
76  
10  
50  
30  
40  
85  
10  
60  
35  
Fast Page mode read-modify-write cycle time  
CAS precharge time (Fast page cycle)  
RAS pulse width (Fast page cycle)  
RAS hold time from CAS precharge  
OE access time  
tPRWC  
tCP  
45  
28  
200K  
12  
200K  
13  
200K  
15  
tRASP  
tRHCP  
tOEA  
tOED  
tOEZ  
tOEH  
tWTS  
tWTH  
tWRP  
tWRH  
tRASS  
tRPS  
tCHS  
3
6
OE to data delay  
12  
0
13  
0
13  
0
Output buffer turn off delay time from OE  
OE command hold time  
13  
13  
13  
12  
10  
15  
10  
10  
100  
80  
-50  
13  
10  
15  
10  
10  
100  
90  
-50  
15  
Write command set-up time (Test mode in)  
Write command hold time (Test mode in)  
W to RAS precharge time (C-B-R refresh)  
W to RAS hold time (C-B-R refresh)  
RAS pulse width (C-B-R self refresh)  
RAS precharge time (C-B-R self refresh)  
CAS hold time (C-B-R self refresh)  
10  
11  
11  
15  
10  
10  
100  
110  
-50  
13,14,15  
13,14,15  
13,14,15  
K4F660812C,K4F640812C  
TEST MODE CYCLE  
Parameter  
CMOS DRAM  
( Note 11 )  
-45  
-50  
-60  
Symbol  
Units  
Note  
Min  
85  
Max  
Min  
95  
Max  
Min  
115  
160  
Max  
Random read or write cycle time  
Read-modify-write cycle time  
Access time from RAS  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tRC  
120  
138  
tRWC  
tRAC  
tCAC  
tAA  
50  
17  
55  
18  
65  
20  
3,4,10,12  
3,4,5,12  
3,10,12  
Access time from CAS  
Access time from column address  
RAS pulse width  
28  
30  
35  
50  
17  
17  
50  
28  
37  
72  
48  
36  
75  
50  
10K  
10K  
55  
18  
18  
55  
30  
41  
78  
53  
40  
81  
55  
10K  
10K  
65  
20  
20  
65  
35  
43  
88  
58  
45  
90  
65  
10K  
10K  
tRAS  
tCAS  
tRSH  
tCSH  
tRAL  
tCWD  
tRWD  
tAWD  
tPC  
CAS pulse width  
RAS hold time  
CAS hold time  
Column Address to RAS lead time  
CAS to W delay time  
7
7
7
RAS to W delay time  
Column Address to W delay time  
Fast Page mode cycle time  
Fast Page mode read-modify-write cycle time  
RAS pulse width (Fast page cycle)  
Access time from CAS precharge  
OE access time  
tPRWC  
tRASP  
tCPA  
tOEA  
tOED  
tOEH  
200K  
31  
200K  
35  
200K  
40  
3
3
17  
18  
20  
OE to data delay  
17  
17  
18  
18  
18  
20  
OE command hold time  
K4F660812C,K4F640812C  
CMOS DRAM  
NOTES  
1. An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is  
achieved.  
VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between  
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.  
2.  
3.  
4.  
Measured with a load equivalent to 1 TTL load and 100pF.  
Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.  
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.  
Assumes that tRCD³ tRCD(max).  
5.  
6. tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced Voh  
or Vol.  
7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric charac-  
teristics only. If tWCS³ tWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the  
duration of the cycle. If tCWD³ tCWD(min), tRWD³ tRWD(min) and tAWD³ tAWD(min), then the cycle is a read-modify-write cycle  
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the  
condition of the data out is indeterminate.  
Either tRCH or tRRH must be satisfied for a read cycle.  
8.  
9.  
This parameters are referenced to the CAS falling edge in early write cycles and to the W falling edge in read-modify-write  
cycles.  
10.  
11.  
Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.  
If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.  
These specifications are applied in the test mode.  
12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters  
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.  
13.  
14.  
If tRASS³ 100us, then RAS precharge time must use tRPS instead of tRP.  
For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed  
within 64ms before and after self refresh, in order to meet refresh specification.  
For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before  
and after self refresh in order to meet refresh specification.  
15.  
K4F660812C,K4F640812C  
CMOS DRAM  
READ CYCLE  
tRC  
tRAS  
tRP  
VIH -  
RAS  
VIL -  
tCSH  
tCRP  
tCRP  
tRCD  
tRSH  
tCAS  
VIH -  
CAS  
VIL -  
tRAD  
tRAL  
tASR  
tRAH  
tASC  
tRCS  
tCAH  
VIH -  
VIL -  
ROW  
ADDRESS  
COLUMN  
ADDRESS  
A
W
tRCH  
tRRH  
VIH -  
VIL -  
tOFF  
tOEZ  
tAA  
VIH -  
VIL -  
tOEA  
OE  
tCAC  
tCLZ  
DQ0 ~ DQ3(7)  
VOH -  
VOL -  
tRAC  
OPEN  
DATA-OUT  
Don¢t care  
Undefined  
K4F660812C,K4F640812C  
CMOS DRAM  
WRITE CYCLE ( EARLY WRITE )  
NOTE : DOUT = OPEN  
tRC  
tRAS  
tRP  
VIH -  
RAS  
VIL -  
tCSH  
tCRP  
tCRP  
tRCD  
tRSH  
tCAS  
VIH -  
CAS  
VIL -  
tRAD  
tRAL  
tASR  
tRAH  
tASC  
tCAH  
VIH -  
VIL -  
ROW  
ADDRESS  
COLUMN  
ADDRESS  
A
tCWL  
tRWL  
tWCS  
tWCH  
tWP  
VIH -  
VIL -  
W
VIH -  
VIL -  
OE  
DQ0 ~ DQ3(7)  
VIH -  
tDS  
tDH  
DATA-IN  
VIL -  
Don¢t care  
Undefined  
K4F660812C,K4F640812C  
CMOS DRAM  
WRITE CYCLE ( OE CONTROLLED WRITE )  
NOTE : DOUT = OPEN  
tRC  
tRAS  
tRP  
VIH -  
RAS  
VIL -  
tCSH  
tCRP  
tCRP  
tRCD  
tRSH  
tCAS  
VIH -  
VIL -  
CAS  
tRAD  
tRAL  
tASR  
tRAH  
tASC  
tCAH  
COLUMN  
ADDRESS  
VIH -  
VIL -  
ROW  
ADDRESS  
A
W
tCWL  
tRWL  
VIH -  
VIL -  
tWP  
VIH -  
VIL -  
OE  
tOED  
tOEH  
tDS  
DQ0 ~ DQ3(7)  
VIH -  
tDH  
DATA-IN  
VIL -  
Don¢t care  
Undefined  
K4F660812C,K4F640812C  
CMOS DRAM  
READ - MODIFY - WRTIE CYCLE  
tRWC  
tRP  
tRAS  
VIH -  
RAS  
VIL -  
tCRP  
tRCD  
tRSH  
tCAS  
VIH -  
CAS  
VIL -  
tRAD  
tRAH  
tASR  
tASC  
tCAH  
tCSH  
VIH -  
VIL -  
COLUMN  
ADDRESS  
ROW  
ADDR  
A
tRWL  
tCWL  
tAWD  
tCWD  
VIH -  
VIL -  
tWP  
W
tRWD  
tOEA  
VIH -  
VIL -  
OE  
tCLZ  
tCAC  
tOED  
tAA  
tDS  
tDH  
DQ0 ~ DQ3(7)  
VI/OH -  
tOEZ  
tRAC  
VALID  
DATA-OUT  
VALID  
DATA-IN  
VI/OL -  
Don¢t care  
Undefined  
K4F660812C,K4F640812C  
CMOS DRAM  
FAST PAGE READ CYCLE  
tRP  
tRASP  
¡ó  
VIH -  
RAS  
tRHCP  
VIL -  
tPC  
tCRP  
tRCD  
tCP  
tCP  
tRSH  
tCAS  
tCAS  
¡ó  
VIH -  
CAS  
tCAS  
VIL -  
tRAD  
tASC  
tCSH  
tASR  
ROW  
tASC  
tCAH  
tASC  
tCAH  
tRAH  
tCAH  
tRCH  
¡ó  
¡ó  
VIH -  
VIL -  
COLUMN  
COLUMN  
ADDRESS  
COLUMN  
A
W
ADDR  
ADDRESS  
tRCS  
ADDRESS  
tRAL  
tRCS  
tRRH  
tRCS  
tRCH  
¡ó  
VIH -  
VIL -  
tCAC  
tOEA  
tCAC  
tOEA  
tCAC  
tOEA  
¡ó  
¡ó  
VIH -  
VIL -  
OE  
tAA  
tOFF  
tCLZ  
tAA  
tOFF  
tCLZ  
tAA  
tOFF  
tOEZ  
tRAC  
tCLZ  
DQ0 ~ DQ3(7)  
VOH -  
VOL -  
tOEZ  
VALID  
tOEZ  
VALID  
VALID  
DATA-OUT  
DATA-OUT  
DATA-OUT  
Don¢t care  
Undefined  
K4F660812C,K4F640812C  
CMOS DRAM  
FAST PAGE WRITE CYCLE ( EARLY WRITE )  
NOTE : DOUT = OPEN  
tRP  
tRASP  
¡ó  
VIH -  
RAS  
tRHCP  
VIL -  
tPC  
tPC  
tCRP  
tCP  
tRCD  
tCP  
tRSH  
tCAS  
tCAS  
¡ó  
VIH -  
VIL -  
tCAS  
CAS  
tRAD  
tASC  
tRAH  
ROW  
tRAL  
tCAH  
tCStHCAH  
tASC  
tCAH  
tASC  
tASR  
¡ó  
¡ó  
VIH -  
VIL -  
COLUMN  
ADDRESS  
COLUMN  
ADDRESS  
COLUMN  
A
ADDRESS  
ADDR  
tWCS  
tWCS  
tWCH  
tWP  
tWCS  
tWCH  
¡ó  
tWCH  
VIH -  
VIL -  
tWP  
tWP  
W
tCWL  
tCWL  
tRWL  
tCWL  
¡ó  
VIH -  
VIL -  
OE  
¡ó  
tDS  
tDH  
tDS  
tDH  
tDS  
tDH  
DQ0 ~ DQ3(7)  
VIH -  
VIL -  
¡ó  
¡ó  
VALID  
DATA-IN  
VALID  
DATA-IN  
VALID  
DATA-IN  
Don¢t care  
Undefined  
K4F660812C,K4F640812C  
CMOS DRAM  
FAST PAGE READ - MODIFY - WRITE CYCLE  
tRP  
tRASP  
tCP  
VIH -  
VIL -  
tCSH  
RAS  
CAS  
tRSH  
tCAS  
tRCD  
tRAD  
tCRP  
VIH -  
VIL -  
tCAS  
tPRWC  
tCAH  
tRAH  
tRAL  
tCAH  
tASR  
ROW  
tASC  
tASC  
VIH -  
VIL -  
COL.  
COL.  
ADDR  
A
ADDR  
ADDR  
tRWL  
tWP  
tRCS  
tCWL  
tCWL  
VIH -  
VIL -  
tWP  
W
tCWD  
tAWD  
tRWD  
tCWD  
tAWD  
tCPWD  
tOEA  
VIH -  
VIL -  
tOEA  
OE  
tOED  
tCAC  
tAA  
tOED  
tCAC  
tDH  
tDH  
tAA  
tDS  
tOEZ  
tDS  
DQ0 ~ DQ3(7)  
tOEZ  
tRAC  
VI/OH -  
VI/OL -  
tCLZ  
tCLZ  
VALID  
VALID  
DATA-IN  
VALID  
VALID  
DATA-OUT  
DATA-IN  
DATA-OUT  
Don¢t care  
Undefined  
K4F660812C,K4F640812C  
CMOS DRAM  
RAS - ONLY REFRESH CYCLE  
NOTE : W, OE, DIN = Don¢t care  
DOUT = OPEN  
tRC  
tRP  
tRAS  
VIH -  
RAS  
VIL -  
tRPC  
tCRP  
tCRP  
VIH -  
CAS  
VIL -  
tASR  
tRAH  
VIH -  
VIL -  
ROW  
ADDR  
A
CAS - BEFORE - RAS REFRESH CYCLE  
NOTE : OE, A = Don¢t care  
tRC  
tRP  
tRAS  
tRP  
VIH -  
RAS  
tRPC  
tCP  
VIL -  
tRPC  
VIH -  
VIL -  
tCSR  
tWRP  
CAS  
W
tCHR  
tWRH  
VIH -  
VIL -  
tOFF  
DQ0 ~ DQ3(7)  
VOH -  
VOL -  
OPEN  
Don¢t care  
Undefined  
K4F660812C,K4F640812C  
CMOS DRAM  
HIDDEN REFRESH CYCLE ( READ )  
tRC  
tRC  
tRP  
tRP  
tRAS  
tRAS  
VIH -  
RAS  
VIL -  
tCRP  
tRCD  
tRSH  
tCHR  
VIH -  
VIL -  
CAS  
tRAD  
tASR  
tRAH  
tASC  
tRCS  
tCAH  
COLUMN  
ADDRESS  
VIH -  
VIL -  
ROW  
ADDRESS  
A
tWRH  
tRAL  
VIH -  
VIL -  
W
tAA  
VIH -  
VIL -  
OE  
tOEA  
tOFF  
tCAC  
tCLZ  
DQ0 ~ DQ3(7)  
VOH -  
VOL -  
tRAC  
tOEZ  
DATA-OUT  
OPEN  
Don¢t care  
Undefined  
K4F660812C,K4F640812C  
CMOS DRAM  
HIDDEN REFRESH CYCLE ( WRITE )  
NOTE : DOUT = OPEN  
tRC  
tRC  
tRP  
tRP  
tRAS  
tRAS  
VIH -  
RAS  
VIL -  
tCRP  
tRCD  
tRSH  
tCHR  
VIH -  
CAS  
VIL -  
tRAD  
tASR  
tRAH  
tASC  
tCAH  
VIH -  
VIL -  
ROW  
ADDRESS  
COLUMN  
ADDRESS  
A
tWRH  
tWRP  
tRAL  
tWCS  
tWCH  
VIH -  
VIL -  
W
tWP  
VIH -  
VIL -  
OE  
tDS  
tDH  
DQ0 ~ DQ3(7)  
VIH -  
VIL -  
DATA-IN  
Don¢t care  
Undefined  
K4F660812C,K4F640812C  
CMOS DRAM  
CAS - BEFORE - RAS SELF REFRESH CYCLE  
NOTE : OE, A = Don¢t care  
tRP  
tRASS  
tRPS  
VIH -  
RAS  
tRPC  
tCP  
VIL -  
tRPC  
tCHS  
VIH -  
VIL -  
tCSR  
CAS  
DQ0 ~ DQ3(7)  
VOH -  
tOFF  
OPEN  
VOL -  
tWRP  
tWRH  
VIH -  
W
VIL -  
TEST MODE IN CYCLE  
NOTE : OE, A = Don¢t care  
tRC  
tRP  
tRAS  
tRP  
VIH -  
RAS  
VIL -  
tRPC  
tCP  
tRPC  
VIH -  
CAS  
tCSR  
tWTS  
tCHR  
VIL -  
tWTH  
VIH -  
W
VIL -  
DQ0 ~ DQ3(7)  
VOH -  
tOFF  
OPEN  
VOL -  
Don¢t care  
Undefined  
K4F660812C,K4F640812C  
PACKAGE DIMENSION  
32 SOJ 400mil  
CMOS DRAM  
Units : Inches (millimeters)  
#32  
0.006 (0.15)  
0.012 (0.30)  
#1  
0.027 (0.69)  
MIN  
0.841 (21.36)  
MAX  
0.820 (20.84)  
0.830 (21.08)  
0.0375 (0.95)  
0.050 (1.27)  
0.026 (0.66)  
0.032 (0.81)  
0.015 (0.38)  
0.021 (0.53)  
32 TSOP(II) 400mil  
Units : Inches (millimeters)  
0.004 (0.10)  
0.010 (0.25)  
0.841 (21.35)  
MAX  
0.821 (20.85)  
0.829 (21.05)  
0.047 (1.20)  
MAX  
0.010 (0.25)  
TYP  
0.002 (0.05)  
0.037 (0.95)  
0.050 (1.27)  
MIN  
O
0.012 (0.30)  
0.020 (0.50)  
0~8  
0.018 (0.45)  
0.030 (0.75)  

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