K4F661612B-TC50

更新时间:2024-10-29 14:23:50
品牌:SAMSUNG
描述:Fast Page DRAM, 4MX16, 50ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50

K4F661612B-TC50 概述

Fast Page DRAM, 4MX16, 50ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50 DRAM

K4F661612B-TC50 规格参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2, TSOP50,.46,32
针数:50Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.5访问模式:FAST PAGE
最长访问时间:50 ns其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
I/O 类型:COMMONJESD-30 代码:R-PDSO-G50
JESD-609代码:e0长度:20.95 mm
内存密度:67108864 bit内存集成电路类型:FAST PAGE DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:50
字数:4194304 words字数代码:4000000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP50,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified刷新周期:8192
座面最大高度:1.2 mm自我刷新:NO
最大待机电流:0.0005 A子类别:DRAMs
最大压摆率:0.09 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10.16 mmBase Number Matches:1

K4F661612B-TC50 数据手册

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K4F661612B,K4F641612B  
CMOS DRAM  
4M x 16bit CMOS Dynamic RAM with Fast Page Mode  
DESCRIPTION  
This is a family of 4,194,304 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory  
cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power)  
are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities.  
Furthermore, Self-refresh operation is available in L-version. This 4Mx16 Fast Page Mode DRAM family is fabricated using Samsung¢s  
advanced CMOS process to realize high band-width, low power consumption and high reliability.  
• Fast Page Mode operation  
FEATURES  
• 2CAS Byte/Word Read/Write operation  
• Part Identification  
• CAS-before-RAS refresh capability  
• RAS-only and Hidden refresh capability  
• Self-refresh capability (L-ver only)  
• Fast parallel test mode capability  
• LVTTL(3.3V) compatible inputs and outputs  
• Early Write or output enable controlled write  
• JEDEC Standard pinout  
- K4F661612B-TC/L(3.3V, 8K Ref., TSOP)  
- K4F641612B-TC/L(3.3V, 4K Ref., TSOP)  
ActivePowerDissipation  
Unit : mW  
4K  
Speed  
-45  
8K  
• Available in Plastic TSOP(II) packages  
• +3.3V±0.3V power supply  
360  
324  
288  
468  
432  
396  
-50  
-60  
Refresh Cycles  
Part  
NO.  
Refresh  
cycle  
Refresh time  
FUNCTIONAL BLOCK DIAGRAM  
Normal  
64ms  
L-ver  
K4F661612B*  
K4F641612B  
8K  
4K  
RAS  
UCAS  
LCAS  
W
128ms  
Vcc  
Vss  
Control  
Clocks  
VBB Generator  
* Access mode & RAS only refresh mode  
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)  
CAS-before-RAS & Hidden refresh mode  
Lower  
Data in  
Buffer  
DQ0  
to  
Row Decoder  
Refresh Timer  
DQ7  
Lower  
Data out  
Buffer  
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)  
Refresh Control  
Memory Array  
OE  
4,194,304 x 16  
Cells  
Refresh Counter  
Row Address Buffer  
Col. Address Buffer  
Upper  
Data in  
Buffer  
Performance Range  
DQ8  
to  
DQ15  
Speed  
tRAC  
45ns  
50ns  
60ns  
tCAC  
12ns  
13ns  
15ns  
tRC  
tPC  
A0~A12  
(A0~A11)*1  
Upper  
Data out  
Buffer  
-45  
-50  
-60  
80ns  
90ns  
110ns  
31ns  
35ns  
40ns  
A0~A8  
(A0~A9)*1  
Column Decoder  
Note) *1 : 4K Refresh  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  
K4F661612B,K4F641612B  
CMOS DRAM  
PIN CONFIGURATION (Top Views)  
K4F661612B-T  
K4F641612B-T  
1
2
3
4
5
6
7
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
VCC  
DQ0  
DQ1  
DQ2  
DQ3  
VCC  
DQ4  
DQ5  
DQ6  
DQ7  
N.C  
VCC  
W
RAS  
N.C  
N.C  
N.C  
N.C  
A0  
VSS  
DQ15  
DQ14  
DQ13  
DQ12  
VSS  
DQ11  
DQ10  
DQ9  
DQ8  
N.C  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
VSS  
LCAS  
UCAS  
OE  
N.C  
N.C  
A12(N.C)*  
A11  
A10  
A9  
A8  
A1  
A2  
A3  
A4  
A5  
VCC  
A7  
A6  
VSS  
26  
(400mil TSOP(II))  
*(N.C) : N.C for 4K Refresh Product  
Pin Name  
Pin function  
A0 - A12  
A0 - A11  
DQ0 - 15  
VSS  
Address Inputs(8K Product)  
Address Inputs(4K Product)  
Data In/Out  
Ground  
RAS  
Row Address Strobe  
Upper Column Address Strobe  
Lower Column Address Strobe  
Read/Write Input  
UCAS  
LCAS  
W
OE  
Data Output Enable  
Power(+3.3V)  
VCC  
N.C  
No Connection  
K4F661612B,K4F641612B  
CMOS DRAM  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Symbol  
VIN,VOUT  
VCC  
Rating  
-0.5 to +6.5  
-0.5 to +4.6  
-55 to +150  
1
Units  
V
Voltage on any pin relative to VSS  
Voltage on VCC supply relative to VSS  
Storage Temperature  
V
Tstg  
°C  
W
Power Dissipation  
PD  
Short Circuit Output Current  
IOS Address  
50  
mA  
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to  
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended  
periods may affect device reliability.  
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)  
Parameter  
Supply Voltage  
Symbol  
VCC  
VSS  
Min  
3.0  
0
Typ  
Max  
3.6  
0
Units  
3.3  
V
V
V
V
Ground  
0
-
*1  
Input High Voltage  
Input Low Voltage  
VIH  
2.0  
+5.5  
0.8  
*2  
VIL  
-
-0.3  
*1 : 6.5V at pulse width £15ns which is measured at VCC  
*2 : -1.3 at pulse width £15ns which is measured at VSS  
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)  
Parameter  
Symbol  
Min  
Max  
Units  
Input Leakage Current (Any input 0£VIN£VCC+0.3V,  
all other pins not under test=0 Volt)  
II(L)  
-5  
5
uA  
Output Leakage Current  
(Data out is disabled, 0V£VOUT£VCC)  
IO(L)  
-5  
5
uA  
Output High Voltage Level(IOH=-2mA)  
Output Low Voltage Level(IOL=2mA)  
VOH  
VOL  
2.4  
-
-
V
V
0.4  
K4F661612B,K4F641612B  
CMOS DRAM  
DC AND OPERATING CHARACTERISTICS (Continued)  
Max  
Symbol  
Power  
Speed  
Units  
K4F661612B  
K4F641612B  
-45  
-50  
-60  
100  
90  
80  
130  
120  
110  
mA  
mA  
mA  
ICC1  
Don¢t care  
Normal  
L
2
2
2
2
mA  
mA  
ICC2  
ICC3  
Don¢t care  
-45  
-50  
-60  
100  
90  
80  
130  
120  
110  
mA  
mA  
mA  
Don¢t care  
Don¢t care  
-45  
-50  
-60  
70  
60  
50  
80  
70  
60  
mA  
mA  
mA  
ICC4  
ICC5  
ICC6  
Normal  
L
500  
300  
500  
300  
uA  
uA  
Don¢t care  
-45  
-50  
-60  
100  
90  
80  
130  
120  
110  
mA  
mA  
mA  
Don¢t care  
ICC7  
ICCS  
L
L
Don¢t care  
Don¢t care  
400  
400  
400  
400  
uA  
uA  
ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.)  
ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH)  
ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.)  
ICC4* : Fast Page Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tPC=min.)  
ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V)  
ICC6* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min)  
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode  
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=CAS-before-RAS cycling or 0.2V,  
W, OE=VIH, Address=Don¢t care DQ=Open, TRC=31.25us  
ICCS : Self Refresh Current  
RAS=UCAS=LCAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open  
*Note :  
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.  
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4,  
address can be changed maximum once within one fast page mode cycle time, tPC.  
K4F661612B,K4F641612B  
CMOS DRAM  
CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz)  
Parameter  
Input capacitance [A0 ~ A12]  
Symbol  
CIN1  
Min  
Max  
Units  
pF  
-
-
-
5
7
7
Input capacitance [RAS, UCAS, LCAS, W, OE]  
Output capacitance [DQ0 - DQ15]  
CIN2  
pF  
CDQ  
pF  
AC CHARACTERISTICS (0°C£TA£70°C, See note 1,2)  
Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V  
-45  
-50  
-60  
Parameter  
Symbol  
Units  
Note  
Min  
80  
Max  
Min  
Max  
Min  
110  
153  
Max  
Random read or write cycle time  
Read-modify-write cycle time  
Access time from RAS  
90  
tRC  
ns  
ns  
115  
133  
tRWC  
tRAC  
tCAC  
tAA  
45  
12  
23  
50  
13  
25  
60  
15  
30  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
3,4,10  
3,4,5  
3,10  
3
Access time from CAS  
Access time from column address  
CAS to output in Low-Z  
0
0
0
0
0
tCLZ  
tOFF  
tT  
Output buffer turn-off delay  
Transition time (rise and fall)  
RAS precharge time  
13  
50  
0
13  
50  
13  
50  
6
1
1
1
2
25  
45  
12  
45  
12  
18  
13  
5
30  
50  
13  
50  
13  
20  
15  
5
40  
60  
15  
60  
15  
20  
15  
5
tRP  
RAS pulse width  
10K  
10K  
10K  
tRAS  
tRSH  
tCSH  
tCAS  
tRCD  
tRAD  
tCRP  
tASR  
tRAH  
tASC  
tCAH  
tRAL  
tRCS  
tRCH  
tRRH  
tWCH  
tWP  
RAS hold time  
CAS hold time  
CAS pulse width  
10K  
33  
10K  
37  
10K  
45  
RAS to CAS delay time  
4
RAS to column address delay time  
CAS to RAS precharge time  
Row address set-up time  
Row address hold time  
22  
25  
30  
10  
0
0
0
8
10  
0
10  
0
Column address set-up time  
Column address hold time  
Column address to RAS lead time  
Read command set-up time  
Read command hold time referenced to CAS  
Read command hold time referenced to RAS  
Write command hold time  
Write command pulse width  
Write command to RAS lead time  
Write command to CAS lead time  
Data set-up time  
0
13  
13  
8
10  
25  
0
10  
30  
0
23  
0
0
0
0
8
8
0
0
0
8
10  
10  
15  
13  
0
10  
10  
15  
15  
0
8
13  
12  
0
tRWL  
tCWL  
tDS  
16  
9,19  
9,19  
Data hold time  
10  
10  
10  
tDH  
K4F661612B,K4F641612B  
CMOS DRAM  
AC CHARACTERISTICS (Continued)  
-45  
-50  
-60  
Parameter  
Symbol  
Units  
Note  
Min  
Max  
64  
Min  
Max  
64  
Min  
Max  
64  
Refresh period (Normal)  
ms  
ms  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
us  
ns  
ns  
tREF  
Refresh period (L-ver)  
128  
128  
128  
tREF  
Write command set-up time  
0
32  
67  
43  
48  
5
0
0
7
7,15  
7
tWCS  
tCWD  
tRWD  
tAWD  
tCPWD  
tCSR  
tCHR  
tRPC  
tCPA  
tPC  
CAS to W delay time  
36  
73  
48  
53  
5
38  
83  
53  
60  
5
RAS to W delay time  
Column address to W delay time  
CAS precharge W delay time  
7
CAS set-up time (CAS -before-RAS refresh)  
CAS hold time (CAS -before-RAS refresh)  
RAS to CAS precharge time  
17  
18  
10  
5
10  
5
10  
5
Access time from CAS precharge  
Fast Page mode cycle time  
26  
30  
35  
3
31  
70  
9
35  
76  
10  
50  
30  
40  
85  
10  
60  
35  
Fast Page mode read-modify-write cycle time  
CAS precharge time (Fast page cycle)  
RAS pulse width (Fast page cycle)  
RAS hold time from CAS precharge  
OE access time  
tPRWC  
tCP  
14  
45  
28  
200K  
12  
200K  
13  
200K  
15  
tRASP  
tRHCP  
tOEA  
tOED  
tOEZ  
tOEH  
tWTS  
tWTH  
tWRP  
tWRH  
tRASS  
tRPS  
tCHS  
OE to data delay  
12  
0
13  
0
13  
0
Output buffer turn off delay time from OE  
OE command hold time  
13  
13  
13  
6
12  
10  
15  
10  
10  
100  
80  
-50  
13  
10  
15  
10  
10  
100  
90  
-50  
15  
Write command set-up time (Test mode in)  
Write command hold time (Test mode in)  
W to RAS precharge time (C-B-R refresh)  
W to RAS hold time (C-B-R refresh)  
RAS pulse width (C-B-R self refresh)  
RAS precharge time (C-B-R self refresh)  
CAS hold time (C-B-R self refresh)  
10  
11  
11  
15  
10  
10  
100  
110  
-50  
20,21,22  
20,21,22  
20,21,22  
K4F661612B,K4F641612B  
CMOS DRAM  
( Note 11 )  
TEST MODE CYCLE  
-45  
-50  
-60  
Parameter  
Symbol  
Units  
Note  
Min  
85  
Max  
Min  
95  
Max  
Min  
115  
160  
Max  
Random read or write cycle time  
Read-modify-write cycle time  
Access time from RAS  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tRC  
120  
138  
tRWC  
tRAC  
tCAC  
tAA  
50  
17  
55  
18  
65  
20  
3,4,10,12  
3,4,5,12  
3,10,12  
Access time from CAS  
Access time from column address  
RAS pulse width  
28  
30  
35  
50  
17  
17  
50  
28  
37  
72  
48  
36  
75  
50  
10K  
10K  
55  
18  
18  
55  
30  
41  
78  
53  
40  
81  
55  
10K  
10K  
65  
20  
20  
65  
35  
43  
88  
58  
45  
90  
65  
10K  
10K  
tRAS  
tCAS  
tRSH  
tCSH  
tRAL  
tCWD  
tRWD  
tAWD  
tPC  
CAS pulse width  
RAS hold time  
CAS hold time  
Column Address to RAS lead time  
CAS to W delay time  
7
7
7
RAS to W delay time  
Column Address to W delay time  
Fast Page mode cycle time  
Fast Page mode read-modify-write cycle time  
RAS pulse width (Fast page cycle)  
Access time from CAS precharge  
OE access time  
tPRWC  
tRASP  
tCPA  
tOEA  
tOED  
tOEH  
200K  
31  
200K  
35  
200K  
40  
3
17  
18  
20  
OE to data delay  
17  
17  
18  
18  
18  
20  
OE command hold time  
K4F661612B,K4F641612B  
CMOS DRAM  
NOTES  
1.  
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles  
before proper device operation is achieved.  
2.  
VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between  
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.  
3.  
4.  
Measured with a load equivalent to 1 TTL load and 100pF.  
Operation within the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only.  
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.  
Assumes that tRCD³ tRCD(max).  
5.  
6.  
tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced Voh  
or Vol.  
7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical char-  
acteristics only. If tWCS³ tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the  
duration of the cycle. If tCWD³ tCWD(min), tRWD³ tRWD(min) and tAWD³ tAWD(min), then the cycle is a read-modify-write cycle  
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the  
condition of the data out is indeterminate.  
Either tRCH or tRRH must be satisfied for a read cycle.  
8.  
9.  
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles.  
Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.  
If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.  
These specifications are applied in the test mode.  
10.  
11.  
12.  
In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters  
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.  
K4F64(6)1612B Truth Table  
RAS  
H
L
LCAS  
UCAS  
W
X
X
H
H
H
L
OE  
X
DQ0 - DQ7  
Hi-Z  
DQ8-DQ15  
Hi-Z  
STATE  
Standby  
Refresh  
X
H
L
X
H
H
L
X
Hi-Z  
Hi-Z  
L
L
DQ-OUT  
Hi-Z  
Hi-Z  
Byte Read  
Byte Read  
Word Read  
Byte Write  
Byte Write  
Word Write  
-
L
H
L
L
DQ-OUT  
DQ-OUT  
-
L
L
L
DQ-OUT  
DQ-IN  
-
L
L
H
L
H
H
H
H
L
H
L
L
DQ-IN  
DQ-IN  
Hi-Z  
L
L
L
DQ-IN  
Hi-Z  
L
L
L
H
K4F661612B,K4F641612B  
CMOS DRAM  
tASC, tCAH are referenced to the earlier CAS falling edge.  
13.  
14.  
tCP is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.  
15.  
tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.  
tCWL is specified from W falling edge to the earlier CAS rising edge.  
tCSR is referenced to the earlier CAS falling edge before RAS transition low.  
tCHR is referenced to the later CAS rising edge after RAS transition low.  
16.  
17.  
18.  
RAS  
LCAS  
UCAS  
tCSR  
tCHR  
tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge.  
19.  
LCAS  
UCAS  
tDS  
tDH  
Din  
DQ0 ~ DQ15  
If tRASS³ 100us, then RAS precharge time must use tRPS instead of tRP.  
20.  
21. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within  
64ms before and after self refresh, in order to meet refresh specification.  
22. For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS should be executed with in 15.6us immediately before  
and after self refresh in order to meet refresh specification.  
K4F661612B,K4F641612B  
CMOS DRAM  
WORD READ CYCLE  
tRC  
tRAS  
tRP  
VIH -  
RAS  
VIL -  
tCSH  
tCSH  
tCRP  
tCRP  
tCRP  
tRCD  
tRCD  
tRSH  
tCAS  
VIH -  
UCAS  
VIL -  
tCRP  
tRSH  
VIH -  
LCAS  
tCAS  
VIL -  
tRAD  
tRAL  
tASR  
tRAH  
tASC  
tRCS  
tCAH  
COLUMN  
ADDRESS  
VIH -  
VIL -  
ROW  
ADDRESS  
A
W
tRCH  
tRRH  
VIH -  
VIL -  
tAA  
VIH -  
VIL -  
OE  
tOEA  
tOFF  
tOFF  
tCAC  
tCLZ  
DQ0 ~ DQ7  
VOH -  
VOL -  
tOEZ  
DATA-OUT  
tRAC  
tRAC  
OPEN  
tCAC  
tCLZ  
DQ8 ~ DQ15  
tOEZ  
DATA-OUT  
VOH -  
OPEN  
VOL -  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
LOWER BYTE READ CYCLE  
NOTE : DIN = OPEN  
tRC  
tRAS  
tRP  
VIH -  
RAS  
VIL -  
tCRP  
tRPC  
VIH -  
UCAS  
VIL -  
tCSH  
tCRP  
tRCD  
tRSH  
tCAS  
VIH -  
LCAS  
VIL -  
tRAD  
tRAL  
tASR  
tRAH  
tASC  
tRCS  
tCAH  
COLUMN  
ADDRESS  
VIH -  
VIL -  
ROW  
ADDRESS  
A
W
tRCH  
tRRH  
VIH -  
VIL -  
tOFF  
tOEZ  
tAA  
VIH -  
VIL -  
OE  
tOEA  
tCAC  
tCLZ  
DQ0 ~ DQ7  
VOH -  
VOL -  
tRAC  
DATA-OUT  
OPEN  
DQ8 ~ DQ15  
VOH -  
OPEN  
VOL -  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
UPPER BYTE READ CYCLE  
NOTE : DIN = OPEN  
tRC  
tRAS  
tRP  
VIH -  
RAS  
VIL -  
tCSH  
tCRP  
tCRP  
tRCD  
tRSH  
tCAS  
VIH -  
UCAS  
VIL -  
tRPC  
tCRP  
VIH -  
LCAS  
VIL -  
tRAD  
tRAL  
tASR  
tRAH  
tASC  
tRCS  
tCAH  
COLUMN  
ADDRESS  
VIH -  
VIL -  
ROW  
ADDRESS  
A
W
tRCH  
tRRH  
VIH -  
VIL -  
tOFF  
tOEZ  
tAA  
VIH -  
VIL -  
OE  
tOEA  
DQ0 ~ DQ7  
VOH -  
VOL -  
OPEN  
tCAC  
tCLZ  
DQ8 ~ DQ15  
tRAC  
VOH -  
OPEN  
DATA-OUT  
VOL -  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
WORD WRITE CYCLE ( EARLY WRITE )  
NOTE : DOUT = OPEN  
tRC  
tRAS  
tRP  
VIH -  
RAS  
VIL -  
tCSH  
tCSH  
tCRP  
tCRP  
tCRP  
tRCD  
tRSH  
tCAS  
VIH -  
UCAS  
VIL -  
tCRP  
tRCD  
tRSH  
VIH -  
LCAS  
VIL -  
tCAS  
tRAD  
tRAL  
tASR  
tRAH  
tASC  
tCAH  
VIH -  
VIL -  
COLUMN  
ADDRESS  
ROW  
ADDRESS  
A
W
tWCS  
tWCH  
VIH -  
VIL -  
tWP  
VIH -  
VIL -  
OE  
tDS  
tDS  
DQ0 ~ DQ7  
VIH -  
tDH  
DATA-IN  
VIL -  
tDH  
DATA-IN  
DQ8 ~ DQ15  
VIH -  
VIL -  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
LOWER BYTE WRITE CYCLE ( EARLY WRITE )  
NOTE : DOUT = OPEN  
tRC  
tRAS  
tRP  
VIH -  
VIL -  
RAS  
UCAS  
LCAS  
tCRP  
tCRP  
tRPC  
VIH -  
VIL -  
tCSH  
tCRP  
tRCD  
tRSH  
VIH -  
VIL -  
tCAS  
tRAD  
tRAL  
tASR  
tRAH  
tASC  
tCAH  
VIH -  
VIL -  
ROW  
ADDRESS  
COLUMN  
ADDRESS  
A
W
tWCS  
tWCH  
VIH -  
VIL -  
tWP  
VIH -  
VIL -  
OE  
tDS  
DQ0 ~ DQ7  
VIH -  
tDH  
DATA-IN  
VIL -  
DQ8 ~ DQ15  
VIH -  
VIL -  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
UPPER BYTE WRITE CYCLE ( EARLY WRITE )  
NOTE : DOUT = OPEN  
tRC  
tRAS  
tRP  
VIH -  
VIL -  
RAS  
UCAS  
LCAS  
tCSH  
tCRP  
tCRP  
tCRP  
tRCD  
tRSH  
tCAS  
VIH -  
VIL -  
tRPC  
VIH -  
VIL -  
tRAD  
tRAL  
tASR  
tRAH  
tASC  
tCAH  
VIH -  
VIL -  
ROW  
ADDRESS  
COLUMN  
ADDRESS  
A
tWCS  
tWCH  
VIH -  
VIL -  
W
tWP  
VIH -  
VIL -  
OE  
DQ0 ~ DQ7  
VIH -  
VIL -  
tDS  
tDH  
DATA-IN  
DQ8 ~ DQ15  
VIH -  
VIL -  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
WORD WRITE CYCLE ( OE CONTROLLED WRITE )  
NOTE : DOUT = OPEN  
tRC  
tRP  
tRAS  
VIH -  
RAS  
VIL -  
tCSH  
tCRP  
tCRP  
tCRP  
tRCD  
tRSH  
tCAS  
VIH -  
UCAS  
LCAS  
VIL -  
tCSH  
tCRP  
tRCD  
tRSH  
VIH -  
VIL -  
tCAS  
tRAD  
tRAL  
tASR  
tRAH  
tASC  
tCAH  
VIH -  
VIL -  
COLUMN  
ADDRESS  
ROW  
ADDRESS  
A
W
tCWL  
tRWL  
VIH -  
VIL -  
tWP  
VIH -  
VIL -  
OE  
tOEH  
tOED  
tDS  
tDS  
DQ0 ~ DQ7  
VIH -  
tDH  
DATA-IN  
VIL -  
tDH  
DQ8 ~ DQ15  
VIH -  
DATA-IN  
VIL -  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )  
NOTE : DOUT = OPEN  
tRC  
tRAS  
tRP  
VIH -  
RAS  
VIL -  
tRPC  
tCRP  
VIH -  
UCAS  
VIL -  
tCSH  
tCRP  
tCRP  
tRCD  
tRSH  
tCAS  
VIH -  
VIL -  
LCAS  
tRAD  
tRAL  
tASR  
tRAH  
tASC  
tCAH  
COLUMN  
ADDRESS  
VIH -  
VIL -  
ROW  
ADDRESS  
A
tCWL  
tRWL  
VIH -  
VIL -  
tWP  
W
VIH -  
VIL -  
tOEH  
OE  
tOED  
tDS  
tDH  
DATA-IN  
DQ0 ~ DQ7  
VIH -  
VIL -  
DQ8 ~ DQ15  
VIH -  
VIL -  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )  
NOTE : DOUT = OPEN  
tRC  
tRAS  
tRP  
VIH -  
RAS  
VIL -  
tCSH  
tCRP  
tCRP  
tRCD  
tRSH  
tCAS  
VIH -  
VIL -  
UCAS  
LCAS  
tCRP  
tRPC  
VIH -  
VIL -  
tRAD  
tRAL  
tASR  
tRAH  
tASC  
tCAH  
COLUMN  
ADDRESS  
VIH -  
VIL -  
ROW  
ADDRESS  
A
tCWL  
tRWL  
VIH -  
VIL -  
W
tWP  
VIH -  
VIL -  
tOEH  
OE  
tOED  
DQ0 ~ DQ7  
VIH -  
VIL -  
tDS  
tDH  
DATA-IN  
DQ8 ~ DQ15  
VIH -  
VIL -  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
WORD READ - MODIFY - WRITE CYCLE  
tRWC  
tRAS  
tRP  
VIH -  
RAS  
VIL -  
tCRP  
tRCD  
tRSH  
VIH -  
tCAS  
tCAS  
UCAS  
VIL -  
tCRP  
tRCD  
tRSH  
tCSH  
VIH -  
LCAS  
VIL -  
tRAD  
tRAH  
tASR  
tASC  
tCAH  
VIH -  
VIL -  
ROW  
ADDR  
COLUMN  
ADDRESS  
A
tRWL  
tAWD  
tCWL  
tWP  
tCWD  
VIH -  
VIL -  
W
tRWD  
tOEA  
VIH -  
VIL -  
OE  
tCLZ  
tCAC  
tOED  
tOEZ  
tAA  
tDS  
tDH  
DQ0 ~ DQ7  
tRAC  
VI/OH -  
VI/OL -  
VALID  
DATA-OUT  
VALID  
DATA-IN  
tCLZ  
tCAC  
tOED  
tOEZ  
tAA  
tDS  
tDH  
DQ8 ~ DQ15  
tRAC  
VI/OH -  
VALID  
DATA-OUT  
VALID  
DATA-IN  
VI/OL -  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
LOWER-BYTE READ - MODIFY - WRITE CYCLE  
tRWC  
tRAS  
tRP  
VIH -  
RAS  
VIL -  
tRPC  
tCRP  
VIH -  
UCAS  
VIL -  
tCRP  
tRCD  
tRSH  
VIH -  
tCAS  
LCAS  
VIL -  
tRAD  
tRAH  
tCSH  
tASR  
tASC  
tCAH  
VIH -  
VIL -  
ROW  
ADDR  
COLUMN  
ADDRESS  
A
tRWL  
tCWL  
tWP  
tAWD  
tCWD  
VIH -  
VIL -  
W
tRWD  
tOEA  
VIH -  
VIL -  
OE  
tCLZ  
tCAC  
tOED  
tOEZ  
tAA  
tDS  
tDH  
DQ0 ~ DQ7  
tRAC  
VI/OH -  
VALID  
DATA-OUT  
VALID  
DATA-IN  
VI/OL -  
DQ8 ~ DQ15  
VI/OH -  
OPEN  
VI/OL -  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
UPPER-BYTE READ - MODIFY - WRITE CYCLE  
tRWC  
tRP  
tRAS  
VIH -  
VIL -  
RAS  
UCAS  
LCAS  
tCRP  
tCRP  
tRCD  
tRSH  
VIH -  
VIL -  
tCAS  
tRPC  
VIH -  
VIL -  
tRAD  
tRAH  
tCSH  
tASR  
tASC  
tCAH  
VIH -  
VIL -  
ROW  
ADDR  
COLUMN  
ADDRESS  
A
tRWL  
tAWD  
tCWL  
tWP  
tCWD  
VIH -  
VIL -  
W
tRWD  
tOEA  
VIH -  
VIL -  
OE  
DQ0 ~ DQ7  
VI/OH -  
OPEN  
VI/OL -  
tCLZ  
tCAC  
tOED  
tAA  
tDS  
tDH  
DQ8 ~ DQ15  
tOEZ  
tRAC  
VI/OH -  
VALID  
DATA-OUT  
VALID  
DATA-IN  
VI/OL -  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
FAST PAGE MODE WORD READ CYCLE  
tRP  
tRASP  
¡ó  
VIH -  
RAS  
VIL -  
tRHCP  
tCAS  
tCSH  
tPC  
tPC  
tCAS  
tPC  
tCAS  
tCRP  
tCP  
tCP  
tCP  
tCP  
tRPC  
tRPC  
tRCD  
tCAS  
VIH -  
VIL -  
UCAS  
tRAL  
tCAS  
tCRP  
tASR  
tCP  
tCP  
tRCD  
tCAS  
tCAS  
tCAH  
tCAS  
tCAH  
VIH -  
VIL -  
LCAS  
tRAD  
tRAH tASC  
tCAH tASC  
tASC  
tASC  
tCAH  
VIH -  
VIL -  
COLUMN  
ADDRESS  
COLUMN  
ADDR  
COLUMN  
ROW  
ADDR  
COLUMN  
ADDRESS  
A
ADDRESS  
tRCS  
tRCH  
tRCS  
tRCH  
tRCS  
tRRH  
tRCH  
tRCS  
tRCH  
VIH -  
VIL -  
W
tCAC  
tCAC  
tCAC  
tAA  
tAA  
tAA  
tCPA  
tOEA  
tAA  
tOEA  
tCPA  
tCPA  
tOEA  
tOEA  
VIH -  
VIL -  
OE  
tCAC  
tRAC  
tOFF  
tOEZ  
tOFF  
tOEZ  
tOFF  
tOEZ  
tOFF  
tOEZ  
DQ0 ~ DQ7  
VOH -  
VALID  
VALID  
VALID  
VALID  
DATA-OUT  
DATA-OUT  
DATA-OUT  
DATA-OUT  
VOL -  
tCLZ  
tCAC  
tOFF  
tOEZ  
tOFF  
tOEZ  
tOFF  
tOEZ  
tOFF  
tOEZ  
DQ8 ~ DQ15  
VOH -  
tRAC  
VALID  
VALID  
VALID  
VALID  
VOL -  
DATA-OUT  
DATA-OUT  
DATA-OUT  
DATA-OUT  
tCLZ  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
FAST PAGE MODE LOWER BYTE READ CYCLE  
tRASP  
tRP  
VIH -  
VIL -  
RAS  
¡ó  
tRHCP  
tRAL  
tCRP  
tRPC  
tRPC  
VIH -  
VIL -  
UCAS  
tCSH  
tPC  
tCAS  
tPC  
tCAS  
tPC  
tCAS  
tCRP  
tASR  
tCP  
tCP  
tCP  
tRCD  
tCAS  
tCAH  
VIH -  
VIL -  
LCAS  
tRAD  
tRAH  
tASC tCAH  
tASC tCAH  
tASC  
tCAH  
tASC  
VIH -  
VIL -  
COLUMN  
COLUMN  
ADDR  
COLUMN  
ROW  
ADDR  
COLUMN  
ADDRESS  
A
ADDRESS  
ADDRESS  
tRCS  
tRCS  
tRCH  
tRCS  
tRRH  
tRCH  
tRCS  
tRCH  
tRCH  
VIH -  
VIL -  
W
tCAC  
tCAC  
tCAC  
tAA  
tCPA  
tOEA  
tAA  
tCPA  
tOEA  
tAA  
tCPA  
tOEA  
tAA  
tOEA  
VIH -  
VIL -  
OE  
tCAC  
tRAC  
tOFF  
tOEZ  
tOFF  
tOEZ  
tOFF  
tOEZ  
tOFF  
tOEZ  
DQ0 ~ DQ7  
VOH -  
VALID  
VALID  
VALID  
VALID  
DATA-OUT  
DATA-OUT  
DATA-OUT  
DATA-OUT  
VOL -  
tCLZ  
DQ8 ~ DQ15  
VOH -  
OPEN  
VOL -  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
FAST PAGE MODE UPPER BYTE READ CYCLE  
tRP  
tRASP  
VIH -  
VIL -  
RAS  
¡ó  
tCSH  
tRCD  
tRHCP  
tCAS  
tPC  
tCAS  
tPC  
tCAS  
tPC  
tCAS  
tCRP  
tCP  
tCP  
tCP  
tRPC  
tRPC  
VIH -  
VIL -  
UCAS  
tCRP  
tASR  
VIH -  
VIL -  
LCAS  
tRAL  
tCAH  
tRAD  
tRAH tASC  
tCAH  
tASC  
tCAH  
tASC  
tCAH  
tASC  
VIH -  
VIL -  
ROW  
COLUMN  
ADDRESS  
COLUMN  
ADDRESS  
COLUMN  
ADDR  
COLUMN  
ADDRESS  
A
ADDR  
tRCS  
tRCS  
tRCH  
tRCS  
tRRH  
tRCH  
tRCS  
tRCH  
tRCH  
VIH -  
VIL -  
W
tCAC  
tCAC  
tCAC  
tAA  
tAA  
tCPA  
tOEA  
tAA  
tCPA  
tOEA  
tAA  
tOEA  
tCPA  
tOEA  
VIH -  
VIL -  
OE  
DQ0 ~ DQ7  
VOH -  
OPEN  
VOL -  
tCAC  
tOFF  
tOEZ  
tOFF  
tOEZ  
tOFF  
tOEZ  
tOFF  
tOEZ  
tRAC  
DQ8 ~ DQ15  
VOH -  
VALID  
DATA-OUT  
VALID  
DATA-OUT  
VALID  
DATA-OUT  
VALID  
DATA-OUT  
VOL -  
tCLZ  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
FAST PAGE MODE WORD WRITE CYCLE ( EARLY WRITE )  
NOTE : DOUT = OPEN  
tRASP  
tRP  
VIH -  
RAS  
tRHCP  
VIL -  
¡ó  
tPC  
tPC  
tPC  
tPC  
tRSH  
tCRP  
tCRP  
tRCD  
tRCD  
tCP  
tCP  
tCP  
tCP  
tCRP  
VIH -  
VIL -  
tCAS  
tCAS  
tCAS  
¡ó  
tCAS  
UCAS  
LCAS  
tRSH  
VIH -  
VIL -  
tCAS  
¡ó  
tCAS  
tRAD  
tRAH  
tRAL  
tCAH  
tCSH  
tASC  
tASR  
tCAH  
tASC  
tCAH  
tASC  
¡ó  
¡ó  
VIH -  
VIL -  
ROW  
ADDR  
COLUMN  
ADDRESS  
COLUMN  
ADDRESS  
COLUMN  
ADDRESS  
A
tWCS tWCH  
tWP  
tWCS  
tWCH  
tWP  
tWCS  
tWCH  
tWP  
¡ó  
VIH -  
VIL -  
W
¡ó  
¡ó  
VIH -  
VIL -  
OE  
tDS  
tDS  
tDH  
tDS  
tDH  
tDS  
tDH  
DQ0 ~ DQ7  
VIH -  
¡ó  
¡ó  
VALID  
DATA-IN  
VALID  
DATA-IN  
VALID  
DATA-IN  
VIL -  
tDH  
tDS  
tDH  
tDS  
tDH  
DQ8 ~ DQ15  
¡ó  
¡ó  
VIH -  
VALID  
DATA-IN  
VALID  
DATA-IN  
VALID  
DATA-IN  
VIL -  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
FAST PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE )  
NOTE : DOUT = OPEN  
tRASP  
tRP  
VIH -  
tRHCP  
RAS  
VIL -  
¡ó  
tRPC  
tCRP  
¡ó  
VIH -  
UCAS  
VIL -  
tPC  
tPC  
tRSH  
tCRP  
tRCD  
tCP  
tCP  
VIH -  
VIL -  
tCAS  
tCAS  
¡ó  
tCAS  
LCAS  
tRAD  
tRAH  
tRAL  
tCAH  
tCSH  
tASC  
tASR  
tCAH  
tASC  
tCAH  
tASC  
¡ó  
¡ó  
VIH -  
VIL -  
ROW  
ADDR  
COLUMN  
COLUMN  
ADDRESS  
COLUMN  
ADDRESS  
A
ADDRESS  
tWCS  
tWP  
tWCH  
tWCS  
tWCH  
tWP  
tWCS  
tWCH  
tWP  
¡ó  
VIH -  
VIL -  
W
¡ó  
¡ó  
VIH -  
VIL -  
OE  
tDS  
tDH  
tDS  
tDH  
tDS  
tDH  
DQ0 ~ DQ7  
VIH -  
VIL -  
¡ó  
¡ó  
VALID  
DATA-IN  
VALID  
DATA-IN  
VALID  
DATA-IN  
DQ8 ~ DQ15  
VIH -  
VIL -  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
FAST PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE )  
NOTE : DOUT = OPEN  
tRASP  
tRP  
VIH -  
tRHCP  
RAS  
VIL -  
¡ó  
tPC  
tPC  
tRSH  
tCRP  
tCRP  
tRCD  
tCP  
tCP  
VIH -  
VIL -  
tCAS  
tCAS  
¡ó  
tCAS  
UCAS  
LCAS  
tRPC  
VIH -  
VIL -  
tRAD  
tRAH  
tRAL  
tCAH  
tCSH  
tASC  
tASR  
tCAH  
tASC  
tCAH  
tASC  
¡ó  
¡ó  
VIH -  
VIL -  
ROW  
ADDR.  
COLUMN  
ADDRESS  
COLUMN  
ADDRESS  
COLUMN  
ADDRESS  
A
tWCS tWCH  
tWP  
tWCS  
tWCH  
tWP  
tWCS  
tWCH  
tWP  
¡ó  
VIH -  
VIL -  
W
¡ó  
¡ó  
VIH -  
VIL -  
OE  
DQ0 ~ DQ7  
VIH -  
VIL -  
¡ó  
¡ó  
tDS  
tDH  
tDS  
tDH  
tDS  
tDH  
DQ8 ~ DQ15  
¡ó  
¡ó  
VIH -  
VALID  
DATA-IN  
VALID  
DATA-IN  
VALID  
DATA-IN  
VIL -  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
FAST PAGE MODE WORD READ-MODIFY-WRITE CYCLE  
tRP  
tRASP  
VIH -  
VIL -  
tCSH  
RAS  
tPRWC  
tRSH  
tCRP  
tCRP  
tCRP  
tCRP  
tRCD  
tRCD  
tCP  
tCP  
VIH -  
VIL -  
tCAS  
tCAS  
UCAS  
LCAS  
VIH -  
VIL -  
tCAS  
tRAL  
tCAS  
tRAD  
tRAH  
tCAH  
tCAH  
tASR  
tASC  
tASC  
VIH -  
VIL -  
ROW  
ADDR  
COL.  
ADDR  
COL.  
ADDR  
A
W
tRWL  
tCWL  
tRCS  
tCWL  
tRCS  
VIH -  
VIL -  
tWP  
tWP  
tCWD  
tAWD  
tRWD  
tCWD  
tAWD  
tCPWD  
VIH -  
VIL -  
tOEA  
tOEA  
OE  
tOED  
tOED  
tCAC  
tAA  
tCAC  
tAA  
tDH  
tDH  
tDS  
tOEZ  
tDS  
DQ0 ~ DQ7  
tRAC  
tOEZ  
VI/OH -  
VI/OL -  
tCLZ  
tCLZ  
VALID  
DATA-OUT  
VALID  
DATA-IN  
VALID  
DATA-OUT  
VALID  
DATA-IN  
tOED  
tOED  
tCAC  
tAA  
tCAC  
tAA  
tDH  
tDH  
tDS  
tOEZ  
tDS  
DQ8 ~ DQ15  
tOEZ  
tRAC  
VI/OH -  
VI/OL -  
tCLZ  
tCLZ  
VALID  
DATA-IN  
VALID  
DATA-IN  
VALID  
DATA-OUT  
VALID  
DATA-OUT  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
FAST PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE  
tRP  
tRASP  
VIH -  
VIL -  
tCSH  
RAS  
tCRP  
tCRP  
tRPC  
VIH -  
VIL -  
UCAS  
LCAS  
tPRWC  
tCAS  
tRSH  
tCAS  
tCRP  
tRCD  
tCP  
VIH -  
VIL -  
tRAD  
tRAH  
tRAL  
tCAH  
tCAH  
tASR  
tASC  
tASC  
VIH -  
VIL -  
ROW  
ADDR  
COL.  
ADDR  
COL.  
A
W
ADDR  
tRWL  
tCWL  
tRCS  
tCWL  
tRCS  
VIH -  
VIL -  
tWP  
tWP  
tCWD  
tAWD  
tRWD  
tCWD  
tAWD  
tCPWD  
VIH -  
VIL -  
tOEA  
tOEA  
OE  
tOED  
tOED  
tCAC  
tAA  
tCAC  
tAA  
tDH  
tDH  
tDS  
tOEZ  
tDS  
DQ0 ~ DQ7  
tRAC  
tOEZ  
VI/OH -  
VI/OL -  
tCLZ  
tCLZ  
VALID  
DATA-OUT  
VALID  
DATA-IN  
VALID  
DATA-OUT  
VALID  
DATA-IN  
DQ8 ~ DQ15  
VI/OH -  
OPEN  
VI/OL -  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
FAST PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE  
tRP  
tRASP  
VIH -  
VIL -  
tCSH  
RAS  
tCRP  
tCRP  
tPRWC  
tCAS  
tRSH  
tCAS  
tCRP  
tRCD  
tCP  
VIH -  
VIL -  
UCAS  
LCAS  
tRPC  
VIH -  
VIL -  
tRAD  
tRAH  
tRAL  
tCAH  
tASR  
tCAH  
tASC  
tASC  
VIH -  
VIL -  
ROW  
ADDR  
COL.  
ADDR  
COL.  
A
W
ADDR  
tRWL  
tCWL  
tRCS  
tCWL  
tRCS  
VIH -  
VIL -  
tWP  
tWP  
tCWD  
tAWD  
tRWD  
tCWD  
tAWD  
tCPWD  
VIH -  
VIL -  
tOEA  
tOEA  
OE  
DQ0 ~ DQ7  
VI/OH -  
OPEN  
VI/OL -  
tOED  
tOED  
tCAC  
tAA  
tCAC  
tAA  
tDH  
tDH  
tOEZ  
tOEZ  
tDS  
tDS  
DQ8 ~ DQ15  
VI/OH -  
tRAC  
VI/OL -  
tCLZ  
tCLZ  
VALID  
DATA-OUT  
VALID  
DATA-IN  
VALID  
DATA-OUT  
VALID  
DATA-IN  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
RAS - ONLY REFRESH CYCLE  
NOTE : W, OE , DIN = Don¢t care  
DOUT = OPEN  
tRC  
tRP  
VIH -  
RAS  
tRAS  
VIL -  
tRPC  
tCRP  
VIH -  
UCAS  
VIL -  
tCRP  
VIH -  
LCAS  
VIL -  
tASR  
tRAH  
VIH -  
VIL -  
ROW  
ADDR  
A
CAS - BEFORE - RAS REFRESH CYCLE  
NOTE : OE , A = Don¢t care  
tRC  
tRP  
tRP  
tRAS  
VIH -  
RAS  
VIL -  
tCRP  
tCP  
tRPC  
tCSR  
tCSR  
VIH -  
VIL -  
tCHR  
tCHR  
UCAS  
LCAS  
tCP  
VIH -  
VIL -  
DQ0 ~ DQ7  
VOH -  
VOL -  
tOFF  
OPEN  
DQ8 ~ DQ15  
VOH -  
OPEN  
VOL -  
tWRP  
tWRH  
VIH -  
VIL -  
W
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
HIDDEN REFRESH CYCLE ( READ )  
tRC  
tRC  
tRAS  
tRP  
tRP  
tRAS  
VIH -  
RAS  
VIL -  
tCRP  
tRCD  
tRSH  
tRSH  
tCHR  
tCHR  
VIH -  
VIL -  
UCAS  
LCAS  
tCRP  
tRCD  
VIH -  
VIL -  
tRAD  
tRAL  
tCAH  
tASR  
tRAH  
tASC  
VIH -  
VIL -  
ROW  
ADDRESS  
COLUMN  
ADDRESS  
A
W
tWRH  
tRCS  
VIH -  
VIL -  
tAA  
VIH -  
VIL -  
tOEA  
OE  
tOFF  
tCAC  
tCLZ  
tRAC  
DQ0 ~ DQ7  
VOH -  
VOL -  
tOEZ  
DATA-OUT  
OPEN  
DQ8 ~ DQ15  
VOH -  
DATA-OUT  
OPEN  
VOL -  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
HIDDEN REFRESH CYCLE ( WRITE )  
NOTE : DOUT = OPEN  
tRC  
tRC  
tRP  
tRP  
tRAS  
tRAS  
VIH -  
RAS  
VIL -  
tCRP  
tRCD  
tCHR  
tRSH  
tRSH  
VIH -  
UCAS  
VIL -  
tCRP  
tRCD  
tCHR  
VIH -  
LCAS  
VIL -  
tRAD  
tRAL  
tCAH  
COLUMN  
ADDRESS  
tASR  
ROW  
tRAH  
tASC  
VIH -  
VIL -  
A
W
ADDRESS  
tWRH  
tWRP  
tWCS  
tWCH  
VIH -  
VIL -  
tWP  
VIH -  
VIL -  
OE  
tDS  
tDS  
tDH  
DATA-IN  
DQ0 ~ DQ7  
VIH -  
VIL -  
tDH  
DATA-IN  
DQ8 ~ DQ15  
VIH -  
VIL -  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
CMOS DRAM  
CAS - BEFORE - RAS SELF REFRESH CYCLE  
NOTE : OE , A = Don¢t care  
tRP  
tRASS  
tRPS  
VIH -  
RAS  
VIL -  
tRPC  
tCP  
tRPC  
tCHS  
tCHS  
tCSR  
tCSR  
VIH -  
VIL -  
UCAS  
LCAS  
tCP  
VIH -  
VIL -  
tOFF  
DQ0 ~ DQ7  
VOH -  
OPEN  
OPEN  
VOL -  
DQ8 ~ DQ15  
VOH -  
VOL -  
tWRP  
tWRH  
VIH -  
VIL -  
W
TEST MODE IN CYCLE  
NOTE : OE , A = Don¢t care  
tRC  
tRP  
tRP  
tRAS  
VIH -  
RAS  
VIL -  
tCRP  
tRPC  
tCP  
tCSR  
tCSR  
VIH -  
VIL -  
tCHR  
tCHR  
UCAS  
LCAS  
tCP  
VIH -  
VIL -  
tWTS  
VIH -  
VIL -  
tWTH  
W
tOFF  
DQ0 ~ DQ15  
VOH -  
VOL -  
OPEN  
Don¢t care  
Undefined  
K4F661612B,K4F641612B  
PACKAGE DIMENSION  
50 TSOP(II) 400mil  
CMOS DRAM  
Units : Inches (millimeters)  
0.004 (0.10)  
0.010 (0.25)  
0.841 (21.35)  
MAX  
0.821 (20.85)  
0.829 (21.05)  
0.047 (1.20)  
MAX  
0.010 (0.25)  
TYP  
O
0~8  
0.018 (0.45)  
0.030 (0.75)  
0.034 (0.875)  
0.0315 (0.80)  
0.002 (0.05)  
MIN  
0.010 (0.25)  
0.018 (0.45)  

K4F661612B-TC50 相关器件

型号 制造商 描述 价格 文档
K4F661612B-TC500 SAMSUNG Fast Page DRAM, 4MX16, 50ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50 获取价格
K4F661612B-TC60 SAMSUNG Fast Page DRAM, 4MX16, 60ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50 获取价格
K4F661612B-TC600 SAMSUNG Fast Page DRAM, 4MX16, 60ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50 获取价格
K4F661612B-TL45 SAMSUNG Fast Page DRAM, 4MX16, 45ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50 获取价格
K4F661612B-TL450 SAMSUNG Fast Page DRAM, 4MX16, 45ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50 获取价格
K4F661612B-TL50 SAMSUNG Fast Page DRAM, 4MX16, 50ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50 获取价格
K4F661612B-TL500 SAMSUNG Fast Page DRAM, 4MX16, 50ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50 获取价格
K4F661612B-TL600 SAMSUNG Fast Page DRAM, 4MX16, 60ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50 获取价格
K4F661612C SAMSUNG 4M x 16bit CMOS Dynamic RAM with Fast Page Mode 获取价格
K4F661612C-L SAMSUNG 4M x 16bit CMOS Dynamic RAM with Fast Page Mode 获取价格

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