K4H510838C-ZCB0 [SAMSUNG]
DDR DRAM, 64MX8, 0.75ns, CMOS, PBGA60;
| 型号： | K4H510838C-ZCB0 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM, 64MX8, 0.75ns, CMOS, PBGA60 动态存储器 双倍数据速率 |
| 文件： | 总23页 (文件大小：237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
512Mb C-die DDR SDRAM Specification
60 FBGA with Pb-Free
(RoHS compliant)
Revision 0.0
October. 2004
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
512Mb C-die Revision History
Revision 0.0 (October, 2004)
- First version for internal review
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
Key Features
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 60Ball FBGA Pb-Free package
• RoHS compliant
Ordering Information
Part No.
Org.
Max Freq.
Interface
Package
K4H510438C-ZC/LCC
K4H510438C-ZC/LB3
K4H510438C-ZC/LA2
K4H510438C-ZC/LB0
K4H510838C-ZC/LCC
K4H510838C-ZC/LB3
K4H510838C-ZC/LA2
K4H510838C-ZC/LB0
K4H511638C-ZC/LCC
K4H511638C-ZC/LB3
K4H511638C-ZC/LA2
K4H511638C-ZC/LB0
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
128M x 4
SSTL2
60ball FBGA
64M x 8
SSTL2
SSTL2
60ball FBGA
60ball FBGA
32M x 16
Operating Frequencies
CC(DDR400@CL=3)
B3(DDR333@CL=2.5) A2(DDR266@CL=2.0) B0(DDR266@CL=2.5)
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
-
133MHz
166MHz
-
133MHz
133MHz
-
100MHz
133MHz
-
166MHz
200MHz
3-3-3
2.5-3-3
2-3-3
2.5-3-3
*CL : CAS Latency
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
Ball Description (Bottom View)
128M x 4
1
2
3
VSSQ
NC
NC
NC
NC
VREF
VSS
DM
F
NC
VDDQ VSSQ VDDQ VSSQ
CK
CK
G
A12
CKE
H
A11
A9
A8
A7
K
A6
A5
L
A4
VSS
M
VSS
A
DQ3
B
NC
C
DQ2
D
DQS
E
J
7
8
9
VDD
NC
DQ0
NC
DQ1
NC
NC
WE
CAS
RAS
CS
BA1
A0
A2
A1
VDD
A3
VSSQ VDDQ VSSQ VDDQ VDD
BA0 A10/AP
VDDQ
NC
NC
NC
NC
NC
64M x 8
1
2
3
VSSQ
NC
NC
NC
NC
VREF
VSS
DM
F
DQ7
VSS
A
VDDQ VSSQ VDDQ VSSQ
CK
CK
G
A12
CKE
H
A11
A9
A8
A7
K
A6
A5
L
A4
VSS
M
DQ6
B
DQ5
C
DQ4
D
DQS
E
J
7
8
9
VDD
DQ0
VDDQ
DQ1
DQ2
DQ3
NC
NC
WE
CAS
RAS
CS
BA1
A0
A2
A1
VDD
A3
VSSQ VDDQ VSSQ VDDQ VDD
BA0 A10/AP
NC
NC
NC
NC
NC
32M x 16
1
2
3
VSSQ DQ14 DQ12 DQ10
DQ8
VREF
VSS
DQ15 VDDQ VSSQ VDDQ VSSQ
CK
CK
G
A12
CKE
H
A11
A9
A8
A7
K
A6
A5
L
A4
VSS
M
VSS
A
DQ13 DQ11
DQ9
D
UDQS UDM
B
C
E
F
J
7
8
9
VDD
DQ0
VDDQ
DQ2
DQ4
DQ6
LDQS
LDM
WE
CAS
RAS
CS
BA1
A0
A2
A1
VDD
A3
VSSQ VDDQ VSSQ VDDQ VDD
DQ1 DQ3 DQ5 DQ7 NC
BA0 A10/AP
Organization
128Mx4
Row Address
A0~A12
Column Address
A0-A9, A11, A12
A0-A9, A11
A0-A9
64Mx8
A0~A12
32Mx16
A0~A12
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
( Unit : mm )
Package Physical Dimension
10.00 ± 0.10
#A1
1.20 MAX
Top view
10.00 ± 0.10
A
x8
=
0.80
6.40
3.20
0.80
x4 =
WINDOW MOLD AREA
#A1 MARK(option)
0.80 x2= 1.60
0.80 x2 = 1.60
B
9
8
7
6
5
4
3
2
1
0.80
A
B
C
D
E
F
(Datum B)
G
H
J
K
L
M
60-∅0.45 ± 0.05
0.20 M
(0.90)
(0.90)
A
B
(1.80)
(Datum A)
4-CORNER MARK(option)
Bottom view
60Ball FBGA 512Mb Package Dimension
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
Block Diagram (32Mb x 4 / 16Mb x 8 / 8Mb x 16 I/O x 4 Banks)
LWE
x4/8/16
CK, CK
Data Input Register
Serial to parallel
LDM (x4x8)
LUDM (x16)
Bank Select
x8/16/32
16Mx8/ 8Mx16/ 4Mx32
16Mx8/ 8Mx16/ 4Mx32
16Mx8/ 8Mx16/ 4Mx32
16Mx8/ 8Mx16/ 4Mx32
x8/16/32
x4/8/16
x4/8/16
DQi
CK, CK
ADD
Column Decoder
Latency & Burst Length
Data Strobe
Programming Register
LWCBR
LCKE
LDM (x4x8)
LUDM (x16)
LRAS LCBR
LWE
LCAS
CK, CK
DM Input Register
Timing Register
LDM (x4x8)
LUDM (x16)
CK, CK
CKE
CS
RAS
CAS
WE
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
Input/Output Function Description
SYMBOL
TYPE
DESCRIPTION
Clock : CK and CK are differential clock inputs. All address and control input signals are sam-
pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to
both edges of CK. Internal clock signals are derived from CK/CK.
CK, CK
Input
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs,
which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled dur-
ing power-down and self refresh modes, providing low standby power. CKE will recognize an
LVCMOS LOW level prior to VREF being stable on power-up.
CKE
Input
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command
decoder. All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code.
CS
Input
Input
RAS, CAS, WE
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS
loading. For the x16, LDM corresponds to the data on DQ0~D7 ; UDM corresponds to the data
on DQ8~DQ15. DM may be driven high, low, or floating during READs.
DM (x4, x8)
L(U)DM (x16)
Input
Input
Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-
CHARGE command is being applied.
BA0, BA1
Address Inputs : Provide the row address for ACTIVE commands, and the column address and
AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the mem-
ory array in the respective bank. A10 is sampled during a PRECHARGE command to deter-
mine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also
provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which
mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).
A [0 : 12]
Input
DQ
I/O
I/O
Data Input/Output : Data bus
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on
DQ0~D7 ; UDQS corresponds to the data on DQ8~DQ15
DQS (x4, x8)
L(U)DQS (x16)
NC
-
No Connect : No internal electrical connection is present.
DQ Power Supply : +2.5V ± 0.2V. (+2.6V ± 0.1V for DDR400)
DQ Ground.
VDDQ
VSSQ
VDD
Supply
Supply
Supply
Supply
Input
Power Supply : +2.5V ± 0.2V. (+2.6V ± 0.1V for DDR400).
Ground.
VSS
VREF
SSTL_2 reference voltage.
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
Command Truth Table
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
A0 ~ A9,
A11,A12
COMMAND
CKEn-1 CKEn CS RAS CAS
WE BA0,1 A10/AP
Note
Register
Register
Extended MRS
H
H
X
X
H
L
L
L
L
L
L
L
L
L
OP CODE
1, 2
1, 2
3
Mode Register Set
Auto Refresh
OP CODE
H
L
L
L
H
X
Entry
3
Refresh
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit
L
H
H
H
X
X
X
3
Bank Active & Row Addr.
V
V
Row Address
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
4
4
Column
Address
L
H
L
H
Write &
Column Address
4
Column
Address
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
V
H
4, 6
7
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
X
H
5
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
Active Power Down
X
X
X
H
L
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
H
H
X
DM(UDM/LDM for x16 only)
X
X
X
8
9
9
H
L
X
H
X
H
X
H
No operation (NOP) : Not defined
Note :1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
UDM/LDM(x16 only) sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges
(Write UDM/LDM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
32M x 4Bit x 4 Banks / 16M x 8Bit x 4 Banks / 8M x 16Bit x 4 Banks Double Data
Rate SDRAM
General Description
The K4H510438C / K4H510838C / K4H511638C is 536,870,912 bits of double data rate synchronous DRAM organized as 4x
33,554,432 / 4x 16,777,216 / 4x 8,388,608 words by 4/8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Syn-
chronous features with Data Strobe allow extremely high performance up to 400Mb/s per pin. I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful
for a variety of high performance memory system applications.
Absolute Maximum Rating
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD & VDDQ supply relative to VSS
Storage temperature
VDD, VDDQ
TSTG
PD
-1.0 ~ 3.6
-55 ~ +150
1.5
V
°C
W
Power dissipation
Short circuit current
IOS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Symbol
Min
Max
Unit Note
Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333)
Supply voltage(for device with a nominal VDD of 2.6V for DDR400)
VDD
2.3
2.7
V
VDD
2.5
2.7
2.7
V
V
V
I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333)
I/O Supply voltage(for device with a nominal VDD of 2.6V for DDR400)
I/O Reference voltage
VDDQ
VDDQ
VREF
VTT
2.3
2.5
2.7
0.49*VDDQ
VREF-0.04
0.51*VDDQ
VREF+0.04
V
V
1
2
I/O Termination voltage(system)
Input logic high voltage
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VI(Ratio)
II
VREF+0.15
-0.3
VDDQ+0.3
VREF-0.15
VDDQ+0.3
VDDQ+0.6
1.4
V
Input logic low voltage
V
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
V-I Matching: Pullup to Pulldown Current Ratio
Input leakage current
-0.3
V
0.36
0.71
-2
V
3
4
-
2
uA
uA
mA
Output leakage current
IOZ
-5
5
Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V
IOH
-16.8
Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V
Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V
Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
IOL
IOH
IOL
16.8
-9
mA
mA
mA
9
Note :
1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to
peak noise on VREF may not exceed +/-2% of the dc value.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temper-
ature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum
difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to mini-
mum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0.
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
DDR SDRAM Spec Items & Test Conditions
Conditions
Symbol
IDD0
Operating current - One bank Active-Precharge;
tRC=tRCmin; tCK=10ns for DDR200, 7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400;
DQ,DM and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating current - One bank operation ; One bank open, BL=4, Reads
- Refer to the following page for detailed test condition
IDD1
Percharge power-down standby current; All banks idle; power - down mode;
CKE = <VIL(max); tCK=10ns for DDR200,7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400;
Vin = Vref for DQ,DQS and DM.
IDD2P
Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=10ns for DDR200,
7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; Address and other control inputs changing once per clock cycle;
Vin = Vref for DQ,DQS and DM
IDD2F
Precharge Quiet standby current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK=10ns for DDR200, 7.5ns
for DDR266, 6ns for DDR333, 5ns for DDR400; Address and other control inputs stable at >= VIH(min) or =<VIL(max);
Vin = Vref for DQ ,DQS and DM
IDD2Q
IDD3P
IDD3N
Active power - down standby current ; one bank active ; power-down mode; CKE=< VIL (max); tCK=10ns for
DDR200, 7.5ns for DDR266, 6ns for DDR333 , 5ns for DDR400; Vin = Vref for DQ,DQS and DM
Active standby current; CS# >= VIH(min); CKE>=VIH(min); one bank active; active - precharge; tRC=tRASmax;
tCK=10ns for DDR200, 7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; DQ, DQS and DM inputs changing twice
per clock cycle; address and other control inputs changing once per clock cycle
Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control
inputs changing once per clock cycle; CL=2 at tCK=10ns for DDR200, CL=2 at 7.5ns for DDR266(A2), CL=2.5 at 7.5ns
for DDR266(B0), 6ns for DDR333, CL=3 at 5ns for DDR400; 50% of data changing on every transfer; lout = 0 m A
IDD4R
IDD4W
Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address and control
inputs changing once per clock cycle; CL=2 at tCK= 10ns for DDR200, CL=2 at tCK=7.5ns for DDR266(A2), CL=2.5 at
tCK=7.5ns for DDR266(B0), 6ns for DDR333, CL=3 at 5ns for DDR400; DQ, DM and DQS inputs changing twice per
clock cycle, 50% of input data changing at every burst
Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at tCK=10ns; 10*tCK for DDR266 at tCK=7.5ns; 12*tCK
for DDR333 at tCK=6ns14*tCK for DDR400 at tCK=5ns; distributed refresh
IDD5
IDD6
Self refresh current; CKE =< 0.2V; External clock on; tCK = 10ns for DDR200, tCK=7.5ns for DDR266, 6ns for
DDR333, 5ns for DDR400.
Orerating current - Four bank operation ; Four bank interleaving with BL=4
-Refer to the following page for detailed test condition
IDD7A
Input/Output Capacitance
(TA= 25°C, f=100MHz)
Delta
0.5
Parameter
Symbol
Min
Max
Unit
Note
Input capacitance
CIN1
1.5
2.5
pF
4
(A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)
Input capacitance( CK, CK )
CIN2
COUT
CIN3
1.5
3.5
3.5
2.5
4.5
4.5
0.25
pF
pF
pF
4
Data & DQS input/output capacitance
Input capacitance(UDM/LDM)
1,2,3,4
1,2,3,4
0.5
Note :
1.These values are guaranteed by design and are tested on a sample basis only.
2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins.
This is required to match signal propagation times of DQ, DQS, and DM in the system.
3. Unused pins are tied to ground.
4. This parameteer is sampled. For DDR266 and 333, VDDQ = +2.5V +0.2V, VDD = +3.3V +0.3V or +2.5V +0.2V. For DDR400,
VDDQ = +2.6V +0.1V, VDD = +2.6V+0.1V. For all devices, f=100MHz, tA=25°C, Vout(dc) = VDDQ/2, Vout(peak to peak) =
0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to facilitate trace matching at
the board level).
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Worst Case : Vdd = 2.7V, T= 10’ C
2. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
3. Timing patterns
- B0(133Mhz, CL = 2.5) : tCK = 7.5ns, CL = 2.5, BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK
A2 (133Mhz, CL = 2) : tCK = 7.5ns, CL = 2, BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK
Setup : A0 N N R0 N N P0 N N
Read : A0 N N R0 N N P0 N N - repeat the same timing with random address changing
*50% of data changing at every burst
- B3(166Mhz, CL = 2.5) : tCK = 6ns, CL = 2.5, BL = 4, tRCD = 3*tCK, tRC = 10*tCK, tRAS = 7*tCK
Setup : A0 N N R0 N N N P0 N N
Read : A0 N N R0 N N N P0 N N - repeat the same timing with random address changing
*50% of data changing at every burst
- CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK , tRC = 11*tCK, tRAS = 8*tCK
Setup : A0 N N R0 N N N N P0 N N
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP
IDD7A : Operating current: Four bank operation
1. Worst Case : Vdd = 2.7V, T= 10’ C
2. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
3. Timing patterns
- B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL= 2.5, BL= 4, tRRD = 2*tCK, tRCD = 3*tCK, tRAS = 6*tCK Read with autoprecharge
A2(133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Setup : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 - repeat the same timing with random address changing
*50% of data changing at every burst
- B3(166Mhz,CL=2.5) : tCK = 6ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, tRAS = 7*tCK Read with autoprecharge
Setup : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 - repeat the same timing with random address changing
*50% of data changing at every burst
- CC(200Mhz,CL=3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK, tRC = 11*tCK, tRAS = 8*tCK, Read with autoprecharge
Setup : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
DDR SDRAM I spec table
(VDD=2.7V, T = 10°C)
DD
128Mx4 (K4H510438C)
B3(DDR333@CL=2.5)
Symbol
Unit
Notes
A2(DDR266@CL=2.0)
B0(DDR266@CL=2.5)
CC(DDR400@CL=3)
IDD0
IDD1
120
150
5
105
135
5
95
125
5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
30
30
30
25
30
45
125
130
195
5
25
25
45
30
60
45
155
175
220
5
140
150
205
5
Normal
Low power
IDD7A
IDD6
IDD6
IDD6
3
3
3
Optional
385
360
325
64Mx8 (K4H510838C)
B3(DDR333@CL=2.5)
Symbol
Unit
Notes
A2(DDR266@CL=2.0)
B0(DDR266@CL=2.5)
CC(DDR400@CL=3)
IDD0
IDD1
120
150
5
105
135
5
95
125
5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
30
30
30
25
30
45
125
130
195
5
25
25
45
30
60
45
155
175
220
5
140
150
205
5
Normal
Low power
IDD7A
3
3
3
Optional
385
360
325
32Mx16 (K4H511638C)
B3(DDR333@CL=2.5)
Symbol
Unit
Notes
A2(DDR266@CL=2.0)
B0(DDR266@CL=2.5)
CC(DDR400@CL=3)
IDD0
IDD1
120
160
5
105
140
5
95
130
5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
30
30
30
25
30
45
155
160
195
5
25
25
45
30
60
45
190
215
220
5
170
185
205
5
Normal
Low power
IDD7A
3
3
3
Optional
400
380
345
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
AC Operating Conditions
Parameter/Condition
Symbol
VIH(AC)
VIL(AC)
VID(AC)
Min
Max-10
Unit
V
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and /CK inputs
VREF + 0.31
VREF - 0.31
VDDQ+0.6
V
0.7
V
1
2
Input Crossing Point Voltage, CK and /CK inputs
VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2
V
Notes :
1. VID is the magnitude of the difference between the input level on CK and the input level on /CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
AC Overshoot/Undershoot specification for Address and Control Pins
Parameter
Specification
DDR333
DDR200/266
1.5 V
Maximum peak amplitude allowed for overshoot
TBD
TBD
TBD
TBD
Maximum peak amplitude allowed for undershoot
1.5 V
The area between the overshoot signal and VDD must be less than or equal to
The area between the undershoot signal and GND must be less than or equal to
4.5 V-ns
4.5 V-ns
VDD
Overshoot
5
4
3
Maximum Amplitude = 1.5V
2
Area = 4.5V-ns
1
0
-1
-2
Maximum Amplitude = 1.5V
GND
-3
-4
-5
0
0.6875
0.5 1.0
1.5
2.5
3.5
4.5
5.5
6.3125
6.0 6.5
undershoot
7.0
2.0
3.0
4.0
5.0
Tims(ns)
AC overshoot/Undershoot Definition
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
Overshoot/Undershoot specification for Data, Strobe, and Mask Pins
Specification
Parameter
DDR333
DDR200/266
1.2 V
Maximum peak amplitude allowed for overshoot
TBD
TBD
TBD
TBD
Maximum peak amplitude allowed for undershoot
1.2 V
The area between the overshoot signal and VDD must be less than or equal to
The area between the undershoot signal and GND must be less than or equal to
2.4 V-ns
2.4 V-ns
VDDQ
Overshoot
5
Maximum Amplitude = 1.2V
4
3
2
Area = 2.4V-ns
1
0
-1
-2
Maximum Amplitude = 1.2V
GND
-3
-4
-5
0
0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0
Tims(ns)
undershoot
DQ/DM/DQS AC overshoot/Undershoot Definition
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
AC Timming Parameters & Specifications
CC
B3
A2
B0
(DDR400@CL=3.0) (DDR333@CL=2.5) (DDR266@CL=2.0) (DDR266@CL=2.5)
Parameter
Symbol
Unit Note
Min
55
Max
Min
60
Max
Min
65
Max
Min
65
Max
Row cycle time
tRC
tRFC
tRAS
tRCD
tRP
ns
ns
ns
ns
ns
ns
ns
tCK
ns
ns
Refresh row cycle time
Row active time
70
72
75
75
40
70K
42
70K
45
120K
45
120K
RAS to CAS delay
15
18
20
20
Row precharge time
15
18
20
20
Row active to Row active delay
Write recovery time
tRRD
tWR
10
12
15
15
15
15
15
15
Last data in to Read command
tWTR
2
1
1
1
CL=2.0
CL=2.5
CL=3.0
-
-
7.5
6
12
12
7.5
7.5
-
12
12
10
12
12
Clock cycle time
tCK
6
12
7.5
-
5
10
-
-
-
-
Clock high level width
tCH
tCL
0.45
0.45
-0.55
-0.65
-
0.55
0.55
+0.55
+0.65
0.4
0.45
0.45
-0.6
-0.7
-
0.55
0.55
+0.6
+0.7
0.45
1.1
0.45
0.45
-0.75
-0.75
-
0.55
0.55
+0.75
+0.75
0.5
0.45
0.45
-0.75
-0.75
-
0.55
0.55
+0.75
+0.75
0.5
tCK
tCK
ns
Clock low level width
DQS-out access time from CK/CK
tDQSCK
tAC
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
ns
22
13
0.9
0.4
0.72
0
1.1
0.9
0.4
0.75
0
0.9
0.4
0.75
0
1.1
0.9
0.4
0.75
0
1.1
tCK
tCK
tCK
ns
Read Postamble
0.6
0.6
0.6
0.6
CK to valid DQS-in
1.25
1.25
1.25
1.25
DQS-in setup time
DQS-in hold time
0.25
0.2
0.2
0.35
0.35
0.6
0.6
0.25
0.2
0.2
0.35
0.35
0.75
0.75
0.25
0.2
0.2
0.35
0.35
0.9
0.9
0.25
0.2
0.2
0.35
0.35
0.9
0.9
tCK
tCK
tCK
tCK
tCK
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
tDSH
tDQSH
tDQSL
tIS
DQS-in low level width
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup
ns 15, 17~19
ns 15, 17~19
tIH
tIS
0.7
0.8
1.0
1.0
ns
16~19
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
tIH
tHZ
0.7
-
0.8
-
1.0
-
1.0
-
ns
ns
ns
ns
ns
ns
16~19
11
+0.65
+0.65
+0.7
+0.7
+0.75
+0.75
+0.75
+0.75
tLZ
-0.65
10
-0.7
12
-0.75
15
-0.75
15
11
tMRD
tDS
DQ & DM setup time to DQS
0.4
0.45
0.5
0.5
j, k
j, k
DQ & DM hold time to DQS
tDH
0.4
0.45
0.5
0.5
Control & Address input pulse width
DQ & DM input pulse width
tIPW
tDIPW
tXSNR
tXSRD
tREFI
2.2
1.75
75
2.2
1.75
75
2.2
1.75
75
2.2
1.75
75
ns
ns
18
18
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
ns
200
200
200
200
tCK
us
7.8
7.8
7.8
7.8
-
14
21
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
Output DQS valid window
Clock half period
tQH
tHP
-
-
-
ns
ns
tCLmin
or tCHmin
tCLmin
or tCHmin
tCLmin
or tCHmin
tCLmin
or tCHmin
-
-
-
-
20, 21
Data hold skew factor
tQHS
0.5
0.6
0.55
0.6
0.75
0.6
0.75
0.6
ns
21
12
DQS write postamble time
tWPST
0.4
15
0.4
18
0.4
20
0.4
20
tCK
Active to Read with Auto precharge
command
tRAP
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
Autoprecharge write recovery +
Precharge time
tDAL
tCK
23
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR333, DDR266 & DDR200 devices to ensure
proper system performance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS
DDR333
DDR266
DDR200
PARAMETER
SYMBOL
DCSLEW
MIN
TBD
MAX
TBD
MIN
TBD
MAX
TBD
MIN
0.5
MAX
4.0
Units
V/ns
Notes
a, m
DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate
0.5 V/ns
∆tIS
0
∆tIH
0
Units
ps
Notes
i
i
i
0.4 V/ns
+50
+100
0
ps
0.3 V/ns
0
ps
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Input Slew Rate
0.5 V/ns
∆tDS
0
∆tDH
0
Units
ps
Notes
k
k
k
0.4 V/ns
+75
+150
+75
+150
ps
0.3 V/ns
ps
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Delta Slew Rate
+/- 0.0 V/ns
∆tDS
0
∆tDH
0
Units
ps
Notes
j
j
j
+/- 0.25 V/ns
+/- 0.5 V/ns
+50
+100
+50
+100
ps
ps
Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Slew Rate Characteristic
Notes
Pullup Slew Rate
Pulldown slew
1.2 ~ 2.5
1.2 ~ 2.5
1.0
1.0
4.5
4.5
a,c,d,f,g,h
b,c,d,f,g,h
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Slew Rate Characteristic
Notes
Pullup Slew Rate
Pulldown slew
1.2 ~ 2.5
1.2 ~ 2.5
0.7
0.7
5.0
5.0
a,c,d,f,g,h
b,c,d,f,g,h
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS DDR266B
DDR200
PARAMETER
Output Slew Rate Matching Ratio (Pullup to Pulldown)
MIN
TBD
MAX
TBD
MIN
0.67
MAX
1.5
Notes
e,m
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
Component Notes
1. All voltages referenced to Vss.
2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels,
but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be
either a precise representation of the typical system environment nor a depiction of the actual load presented by a production
tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment.
Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester elec-
tronics).
VDDQ
50Ω
Output
(Vout)
30pF
Figure 1 : Timing Reference Load
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to
VREF (or to the crossing point for CK/CK), and parameter specifications are guaranteed for the specified ac input levels under nor-
mal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac).
5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result
of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc
input LOW (HIGH) level.
6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.2VDDQ is
recognized as LOW.
7. Enables on.chip refresh and address counters.
8. IDD specifications are tested after the device is properly initialized.
9. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level
for signals other than CK/CK, is VREF.
10. The output timing reference voltage level is VTT.
11. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to
a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys
tem performance (bus turnaround) will degrade accordingly.
13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A
valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ
ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could
be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
15. For command/address input slew rate ≥ 1.0 V/ns
16. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
Component Notes
17. For CK & CK slew rate ≥ 1.0 V/ns
18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by
device design or tester correlation.
19. Slew Rate is measured between VOH(ac) and VOL(ac).
20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the
period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into
the clock traces.
21. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The
pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-
channel to n-channel variation of the output drivers.
22. tDQSQ
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle.
23. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and
tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3)
tDAL = 5 clocks
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
System Notes :
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2.
Test point
Output
50Ω
VSSQ
Figure 2 : Pullup slew rate test load
b. Pulldown slew rate is measured under the test conditions shown in Figure 3.
VDDQ
50Ω
Output
Test point
Figure 3 : Pulldown slew rate test load
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)
Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output
switching.
Example : For typical slew rate, DQ0 is switching
For minmum slew rate, all DQ bits are switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
d. Evaluation conditions
Typical : 25 °C (T Ambient), VDDQ = 2.5V(for DDR266/333) and 2.6V(for DDR400), typical process
Minimum : 70 °C (T Ambient), VDDQ = 2.3V(for DDR266/333) and 2.5V(for DDR400), slow - slow process
Maximum : 0 °C (T Ambient), VDDQ = 2.7V(for DDR266/333) and 2.7V(for DDR400), fast - fast process
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and
voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
f. Verified under typical conditions for qualification purposes.
g. TSOPII package divices only.
h. Only intended for operation up to 266 Mbps per pin.
i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns
as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or
VIH(DC) to VIL(DC), similarly for rising transitions.
j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4.
Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the
slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
The delta rise/fall rate is calculated as:
{1/(Slew Rate1)} - {1/(Slew Rate2)}
For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this
would result in the need for an increase in tDS and tDH of 100 ps.
k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser
on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter
mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.
m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
tions through the DC region must be monotonic.
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
IBIS :I/V Characteristics for Input and Output Buffers
DDR SDRAM Output Driver V-I Characteristics
DDR SDRAM Output driver characteristics are defined for full and half strength operation as selected by the EMRS bit A1.
Figures 3 and 4 show the driver characteristics graphically, and tables 8 and 9 show the same data in tabular format suitable for input
into simulation tools. The driver characteristcs evaluation conditions are:
Typical
Minimum
Maximum
25×C
70×C
0×C
Vdd/Vddq = 2.5V, typical process
Vdd/Vddq = 2.3V, slow-slow process
Vdd/Vddq = 2.7V, fast-fast process
Output Driver Characteristic Curves Notes:
1. The full variation in driver current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines
the of the V-I curve of Figure 3 and 4.
2. It is recommended that the "typical" IBIS V-I curve lie within the inner bounding lines of the V-I curves of Figure 3 and 4.
3. The full variation in the ratio of the "typical" IBIS pullup to "typical" IBIS pulldown current should be unity +/- 10%, for device drain to
source voltages from 0.1 to1.0. This specification is a design objective only. It is not guaranteed.
160
Maximum
140
120
Typical High
100
80
Typical Low
Minimum
60
40
20
0
0.0
0.5
1.0
1.5
2.0
2.5
Vout(V)
Pullup Characteristics for Full Strength Output Driver
0.0
1.0
2.0
0
-20
Minumum
-40
Typical Low
-60
-80
-100
-120
-140
-160
-180
-200
-220
Typical High
Maximum
Vout(V)
Pulldown Characteristics for Full Strength Output Driver
Figure 4. I/V characteristics for input/output buffers:Pull up(above) and pull down(below)
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
Pulldown Current (mA)
pullup Current (mA)
Voltage
(V)
Typical
Low
Typical
High
Typical
Low
Typical
High
Minimum
Maximum
Minimum
Maximum
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
6.0
6.8
13.5
20.1
26.6
33.0
39.1
44.2
49.8
55.2
60.3
65.2
69.9
74.2
78.4
82.3
85.9
89.1
92.2
95.3
97.2
99.1
100.9
101.9
102.8
103.8
104.6
105.4
4.6
9.6
-6.1
-7.6
-4.6
-10.0
-20.0
12.2
18.1
24.1
29.8
34.6
39.4
43.7
47.5
51.3
54.1
56.2
57.9
59.3
60.1
60.5
61.0
61.5
62.0
62.5
62.9
63.3
63.8
64.1
64.6
64.8
65.0
9.2
18.2
-12.2
-18.1
-24.0
-29.8
-34.3
-38.1
-41.1
-41.8
-46.0
-47.8
-49.2
-50.0
-50.5
-50.7
-51.0
-51.1
-51.3
-51.5
-51.6
-51.8
-52.0
-52.2
-52.3
-52.5
-52.7
-52.8
-14.5
-9.2
13.8
18.4
23.0
27.7
32.2
36.8
39.6
42.6
44.8
46.2
47.1
47.4
47.7
48.0
48.4
48.9
49.1
49.4
49.6
49.8
49.9
50.0
50.2
50.4
50.5
26.0
-21.2
-13.8
-18.4
-23.0
-27.7
-32.2
-36.0
-38.2
-38.7
-39.0
-39.2
-39.4
-39.6
-39.9
-40.1
-40.2
-40.3
-40.4
-40.5
-40.6
-40.7
-40.8
-40.9
-41.0
-41.1
-41.2
-29.8
33.9
-27.7
-38.8
41.8
-34.1
-46.8
49.4
-40.5
-54.4
56.8
-46.9
-61.8
63.2
-53.1
-69.5
69.9
-59.4
-77.3
76.3
-65.5
-85.2
82.5
-71.6
-93.0
88.3
-77.6
-100.6
-108.1
-115.5
-123.0
-130.4
-136.7
-144.2
-150.5
-156.9
-163.2
-169.6
-176.0
-181.3
-187.6
-192.9
-198.2
93.8
-83.6
99.1
-89.7
103.8
108.4
112.1
115.9
119.6
123.3
126.5
129.5
132.4
135.0
137.3
139.2
140.8
-95.5
-101.3
-107.1
-112.4
-118.7
-124.0
-129.3
-134.6
-139.9
-145.2
-150.5
-155.3
-160.1
Table 8. Full Strength Driver Characteristics
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
90
80
70
60
50
40
30
20
10
0
Maximum
Typical High
Typical Low
Minimum
0.0
1.0
2.0
Vout(V)
Pullup Characteristics for Weak Output Driver
0.0
1.0
2.0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
Minumum
Typical Low
Typical High
Maximum
Vout(V)
Pulldown Characteristics for Weak Output Driver
Figure 5. I/V characteristics for input/output buffers:Pull up(above) and pull down(below)
Rev. 0.0 October. 2004
Preliminary
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
Pulldown Current (mA)
pullup Current (mA)
Voltage
(V)
Typical
Low
Typical
High
Typical
Low
Typical
High
Minimum
Maximum
Minimum
Maximum
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3.4
3.8
2.6
5.0
-3.5
-4.3
-2.6
-5.0
6.9
7.6
5.2
9.9
-6.9
-8.2
-5.2
-9.9
10.3
13.6
16.9
19.6
22.3
24.7
26.9
29.0
30.6
31.8
32.8
33.5
34.0
34.3
34.5
34.8
35.1
35.4
35.6
35.8
36.1
36.3
36.5
36.7
36.8
11.4
15.1
18.7
22.1
25.0
28.2
31.3
34.1
36.9
39.5
42.0
44.4
46.6
48.6
50.5
52.2
53.9
55.0
56.1
57.1
57.7
58.2
58.7
59.2
59.6
7.8
14.6
19.2
23.6
28.0
32.2
35.8
39.5
43.2
46.7
50.0
53.1
56.1
58.7
61.4
63.5
65.6
67.7
69.8
71.6
73.3
74.9
76.4
77.7
78.8
79.7
-10.3
-13.6
-16.9
-19.4
-21.5
-23.3
-24.8
-26.0
-27.1
-27.8
-28.3
-28.6
-28.7
-28.9
-28.9
-29.0
-29.2
-29.2
-29.3
-29.5
-29.5
-29.6
-29.7
-29.8
-29.9
-12.0
-15.7
-19.3
-22.9
-26.5
-30.1
-33.6
-37.1
-40.3
-43.1
-45.8
-48.4
-50.7
-52.9
-55.0
-56.8
-58.7
-60.0
-61.2
-62.4
-63.1
-63.8
-64.4
-65.1
-65.8
-7.8
-14.6
-19.2
-23.6
-28.0
-32.2
-35.8
-39.5
-43.2
-46.7
-50.0
-53.1
-56.1
-58.7
-61.4
-63.5
-65.6
-67.7
-69.8
-71.6
-73.3
-74.9
-76.4
-77.7
-78.8
-79.7
10.4
13.0
15.7
18.2
20.8
22.4
24.1
25.4
26.2
26.6
26.8
27.0
27.2
27.4
27.7
27.8
28.0
28.1
28.2
28.3
28.3
28.4
28.5
28.6
-10.4
-13.0
-15.7
-18.2
-20.4
-21.6
-21.9
-22.1
-22.2
-22.3
-22.4
-22.6
-22.7
-22.7
-22.8
-22.9
-22.9
-23.0
-23.0
-23.1
-23.2
-23.2
-23.3
-23.3
Table 9. Weak Driver Characteristics
Rev. 0.0 October. 2004
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