K4H561638D-TCC4 [SAMSUNG]
256Mb D-die DDR400 SDRAM Specification; 256Mb的D-死DDR400 SDRAM规格
| 型号： | K4H561638D-TCC4 |
| 厂家： | 
SAMSUNG |
| 描述： | 256Mb D-die DDR400 SDRAM Specification |
| 文件： | 总18页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM
256Mb D-die DDR400 SDRAM Specification
Revision 1.1
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM
256Mb D-die Revision History
Revison 0.0 (June. 2002)
1. First release
Revison 0.1 (Aug. 2002)
- Changed IDD3P value from 40mA to 55m
- Changed IDD3N value from 60mA to 75mA
Revision 1.0 (February, 2003)
- Modified AC Timing Parameters and Idd value.
Revision 1.1 (February, 2003)
- Modified tAC value +/-0.7ns => +/-0.65ns
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM
Key Features
• 200MHz Clock, 400Mbps data rate.
• VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
Ordering Information
Part No.
Org.
Max Freq.
CC(DDR400@CL=3)
C4(DDR400@CL=3)
CC(DDR400@CL=3)
C4(DDR400@CL=3)
Interface
Package
K4H560838D-TCCC
K4H560838D-TCC4
K4H561638D-TCCC
K4H561638D-TCC4
32M x 8
SSTL2
66pin TSOP II
16M x 16
SSTL2
66pin TSOP II
Operating Frequencies
- CC(DDR400@CL=3)
200MHz
- C4(DDR400@CL=3)
200MHz
Speed @CL3
CL-tRCD-tRP
3 - 3 - 3
3 - 4 - 4
*CL : CAS Latency
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM
Pin Description
16Mb x 16
32Mb x 8
V
SS
VSS
1
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
V
DD
VDD
V
DD
NC
DQ7
2
DQ15
DQ
0
NC
DDQ
NC
DQ
0
VSSQ
VSSQ
3
V
SSQ
VDDQ
V
VDDQ
NC
DQ
NC
DQ
DQ14
DQ13
4
NC
DQ
1
2
3
6
5
DQ
1
DQ
0
DQ
VDDQ
VDDQ
VDDQ
6
VSSQ
VSSQ
VSSQ
NC
NC
NC
DQ
DQ12
DQ11
7
NC
NC
NC
DDQ
NC
DQ
3
4
5
8
DQ
2
DDQ
NC
DQ
VSSQ
VSSQ
VSSQ
9
V
V
VDDQ
NC
DQ
NC
DQ
DQ10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
DQ
5
6
66Pin TSOPII
(400mil x 875mil)
(0.65mm Pin Pitch)
2
4
DQ
9
DQ
3
DQ
1
DQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
NC
NC
NC
NC
DQ
NC
8
NC
NC
DDQ
NC
NC
NC
NC
DDQ
NC
NC
DQ
7
NC
Bank Address
BA0~BA1
VSSQ
VSSQ
VSSQ
V
V
VDDQ
DQS
NC
DQS
NC
UDQS
NC
LDQS
NC
Auto Precharge
A10
V
REF
SS
V
REF
SS
V
REF
SS
VDD
VDD
VDD
V
V
V
NC
NC
NC
NC
NC
LDM
WE
DM
CK
DM
CK
UDM
CK
WE
CAS
RAS
CS
WE
CAS
RAS
CS
CK
CK
CK
CAS
RAS
CS
CKE
NC
CKE
NC
CKE
NC
24
25
26
27
28
29
30
31
32
33
A
A
A
A
A
A
A
A
V
12
11
9
A
A
A
A
A
A
A
A
V
12
11
9
A
A
A
A
A
A
A
A
V
12
11
9
NC
NC
NC
BA
0
1
BA
0
1
BA
0
1
BA
BA
BA
8
8
8
AP/A10
AP/A10
AP/A10
7
7
7
A
A
A
A
0
1
2
3
A0
A1
A2
A3
A
A
A
A
0
1
2
3
6
6
6
5
5
5
4
4
4
SS
SS
SS
VDD
VDD
VDD
256Mb Package Pinout
Organization
32Mx8
Row Address
A0~A12
Column Address
A0-A9
16Mx16
A0~A12
A0-A8
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM
Package Physical Demension
Units : Millimeters
#66
#34
(10×
)
(10×)
#1
#33
+0.075
-0.035
0.125
(1.50)
22.22±0.10
(10
×
)
)
0.10 MAX
0.25TYP
(0.71)
0.65TYP
0.65 0.08
0.30±0.08
[
]
0.075 MAX
±
(10×
NOTE
1. (
0×~8×
) IS REFERENCE
2. [
] IS ASS’Y OUT QUALITY
66pin TSOPII / Package dimension
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM
Block Diagram (8Mbx8 / 4Mbx16 I/O x 4 Banks)
(L)WE
8 /16
LDM(x8)
CK, CK
Data Input Register
Serial to parallel
LL(U)DM(x16)
Bank Select
16/ 32
4Mx16/ 2Mx32
4Mx16/ 2Mx32
4Mx16/ 2Mx32
4Mx16/ 2Mx32
16/32
8/16
x8/x16
DQi
CK, CK
ADD
Column Decoder
Latency & Burst Length
Data Strobe
Programming Register
LWCBR
LCKE
LRAS LCBR
LWE
LL(U)DM(x16)
LDM(x8)
LCAS
CK, CK
DM Input Register
Timing Register
DM(x8)
CK, CK
CKE
CS
RAS
CAS
WE
L(U)DM(x16)
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM
Input/Output Function Description
SYMBOL
TYPE
DESCRIPTION
Clock : CK and CK are differential clock inputs. All address and control input signals are sam-
pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to
both edges of CK. Internal clock signals are derived from CK/CK.
CK, CK
Input
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs,
which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled dur-
ing power-down and self refresh modes, providing low standby power. CKE will recognize an
LVCMOS LOW level prior to VREF being stable on power-up.
CKE
Input
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command
decoder. All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code.
CS
Input
Input
RAS, CAS, WE
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS
loading. For the x16, LDM corresponds to the data on DQ0~D7 ; UDM corresponds to the data
on DQ8~DQ15. DM may be driven high, low, or floating during READs.
LDM,(UDM)
BA0, BA1
Input
Input
Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-
CHARGE command is being applied.
Address Inputs : Provide the row address for ACTIVE commands, and the column address and
AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the mem-
ory array in the respective bank. A10 is sampled during a PRECHARGE command to deter-
mine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also
provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which
mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).
A12 & A13 are used on device densities of 256Mb and greater, and A13 is used only on 1Gb
decices.
A [0 : 12]
Input
DQ
I/O
I/O
Data Input/Output : Data bus
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on
DQ0~D7 ; UDQS corresponds to the data on DQ8~DQ15
LDQS,(U)DQS
NC
-
No Connect : No internal electrical connection is present.
DQ Power Supply : +2.6V ± 0.1V.
DQ Ground.
VDDQ
VSSQ
VDD
Supply
Supply
Supply
Supply
Input
Power Supply : +2.6V ± 0.1V (device specific).
Ground.
VSS
VREF
SSTL_2 reference voltage.
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM
Command Truth Table
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
A0 ~ A9,
COMMAND
Extended MRS
CKEn-1 CKEn CS RAS CAS
WE BA0,1 A10/AP
Note
A11, A12
OP CODE
OP CODE
Register
Register
H
H
X
X
H
L
L
L
L
L
L
L
L
L
1, 2
1, 2
3
Mode Register Set
Auto Refresh
H
L
L
L
H
X
Entry
3
Refresh
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit
L
H
H
H
X
X
X
3
Bank Active & Row Addr.
V
V
Row Address
Read &
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
4
4
Column
Address
L
H
L
H
Column Address
Write &
4
Column
Address
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
V
Column Address
H
4, 6
7
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
X
H
5
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
Active Power Down
X
X
X
H
L
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
H
H
DM(UDM/LDM for x16 only)
X
X
X
8
9
9
H
L
X
H
X
H
X
H
No operation (NOP) : Not defined
X
Note :1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
UDM/LDM(x16 only) sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges
(Write UDM/LDM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM
8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks Double Data Rate SDRAM
General Description
The K4H560838D / K4H561638D is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 8,388,608 / 4x 4,194,304
words by 8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 400Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequen-
cies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory
system applications.
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD & VDDQ supply relative to VSS
Storage temperature
VDD, VDDQ
TSTG
PD
-1.0 ~ 3.6
-55 ~ +150
1.5
V
°C
W
Power dissipation
Short circuit current
IOS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Symbol
Min
Max
2.7
Unit
Note
Supply voltage(for device with a nominal VDD of 2.5V)
VDD
2.5
5
5
1
2
I/O Supply voltage
VDDQ
VREF
VTT
2.5
2.7
V
V
I/O Reference voltage
I/O Termination voltage(system)
0.49*VDDQ
VREF-0.04
0.51*VDDQ
VREF+0.04
V
Input logic high voltage
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VI(Ratio)
II
VREF+0.15
-0.3
VDDQ+0.3
VREF-0.15
VDDQ+0.3
VDDQ+0.6
1.4
V
Input logic low voltage
V
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
V-I Matching: Pullup to Pulldown Current Ratio
Input leakage current
-0.3
V
0.36
0.71
-2
V
3
4
-
2
uA
uA
mA
Output leakage current
IOZ
-5
5
Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V
IOH
-16.8
Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V
Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V
Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
IOL
IOH
IOL
16.8
-9
mA
mA
mA
9
Note :
1.VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same.
Peak-to peak noise on VREF may not exceed +/-2% of the dc value.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the
maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the
maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.
5. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20MHz. Any noise above 20MHz at the DRAM
generated from any source other than the DRAM itself may not exceed the DC voltage range of 2.6V +/-100mV.
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM
DDR SDRAM Spec Items & Test Conditions
Conditions
Conditions
Symbol
Symbol
Operating current - One bank Active-Precharge;
tRC=tRCmin; tCK=5ns for DDR400; DQ,DM and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles; CS = high between valid commands.
IDD0
Operating current - One bank operation ; One bank open, BL=4, Reads
- Refer to the following page for detailed test condition; CS = high between valid commands.
IDD1
Percharge power-down standby current; All banks idle; power - down mode; CKE = <VIL(max); tCK=5ns for
DDR400; Vin = Vref for DQ,DQS and DM.
IDD2P
Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=5ns for DDR400;
Address and other control inputs changing once per clock cycle; Vin = Vref for DQ,DQS and DM
IDD2F
IDD2Q
IDD3P
IDD3N
Precharge Quiet standby current; CS# > = VIH(min); All banks idle;
CKE > = VIH(min); tCK=5ns for DDR400; Address and other control inputs stable at >= VIH(min) or =<VIL(max);
Vin = Vref for DQ ,DQS and DM
Active power - down standby current ; one bank active; power-down mode; CKE=< VIL (max); tCK=5ns
DDR400; Vin = Vref for DQ,DQS and DM
Active standby current; CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax; tCK=5ns for DDR400; DQ, DQS and DM inputs changing twice
per clock cycle; address and other control inputs changing once per clock cycle
Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control
inputs changing once per clock cycle; CL=3 at 5ns for DDR400; 50% of data changing on every transfer; lout = 0 m
A
IDD4R
IDD4W
Operating current - burst write; Burst length = 2; writes; continuous burst;
One bank active address and control inputs changing once per clock cycle; CL=3 at tCK=5ns for DDR400; DQ, DM
and DQS inputs changing twice per clock cycle, 50% of input data changing at every transfer
Auto refresh current; tRC = tRFC(min) - 14*tCK for DDR400 at tCK=5ns;
Self refresh current; CKE =< 0.2V; External clock on; tCK = 5ns for DDR400.
IDD5
IDD6
Input/Output Capacitance
(VDD=2.6, VDDQ=2.6V, TA= 25°C, f=1MHz)
Delta
0.5
Parameter
Symbol
Min
Max
Unit
Note
Input capacitance
CIN1
2
3
pF
4
(A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)
Input capacitance( CK, CK )
CIN2
COUT
CIN3
2
4
4
3
5
5
0.25
pF
pF
pF
4
Data & DQS input/output capacitance
Input capacitance(DM for 8, UDM/LDM for x16)
1,2,3,4
1,2,3,4
0.5
Note :
1.These values are guaranteed by design and are tested on a sample basis only.
2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins.
This is required to match signal propagation times of DQ, DQS, and DM in the system.
3. Unused pins are tied to ground.
4. This parameteer is sampled. VDDQ = +2.6V +0.1V, VDD = +2.6V +0.1V, f=100MHz, tA=25°C, Vout(dc) =
VDDQ/2, Vout(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading
(to facilitate trace matching at the board level).
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM
DDR SDRAM I spec table
(VDD=2.7V, T = 10°C)
DD
32Mx8
16Mx16
Symbol
Unit Notes
- CC(DDR400@CL=3) - C4(DDR400@CL=3) - CC(DDR400@CL=3) - C4(DDR400@CL=3)
IDD0
IDD1
105
130
4
100
130
4
110
150
4
105
145
4
mA
mA
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
mA
30
30
30
30
mA
25
25
25
25
mA
55
55
55
55
mA
75
75
75
75
mA
185
220
200
3
185
220
200
3
220
250
200
3
220
250
200
3
mA
mA
mA
IDD6
Normal
Low power
IDD7A
mA
1.5
350
1.5
350
1.5
380
1.5
380
mA Optional
mA
< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs change logic state once per Deselect cycle.
Iout = 0mA
2. Timing patterns
- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
Setup : A0 N N R0 N N N N P0 N N
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
IDD7A : Operating current: Four bank operation
1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on Deselet edge are not changing.
Iout = 1mA
2. Timing patterns
- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
Setup : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
Legend : A = Activate, R=Read, W=Write, P=Precharge, N=NOP
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM
AC Operating Conditions
Parameter/Condition
Symbol
VIH(AC)
VIL(AC)
VID(AC)
Min
Max-10
Unit
V
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
VREF + 0.31
VREF - 0.31
VDDQ+0.6
V
0.7
V
1
2
Input Crossing Point Voltage, CK and CK inputs
VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2
V
Notes :
1. VID is the magnitude of the difference between the input level on CK and the input level on /CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
AC Overshoot/Undershoot specification for Address and Control Pins
Parameter
Specification
DDR400
1.5V
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
1.5V
The area between the overshoot signal and VDD must be less than or equal to
The area between the undershoot signal and GND must be less than or equal to
4.5V-ns
4.5V-ns
VDD
Overshoot
5
4
3
Maximum Amplitude = 1.5V
2
Area = 4.5V-ns
1
0
-1
-2
Maximum Amplitude = 1.5V
GND
-3
-4
-5
0
0.6875
0.5 1.0
1.5
2.5
3.5
4.5
5.5
6.3125
6.0 6.5
undershoot
7.0
2.0
3.0
4.0
5.0
Tims(ns)
AC overshoot/Undershoot Definition
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM
Overshoot/Undershoot specification for Data, Strobe, and Mask Pins
Specification
DDR400
1.2V
Parameter
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
1.2V
The area between the overshoot signal and VDD must be less than or equal to
The area between the undershoot signal and GND must be less than or equal to
2.5V-ns
2.5V-ns
VDDQ
Overshoot
5
Maximum Amplitude = 1.2V
4
3
2
Area = 2.5V-ns
1
0
-1
-2
Maximum Amplitude = 1.2V
GND
-3
-4
-5
0
0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0
Tims(ns)
undershoot
DQ/DM/DQS AC overshoot/Undershoot Definition
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM
AC Timing Parameters and Specifications
- CC(DDR400@CL=3)
- C4(DDR400@CL=3)
Parameter
Symbol
Unit
Note
Min
55
Max
Min
60
Max
Row cycle time
tRC
tRFC
tRAS
tRCD
tRP
ns
ns
Refresh row cycle time
Row active time
70
70
40
70K
40
70K
ns
RAS to CAS delay
15
18
ns
Row precharge time
15
18
ns
Row active to Row active delay
Write recovery time
tRRD
tWR
10
10
ns
15
15
ns
Internal write to read command delay
tWTR
2
2
tCK
ns
CL=3.0
CL=2.5
5
10
12
5
10
12
Clock cycle time
tCK
16
13
6
6
ns
Clock high level width
Clock low level width
tCH
tCL
0.45
0.45
-0.55
-0.65
-
0.55
0.55
+0.55
+0.65
0.4
0.45
0.45
-0.55
-0.65
-
0.55
0.55
+0.55
+0.65
0.4
tCK
tCK
ns
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
tDQSCK
tAC
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tWPST
tDSS
ns
0.9
0.4
0.72
0
1.1
0.9
0.4
0.72
0
1.1
tCK
tCK
tCK
ps
Read Postamble
0.6
0.6
CK to valid DQS-in
1.28
1.28
Write preamble setup time
Write preamble
5
4
0.25
0.4
0.2
0.2
0.35
0.25
0.4
0.2
0.2
0.35
tCK
tCK
tCK
tCK
tCK
tCK
ns
Write postamble
0.6
0.6
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
tDSH
tDQSH
DQS-in low level width
tDQSL
tIS
0.35
0.6
0.35
0.6
Address and Control Input setup time
Address and Control Input hold time
h,7~10
h,7~10
tIH
0.6
0.6
ns
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
tHZ
tLZ
-
tAC max
tAC max
-
tAC max
tAC max
ns
3
3
tAC min
2
tAC min
2
ns
tMRD
tDS
tCK
ns
DQ & DM setup time to DQS, slew rate 0.5V/ns
DQ & DM hold time to DQS, slew rate 0.5V/ns
DQ & DM input pulse width
0.4
0.4
i, j
i, j
9
tDH
0.4
0.4
ns
tDIPW
tIPW
1.75
2.2
1.75
2.2
ns
Control & Address input pulse width for each input
ns
9
Up to 128Mb
Refresh interval time
15.6
7.8
15.6
7.8
us
tREFI
6
256Mb, 512Mb, 1Gb
us
tHP
-tQHS
tHP
-tQHS
Output DQS valid window
Clock half period
tQH
tHP
-
-
-
-
ns
ns
12
min
tCH/tCL
min
tCH/tCL
11, 12
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM
- CC(DDR400@CL=3)
- C4(DDR400@CL=3)
Parameter
Data hold skew factor
Symbol
Unit
Note
Min
Max
0.5
-
Min
Max
0.5
-
tQHS
tDAL
ns
ns
12
14
15
Auto Precharge write recovery + precharge time
Exit self refresh to non-READ command
Exit self refresh to READ command
-
-
tXSNR
tXSRD
75
75
ns
200
-
200
-
tCK
Component Notes
1.VID is the magnitude of the difference between the input level on CK and the input level on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
3. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a
specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ).
4. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys
tem performance (bus turnaround) will degrade accordingly.
5. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A
valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ
ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could
be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
6. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
7. For command/address input slew rate ≥ 0.5 V/ns
8. For CK & CK slew rate ≥ 0.5 V/ns
9. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by
device design or tester correlation.
10. Slew Rate is measured between VOH(ac) and VOL(ac).
11. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the
period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into
the clock traces.
12. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The
pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-
channel to n-channel variation of the output drivers.
13. tDQSQ
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given
cycle.
14. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR400(CC) at CL=3 and
tCK=5ns tDAL = (15 ns / 5 ns) + (15 ns/ 5ns) = {(3) + (3)}CLK
tDAL = 6 clocks
15. In all circumstances, tXSNR can be satisfied using tXSNR=tRFCmin+1*tCK
16. The only time that the clock frequency is allowed to change is during self-refresh mode.
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM
System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR400 devices to ensure proper system perfor-
mance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS
DDR400
PARAMETER
SYMBOL
DCSLEW
MIN
0.5
MAX
4.0
UNITS NOTES
V/ns a, k
DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate
0.5 V/ns
tIS
0
tIH
0
UNITS
ps
NOTES
h
h
h
0.4 V/ns
+50
+100
0
ps
0.3 V/ns
0
ps
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Input Slew Rate
0.5 V/ns
tDS
0
tDH
0
UNITS
ps
NOTES
j
j
j
0.4 V/ns
+75
+150
+75
+150
ps
0.3 V/ns
ps
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Delta Slew Rate
+/- 0.0 V/ns
tDS
0
tDH
0
UNITS
ps
NOTES
i
i
i
+/- 0.25 V/ns
+/- 0.5 V/ns
+50
+100
+50
+100
ps
ps
Table 5 : Output Slew Rate Characteristice (X8 Devices only)
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Slew Rate Characteristic
NOTES
Pullup Slew Rate
Pulldown slew
1.2 ~ 2.5
1.2 ~ 2.5
1.0
1.0
4.5
4.5
a,c,d,f,g
b,c,d,f,g
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Slew Rate Characteristic
NOTES
Pullup Slew Rate
Pulldown slew
1.2 ~ 2.5
1.2 ~ 2.5
0.7
0.7
5.0
5.0
a,c,d,f,g
b,c,d,f,g
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS DDR400
PARAMETER
Output Slew Rate Matching Ration (Pullup to Pulldown)
MIN
-
MAX
-
NOTES
e,k
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM
System Notes :
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.
Test point
Output
50Ω
VSSQ
Figure 1 : Pullup slew rate test load
b. Pulldown slew rate is measured under the test conditions shown in Figure 2.
VDDQ
50Ω
Output
Test point
Figure 2 : Pulldown slew rate test load
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)
Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output
switching.
Example : For typical slew rate, DQ0 is switching
For minmum slew rate, all DQ bits are switching from either high to low, or low to high.
For Maximum slew rate, only one DQ is switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
d. Evaluation conditions
Typical : 25 °C (T Ambient), VDDQ = 2.6V, typical process
Minimum : 70 °C (T Ambient), VDDQ = 2.5V, slow - slow process
Maximum : 0 °C (T Ambient), VDDQ = 2.7V, fast - fast process
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and
voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
f. Verified under typical conditions for qualification purposes.
g. TSOPII package divces only.
h. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5
V/ns as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or
VIH(DC) to VIL(DC), similarly for rising transitions.
i. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4.
Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the
slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
The delta rise/fall rate is calculated as:
{1/(Slew Rate1)} - {1/(Slew Rate2)}
For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this
would result in the need for an increase in tDS and tDH of 100 ps.
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM
j. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser
on the lesser of the AC ~ AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter
mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.
k. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
tions through the DC region must be monotonic.
Rev. 1.1 Feb. 2003
相关型号：
K4H561638D-TLB00
DDR DRAM, 16MX16, 0.75ns, CMOS, PDSO66, 0.400 X 0.875, 0.65 MM PITCH, MS-024FC, TSOP2-66
SAMSUNG
K4H561638D-TLB30
DDR DRAM, 16MX16, 0.7ns, CMOS, PDSO66, 0.400 X 0.875, 0.65 MM PITCH, MS-024FC, TSOP2-66
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