K4R761869A-FCS9 [SAMSUNG]
Rambus DRAM, 32MX18, 35ns, CMOS, PBGA92, WBGA-92;
| 型号： | K4R761869A-FCS9 |
| 厂家： | 
SAMSUNG |
| 描述： | Rambus DRAM, 32MX18, 35ns, CMOS, PBGA92, WBGA-92 动态存储器 内存集成电路 |
| 文件： | 总20页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
512/576Mbit RDRAM(A-die)
1M x 16/18bit x 32s banks
Short channel Direct RDRAMTM
Version 1.4
July 2002
Version 1.4 July 2002
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
Change History
Version 1.4( July 2002) - Preliminary
- First Copy ( Version 1.4 is named to unify the version of component and device operation datasheets)
- Based on the 256/288Mb D-die for Short Channel datasheet version 1.4
Version 1.4 July 2002
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
Overview
The Rambus Direct RDRAM™ is a general purpose high-
performance memory device suitable for use in a broad
range of applications including computer memory, graphics,
video, and any other application where high bandwidth and
low latency are required.
SAMSUNG 320
The 512/576-Mbit Direct Rambus DRAMs (RDRAMâ ) are
extremely high-speed CMOS DRAMs organized as 32M
words by 16 or 18 bits. The use of Rambus Signaling Level
(RSL) technology permits up to 1066 MHz transfer rates
while using conventional system and board design technolo-
gies. Direct RDRAM devices are capable of sustained data
transfers up to at 0.938ns per two bytes (7.5ns per sixteen
bytes).
K4RXXXX69A-Fxxx
The architecture of the Direct RDRAMs allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The Direct RDRAM's 32 banks
support up to four simultaneous transactions.
Figure 1: Direct RDRAM CSP Package
The 512/576-Mbit Direct RDRAMs are offered in a CSP
horizontal package suitable for desktop as well as low-
profile add-in card and mobile applications.
System oriented features for mobile, graphics and large
memory systems include power management, byte masking,
and x18 organization. The two data bits in the x18 organiza-
tion are general and can be used for additional storage and
bandwidth or for error correction.
Key Timing Parameters/Part Numbers
Speed
t
Features
RAC
I/O
Bin Freq.
MHz
Organization
Part Number
(Row
Access
Time) ns
¨ Highest sustained bandwidth per DRAM device
- 2.1GB/s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
1Mx16x32sa
1Mx18x32s
K4R521669A-FbCcS9
K4R761869A-FCS9
-CS9
-CS9
1066
1066
35
35
- Separate row and column control buses for
easy scheduling and highest performance
- 32 banks: four transactions can take place simul-
taneously at full bandwidth data rates
a.“32s” - 32 banks which use a “split” bank architecture.
b.“F” - WBGA package.
¨ Low latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
c.“C” - RDRAM core uses normal power self refresh.
¨ Advanced power management:
- Multiple low power states allows flexibility in power
consumption versus time to transition to active state
- Power-down self-refresh
¨ Organization: 2kbyte pages and 32 banks, x 16/18
- x18 organization allows ECC configurations or
increased storage/bandwidth
- x16 organization for low cost applications
¨ Uses Rambus Signaling Level (RSL) for up to 1066MHz
operation
Version 1.4 July 2002
Page 1
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
Pinouts and Definitions
Center-Bonded Devices
package are shown in a later section. Refer to Section
“Center-Bonded WBGA Package” on page 18. Note - pin #1
is at the A1 position.
These tables shows the pin assignments of the center-bonded
RDRAM package. The mechanical dimensions of this
Table 1: Center-Bonded Device (top view)
V
GND
V
GND
V
V
V
V
GND
V
DD
DD
DD
DD
DD
D D
DD
10
9
GND
V
C M D
V
G N D
GNDa
DQA1
GNDa
CTMN
V
V
G N D
R Q 5
GND
R Q 3
V
V
GND
G N D
V
V
GND
DD
D D
DD
D D
DD
DD
C M O S
DD
8
V
DQA8
DQA7
DQA5
DQA3
CTM
RQ7
RQ1
DQB1
DQB3
DQB5
DQB7
DQB8
V
DD
D D
7
6
5
GND
G N D
G N D
DQA6
SCK
DQA4
DQA2
G N D
DQA0
CFM
G N D
CFMN
RQ6
R Q 4
G N D
R Q 2
RQ0
DQB0
GND
DQB2
DQB4
S I O 0
DQB6
SIO1
G N D
G N D
GND
4
V
V
V
V
V
V
G N D
V
V
D D
C M O S
D D
DDa
R E F
D D
D D
DD
3
2
V
GND
G N D
V
G N D
G N D
GND
GND
GND
V
DD
D D
DD
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
T
U
ROW
COL
SAMSUNG 320
K4RXXXX69A-Fxxx
Top View
Chip
The pin #1(ROW 1, COL A) is located at the
A1 position on the top side and the A1 position
is marked by the marker “ ”.
Version 1.4 July 2002
Page 2
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
Table 2: Pin Description
# Pins
center
Signal
I/O
Type
Description
Serial input/output. Pins for reading from and writing to the control regis-
ters using a serial access protocol. Also used for power management.
a
SIO1,SIO0
I/O
CMOS
CMOS
CMOS
2
Command input. Pins used in conjunction with SIO0 and SIO1 for reading
from and writing to the control registers. Also used for power manage-
ment.
a
a
CMD
SCK
I
I
1
1
Serial clock input. Clock source used for reading from and writing to the
control registers
V
24
1
Supply voltage for the RDRAM core and interface logic.
Supply voltage for the RDRAM analog circuitry.
Supply voltage for CMOS input/output pins.
DD
V
DDa
V
2
CMOS
GND
28
2
Ground reference for RDRAM core and interface.
Ground reference for RDRAM analog circuitry.
GNDa
Data byte A. Nine pins which carry a byte of read or write data between
the Channel and the RDRAM. DQA8 is not used (no connection) by
RDRAMs with a x16 organization.
b
DQA8..DQA0
I/O
RSL
9
1
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Positive polarity.
b
CFM
I
I
RSL
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Negative polarity
b
CFMN
RSL
1
1
1
V
Logic threshold reference voltage for RSL signals
REF
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Negative polarity.
b
CTMN
CTM
I
I
I
I
RSL
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Positive polarity.
b
RSL
1
3
5
RQ7..RQ5 or
ROW2..ROW0
Row access control. Three pins containing control and address informa-
tion for row accesses.
b
RSL
RQ4..RQ0 or
COL4..COL0
Column access control. Five pins containing control and address informa-
tion for column accesses.
b
RSL
Data byte B. Nine pins which carry a byte of read or write data between
the Channel and the RDRAM. DQB8 is not used (no connection) by
RDRAMs with a x16 organization.
DQB8..
DQB0
b
I/O
RSL
9
Total pin count per package
92
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
Version 1.4 July 2002
Page 3
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
RQ7..RQ5 or
ROW2..ROW0
RQ4..RQ0 or
COL4..COL0
5
DQB8..DQB0
9
CTM CTMN SCK,CMD SIO0,SIO1 CFM CFMN
DQA8..DQA0
9
3
2
2
RCLK
RCLK
1:8 Demux
1:8 Demux
TCLK
RCLK
6
Packet Decode
Control Registers
Packet Decode
COLC
ROWR
11
ROWA
9
COLX
5
COLM
5
5
5
5
5
5
7
8
8
ROP DR BR
AV
R
REFR
DEVID
XOP DX BX COP DC BC
C
MB MA
Power Modes
M
S
Match
Mux
Match
Match
Write
Buffer
DM
Row Decode
XOP Decode
PRER
ACT
PREX
Mux
Mux
Column Decode & Mask
PREC
RD, WR
DRAM Core
Sense Amp
64x72
64x72 1024x128x144
64x72
72
Internal DQB Data Path
72
Internal DQA Data Path
72
72
Bank 0
Bank 1
Bank 2
9
9
9
9
Bank 13
Bank 14
Bank 15
9
9
Bank 16
Bank 17
Bank 18
9
9
9
9
Bank 29
Bank 30
Bank 31
Figure 2: 512/576-Mbit (1Mx16/18x32s) Direct RDRAM Block Diagram
Version 1.4 July 2002
Page 4
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
amps of the RDRAM. These pins are de-multiplexed into a
24-bit ROWA (row-activate) or ROWR (row-operation)
packet.
General Description
Figure2 is a block diagram of the 512/576-Mbit Direct
RDRAM. It consists of two major blocks: a “core” block
built from banks and sense amps similar to those found in
other types of DRAM, and a Direct Rambus interface block
which permits an external controller to access this core at up
to 2.1GB/s.
COL Pins: The principle use of these five pins is to
manage the transfer of data between the DQA/DQB pins and
the sense amps of the RDRAM. These pins are de-multi-
plexed into a 23-bit COLC (column-operation) packet and
either a 17-bit COLM (mask) packet or a 17-bit COLX
(extended-operation) packet.
Control Registers: The CMD, SCK, SIO0, and SIO1
pins appear in the upper center of Figure2. They are used to
write and read a block of control registers. These registers
supply the RDRAM configuration information to a
controller and they select the operating modes of the device.
The REFR value is used for tracking the last refreshed row.
Most importantly, the five bit DEVID specifies the device
address of the RDRAM on the Channel.
ACT Command: An ACT (activate) command from an
ROWA packet causes one of the 1024 rows of the selected
bank to be loaded to its associated sense amps (two 512
bytes sense amps for DQA and two for DQB).
PRER Command:A PRER (precharge) command from
an ROWR packet causes the selected bank to release its two
associated sense amps, permitting a different row in that
bank to be activated, or permitting adjacent banks to be acti-
vated.
Clocking: The CTM and CTMN pins (Clock-To-Master)
generate TCLK (Transmit Clock), the internal clock used to
transmit read data. The CFM and CFMN pins (Clock-From-
Master) generate RCLK (Receive Clock), the internal clock
signal used to receive write data and to receive the ROW and
COL pins.
RD Command: The RD (read) command causes one of
the 128 dualocts of one of the sense amps to be transmitted
on the DQA/DQB pins of the Channel.
DQA,DQB Pins: These 16/18 pins carry read (Q) and
write (D) data across the Channel. They are multiplexed/de-
multiplexed from/to two 64/72-bit data paths (running at
one-eighth the data frequency) inside the RDRAM.
WR Command: The WR (write) command causes a
dualoct received from the DQA/DQB data pins of the
Channel to be loaded into the write buffer. There is also
space in the write buffer for the BC bank address and C
column address information. The data in the write buffer is
automatically retired (written with optional bytemask) to one
of the 128 dualocts of one of the sense amps during a subse-
quent COP command. A retire can take place during a RD,
WR, or NOCOP to another device, or during a WR or
NOCOP to the same device. The write buffer will not retire
during a RD to the same device. The write buffer reduces the
delay needed for the internal DQA/DQB data path turn-
around.
Banks: The 64Mbyte core of the RDRAM is divided into
thirty two 2Mbyte banks, each organized as 1024 rows, with
each row containing 128 dualocts, and each dualoct
containing 16/18 bytes. A dualoct is the smallest unit of data
that can be addressed.
Sense Amps: The RDRAM contains 34 sense amps. Each
sense amp consists of 1kbyte of fast storage (512 bytes for
DQA and 512 bytes for DQB) and can hold one-half of one
row of one bank of the RDRAM. The sense amp may hold
any of the 2048 half-rows of an associated bank. However,
each sense amp is shared between two adjacent banks of the
RDRAM (except for sense amps 0, 15, 16, and 31). This
introduces the restriction that adjacent banks may not be
simultaneously accessed.
PREC Precharge: The PREC, RDA and WRA
commands are similar to NOCOP, RD and WR, except that a
precharge operation is performed at the end of the column
operation. These commands provide a second mechanism
for performing precharge.
PREX Precharge: After a RD command, or after a WR
command with no byte masking (M=0), a COLX packet may
be used to specify an extended operation (XOP). The most
important XOP command is PREX. This command provides
a third mechanism for performing precharge.
RQ Pins: These pins carry control and address informa-
tion. They are broken into two groups. RQ7..RQ5 are also
called ROW2..ROW0, and are used primarily for controlling
row accesses. RQ4..RQ0 are also called COL4..COL0, and
are used primarily for controlling column accesses.
ROW Pins: The principle use of these three pins is to
manage the transfer of data between the banks and the sense
Version 1.4 July 2002
Page 5
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
The AV (ROWA/ROWR packet selection) bit distinguishes
between the two packet types. Both the ROWA and ROWR
packet provide a five bit device address and a five bit bank
address. An ROWA packet uses the remaining bits to
specify a nine bit row address, and the ROWR packet uses
the remaining bits for an eleven bit opcode field. Note the
use of the “RsvX” notation to reserve bits for future address
field extension.
Packet Format
Figure3 shows the formats of the ROWA and ROWR
packets on the ROW pins. Table3 describes the fields which
comprise these packets. DR4T and DR4F bits are encoded to
contain both the DR4 device address bit and a framing bit
which allows the ROWA or ROWR packet to be recognized
by the RDRAM.
Table 3: Field Description for ROWA Packet and ROWR Packet
Description
Field
DR4T,DR4F
DR3..DR0
BR4..BR0
AV
Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit.
Device address for ROWA or ROWR packet.
Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the RDRAM.
Selects between ROWA packet (AV=1) and ROWR packet (AV=0).
R9..R0
Row address for ROWA packet. RsvR denotes bits ignored by the RDRAM.
Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions.
ROP10..ROP0
Figure3 also shows the formats of the COLC, COLM, and
COLX packets on the COL pins. Table4 describes the fields
which comprise these packets.
The remaining 17 bits are interpreted as a COLM (M=1) or
COLX (M=0) packet. A COLM packet is used for a COLC
write command which needs bytemask control. The COLM
packet is associated with the COLC packet from at least
The COLC packet uses the S (Start) bit for framing. A
COLM or COLX packet is aligned with this COLC packet,
and is also framed by the S bit.
t
earlier. A COLX packet may be used to specify an
RTR
independent precharge command. It contains a five bit
device address, a five bit bank address, and a five bit opcode.
The COLX packet may also be used to specify some house-
keeping and power management commands. The COLX
packet is framed within a COLC packet but is not otherwise
associated with any other packet.
The 23 bit COLC packet has a five bit device address, a five
bit bank address, a seven bit column address, and a four bit
opcode. The COLC packet specifies a read or write
command, as well as some power management commands.
Table 4: Field Description for COLC Packet, COLM Packet, and COLX Packet
Field
Description
S
Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets.
Device address for COLC packet.
DC4..DC0
BC4..BC0
C6..C0
Bank address for COLC packet. RsvB denotes bits reserved for future extension (controller drives 0 ’ s).
Column address for COLC packet. RsvC denotes bits ignored by the RDRAM.
Opcode field for COLC packet. Specifies read, write, precharge, and power management functions.
Selects between COLM packet (M=1) and COLX packet (M=0).
COP3..COP0
M
MA7..MA0
MB7..MB0
DX4..DX0
BX4..BX0
XOP4..XOP0
Bytemask write control bits. 1=write, 0=no-write. MA0 controls the earliest byte on DQA8..0.
Bytemask write control bits. 1=write, 0=no-write. MB0 controls the earliest byte on DQB8..0.
Device address for COLX packet.
Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drives 0’ s).
Opcode field for COLX packet. Specifies precharge, I control, and power management functions.
OL
Version 1.4 July 2002
Page 6
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
T0
T1
T2
T3
T8
T9
T10
T11
CTM/CFM
CTM/CFM
ROW2 DR4T DR2 BR0 BR3 RsvR R8
R5
R4
R3
R2
R1
R0
ROW2 DR4T DR2 BR0 BR3 ROP10 ROP8 ROP5 ROP2
ROW1
ROW0
DR1 BR1 BR4 R9
R7
ROW1
ROW0
DR1 BR1 BR4 ROP9 ROP7 ROP4 ROP1
DR0 BR2 RsvB AV=0 ROP6 ROP3 ROP0
DR4F
DR3
DR4F
DR3
DR0 BR2 RsvB AV=1 R6
ROWA Packet
ROWR Packet
T0
T1
T2
T3
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
1 4 1 5
0
1
2
3
4
5
6
7
8
9
1 0
1 1 12
13
CTM/CFM
CTM/CFM
ROW2
DC4 S=1
DC3
C6
C5
C4
C3
ACT a0
WR b1
PRER c0
COL4
COL3
COL2
COL1
COL0
..ROW0
t
PACKET
MSK (b1) PREX d0
COL4
..COL0
DC2 COP1
DC1 COP0
DC0 COP2
RsvB BC2 C2
BC4 BC1 C1
DQA8..0
DQB8..0
COP3 BC3 BC0 C0
COLC Packet
T8
T9
T10
T11
T12
T13
T14
T15
CTM/CFM
CTM/CFM
COL4
COL3
COL2
COL1
S=1a MA7 MA5 MA3 MA1
M=1 MA6 MA4 MA2 MA0
MB7 MB4 MB1
COL4
COL3
COL2
COL1
COL0
S=1b DX4 XOP4 RsvB BX1
M=0 DX3 XOP3 BX4 BX0
DX2 XOP2 BX3
MB6 MB3 MB0
DX1 XOP1 BX2
COL0
MB5 MB2
DX0 XOP0
b
a
The COLX is aligned
The COLM is associated with a
previous COLC, and is aligned
with the present COLC, indicated
by the Start bit (S=1) position.
with the present COLC,
COLM Packet
COLX Packet
indicated by the Start
bit (S=1) position.
Figure 3: Packet Formats
Version 1.4 July 2002
Page 7
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
broadcast operation is indicated when both bits are set.
Broadcast operation would typically be used for refresh and
power management commands. If the device is selected, the
DM (DeviceMatch) signal is asserted and an ACT or ROP
command is performed.
Field Encoding Summary
Table5 shows how the six device address bits are decoded
for the ROWA and ROWR packets. The DR4T and DR4F
encoding merges a fifth device bit with a framing bit. When
neither bit is asserted, the device is not selected. Note that a
Table 5: Device Field Encodings for ROWA Packet and ROWR Packet
DR4T
DR4F
Device Selection
Device Match signal (DM)
1
0
1
0
1
1
0
0
All devices (broadcast)
One device selected
One device selected
No packet present
DM is set to 1
DM is set to 1 if {DEVID4..DEVID0} == {0,DR3..DR0} else DM is set to 0
DM is set to 1 if {DEVID4..DEVID0} == {1,DR3..DR0} else DM is set to 0
DM is set to 0
Table6 shows the encodings of the remaining fields of the
ROWA and ROWR packets. An ROWA packet is specified
by asserting the AV bit. This causes the specified row of the
specified bank of this device to be loaded into the associated
sense amps.
row address comes from an internal register REFR, and
REFR is incremented at the largest bank address. The REFP
(refresh-precharge) command is identical to a PRER
command.
The NAPR, NAPRC, PDNR, ATTN, and RLXR commands
are used for managing the power dissipation of the RDRAM
and are described in more detail in “Power State Manage-
ment” on page50. The TCEN and TCAL commands are
used to adjust the output driver slew rate and they are
described in more detail in “Current and Temperature
Control” on page56.
An ROWR packet is specified when AV is not asserted. An
11 bit opcode field encodes a command for one of the banks
of this device. The PRER command causes a bank and its
two associated sense amps to precharge, so another row or
an adjacent bank may be activated. The REFA (refresh-acti-
vate) command is similar to the ACT command, except the
Table 6: ROWA Packet and ROWR Packet Field Encodings
ROP10..ROP0 Field
a
DM
AV
Name
Command Description
10
9
8
7
6
5
4
3
2:0
0
-
-
-
-
-
-
-
-
-
---
-
No operation.
1
1
1
0
Row address
ACT
Activate row R9..R0 of bank BR4..BR0 of device and move device to ATTNb.
Precharge bank BR4..BR0 of this device.
1
0
1
0
0
0
0
1
0
1
xc
0
x
0
x
x
000 PRER
000 REFA
Refresh (activate) row REFR8..REFR0 of bank BR4..BR0 of device.
Increment REFR if BR4..BR0 = 11111 (see Figure52).
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
x
x
x
x
x
0
0
0
0
x
x
x
x
x
0
0
0
1
0
0
0
x
x
0
0
0
0
0
0
0
x
x
0
0
0
1
0
0
0
x
x
0
0
0
0
0
1
1
x
x
0
0
0
0
1
0
1
x
x
0
0
0
x
x
x
x
0
1
x
x
0
000 REFP
000 PDNR
000 NAPR
Precharge bank BR4..BR0 of this device after REFA (see Figure52).
Move this device into the powerdown (PDN) power state (see Figure49).
Move this device into the nap (NAP) power state (see Figure49).
000 NAPRC Move this device into the nap (NAP) power state conditionally
000 ATTNb
000 RLXR
001 TCAL
010 TCEN
Move this device into the attention (ATTN) power state (see Figure47).
Move this device into the standby (STBY) power state (see Figure48).
Temperature calibrate this device (see Figure55).
Temperature calibrate/enable this device (see Figure55).
000 NOROP No operation.
a. The DM (Device Match signal) value is determined by the DR4T,DR4F, DR3..DR0 field of the ROWA and ROWR packets. See Table5.
b. The ATTN command does not cause a RLX-to-ATTN transition for a broadcast operation (DR4T/DR4F=1/1).
c. An “x” entry indicates which commands may be combined. For instance, the three commands PRER/NAPRC/RLXR may be specified in one ROP va lue (011000111000).
Version 1.4 July 2002
Page 8
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
Table7 shows the COP field encoding. The device must be
in the ATTN power state in order to receive COLC packets.
The COLC packet is used primarily to specify RD (read) and
WR (write) commands. Retire operations (moving data from
the write buffer to a sense amp) happen automatically. See
Figure18 for a more detailed description.
The COLC packet can also specify a PREC command,
which precharges a bank and its associated sense amps. The
RDA/WRA commands are equivalent to combining RD/WR
with a PREC. RLXC (relax) performs a power mode transi-
tion. See “Power State Management” on page50.
Table 7: COLC Packet Field Encodings
DC4.. DC0
(select device)
S
COP3..0 Name
Command Description
a
0
----
-----
-
-
No operation.
Retire write buffer of this device.
1
1
1
1
1
1
1
1
1
1
/= (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
-----
x000b
x001
x010
x011
x100
x101
x110
x111
1xxx
NOCOP Retire write buffer of this device.
WR
Retire write buffer of this device, then write column C6..C0 of bank BC4..BC0 to write buffer.
RSRV
RD
Reserved, no operation.
Read column C6..C0 of bank BC4..BC0 of this device.
Retire write buffer of this device, then precharge bank BC4..BC0 (see Figure15).
Same as WR, but precharge bank BC4..BC0 after write buffer (with new data) is retired.
Reserved, no operation.
PREC
WRA
RSRV
RDA
RLXC
Same as RD, but precharge bank BC4..BC0 afterward.
Move this device into the standby (STBY) power state (see Figure48).
a. “/=” means not equal, “==” means equal.
b. An“x” entry indicates which commands may be combined. For instance, the two commands WR/RLXC may be specified in one COP value (1001) .
Table8 shows the COLM and COLX field encodings. The
M bit is asserted to specify a COLM packet with two 8 bit
bytemask fields MA and MB. If the M bit is not asserted, an
COLX is specified. It has device and bank address fields,
and an opcode field. The primary use of the COLX packet is
to permit an independent PREX (precharge) command to be
specified without consuming control bandwidth on the ROW
pins. It is also used for the CAL(calibrate) and SAM (sam-
ple) current control commands (see “Current and Tempera-
ture Control” on page56), and for the RLXX power mode
command (see “Power State Management” on page50).
Table 8: COLM Packet and COLX Packet Field Encodings
DX4 .. DX0
(selects device)
M
XOP4..0
Name
MSK
Command Description
1
----
-
-
MB/MA bytemasks used by WR/WRA.
0
0
0
0
0
0
0
/= (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
-
No operation.
00000
1xxx0a
x10x0
x11x0
xxx10
xxxx1
NOXOP
PREX
CAL
No operation.
Precharge bank BX3..BX0 of this device (see Figure15).
Calibrate (drive) IOL current for this device (see Figure54).
Calibrate (drive) and Sample ( update) IOL current for this device (see Figure54).
Move this device into the standby (STBY) power state (see Figure48).
Reserved, no operation.
CAL/SAM
RLXX
RSRV
a. An “x” entry indicates which commands may be combined. For instance, the two commands PREX/RLXX may be specified in one XOP value (100 10).
Version 1.4 July 2002
Page 9
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
Electrical Conditions
Table 9: Electrical Conditions
Symbol
Parameter and Conditions
Junction temperature under bias
Min
Max
Unit
TJ
-
100
2.50 + 0.13
2.0
°C
V
VDD, VDDA
Supply voltage
2.50 - 0.13
VDD,N, VDDA ,N
vDD,N, vDDA,N
Supply voltage droop (DC) during NAP interval (tNLIMIT
Supply voltage ripple (AC) during NAP interval (tNLIMIT
)
)
-
%
%
-2.0
2.0
a
VCMOS
Supply voltage for CMOS pins (2.5V controllers)
Supply voltage for CMOS pins (1.8V controllers)
VDD
1.80 - 0.1
VDD
1.80 + 0.2
V
V
VREF
Reference voltage
1.40 - 0.2
VREF - 0.5
VREF + 0.2
0.67
1.40 + 0.2
VREF - 0.2
VREF + 0.5
1.00
V
V
V
-
VDIL
RSL data input - low voltage @ tCYCLE =1.875ns
RSL data input - high voltageb @ tCYCLE =1.875ns
VDIH
RDA
RSL data asymmetry : RDA = (VDIH - VREF ) / (VREF - VDIL
RSL clock input - common mode VCM = (VCIH+VCIL) /2
)
VCM
1.3
1.8
V
V
V
V
V
VCIS,CTM
VCIS,CFM
VIL,CMOS
VIH,CMOS
RSL clock input swing: VCIS = VCIH - VCIL (CTM,CTMN pins).
RSL clock input swing: VCIS = VCIH - VCIL (CFM,CFMN pins).
CMOS input low voltage
0.35
1.00
0.225
1.00
- 0.3c
VCMOS/2 - 0.25
VCMOS+0.3d
CMOS input high voltage
VCMOS/2 + 0.25
a. VCMOS must remain on as long as VDD is applied and cannot be turned off.
b. VDIH is typically equal to VTERM (1.8V±0.1V) under DC conditions in a system.
c. Voltage undershoot is limited to -0.7V for a duration of less than 5ns.
d. Voltage overshoot is limited toVCMOS +0.7V for a duration of less than 5ns
Version 1.4 July 2002
Page 10
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
Electrical Characteristics
Table 10: Electrical Characteristics
Symbol
Parameter and Conditions
Junction-to-Case thermal resistance
Min
Max
Unit
QJC
-
0.5
10
°C/Watt
mA
IREF
IOH
VREF current @ VREF,MAX
-10
RSL output high current @ (0£VOUT£VDD
)
-10
10
mA
a
IALL
DIOL
rOUT
RSL IOL current @ tCYCLE = 1.875ns VOL = 0.9V, VDD,MIN , TJ,MAX
RSL IOL current resolution step
30.0
90.0
2.0
-
mA
mA
W
-
150
Dynamic output impedance @ VOL= 0.9V
IOL,NOM
RSL IOL current @ VOL = 1.0V b,c@ tCYCLE =1.875ns
26.6
30.6
10.0
0.3
-
mA
mA
II,CMOS
CMOS input leakage current @ (0£VI,CMOS£ VCMOS
)
-10.0
-
VOL,CMOS
VOH,CMOS
CMOS output voltage @ IOL,CMOS= 1.0mA
V
CMOS output high voltage @ IOH,CMOS= -0.25mA
VCMOS-0.3
V
a. This measurement is made in manual current control mode; i.e. with all output device legs sinking current.
b. This measurement is made in automatic current control mode after at least 64 current control calibration operations to a device and after CCA and
CCB are initialized to a value of 64. This value applies to all DQA and DQB pins.
c. This measurement is made in automatic current control mode in a 25W test system with VTERM= 1.714V and VREF= 1.357V and with the ASYMA
and ASYMB register fields set to 0.
Version 1.4 July 2002
Page 11
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
Timing Conditions
Table 11: Timing Conditions
Symbol
tCYCLE
Parameter
CTM and CFM cycle times (-1066)
Min
Max
Unit
Figure(s)
1.875
2.5
ns
Figure56
CTM and CFM input rise and fall times. Use the minimum value of
these parameters during testing.
tC R, tCF
tC H, tCL
tTR
0.2
0.5
ns
Figure56
Figure56
CTM and CFM high and low times
40%
60%
tCYCLE
tCYCLE
tCYCLE
ns
CTM-CFM differential (MSE/MS=0/0)
CTM-CFM differential (MSE/MS=1/1)a
0.0
0.9
1.0
1.0
Figure43
Figure56
tDCW
Domain crossing window
-0.1
0.2
0.1
Figure62
Figure57
DQA/DQB/ROW/COL input rise/fall times (20% to 80%). Use the
minimum value of these parameters during testing.@ t CYCLE=1.875ns
tD R, tDF
0.65
tS , tH
DQA/DQB/ROW/COL-to-CFM set/hold @ t CYCLE=1.875ns
SIO0, SIO1 input rise and fall times
0.190b
-
-
ns
ns
ns
Figure57
Figure59
Figure59
tDR1, tDF1
tDR2, tDF2
5.0
CMD, SCK input rise and fall times
-
2.0
SCK cycle time - Serial control register transactions
SCK cycle time - Power transitions @ t CYCLE=1.875ns
SCK high and low times @ t CYCLE=1.875ns
CMD setup time to SCK rising or falling edge c @ t CYCLE=1.875ns
CMD hold time to SCK rising or falling edged
SIO0 setup time to SCK falling edge
1000
7.5
4.25
1.25
1
-
tCYCLE1
ns
Figure59
-
tCH1 , tCL1
-
ns
ns
Figure59
Figure59
Figure59
Figure59
Figure59
Figure50
Figure60
Figure50
Figure50
Figure49
Figure54
Figure54
Figure50
Figure49
Figure48
Figure47
Figure52
tS 1
-
tH1
-
ns
tS 2
40
40
0
-
ns
tH2
SIO0 hold time to SCK falling edge
-
ns
tS 3
PDEV setup time on DQA5..0 to SCK rising edge.
PDEV hold time on DQA5..0 to SCK rising edge.
ROW2..0, COL4..0 setup time for quiet window
ROW2..0, COL4..0 hold time for quiet windowd
Quiet on ROW/COL bits during NAP/PDN entry
Offset between read data and CC packets (same device)
Offset between CC packet and read data (same device)
CTM/CFM stable before NAP/PDN exit
-
ns
tH3
5.5
-1
-
ns
tS 4
-
tCYCLE
tCYCLE
tCYCLE
tCYCLE
tCYCLE
tCYCLE
tCYCLE
tCYCLE
ms
tH4
5
-
tNPQ
4
-
tREADTOCC
tCCSAMTOREAD
tC E
12
8
-
-
2
-
-
tC D
CTM/CFM stable after NAP/PDN entry
100
7
tFRM
ROW packet to COL packet ATTN framing delay
Maximum time in NAP mode
-
tNLIMIT
tREF
tBURST
tCCTRL
10.0
32
Refresh interval
ms
Interval after PDN or NAP (with self-refresh) exit in which all banks
of the RDRAM must be refreshed at least once.
200
ms
Figure53
Figure54
Current control interval
34 tCYCLE
100ms
ms/tCYCLE
Version 1.4 July 2002
Page 12
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
Table 11: Timing Conditions
Symbol
tTEMP
Parameter
Temperature control interval
Min
Max
Unit
Figure(s)
100
ms
Figure55
Figure55
Figure55
Figure55
tTCEN
TCE command to TCAL command
TCAL command to quiet window
Quiet window (no read data)
150
2
-
tCYCLE
tCYCLE
tCYCLE
tTCAL
2
-
tTCQUIET
140
tPAUSE
RDRAM delay (no RSL operations allowed)
200.0
ms
page 38
a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0.
b. tS,MIN and tH,MIN for other tCYCLE values can be interpolated between or extrapolated from the timings at the 2 specified t
c. With VIL,CMOS=0.5VCMOS-0.4V and VIH,CMOS=0.5VCMOS+0.4V
values.
CYCLE
d. Effective hold becomes tH4’ =tH4+[PDNXA•64•tSCYCLE+tPDNXB,MAX]-[PDNX•256•tSCYCLE
if [PDNX•256•tSCYCLE] < [PDNXA•64•tSCYCLE+tPDNXB,MAX ]. See Figure50.
]
Version 1.4 July 2002
Page 13
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
Timing Characteristics
Table 12: Timing Characteristics
Symbol
Parameter
Min
Max
Unit
Figure(s)
tQ
tQ R, tQF
tQ1
CTM-to-DQA/DQB output time @ tCYCLE=1.875ns
DQA/DQB output rise and fall times @ tCYCLE=1.875ns
SCK(neg)-to-SIO0 delay @ CLOAD,MAX = 20pF (SD read data valid).
SCK(pos)-to-SIO0 delay @ CLOAD,MAX = 20pF (SD read data hold).
SIOOUT rise/fall @ CLOAD,MAX = 20pF
SIO0-to-SIO1 or SIO1-to-SIO0 delay @ CLOAD,MAX = 20pF
NAP exit delay - phase A
-0.240a
+0.240a
ns
ns
Figure58
Figure58
Figure61
Figure61
Figure61
Figure61
Figure50
Figure50
Figure50
Figure50
Figure48
Figure48
Figure49
Figure49
0.2
-
0.45
10
-
ns
tH R
2
-
ns
tQR1, tQF1
tPROP1
tNAPXA
tNAPXB
tPDNXA
tPDNXB
tAS
12
20
50
40
4
ns
-
ns
-
ns
NAP exit delay - phase B
-
ns
PDN exit delay - phase A
-
ms
PDN exit delay - phase B
-
9000
1
tCYCLE
tCYCLE
tCYCLE
tCYCLE
tCYCLE
ATTN-to-STBY power state delay
-
tSA
STBY-to-ATTN power state delay
-
0
tASN
ATTN/STBY-to-NAP power state delay
ATTN/STBY-to-PDN power state delay
-
8
tASP
-
8
a. tQ,MIN and tQ,MAX for other tCYCLE values can be interpolated between or extrapolated from the timings at the 3 specified tCYCLE values.
Version 1.4 July 2002
Page 14
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
Timing Parameters
Table 13: Timing Parameter Summary
Min
-35
Parameter
Description
Max
Units
Figure(s)
-1066
Row Cycle time of RDRAM banks -the interval between ROWA packets with ACT commands
to the same bank.
Figure16
Figure17
tRC
tRAS
tRP
32
22
10
8
-
tCYCLE
RAS-asserted time of RDRAM bank - the interval between ROWA packet with ACT command
and next ROWR packet with PRERa command to the same bank.
Figure16
Figure17
64msb tCYCLE
Row Precharge time of RDRAM banks - the interval between ROWR packet with PRERa com-
mand and next ROWA packet with ACT command to the same bank.
Figure16
Figure17
-
-
-
tCYCLE
tCYCLE
tCYCLE
Precharge-to-precharge time of RDRAM device - the interval between successive ROWR
packets with PRERa commands to any banks of the same device.
tPP
Figure13
Figure14
RAS-to-RAS time of RDRAM device - the interval between successive ROWA packets with
ACT commands to any banks of the same device.
tRR
8
RAS-to-CAS Delay - the interval from ROWA packet with ACT command to COLC packet
with RD or WR command). Note - the RAS-to-CAS delay seen by the RDRAM core (tRCD-C
is equal to tRCD-C = 1 + tRCD because of differences in the row and column paths through the
RDRAM interface.
)
Figure16
Figure17
tRCD
9
-
tCYCLE
CAS Access delay - the interval from RD command to Q read data. The equation for tCAC is
given in the TPARM register in Figure40.
Figure5
Figure40
tCAC
tCWD
tCC
9
6
4
4
8
12
6
-
tCYCLE
tCYCLE
tCYCLE
tCYCLE
tCYCLE
CAS Write Delay (interval from WR command to D write data.
Figure5
Figure16
Figure17
CAS-to-CAS time of RDRAM bank - the interval between successive COLC commands).
Length of ROWA, ROWR, COLC, COLM or COLX packet.
tPACKET
tRTR
4
-
Figure3
Figure18
Interval from COLC packet with WR command to COLC packet which causes retire, and to
COLM packet with bytemask.
The interval (offset) from COLC packet with RDA command, or from COLC packet with retire
command (after WRA automatic precharge), or from COLC packet with PREC command, or
from COLX packet with PREX command to the equivalent ROWR packet with PRER. The
equation for tOFFP is given in the TPARM register in Figure40.
Figure15
Figure40
tOFFP
4
4
tCYCLE
tRDP
tRTP
Interval from last COLC packet with RD command to ROWR packet with PRER.
5
5
-
-
tCYCLE
tCYCLE
Figure16
Figure17
Interval from last COLC packet with automatic retire command to ROWR packet with PRER.
a. Or equivalent PREC or PREX command. See Figure15.
b. This is a constraint imposed by the core, and is therefore in units of ms rather than tCYCLE
.
Version 1.4 July 2002
Page 15
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
Absolute Maximum Ratings
Table 14: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
VI,ABS
VDD,ABS , VDDA,ABS
TSTORE
Voltage applied to any RSL or CMOS pin with respect to Gnd
Voltage on VDD and VDDA with respect to Gnd
Storage temperature
- 0.3
- 0.5
- 50
0
VDD+0.3
VDD+1.0
100
V
V
°C
°C
TMIN
Minimum operation temperature
Note*
Note*) Component : refer to TJ,QJC RIMM: refre to TPLATE, MAX
I
- Supply Current Profile
DD
Table 15: Supply Current Profile
Max
(1066MHz,
-35)
a
I
value
RDRAM Power State and Steady-State Transaction Rates
Min
Unit
D D
IDD,PDN
IDD,NAP
Device in PDN, self-refresh enabled and INIT.LSR=0.
Device in NAP.
-
-
TBD
TBD
mA
mA
Device in STBY. This is the average for a device in STBY with (1) no packets on the
Channel, and (2) with packets sent to other devices.
IDD,STBY
-
-
-
TBD
TBD
TBD
mA
mA
mA
IDD,REFRESH
IDD,ATTN
Device in STBY and refreshing rows at the tREF,MAX period.
Device in ATTN. This is the average for a device in ATTN with (1) no packets on the
Channel, and (2) with packets sent to other devices.
Device in ATTN. ACT command every 8• t CYCLE , PRE command every 8• t CYCLE
WR command every 4•tCYCLE, and data is 1100..1100
,
,
IDD,ATTN-W
-
-
TBD
TBD
mA
mA
Device in ATTN. ACT command every 8• t CYCLE , PRE command every 8•tCYCLE
RD command every 4•tCYCLE, and data is 1111..1111b
IDD,ATTN-R
a. CMOS interface consumes power in all power states.
b. This does not include the IOL sink current. The RDRAM dissipates IOL•VOL in each output driver when a logic one is driven.
Table 16: Supply Current at Initialization
Symbol
Parameter
Allowed Range of t
V
Min
Max
Unit
CYCLE
DD
VDD,MIN
VDD,MIN
IDD,PWRUP,D
IDD,SETR,D
IDD from power -on to SETR
IDD from SETR to CLRR
1.875ns to 2.5ns
1.875ns to 2.5ns
-
-
TBD
TBD
mA
mA
Version 1.4 July 2002
Page 16
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
Capacitance and Inductance
Table 17: RSL Pin Parasitics
Symbol
Parameter and Conditions - RSL pins
RSL effective input inductance @ tCYCLE=1.875ns
Min
Max
4.0
0.2
0.6
1.0
2.4
0.1
Unit
nH
nH
nH
nH
pF
Figure
L
L
-
Figure 63
I
Mutual inductance between any DQA or DQB RSL signals.
Mutual inductance between any ROW or COL RSL signals.
-
-
Figure 63
12
DL
Difference in L value between any RSL pins of a single device.
-
Figure 63
Figure 63
Figure 63
I
I
a
C
C
RSL effective input capacitance @ tCYCLE=1.875ns
2.0
-
I
Mutual capacitance between any RSL signals.
pF
12
Difference in C value between average of {CTM, CTMN,
I
DC
-
0.06
15
pF
Figure 63
Figure 63
I
CFM, CFMN} and any RSL pins of a single device.
R
RSL effective input resistance @ tCYCLE=1.875ns
4
W
I
a. This value is a combination of the device IO circuitry and package capacitances measured at VDD=2.5V and f=400MHz with pin biased at 1.4V.
Table 18: CMOS Pin Parasitics
Symbol
Parameter and Conditions - CMOS pins
CMOS effective input inductance
CMOS effective input capacitance (SCK,CMD)
Min
Max
Unit
Figure
L
8.0
2.1
7.0
nH
pF
pF
I ,CMOS
a
C
C
1.7
-
Figure 63
I ,CMOS
I ,CMOS,SIO
a
CMOS effective input capacitance (SIO1, SIO0)
a. This value is a combination of the device IO circuitry and package capacitances.
Version 1.4 July 2002
Page 17
Preliminary
Direct RDRAM™
K4R521669A
/K4R761869A for short channel 1066 MHz
Center-Bonded WBGA Package
(92balls)
Figure4 shows the form and dimensions of the recom-
mended package for the 92balls center-bonded WBGA
device class.
D
Bottom
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
T
U
Bottom
Top
1
2
3
4
A
5
6
7
8
e2
9
10
d
e1
Bottom
E
E1
Figure 4: Center-Bonded WBGA Package
Table19 lists the numerical values corresponding to dimen-
sions shown in Figure4.
Table 19: Center-Bonded WBGA Package Dimensions
Symbol
Parameter
Min.
Max.
Unit
e1
e2
A
Ball pitch (x-axis)
0.80
0.80
13.3
15.0
0.98
0.30
0.40
0.80
0.80
13.5
15.2
1.08
0.40
0.50
mm
mm
mm
mm
mm
mm
mm
Ball pitch (y-axis)
Package body length
Package body width
D
E
Package total thickness
Ball height
E1
d
Ball diameter
Version 1.4 July 2002
Page 18
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