K4S161622H-TC700 [SAMSUNG]

Synchronous DRAM, 1MX16, 5.5ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50;


型号：	K4S161622H-TC700
厂家：	SAMSUNG
描述：	Synchronous DRAM, 1MX16, 5.5ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50 动态存储器光电二极管内存集成电路
文件：	总11页 (文件大小：108K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SDRAM 16Mb H-die(x16)

CMOS SDRAM

16Mb H-die SDRAM Specification

Revision 1.5

August 2004

Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.5 August 2004

SDRAM 16Mb H-die(x16)

CMOS SDRAM

Revision History

Revision 0.0 (May, 2003)

- Target spec release.

Revision 0.1 (October, 2003)

- Modified tRDL from 1CLK to 2CLK.

Revision 0.2 (October, 2003)

- Deleted AC parameter notes 5.

Revision 0.3 (October, 2003)

- Modified tRDL & deleted speed 200MHz.

Revision 1.0 (November, 2003)

- Revision 1.0 spec. release.

Revision 1.1 (December, 2003)

- Corrected PKG dimension.

Revision 1.2 (January, 2004)

- Deleted -10(10ns) speed.

- Modified load cap 50pF -> 30pF.

- Modified DC current .

Revision 1.3 (January, 2004)

- Corrected typo

Revision 1.4 (May, 2004)

- Added Note 8. sentense of tRDL parameter.

Revision 1.5 (August, 2004)

- Modified CLK cycle time(tcc) parameter in AC Characteristics.

( If you want use of CL=2 not CL=3, the maximum operating frequency is 100MHz regardless of its speed bin.)

Rev. 1.5 August 2004

SDRAM 16Mb H-die(x16)

CMOS SDRAM

512K x 16Bit x 2 Banks SDRAM

FEATURES

• 3.3V power supply

• LVTTL compatible with multiplexed address

• two banks operation

• MRS cycle with address key programs

-. CAS Latency ( 2 & 3)

-. Burst Length (1, 2, 4, 8 & full page)

-. Burst Type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system clock

• Burst Read Single-bit Write operation

• DQM for masking

• Auto & self refresh

• 32ms refresh period (2K cycle)

GENERAL DESCRIPTION

The K4S161622H is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated

with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/

O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable laten-

cies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

ORDERING INFORMATION

Part NO.

MAX Freq.

183MHz

166MHz

143MHz

125MHz

Interface

Package

K4S161622H-TC55

K4S161622H-TC60

K4S161622H-TC70

K4S161622H-TC80

50pin

TSOP(II)

LVTTL

Organization

Row Address

Column Address

1Mx16

A0~A10

A0-A7

Row & Column address configuration

Rev. 1.5 August 2004

SDRAM 16Mb H-die(x16)

CMOS SDRAM

Package Physical Dimension

0~8°

#50

#26

0.25 TYP

#25

+0.075

-0.035

0.125

20.95

± 0.10

1.20MAX

1.00± 0.10

0.10MAX

0.075MAX

[

]

0.80TYP

[0.80±0.08]

0.30 ^+0.10

0.35 ^+0.10

-0.05

0.05MIN

(0.875)

-0.05

50Pin TSOP(II) Package Dimension

Rev. 1.5 August 2004

SDRAM 16Mb H-die(x16)

CMOS SDRAM

FUNCTIONAL BLOCK DIAGRAM

LWE

Data Input Register

LDQM

Bank Select

512K x 16

DQi

CLK

ADD

Column Decoder

Latency & Burst Length

LCKE

Programming Register

LWCBR

LRAS

LCBR

LWE

LCAS

LDQM

Timing Register

CLK

CKE

RAS

CAS

L(U)DQM

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.5 August 2004

SDRAM 16Mb H-die(x16)

CMOS SDRAM

PIN CONFIGURATION (TOP VIEW)

VDD

DQ0

DQ1

VSSQ

DQ2

DQ3

VDDQ

DQ4

DQ5

VSSQ

VSS

49 DQ15

48 DQ14

46 DQ13

45 DQ12

43 DQ11

42 DQ10

VSSQ

VDDQ

VSSQ

DQ6 11

DQ7 12

40 DQ9

39 DQ8

VDDQ

LDQM 14

WE 15

CAS 16

RAS 17

CS 18

37 N.C/RFU

36 UDQM

35 CLK

34 CKE

33 N.C

32 A9

BA 19

A10/AP 20

A0 21

31 A8

30 A7

A1 22

29 A6

A2 23

A3 24

28 A5

27 A4

50PIN TSOP (II)

(400mil x 825mil)

(0.8 mm PIN PITCH)

VDD

VSS

PIN FUNCTION DESCRIPTION

Name

System Clock

Input Function

CLK

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and L(U)DQM

Chip Select

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE

Clock Enable

Row / column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA10, column address : CA0 ~ CA7

A0 ~ A10/AP Address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Bank Select Address

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

RAS

Row Address Strobe

Column Address Strobe

Write Enable

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

CAS

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when L(U)DQM active.

L(U)DQM

Data Input/Output Mask

DQ0 ~ 15

VDD/VSS

Data Input/Output

Data inputs/outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Power Supply/Ground

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

VDDQ/VSSQ

N.C/RFU

Data Output Power/Ground

No Connection/

Reserved for Future Use

This pin is recommended to be left No Connection on the device.

Rev. 1.5 August 2004

SDRAM 16Mb H-die(x16)

CMOS SDRAM

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Storage temperature

Symbol

VIN, VOUT

VDD, VDDQ

TSTG

Value

-1.0 ~ 4.6

-55 ~ +150

Unit

°C

Power dissipation

Short circuit current

IOS

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)

Parameter

Supply voltage

Symbol

VDD, VDDQ

VIH

Min

3.0

2.0

-0.3

2.4

Typ

3.3

3.0

Max

Unit

Note

3.6

Input logic high votlage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

VDDQ+0.3

VIL

0.8

VOH

IOH = -2mA

IOL = 2mA

VOL

0.4

ILI

-10

Note :

1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ VIN ≤ VDDQ.

Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)

Symbol

CCLK

CIN

Min

Max

Unit

Clock

RAS, CAS, WE, CS, CKE, L(U)DQM

Address

CADD

COUT

DQ0 ~ DQ15

Rev. 1.5 August 2004

SDRAM 16Mb H-die(x16)

CMOS SDRAM

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C )

Version

Parameter

Symbol

Test Condition

Unit

Note

Burst Length =1

Operating Current

(One Bank Active)

ICC1

tRC≥tRC(min)

Io = 0 mA

120

115

105

ICC2P

CKE≤VIL(max), tCC = 10ns

Precharge Standby Current in

power-down mode

ICC2PS

CKE & CLK≤VIL(max), tCC = ∞

CKE≥VIH(min), CS≥VIH(min), tCC = 10ns

Input signals are changed one time during

30ns

ICC2N

Precharge Standby Current

in non power-down mode

CKE≥VIH(min), CLK≤VIL(max), tCC = ∞

Input signals are stable

ICC2NS

ICC3P

CKE≤VIL(max), tCC = 10ns

Active Standby Current

in power-down mode

ICC3PS

CKE & CLK≤VIL(max), tCC = ∞

CKE≥VIH(min), CS≥VIH(min), tCC = 10ns

Input signals are changed one time during

30ns

ICC3N

ICC3NS

ICC4

Active Standby Current

in non power-down mode

(One Bank Active)

CKE≥VIH(min), CLK≤VIL(max), tCC = ∞

Input signals are stable

Io = 0 mA

Page Burst 2Banks Activated

tCCD = 2CLKs

Operating Current

(Burst Mode)

155

105

150 140 130

Refresh Current

ICC5

ICC6

tRC≥tRC(min)

CKE≤0.2V

100

Self Refresh Current

Note :

1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.

2. Measured with outputs open. Addresses are changed only one time during tcc(min).

3. Refresh period is 32ms. Addresses are changed only one time during tcc(min).

4. K4S161622H-TC

Rev. 1.5 August 2004

SDRAM 16Mb H-die(x16)

CMOS SDRAM

AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)

Parameter

Input levels (Vih/Vil)

Value

2.4 / 0.4

1.4

Unit

Input timing measurement reference level

Input rise and fall time

tr / tf = 1 / 1

1.4

Output timing measurement reference level

Output load condition

See Fig. 2

3.3V

Vtt=1.4V

1200Ω

50Ω

VOH (DC) = 2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

Output

Z0=50Ω

30pF

870Ω

(Fig. 1) DC Output Load Circuit

(Fig. 2) AC Output Load Circuit

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

Parameter Symbol

Unit Note

Min

5.5

Max

Min

Max

Min

Max

Min

Max

CAS Latency=3

CAS Latency=2

CLK cycle time

tCC

1000

Row active to row active delay

RAS to CAS delay

tRRD(min)

tRCD(min)

tRP(min)

16.5

38.5

Row precharge time

tRAS(min)

tRAS(max)

tRC(min)

tRDL(min)

tCDL(min)

tBDL(min)

tCCD(min)

tMRS(min)

100

Row active time

Row cycle time

Last data in to row precharge

Last data in to new col.address delay

Last data in to burst stop

CLK

2,8

Col. address to col. address delay

Mode Register Set cycle time

CAS Latency=3

CAS Latency=2

Number of valid out-

put data

Rev. 1.5 August 2004

SDRAM 16Mb H-die(x16)

CMOS SDRAM

(AC operating conditions unless otherwise noted)

-70

-80

Parameter

CAS Latency=3

Symbol

Unit Note

Min

5.5

Max

Min

Max

Min

Max

Min

Max

CLK cycle time

tCC

1000

CAS Latency=2

CAS Latency=3

CAS Latency=2

5.5

CLK to valid

output delay

tSAC

5, 6

Output data

tOH

tCH

2.5

CAS Latency=3

CAS Latency=2

CAS Latency=3

CAS Latency=2

CAS Latency=3

CAS Latency=2

CLK high pulse

width

2.5

CLK low pulse

width

tCL

tSS

1.5

1.75

Input setup time

Input hold time

tSH

CLK to output in Low-Z

tSLZ

CAS Latency=3

CAS Latency=2

5.5

CLK to output

in Hi-Z

tSHZ

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then

rounding off to the next higher integer. Refer to the following clock unit based AC conversion table

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. Parameters depend on programmed CAS latency.

6. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

7. Assumed input rise and fall time (tr & tf)=1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

8. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.

SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.

Rev. 1.5 August 2004

SDRAM 16Mb H-die(x16)

CMOS SDRAM

SIMPLIFIED TRUTH TABLE

CKEn-1

CKEn

RAS

CAS

DQM

A10/AP

A9~ A0

Note

1, 2

COMMAND

Refresh

Mode Register Set

Auto Refresh

OP CODE

Entry

Self

Refresh

Exit

Bank Active & Row Addr.

Row Address

Read &

Auto Precharge Disable

Auto Precharge Enable

Auto Precharge Disable

Auto Precharge Enable

4, 5

Column

Address

Column Address

Write &

Column

Address

Column Address

4, 5

Burst Stop

Precharge

Bank Selection

Both Banks

Entry

Clock Suspend or

Active Power Down

Exit

Entry

Precharge Power Down Mode

Exit

DQM

No Operation Command

(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)

Note :

1. OP Code : Operand Code

A0 ~ A10/AP, BA : Program keys. (@MRS)

2. MRS can be issued only at both banks precharge state.

A new command can be issued after 2 clock cycle of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at both banks precharge state.

4. BA : Bank select address.

If "Low" at read, write, row active and precharge, bank A is selected.

If "High" at read, write, row active and precharge, bank B is selected.

If A10/AP is "High" at row precharge, BA is ignored and both banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the assoiated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Rev. 1.5 August 2004

K4S161622H-TC700 [SAMSUNG]

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